A wide swing gain scalable folded cascode floating inverting amplifier

Abstract

The application belongs to the field of analog integrated circuits, and particularly relates to a wide-swing gain-extensible folded cascode floating inverting amplifier. The application adopts a differential structure, and each energy storage capacitor provides independent power supply for an input transistor pair and a cascode transistor pair, breaks through the limitation of a traditional laminated structure, and provides a mutual decoupling and extremely abundant voltage margin for the input transistor pair and the output cascode transistor pair. Through capacitor suspension power supply, each layer of transistor can obtain sufficient transient bias in a low-voltage environment, so that a differential signal with high DC gain and large swing is constructed at the output end. Meanwhile, by using the pole distribution law of a single-stage folding topology, the main pole is locked at the output high resistance node, and the non-main pole is pushed to an extremely high frequency band, so that the gain accuracy, dynamic output range and loop stability are deeply optimized.

Description

Technical Field

[0001] This invention belongs to the field of analog integrated circuits and relates to operational amplifiers in integrated circuits, specifically a folded cascode floating inverting amplifier with wide swing gain scalability. Background Technology

[0002] As CMOS process nodes continue to evolve, the continuous reduction in integrated circuit power supply voltage provides the necessary conditions for improving speed and reducing power consumption, but it also brings severe challenges to the design of high-performance analog integrated circuits. In advanced process environments, the short-channel effect and channel length modulation effect of transistors become increasingly significant, leading to a continuous decay in the intrinsic gain of devices. At the same time, due to the ever-compressing power supply voltage, the traditional approach of vertically stacking transistors to improve DC gain is greatly limited, and the severe compression of the output voltage swing directly threatens the signal-to-noise ratio (SNR) and linearity of analog signals.

[0003] To overcome the aforementioned performance bottlenecks, the Floating Inverter Amplifier (FIA) architecture, with its unique dynamic energy efficiency advantages, has become a highly promising solution. The FIA ​​utilizes a storage capacitor C1 to replace the static bias circuit and common-mode feedback network in traditional amplifiers, completely eliminating static power consumption while avoiding the drain of overdrive voltage by tail current sources. This optimizes the voltage margin at the physical level and improves the output swing to some extent.

[0004] However, when faced with the demands of high-gain, large-swing high-performance applications, traditional FIA architectures often face a dilemma: if a cascode structure is used, the number of vertical stacking layers is difficult to maintain under low-voltage conditions, and it will significantly squeeze the output voltage swing; if a multi-stage cascaded structure is used, multiple low-frequency poles will be introduced into the signal path, which will not only significantly reduce the available bandwidth of the amplifier, but also bring a tricky closed-loop stability challenge.

[0005] In summary, due to the objective limitation of low power supply voltage under advanced processes, existing amplifier technology cannot simultaneously achieve high gain, high bandwidth, and large output swing. Summary of the Invention

[0006] To address the aforementioned problems and shortcomings, and to solve the issue that traditional FIAs struggle to simultaneously achieve high gain, high bandwidth, and large swing under low power supply voltage, this invention proposes a folded cascode floating inverting amplifier with scalable wide swing gain. This amplifier achieves simultaneous improvement in gain accuracy and swing space while ensuring absolute loop stability.

[0007] A wide-swing, gain-scalable folded cascode floating inverting amplifier, such as... Figure 1As shown, it includes: transistor MP 1A MP 2A MP 1B MP 2B MN 1A MN 2A MN 1B MN 2B Energy storage capacitors C1 and C 2A C 2B and switch SW VDD1 SW GND1 SW C1A+ SW C1A- SW C2A+ SW C2A- SW VDD2A SW GND2A SW C1B+ SW C1B- SW C2B+ SW C2B- SW VDD2B SW GND2B SW OUTA SW OUTB Among them, MP 1A MP 2A MP 1B MP 2B For PMOS transistors, MN 1A MN 2A MN 1B MN 2B It is an NMOS transistor.

[0008] The entire inverting amplifier circuit is a completely symmetrical differential structure: the left half of the circuit includes transistor MP. 1A MP 2A MN 1A MN 2A Energy storage capacitor C 2A and switch SW C1A+ SW C1A- SW C2A+ SW C2A- SW VDD2A SW GND2A SW OUTA The right half of the circuit includes transistor MP. 1B MP 2B MN 1B MN 2B Energy storage capacitor C 2B and switch SW C1B+ SW C1B- SW C2B+ SW C2B- SWVDD2B SW GND2B SW OUTB Energy storage capacitor C1 and switch SW VDD1 SW GND1 This constitutes the middle section of the inverting amplifier circuit. The components in the left and right halves of the circuit are identical in size and performance, and are located in symmetrical positions.

[0009] The transistor MP 1A With MN 1A The gates are connected together and are connected to the input signal V. IN Transistor MP 1A The source and switch SW C1A+ One end is connected to the switch SW C1A+ The other end is connected to the upper plate of the energy storage capacitor C1; transistor MP 1A The drain is connected to transistor MN 2A The source and switch SW C2A- One end; transistor MN 1A The source and switch SW C1A- One end is connected to the switch SW C1A- The other end is connected to the lower plate of the energy storage capacitor C1; transistor MN 1A The drain is connected to the transistor MP 2A The source and switch SW C2A+ One end.

[0010] Transistor MP 1B With MN 1B The gates are connected together and are connected to the input signal V. IP Transistor MP 1B The source and switch SW C1B+ One end is connected to the switch SW C1B+ The other end is connected to the upper plate of the energy storage capacitor C1; transistor MP 1B The drain is connected to transistor MN 2B The source and switch SW C2B- One end; transistor MN 1B The source and switch SW C1B- One end is connected to the switch SW C1B- The other end is connected to the lower plate of the energy storage capacitor C1; transistor MN 1B The drain is connected to the transistor MP 2B The source and switch SW C2B+ One end.

[0011] Switch SW VDD1 One end of the switch is connected to the upper plate of the energy storage capacitor C1, and the other end is connected to the power supply voltage VDD; switch SW GND1One end is connected to the lower plate of the energy storage capacitor C1, and the other end is connected to the ground voltage GND.

[0012] The transistor MP 2A With MN 2A The gate is connected and connected to the common-mode voltage V. CM Transistor MP 2A With MN 2A The drains are connected and defined as the output node V. OUTN Node V OUTN via switch SW OUTA Connected to common-mode voltage V CM Transistor MP 2A The source is connected to transistor MN 1A The drain of the transistor MN 2A The source is connected to the transistor MP. 1A The drain electrode.

[0013] Energy storage capacitor C 2A The upper plate is connected to switch SW VDD2A one end and SW C2A+ At the other end, switch SW VDD2A The other end is connected to the power supply voltage VDD, and the switch SW C2A+ One end is connected to transistor MP 2A The source; energy storage capacitor C 2A The lower electrode plate is connected to switch SW GND2A One end is with SW C2A- At the other end, switch SW GND2A The other end is connected to ground voltage GND, switch SW C2A- One end is connected to transistor MN 2A The source pole.

[0014] The transistor MP 2B With MN 2B The gate is connected and connected to the common-mode voltage V. CM Transistor MP 2B With MN 2B The drains are connected and defined as the output node V. OUTP Node V OUTP via switch SW OUTB Connected to common-mode voltage V CM Transistor MP 2B The source is connected to transistor MN 1B The drain of the transistor MN 2B The source is connected to the transistor MP. 1B The drain electrode.

[0015] Energy storage capacitor C 2B The upper plate is connected to switch SWVDD2B one end and SW C2B+ At the other end, switch SW VDD2B The other end is connected to the power supply voltage VDD, and the switch SW C2B+ The other end is connected to transistor MP 2B The source; energy storage capacitor C 2B The lower electrode plate is connected to switch SW GND2B one end and SW C2B- At the other end, switch SW GND2B The other end is connected to ground voltage GND, switch SW C2B- One end is connected to transistor MN 2B The source pole.

[0016] Furthermore, the control logic and workflow of the aforementioned wide-swing gain scalable folded cascode floating inverting amplifier are as follows:

[0017] During the reset phase, switch SW VDD1 SW GND1 SW VDD2A SW GND2A SW VDD2B SW GND2B SW OUTA SW OUTB Close; Switch SW C1A+ SW C1A- SW C1B+ SW C1B- SW C2A+ SW C2A- SW C2B+ SW C2B- disconnect.

[0018] Power supply voltage VDD and energy storage capacitors C1 and C 2A C 2B The upper plates of the three energy storage capacitors are connected, and the nodes V corresponding to the upper plates of the three energy storage capacitors are connected. C1+ V C2A+ V C2B+ Charge them and pull their voltages up to VDD, and throughout the entire process before the reset state ends, node V C1+ V C2A+ V C2B+ The voltages are all maintained at VDD; while the ground voltage GND and the energy storage capacitors C1 and C2 are... 2A C 2B The lower plates of the three energy storage capacitors are connected, and the nodes V corresponding to the lower plates of the three energy storage capacitors are connected. C1- V C2A- V C2B- Discharge is performed, and their voltages are all pulled down to GND. Throughout the entire process before the reset state ends, node V...C1- V C2A- V C2B- The voltage is maintained at GND; during this period, the amplifier performs energy storage and state initialization, preparing the energy storage capacitors C1 and C2 for the amplification process. 2A C 2B Prepare as a virtual power source and ground; simultaneously, output node V OUTN and V OUTP Reset to common-mode voltage V CM Clear the charge memory from the previous amplification cycle.

[0019] During the dynamic amplification phase, switch SW VDD1 SW GND1 SW VDD2A SW GND2A SW VDD2B SW GND2B SW OUTA SW OUTB Disconnect; switch SW C1A+ SW C1A- SW C1B+ SW C1B- SW C2A+ SW C2A- SW C2B+ SW C2B- The circuit is closed, with the closed switch considered as a wire, and the open switch omitted. The circuit structure diagram in the amplification stage is shown below. Figure 2 As shown.

[0020] The upper plate of the energy storage capacitor C1 is connected to the transistor MP. 1A and MP 1B The source is connected, and the lower plate is connected to the transistor MN. 1A and MN 1B The source is connected; the energy storage capacitor C 2A The upper plate and the transistor MP 2A The source and MN 1A The drain is connected, and the lower plate is connected to transistor MN. 2A The source and MP 1A The drains are connected; the energy storage capacitor C 2B The upper plate and the transistor MP 2B The source and MN 1B The drain is connected, and the lower plate is connected to transistor MN. 2B The source and MP 1B The drains of the capacitors are connected; at this time, the energy storage capacitors C1 and C2 are connected. 2A C 2B Isolated from the external charging and discharging path, the amplifier then enters a state entirely controlled by the energy storage capacitors C1 and C2. 2A C 2BThe dominant dynamic floating amplification state; at this time, the energy storage capacitor C acts as the power source. 2A The current I flowing out of the upper plate C2A+ Flow into transistor MP 2A The source and MN 1A The drain, C 2A The current I flowing into the lower plate C2A- From transistor MN 2A The source and MP 1A The drain of the capacitor; the energy storage capacitor C acts as the power source. 2B The current I flowing out of the upper plate C2B+ Flow into transistor MP 2B The source and MN 1B The drain, C 2B The current I flowing into the lower plate C2B- From transistor MN 2B The source and MP 1B The drain of the capacitor; the current I flowing from the upper plate of the energy storage capacitor C1, which acts as the power source. C1+ Flow into transistor MP 1A The source and MP 1B The source of C1, the current I flowing into the lower plate C1- From transistor MN 1A The source and MN 1B The source pole.

[0021] Input differential signal V IN V IP First, the input transistor acts on MP. 1A MN 1A and MP 1B MN 1B The input differential voltage is amplified using a push-pull method. Subsequently, the amplified differential current is folded and injected into the transistor MP through a cross-coupling path. 2A MN 2A and MP 2B MN 2B The source terminals of the common-source and common-gate transistor pair ultimately achieve a differential voltage output V at the output terminal after amplification via a folded Cascode structure. OUTN V OUTP .

[0022] Furthermore, such as Figure 1 The single-layer folded cascode architecture shown can be extended by connecting Cascode transistors in parallel. Figure 1 Based on the single-layer folded cascode architecture shown, the extended circuits are as follows: Figure 3 As shown.

[0023] The Cascode structure hierarchy is defined by the subscript numbers of the overall cascode floating inverting amplifier:

[0024] The transistor, energy storage capacitor, and switch corresponding to the subscript number 1 constitute the input level common source structure. The subscripts A and B correspond to the left and right halves of the differential structure, respectively.

[0025] Following the input-level common-source structure in both the left and right halves of the circuit, n layers of Cascode structures are cascaded sequentially, 1≤n, to form a differential structure of a folded common-source cascode floating inverting amplifier. For the left half of the circuit, 1≤k≤n, the k-th Cascode structure includes: a PMOS transistor MP kA NMOS transistor MN kA Energy storage capacitor C kA and switch SW VDDkA SW GNDkA SW CkA+ SW CkA- .

[0026] In the k-th layer Cascode structure, transistor MP kA With MN kA The gate is connected to the common-mode voltage V. CM Transistor MP kA The drain is connected to transistor MN in the (k+1)th layer Cascode structure. (k+1)A The source is connected to transistor MN in the (k-1)th layer Cascode structure. (k-1)A The drain of the transistor MN; kA The drain is connected to transistor MP in the (k+1)th layer Cascode structure. (k+1)A The source is connected to the transistor MP in the (k-1)th layer Cascode structure. (k-1)A The drain electrode.

[0027] Energy storage capacitor C kA The upper plate is connected to switch SW VDDkA one end and SW CkA+ At the other end, switch SW VDDkA The other end is connected to the power supply voltage VDD, and the switch SW CkA+ The other end is connected to transistor MP kA The source; energy storage capacitor C kA The lower electrode plate is connected to switch SW GNDkA one end and SW CkA- At the other end, switch SW GNDkA The other end is connected to ground voltage GND, switch SW CkA- One end is connected to transistor MN kA The source pole.

[0028] When k=1, the k-1 layer is an input layer Cascode structure.

[0029] When k=n, then the nth layer is an output-level Cascode structure.

[0030] In the nth layer Cascode structure, transistor MP nA With MN nA The gate is connected to the common-mode voltage V. CM Transistor MP nA The drain is connected to MN nA The drain of the node serves as the output node V. OUTN Node V OUTN via switch SW OUTA Connected to common-mode voltage V CM Transistor MP nA The source is connected to transistor MN (k-1)A The drain of the transistor MN nA The source is connected to the transistor MP. (k-1)A The drain electrode;

[0031] Energy storage capacitor C nA The upper plate is connected to switch SW VDDnA one end and SW CnA+ At the other end, switch SW VDDnA The other end is connected to the power supply voltage VDD, and the switch SW CnA+ One end is connected to transistor MP nA The source; energy storage capacitor C nA The lower electrode plate is connected to switch SW GNDnA One end is with SW CnA- At the other end, switch SW GNDnA The other end is connected to ground voltage GND, switch SW CnA- One end is connected to transistor MN nA The source pole.

[0032] Furthermore, the condition n≤20 is limited by the frequency response characteristics of the amplifier, and there is a physical upper limit to the value of n. By constraining n to the range of n≤20, good stability of the amplifier during operation is ensured.

[0033] This invention is in Figure 1 Based on the common-source input + single-layer Cascode structure shown, a modularly scalable parallel architecture with n layers of Cascode is proposed. This architecture achieves step-by-step gain transfer by introducing an intermediate stage (the k-th layer of Cascode structure). Analyzing from a small-signal model perspective, the parallel expansion increases the original single-stage gain A... V1 Transform into a multi-level product AV1 ×A V2 ×……A Vn (A) Vn (This refers to the gain of the nth Cascode layer). Since each Cascode layer operates in a voltage domain approximately equal to the supply voltage VDD, provided by independent energy storage capacitors, all transistors operate stably in the saturation region, resulting in an exponential increase in total DC gain with the number of layers. Simultaneously, the modularly expanded n-layer Cascode structure exhibits the same voltage swing capability as the unexpanded architecture. The parallel modules at each stage are completely decoupled in the DC path, ensuring that the amplification process of the later stage does not squeeze the voltage margin of the previous stage. Regarding frequency response, although the parallel-expanded architecture increases the number of poles at the parallel nodes of the Cascode structure, since the added poles in each Cascode layer are secondary dominant poles, they are pushed to extremely high frequencies. The expanded amplifier is essentially still a single-pole system, and the phase margin does not significantly deteriorate compared to the unexpanded structure, maintaining high bandwidth and high stability.

[0034] In summary, the wide-swing, gain-scalable folded cascode FIA ​​architecture proposed in this invention solves the technical challenge of balancing high gain, large swing, and loop stability in traditional cascaded amplifiers. While maintaining high DC gain, it ensures excellent output swing even under low-voltage processes, guaranteeing sufficient phase margin. Furthermore, the modularly extended parallel architecture further leverages the advantages of dynamic voltage domain isolation. Through DC decoupling of each cascaded unit, it achieves an exponential increase in total gain with increasing stage number. Since each stage can independently obtain ample voltage margin, the system achieves ultra-high gain while retaining the large voltage swing capability consistent with a single-layer cascode structure, while the single-pole system ensures sufficient bandwidth. Attached Figure Description

[0035] Figure 1 This is a structural block diagram of the present invention.

[0036] Figure 2 This is a schematic diagram of the dynamic amplification stage of the present invention.

[0037] Figure 3 This is a block diagram of the cascaded expansion structure of the present invention.

[0038] Figure 4 This is a structural diagram of an embodiment. Detailed Implementation

[0039] The present invention will now be further explained with reference to the accompanying drawings and embodiments.

[0040] The specific structure of this embodiment is as follows: Figure 4 As shown.

[0041] The PMOS transistor MP acts as a reset switch. VDD1 MP VDD2A MP VDD2B Their gates are all controlled by the operating clock CLK, and their sources are all connected to the power supply voltage VDD. Transistor MP VDD1 The drain of the transistor is connected to the upper plate of the energy storage capacitor C1; transistor MP VDD2A The drain of the energy storage capacitor C is connected. 2A Upper plate; transistor MP VDD2B The drain of the energy storage capacitor C is connected. 2B The upper plate. The NMOS transistor MN acts as a reset switch. GND1 MN GND2A MN GND2B Their gates are all controlled by the reset clock CLKN, and their sources are all connected to ground voltage GND. Transistor MN GND1 The drain of transistor MN is connected to the lower plate of energy storage capacitor C1; GND2A The drain of the energy storage capacitor C is connected. 2A The lower electrode plate; transistor MN GND2B The drain of the energy storage capacitor C is connected. 2B The lower electrode plate.

[0042] The PMOS transistor MP acts as a switch. C2A+ MP C2B+ Their gates are all controlled by the operating clock CLKN, and their sources are respectively connected to C. 2A C 2B The upper plates of the transistor are connected to the drains of the transistor MP. 2A MP 2B The source of the NMOS transistor MN, which acts as a switch. C2A- MN C2B- Their gates are all controlled by the operating clock CLK, and their sources are connected to C respectively. 2A C 2B The lower plates of the transistors are connected to the drains of transistors MN. 2A MN 2B The source pole.

[0043] The PMOS transistor MP acts as a switch. C1A+ MP C1B+ Their gates are all controlled by the operating clock CLKN, their sources are all connected to the upper plate of C1, and their drains are respectively connected to transistor MP. 1A MP 1B The source of the NMOS transistor MN, which acts as a switch. C1A- MN C1B-Their gates are all controlled by the operating clock CLK, their sources are all connected to the lower plate of C1, and their drains are respectively connected to transistors MN. 1A MN 1B The source pole.

[0044] Transmission Gate (TG) OUTA TG OUTB Output signal V for reset phase OUTN V OUTP Reset to common-mode voltage V CM The operating clock CLK controls the gate of the PMOS transistor in the transmission gate, and the reset clock CLKN controls the gate of the NMOS transistor in the transmission gate. Transmission gate TG OUTA TG OUTB One end is connected to the output signal V OUTN V OUTP The other end is connected to a common-mode voltage V. CM .

[0045] Finally, to prevent the input transistor from affecting the MP 1A With MN 1A Drain-source overvoltage: Add a PMOS transistor MP to the N terminal of the differential circuit. cascodeA Its source is connected to the transistor MP. 1A The drain of the transistor is connected to the drain of transistor MN. 2A The source; simultaneously adding an NMOS transistor MN cascodeA Its source is connected to transistor MN 1A The drain of the transistor MP is connected to the drain of the transistor MP. 2A The source. Similarly, PMOS transistors MP are added at the same location on the P terminal. cascodeB With NMOS transistor MN cascodeB Transistor MP cascodeA MP cascodeB With MN cascodeA MN cascodeB The gate of the transistor is controlled by ground voltage GND and power supply voltage VDD respectively, and the transistor always remains in a normally open state. If the voltage withstand capability of the input transistor pair is sufficient, no MP is required. cascodeA MP cascodeB With MN cascodeA MN cascodeB transistor.

[0046] The folded cascode dynamic floating amplifier in this embodiment operates in two stages: a reset stage and a dynamic amplification stage. Based on the perfect symmetry of the differential circuit, the working mechanism of the left half (N-terminal) circuit is described in detail.

[0047] During the reset phase, the reset clock CLKN is high and the operating clock CLK is low, driving the reset circuit to start. Reset switch MP VDD1 MN GND1 MP VDD2A MN GND2A When closed, the power supply voltage VDD affects the energy storage capacitors C1 and C2. 2A Charging is performed to initialize the potential difference between the upper and lower plates to the power supply voltage VDD. Simultaneously, the transmission gate TG... OUTA Turn on, and turn on the output terminal V OUTN Clamped to common-mode level V CM Through this pre-charge process, the circuit establishes a sufficient floating voltage margin for subsequent dynamic amplification operations and eliminates the influence of residual charge on the dynamic amplification stage.

[0048] During the dynamic amplification phase, the reset clock CLKN is low, the operating clock CLK is high, and the reset switch MP... VDD1 MN GND1 MP VDD2A MN GND2A Disconnect, transmission gate TG OUTA Turn off, disengaging the output from common-mode clamping. Switch MP C1A+ With MN C1A- Controlled conduction directs the high potential of the upper plate of the energy storage capacitor C1 to the transistor MP. 1A The source of the transistor MN, and the transistor MN 1A The source of the transistor is connected to the low potential of the lower plate of the energy storage capacitor C1. The switching transistor MP... C2A+ With MN C2A- Controlled conduction, turning on the energy storage capacitor C 2A The high potential of the upper plate is used to guide the transistor MP. 2A The source and MN cascodeA The drain of the transistor MN, and the transistor MN 2A The source, MP cascodeA The drain and energy storage capacitor C 2A The lower plate is connected to the low potential, thus converting the energy storage capacitor into an independent floating voltage source for power supply.

[0049] The differential input signal first acts on MP 1A MN 1A MP cascodeA MN cascodeA The resulting cascode input transistor pair exhibits extremely high amplification during operation. Subsequently, the AC differential current is injected into the MP transistor through a cross-coupling path. 2A MN 2AThis constitutes the Cascode-level source terminal. Under this working mechanism, by fully utilizing the energy stored in the floating capacitors through each stage of the circuit, the three-layer transistors maintain a deep saturation state across the entire signal swing, thereby constructing an extremely high dynamic output impedance at the output node and ensuring the accurate and stable establishment of the amplified signal.

[0050] Because this invention employs a differential structure, its core performance can be derived from the mechanism analysis of the left half of the circuit. Taking the left half of the circuit as an example, let's analyze it from the perspective of signal gain characteristics. Input transistor MN 1A The drain and source terminals are respectively connected across the energy storage capacitor C. 2A The upper plate of the transistor and the lower plate of the energy storage capacitor C1 are powered directly by a dynamic voltage margin between the two plates, approximately VDD, ensuring the power supply of the input transistor MN. 1A (and its symmetrical MP) 1A It can remain in the deep saturation region throughout the entire amplification cycle. In the Cascode output stage, the cascode transistor for MP... 2A MN 2A Directly from the energy storage capacitor C 2A The upper and lower plates provide a floating voltage approximately equal to VDD; ample voltage margin ensures MP 2A and MN 2A The transistors remain locked in a strong saturation operating region during the dynamic amplification phase. This endows the two-stage transistors with extremely high and robust transconductance, which not only greatly improves the open-loop DC gain of the system but also ensures that the gain remains stable over a wide output swing range.

[0051] From the perspective of signal bias, energy storage capacitors C1 and C 2A C 2B This provides independent power supplies for the input transistor pairs and the cascode transistor pairs, breaking through the limitations of traditional stacked structures and enabling independent power supply for the input transistor pairs MP. 1A MN 1A With the output cascode transistor paired with MP 2A MN 2A It provides mutual decoupling and an extremely ample voltage margin. The input transistor pair can operate stably in the strong saturation region while simultaneously supporting the MP from the cascode transistor. 2A Looking at the drain, the MP transistor 2A Let A be a common-gate amplifier with a small-signal gain of A. V When the output signal V OUTN When ΔV changes, the output cascode transistor affects MP. 2A The source minimum signal voltage will change in the same direction by ΔV / A. VThe output node can maintain a larger effective voltage fluctuation range, offering a greater swing range compared to the traditional FIA structure. This ensures that the cascode transistor can fully unleash its voltage swing potential under low-voltage processes, thereby significantly improving the amplifier's linear output range.

[0052] From a frequency response perspective, this architecture effectively optimizes the pole distribution, exhibiting high bandwidth and high stability. As a single-stage folded amplifier, the dominant pole of this invention is located at the high-impedance node at the output, i.e., MP. 2A With MP 2B The drain of the common-gate transistor. The secondary dominant pole is located at the low-impedance source folding node of the common-gate transistor, i.e., MP. 1A MP 1B MN 1A MN 1B The drain of the amplifier pushes the secondary dominant pole to extremely high frequencies, giving the amplifier excellent phase margin. Therefore, compared with multi-stage cascaded structures, this invention not only eliminates the problems of low-frequency pole introduction and frequency compensation, but also significantly improves unity-gain bandwidth, ensuring that the amplifier maintains absolute stability in applications.

[0053] As can be seen from the above embodiments, this invention uses capacitor-floating power supply to ensure that each layer of transistors can obtain sufficient transient bias under low-voltage conditions, thereby constructing a differential signal with both high DC gain and large swing at the output. Simultaneously, by utilizing the pole distribution pattern of the single-stage folded topology, the dominant pole is locked at the high-impedance output node, and the non-dominant poles are pushed to extremely high frequencies, achieving deep optimization of gain accuracy, dynamic output range, and loop stability.

Claims

1. A folded cascode floating inverting amplifier with wide swing gain scalability, characterized in that, include: Transistor MP 1A MP 2A MP 1B MP 2B MN 1A MN 2A MN 1B MN 2B Energy storage capacitors C1 and C 2A C 2B and switch SW VDD1 SW GND1 SW C1A+ SW C1A- SW C2A+ SW C2A- SW VDD2A SW GND2A SW C1B+ SW C1B- SW C2B+ SW C2B- SW VDD2B SW GND2B SW OUTA SW OUTB ; Among them, MP 1A MP 2A MP 1B MP 2B For PMOS transistors, MN 1A MN 2A MN 1B MN 2B It is an NMOS transistor; The entire inverting amplifier circuit is a completely symmetrical differential structure: the left half of the circuit includes transistor MP. 1A MP 2A MN 1A MN 2A Energy storage capacitor C 2A and switch SW C1A+ SW C1A- SW C2A+ SW C2A- SW VDD2A SW GND2A SW OUTA The right half of the circuit includes transistor MP. 1B MP 2B MN 1B MN 2B Energy storage capacitor C 2B and switch SW C1B+ SW C1B- SW C2B+ SW C2B- SW VDD2B SW GND2B SW OUTB Energy storage capacitor C1 and switch SW VDD1 SW GND1 The middle part of the inverting amplifier circuit; the components in the left and right halves of the circuit are exactly the same in size and performance, and are located in symmetrical positions. The transistor MP 1A With MN 1A The gates are connected together and are connected to the input signal V. IN Transistor MP 1A The source and switch SW C1A+ One end is connected to the switch SW C1A+ The other end is connected to the upper plate of the energy storage capacitor C1; transistor MP 1A The drain is connected to transistor MN 2A The source and switch SW C2A- One end; transistor MN 1A The source and switch SW C1A- One end is connected to the switch SW C1A- The other end is connected to the lower plate of the energy storage capacitor C1; transistor MN 1A The drain is connected to the transistor MP 2A The source and switch SW C2A+ One end; Transistor MP 1B With MN 1B The gates are connected together and are connected to the input signal V. IP Transistor MP 1B The source and switch SW C1B+ One end is connected to the switch SW C1B+ The other end is connected to the upper plate of the energy storage capacitor C1; transistor MP 1B The drain is connected to transistor MN 2B The source and switch SW C2B- One end; transistor MN 1B The source and switch SW C1B- One end is connected to the switch SW C1B- The other end is connected to the lower plate of the energy storage capacitor C1; transistor MN 1B The drain is connected to the transistor MP 2B The source and switch SW C2B+ One end; Switch SW VDD1 One end of the switch is connected to the upper plate of the energy storage capacitor C1, and the other end is connected to the power supply voltage VDD; switch SW GND1 One end is connected to the lower plate of the energy storage capacitor C1, and the other end is connected to the ground voltage GND; The transistor MP 2A With MN 2A The gate is connected and connected to the common-mode voltage V. CM Transistor MP 2A With MN 2A The drains are connected and defined as the output node V. OUTN Node V OUTN via switch SW OUTA Connected to common-mode voltage V CM Transistor MP 2A The source is connected to transistor MN 1A The drain of the transistor MN 2A The source is connected to the transistor MP. 1A The drain electrode; Energy storage capacitor C 2A The upper plate is connected to switch SW VDD2A one end and SW C2A+ At the other end, switch SW VDD2A The other end is connected to the power supply voltage VDD, and the switch SW C2A+ One end is connected to transistor MP 2A The source; energy storage capacitor C 2A The lower electrode plate is connected to switch SW GND2A One end is with SW C2A- At the other end, switch SW GND2A The other end is connected to ground voltage GND, switch SW C2A- One end is connected to transistor MN 2A The source pole; The transistor MP 2B With MN 2B The gate is connected and connected to the common-mode voltage V. CM Transistor MP 2B With MN 2B The drains are connected and defined as the output node V. OUTP Node V OUTP via switch SW OUTB Connected to common-mode voltage V CM Transistor MP 2B The source is connected to transistor MN 1B The drain of the transistor MN 2B The source is connected to the transistor MP. 1B The drain electrode; Energy storage capacitor C 2B The upper plate is connected to switch SW VDD2B one end and SW C2B+ At the other end, switch SW VDD2B The other end is connected to the power supply voltage VDD, and the switch SW C2B+ The other end is connected to transistor MP 2B The source; energy storage capacitor C 2B The lower electrode plate is connected to switch SW GND2B one end and SW C2B- At the other end, switch SW GND2B The other end is connected to ground voltage GND, switch SW C2B- One end is connected to transistor MN 2B The source pole.

2. The wide-swing, gain-expandable folded cascode floating inverting amplifier as described in claim 1, characterized in that, The specific control logic and workflow are as follows: During the reset phase, switch SW VDD1 SW GND1 SW VDD2A SW GND2A SW VDD2B SW GND2B SW OUTA SW OUTB Close; Switch SW C1A+ SW C1A- SW C1B+ SW C1B- SW C2A+ SW C2A- SW C2B+ SW C2B- disconnect; Power supply voltage VDD and energy storage capacitors C1 and C 2A C 2B The upper plates of the three energy storage capacitors are connected, and the nodes V corresponding to the upper plates of the three energy storage capacitors are connected. C1+ V C2A+ V C2B+ Charge them and pull their voltages up to VDD, and throughout the entire process before the reset state ends, node V C1+ V C2A+ V C2B+ The voltages are all maintained at VDD; while the ground voltage GND and the energy storage capacitors C1 and C2 are... 2A C 2B The lower plates of the three energy storage capacitors are connected, and the nodes V corresponding to the lower plates of the three energy storage capacitors are connected. C1- V C2A- V C2B- Discharge is performed, and their voltages are all pulled down to GND. Throughout the entire process before the reset state ends, node V... C1- V C2A- V C2B- The voltage is maintained at GND; during this period, the amplifier performs energy storage and state initialization, preparing the energy storage capacitors C1 and C2 for the amplification process. 2A C 2B Prepare as a virtual power source and ground; simultaneously, output node V OUTN and V OUTP Reset to common-mode voltage V CM Clear the charge memory from the previous amplification cycle; During the dynamic amplification phase, switch SW VDD1 SW GND1 SW VDD2A SW GND2A SW VDD2B SW GND2B SW OUTA SW OUTB Disconnect; switch SW C1A+ SW C1A- SW C1B+ SW C1B- SW C2A+ SW C2A- SW C2B+ SW C2B- closure; The upper plate of the energy storage capacitor C1 is connected to the transistor MP. 1A and MP 1B The source is connected, and the lower plate is connected to the transistor MN. 1A and MN 1B The source is connected; the energy storage capacitor C 2A The upper plate and the transistor MP 2A The source and MN 1A The drain is connected, and the lower plate is connected to transistor MN. 2A The source and MP 1A The drains are connected; the energy storage capacitor C 2B The upper plate and the transistor MP 2B The source and MN 1B The drain is connected, and the lower plate is connected to transistor MN. 2B The source and MP 1B The drains of the capacitors are connected; at this time, the energy storage capacitors C1 and C2 are connected. 2A C 2B Isolated from the external charging and discharging path, the amplifier then enters a state entirely controlled by the energy storage capacitors C1 and C2. 2A C 2B The dominant dynamic floating amplification state; at this time, the energy storage capacitor C acts as the power source. 2A The current I flowing out of the upper plate C2A+ Flow into transistor MP 2A The source and MN 1A The drain, C 2A The current I flowing into the lower plate C2A- From transistor MN 2A The source and MP 1A The drain of the capacitor; the energy storage capacitor C acts as the power source. 2B The current I flowing out of the upper plate C2B+ Flow into transistor MP 2B The source and MN 1B The drain, C 2B The current I flowing into the lower plate C2B- From transistor MN 2B The source and MP 1B The drain of the capacitor; the current I flowing from the upper plate of the energy storage capacitor C1, which acts as the power source. C1+ Flow into transistor MP 1A The source and MP 1B The source electrode, the current I flowing into the lower plate of C1 C1- From transistor MN 1A The source and MN 1B The source pole; Input differential signal V IN V IP First, the input transistor acts on MP. 1A MN 1A and MP 1B MN 1B The input differential voltage is amplified using a push-pull method; subsequently, the amplified differential current is folded and injected into the transistor MP through a cross-coupling path. 2A MN 2A and MP 2B MN 2B The source terminals of the common-source and common-gate transistor pair ultimately achieve a differential voltage output V at the output terminal after amplification via a folded Cascode structure. OUTN V OUTP .

3. The wide-swing, gain-expandable folded cascode floating inverting amplifier as described in claim 1, characterized in that: The Cascode structure hierarchy is defined by the subscript numbers of the overall cascode floating inverting amplifier: The transistor, energy storage capacitor, and switch corresponding to the subscript number 1 constitute the input level common source structure. The subscripts A and B correspond to the left and right halves of the differential structure, respectively. After the input level common source structure in the left and right halves of the circuit, n layers of Cascode structure are cascaded in sequence, 1≤n, to form a differential structure folded common source cascode floating inverting amplifier; For the left half of the circuit, 1≤k≤n, and the k-th layer Cascode structure includes: PMOS transistor MP kA NMOS transistor MN kA Energy storage capacitor C kA and switch SW VDDkA SW GNDkA SW CkA+ SW CkA- ; In the k-th layer Cascode structure, transistor MP kA With MN kA The gate is connected to the common-mode voltage V. CM Transistor MP kA The drain is connected to transistor MN in the (k+1)th layer Cascode structure. (k+1)A The source is connected to transistor MN in the (k-1)th layer Cascode structure. (k-1)A The drain of the transistor MN; kA The drain is connected to transistor MP in the (k+1)th layer Cascode structure. (k+1)A The source is connected to the transistor MP in the (k-1)th layer Cascode structure. (k-1)A The drain electrode; Energy storage capacitor C kA The upper plate is connected to switch SW VDDkA one end and SW CkA+ At the other end, switch SW VDDkA The other end is connected to the power supply voltage VDD, and the switch SW CkA+ The other end is connected to transistor MP kA The source; energy storage capacitor C kA The lower electrode plate is connected to switch SW GNDkA one end and SW CkA- At the other end, switch SW GNDkA The other end is connected to ground voltage GND, switch SW CkA- One end is connected to transistor MN kA The source pole; When k=1, then the (k-1)th layer is an input layer Cascode structure; When k=n, then the nth layer is an output layer Cascode structure; In the nth layer Cascode structure, transistor MP nA With MN nA The gate is connected to the common-mode voltage V. CM Transistor MP nA The drain is connected to MN nA The drain of the node serves as the output node V. OUTN Node V OUTN via switch SW OUTA Connected to common-mode voltage V CM Transistor MP nA The source is connected to transistor MN (k-1)A The drain of the transistor MN nA The source is connected to the transistor MP. (k-1)A The drain electrode; Energy storage capacitor C nA The upper plate is connected to switch SW VDDnA one end and SW CnA+ At the other end, switch SW VDDnA The other end is connected to the power supply voltage VDD, and the switch SW CnA+ One end is connected to transistor MP nA The source; energy storage capacitor C nA The lower electrode plate is connected to switch SW GNDnA One end is with SW CnA- At the other end, switch SW GNDnA The other end is connected to ground voltage GND, switch SW CnA- One end is connected to transistor MN nA The source pole.

4. The wide-swing, gain-expandable folded cascode floating inverting amplifier as described in claim 3, characterized in that: n≤20。

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