driver

Abstract

The present application provides a driver. The driver includes a switching signal generating circuit, a comparison circuit, a driving circuit and a port control module. The switching signal generating circuit generates a pull-up path non-inverted switching signal, a pull-up path inverted switching signal, a pull-down path non-inverted switching signal and a pull-down path inverted switching signal. A non-inverted comparator input terminal of the comparison circuit is electrically connected to a driver output terminal. An inverted comparator output terminal of the comparison circuit is electrically connected to a pull-up transistor gate terminal. The driving circuit includes a pull-up circuit and a pull-down circuit. The pull-up circuit and the pull-down circuit selectively adjust a voltage of the driver output terminal according to voltages of the pull-up transistor gate terminal and a pull-down transistor gate terminal. The port control module sets the voltages of the pull-up transistor gate terminal and the pull-down transistor gate terminal.

Description

Technical Field

[0001] This invention relates to a driver, and more particularly to a single-stage driver suitable for low-power applications. Background Technology

[0002] The Mobile Industry Processor Interface (MIPI) is a specification defined for processor designs widely used in mobile devices such as smartphones. In the MIPI architecture, the MIPI controller uses a PHY layer transmitter to transmit clock and data signals to the receiving circuitry. The data signals transmitted by the MIPI transmitter can be transmitted through one or more data lanes, and the MIPI transmitter has a port physical layer driver for each data lane.

[0003] Please see Figure 1 This is a block diagram of a MIPI port physical layer driver used in the prior art. After receiving the driver enable signal EN and the digital format driver input signal inDAT (which switches between 0 and 1) from the MIPI controller, the MIPI port physical layer driver 10 generates a voltage format driver output signal outSIG based on the driver input signal inDAT when the driver enable signal EN is equal to a high logic level L (EN = H). Alternatively, when the driver enable signal EN is equal to a low logic level L (EN = L), the generation of the driver output signal outSIG based on the driver input signal inDAT is stopped. The driver output signal outSIG is then further transmitted to the MIPI receiver.

[0004] The MIPI port physical layer driver 10 includes: a port control circuit 101, a low-dropout regulator (LDO) 103, a first-stage driver circuit (DRV1) 105, and a second-stage driver circuit (DRV2) 107. The first-stage driver circuit (DRV1) 105 includes: a pull-up circuit upCKT1 and a pull-down circuit dnCKT1; the second-stage driver circuit (DRV2) 107 includes: a pull-up path capacitor Cup, a pull-up circuit upCKT1, a pull-down path capacitor Cdn, and a pull-down circuit dnCKT1.

[0005] Port control circuit 101 is electrically connected to the first-stage drive circuit (DRV1) 105 and the second-stage drive circuit (DRV2) 107. Low-dropout regulator 103 is electrically connected to the first-stage drive circuit (DRV1) 105. Furthermore, port control circuit 101, pull-up path capacitor Cup, pull-down path capacitor Cdn, pull-up circuits upCKT1 and upCKT2, and pull-down circuits dnCKT1 and dnCKT2 are all electrically connected to the driver output terminal ND. out The pull-up circuits upCKT1 and upCKT2 are both electrically connected to the high supply voltage terminal Vddh (e.g., 1.8V), and the pull-down circuits dnCKT1 and dnCKT2 are both electrically connected to the ground voltage terminal Gnd.

[0006] For ease of explanation, this document uses the same symbols to represent signal lines and the signal / voltage on those lines. For example, Vddh represents both the high supply voltage endpoint and the high supply voltage.

[0007] The voltage of the driver output signal outSIG changes according to the value of the driver input signal inDAT. When the driver input signal inDAT is "0" (inDAT = "0"), the MIPI port physical layer driver 10 at the driver output terminal ND... out The generated driver output signal outSIG is 1.2V. When the driver input signal inDAT is "1" (inDAT = "1"), the MIPI port physical layer driver 10 is at the driver output terminal ND. out The resulting driver output signal outSIG is 1.2V.

[0008] The port control circuit 101 receives the driver input signal inDAT from the MIPI controller; receives an input reference voltage Vref_in (e.g., 1V) and a high supply voltage Vddh (e.g., 1.8V) with a fixed voltage value; and receives the driver output terminal ND. out Receive the driver output signal outSIG. After receiving the high supply voltage Vddh (e.g., 1.8V) and the low dropout reference voltage Vref_ldo (e.g., 0.6V), the low dropout regulator 103 first generates a low supply voltage Vddl (e.g., 1.2V) to the first-stage driver circuit (DRV1) 105.

[0009] The port control circuit 101 generates control signals ctlSIG_pg1, ctlSIG_ng1, ctlSIG_ng1, and ctlSIG_ng2 in response to changes in the driver input signal inDAT. Specifically, the port control circuit 101 transmits control signal ctlSIG_pg1 to the pull-up circuit upCKT1 of the first-stage driver circuit (DRV1) 105; transmits control signal ctlSIG_ng1 to the pull-down circuit dnCKT1 of the first-stage driver circuit (DRV1) 105; transmits control signal ctlSIG_pg2 to the pull-up circuit upCKT2 and pull-up path capacitor Cup of the second-stage driver circuit (DRV2) 107; and transmits control signal ctlSIG_ng2 to the pull-down circuit dnCKT2 and pull-down path capacitor Cdn of the second-stage driver circuit (DRV2) 107.

[0010] When the driver input signal inDAT is in a transient process (inDAT = L → H) from a low logic level L to a high logic level H, the port control circuit 101 enables the pull-up circuit upCKT2 using the control signal ctlSIG_pg2. On the other hand, the port control circuit 101 disables the pull-up circuit upCKT1 using the control signal ctlSIG_pg1, disables the pull-down circuit dnCKT1 using the control signal ctlSIG_ng1, and disables the pull-down circuit dnCKT2 using the control signal ctlSIG_ng2.

[0011] When the driver input signal inDAT is in a stable state, maintaining a high logic level H, the port control circuit 101 enables the pull-up circuit upCKT1 using the control signal ctlSIG_pg1, keeping the driver output signal outSIG equal to the low supply voltage Vddl (e.g., 1.2V). Simultaneously, the port control circuit 101 disables the pull-down circuit dnCKT1 using the control signal ctlSIG_ng1, disables the pull-up circuit upCKT2 using the control signal ctlSIG_pg2, and disables the pull-down circuit dnCKT2 using the control signal ctlSIG_ng1.

[0012] When the driver input signal inDAT is in a transient process of changing from a high logic level H to a low logic level L (inDAT = H → L), the port control circuit 101 enables the pull-down circuit dnCKT2 using the control signal ctlSIG_ng2. On the other hand, the port control circuit 101 disables the pull-up circuit upCKT1 using the control signal ctlSIG_pg1, disables the pull-down circuit dnCKT1 using the control signal ctlSIG_ng1, and disables the pull-up circuit upCKT2 using the control signal ctlSIG_pg2.

[0013] When the driver input signal inDAT is in a stable state maintained at a low logic level L, the port control circuit 101 enables the pull-down circuit dnCKT1 using the control signal ctlSIG_ng1, so that the driver output signal outSIG is maintained at a ground voltage Gnd. At the same time, the port control circuit 101 disables the pull-up circuit upCKT1 using the control signal ctlSIG_pg1, disables the pull-up circuit upCKT2 using the control signal ctlSIG_pg2, and disables the pull-down circuit dnCKT2 using the control signal ctlSIG_ng1.

[0014] Continuing from the above, in order to generate a 1.2V driver output signal outSIG when the driver input signal inDAT is at a high logic level H (inDAT = "H"), the MIPI port physical layer driver 10 needs to be equipped with two driver circuits: a first-stage driver circuit (DRV1) 105 and a second-stage driver circuit (DRV2) 107. The first-stage driver circuit (DRV1) 105 is used to generate the 1.2V driver output signal outSIG; the second-stage driver circuit (DRV2) 107 is used to adjust the slew rate of the driver output signal outSIG during transients of the driver input signal inDAT (e.g., when the driver input signal inDAT changes from a low logic level L to a high logic level H (inDAT = "L→H"), or when the driver input signal inDAT changes from a high logic level H to a low logic level L (inDAT = "H→L")).

[0015] Depend on Figure 1 It can be seen that the existing MIPI port physical layer driver 10 has at least the following problems: First, it needs to receive two reference voltages from the outside (input reference voltage Vref_in and low dropout reference voltage Vref_ldo); second, it requires an additional low dropout regulator 103 to provide a low supply voltage Vddl; third, an error amplifier needs to be set inside the low dropout regulator 103, and an operational amplifier (OP) used as a comparator also needs to be set inside the port control circuit 101. Therefore, the circuit design of the existing MIPI port physical layer driver 10 is still too complicated. Summary of the Invention

[0016] This invention relates to a driver implemented using a single-stage drive circuit. The driver of this invention requires only one comparator circuit, resulting in a small circuit area and suitability for low-power applications.

[0017] According to one aspect of the present invention, a driver is provided. The driver includes: a switching signal generation circuit, a comparator circuit, a driving circuit, and a port control module. The switching signal generation circuit generates a pull-up path positive phase switching signal, a pull-up path negative phase switching signal, a pull-down path positive phase switching signal, and a pull-down path negative phase switching signal based on a driving circuit enable signal and a driver input signal. The comparator circuit is electrically connected to a first fixed voltage terminal and a second fixed voltage terminal. The comparator circuit includes: a positive comparator input terminal, an negative comparator input terminal, a positive comparator output terminal, and a negative comparator output terminal. The positive comparator input terminal is electrically connected to the driver output terminal of the driver. The negative comparator input terminal receives a reference voltage. The reference voltage is greater than the voltage of the second fixed voltage terminal and less than the voltage of the first fixed voltage terminal. The negative comparator output terminal is electrically connected to the gate control terminal of the pull-up transistor. The driving circuit includes: a pull-up circuit and a pull-down circuit. The pull-up circuit is electrically connected to the switching signal generation circuit and the comparator circuit. The pull-up circuit selectively adjusts the voltage at the driver output terminal based on the voltage of the pull-up path positive switching signal and the voltage at the gate control terminal of the pull-up transistor. The pull-down circuit is electrically connected to the switching signal generation circuit. The pull-down circuit selectively adjusts the voltage at the driver output terminal based on the voltage of the pull-down path negative switching signal and the voltage at the gate control terminal of the pull-down transistor. The port control module is electrically connected to the switching signal generation circuit, the comparator circuit, and the driver circuit. The port control module sets the voltages at the gate control terminals of the pull-up and pull-down transistors based on the pull-up path positive switching signal, the pull-up path negative switching signal, the pull-down path positive switching signal, and the pull-down path negative switching signal.

[0018] To provide a better understanding of the above and other aspects of the present invention, specific embodiments are described below in conjunction with the accompanying drawings: Attached Figure Description

[0019] Figure 1 It is a block diagram of the MIPI port physical layer driver used in the prior art;

[0020] Figure 2 It is a block diagram of the driver portDRV contemplated according to this disclosure;

[0021] Figure 3 It is a schematic diagram illustrating how the switching signal generation circuit swGenCKT of the present disclosure concept can be implemented by logic circuits;

[0022] Figure 4 It is a schematic diagram of the internal components and related signals of the port control module portCtrlMDL according to the present disclosure;

[0023] Figure 5It is a schematic diagram of the internal components and related signal pairs of the comparator circuit cfCKT according to the present disclosure;

[0024] Figure 6 It is a schematic diagram of the internal components and related signals of the drive circuit DRV according to the present disclosure;

[0025] Figure 7 It is a schematic diagram of the internal components and related signals of the compensation circuit compCKT according to the present disclosure;

[0026] Figure 8 It is a circuit diagram of the driver portDRV according to the present disclosure;

[0027] Figure 9 It is a schematic diagram of the circuit state of the driver portDRV according to the present disclosure when the drive circuit enable signal EN is at a low logic level L (EN = L);

[0028] Figure 10 It is a schematic diagram of how the port control module portCtrlMDL according to the present disclosure controls the driver portDRV to change the circuit state in response to the change of the driver input signal inDAT when the driver circuit enable signal EN is at a high logic level H (EN=H).

[0029] Figure 11 It is a schematic diagram of the circuit state of the driver portDRV according to the present disclosure during the rising transient phase PH1.

[0030] Figure 12 It is a schematic diagram of the circuit state of the driver portDRV according to the present disclosure during the high steady-state phase PH2.

[0031] Figure 13 It is a schematic diagram of the circuit state pair of the driver portDRV according to the present disclosure during the falling transient phase PH3;

[0032] Figure 14 It is a schematic diagram of the circuit state of the driver portDRV according to the present disclosure during the low steady-state phase PH4.

[0033] Figure 15 It is a waveform diagram showing how the internal endpoints of the driver portDRV according to the present disclosure change with the driver input signal inDAT when the driver circuit enable signal EN is at a high logic level H (EN = H) and the external enable signal IQ_extEN of the additional current path is set to a low logic level L (IQ_extEN = L) and the additional current path add_curPATH is disabled.

[0034] Figure 16 It is a waveform diagram showing how the internal endpoints of the driver portDRV according to the present disclosure change with the driver input signal inDAT when the driver circuit enable signal EN is at a high logic level H (EN = H) and the external enable signal IQ_extEN of the additional current path is set to a high logic level H (IQ_extEN = H) to enable the additional current path add_curPATH.

[0035] Figure 17 The diagram shows the addition of transistor path output impedance Rout_ts and capacitor path output impedance Rout_cp to the driver portDRV.

[0036] Figure 18A This is a schematic diagram of calculating the equivalent output impedance Rout_eq when the pull-up path is selected in the rising transient phase PH1 and the high steady-state phase PH2 after adding the transistor path output impedance Rout_ts and the capacitor path output impedance Rout_cp to the driver portDRV.

[0037] Figure 18B This is a schematic diagram of calculating the equivalent output impedance Rout_eq when the pull-down path is selected in the transient phase PH3 and the low steady-state phase PH4 after adding the transistor path output impedance Rout_ts and the capacitor path output impedance Rout_cp to the driver portDRV.

[0038] Figure 19 It is a schematic diagram of setting multiple parallel pull-up transistors upPM[1]~upPM[4], multiple parallel pull-down transistors dnNM[1]~dnNM[4] and multiple parallel transistor path output impedances Rout_ts[1]~Rout_ts[4] on the driver portDRV;

[0039] Figure 20 It is in response to Figure 19 A schematic diagram showing the parallel compensation current paths comp_curPATH[1]~comp_curPATH[4] and parallel additional current paths add_curPATH[1]~add_curPATH[4] set by the driver portDRV; and

[0040] Figure 21 This is a schematic diagram of a low-dropout regulator (LDO) formed by a driver portDRV according to the present disclosure, using a comparator circuit cfCKT, a pull-up transistor upPM, and a compensation circuit compCKT.

[0041] The reference numerals in the attached figures are explained as follows:

[0042] 10: MIPI Physical Layer Driver

[0043] 101: Port control circuit

[0044] 103, LDO: Low Dropout Voltage Regulator

[0045] 105, DRV1: First-stage driver circuit

[0046] 107, DRV2: Second-stage drive circuit

[0047] EN: Enable signal for drive circuit

[0048] inDAT: Driver input signal

[0049] Vref_ldo: Low dropout reference voltage

[0050] Vref_in: Input reference voltage

[0051] Vddl: Low supply voltage (terminal)

[0052] Vddh: High supply voltage (endpoint)

[0053] Gnd: Grounding voltage (terminal)

[0054] Cup: Pull-up path capacitor

[0055] Cdn: Pull-down path capacitor

[0056] upCKT2, upCKT1, upCKT: Pull-up circuits

[0057] dnCKT2, dnCKT1, dnCKT: Pull-down circuit

[0058] ctlSIG_pg1, ctlSIG_ng1, ctlSIG_pg2, ctlSIG_ng2: Control signal ND out : Driver output endpoint

[0059] outSIG: Driver output signal

[0060] portDRV: driver

[0061] swGenCKT: Switching signal generation circuit

[0062] extCTL: External Controller

[0063] portCtrlMDL: Port control module

[0064] cfCKT: Comparator circuit

[0065] compCKT: Compensation circuit

[0066] DRV: Drive

[0067] SW_P: Pull-up path positive phase switching signal

[0068] SWB_P: Pull-up path inversion switching signal

[0069] SW_N: Pull-down path positive phase switching signal

[0070] SWB_N: Pull-down path inversion switching signal

[0071] cfout+: Output of the positive comparator

[0072] cfout-: Output of the inverting comparator

[0073] cfin+: Input of the inverting comparator

[0074] cfin-: Input of the inverting comparator

[0075] Vref: Reference voltage

[0076] ND mrr_pm PMOS current mirror bias terminal

[0077] ND Cup Pull-up capacitor endpoint

[0078] ND Cdn Pull-down capacitor endpoint

[0079] ND NG18 Pull-down transistor gate control terminal

[0080] IQ_EN: Additional current path enable signal

[0081] IQ_extEN: External enable signal for additional current path

[0082] Vcc: Supply voltage (terminal)

[0083] ND comp_en Compensation circuit enable endpoint

[0084] ND mrr_comp : Compensation circuit bias terminals

[0085] NAND1, NAND2: NAND gates

[0086] NOT1a, NOT1b, NOT1c: NOT gates

[0087] cfdisPM: PMOS current mirror disabled transistor

[0088] cfdisNM: NMOS current mirror disabling transistor

[0089] updisPM: Pull-up path disabled transistor

[0090] upbpPM: Pull-up path bypass transistor

[0091] dnbpNM: Pull-down path bypass transistor

[0092] dndisNM: Pull-down path disabled transistor

[0093] comp_disNM: Compensation circuit disabling transistor

[0094] ND PG18 Pull-up transistor gate terminal

[0095] pathSelCKT: Path selection circuit

[0096] pMRR: PMOS current mirror

[0097] pmrr_pPM: PMOS current mirror inverting transistor

[0098] pmrr_nPM: PMOS current mirror inverting transistor

[0099] I pPM Comparator reference current

[0100] I nPM Comparator mirror current

[0101] diffpNM: Non-phase differential input transistor

[0102] diffnNM: Inverting differential input transistor

[0103] diffInCKT: Differential input circuit

[0104] I nNM Bias mirror current

[0105] nMRR: NMOS current mirror

[0106] nmrr_nNM: NMOS current mirror inverting transistor

[0107] nmrr_pNM: NMOS current mirror inverting transistor

[0108] I pNM Bias reference current

[0109] upPM, upPM[1], upPM[2], upPM[3], upPM[4]: pull-up transistor; upTG: pull-up path transmission gate

[0110] dnTG: Pull-down path transmission gate

[0111] dnNM, dnNM[1], dnNM[2], dnNM[3], dnNM[4]: pull-down transistors; enTG: drive circuit enable transmission gate.

[0112] Rout: Output impedance

[0113] addEnCKT: Additional current enable circuit

[0114] comp_refPATH: Compensation reference current path

[0115] comp_curPATH[1], comp_curPATH[K]: Compensation current path

[0116] add_curPATH[1], add_curPATH[K]: Additional current paths

[0117] curSRC: Reference current source ND pathSEL : Path selection endpoints

[0118] upselTG: Pull-up path uses a transmission gate

[0119] dnselTG: The pull-down path uses a transmission gate.

[0120] ND diff Differential endpoint

[0121] ND Cfb Capacitor feedback endpoint

[0122] add_iqenNM: Enables transistors with additional current paths

[0123] I add_iq I add_iq [1], I add_iq [2], I add_iq [3], I add_iq [4]: Additional current

[0124] add_iqNM, add_iqNM[1], add_iqNM[2], add_iqNM[3], add_iqNM[4]: Additional current path transistors

[0125] comp_iqNM, comp_iqNM[1], comp_iqNM[2], comp_iqNM[3], comp_iqNM[4]: Compensating current path transistor

[0126] comp_bsnNM: Compensation current source pull-down bias transistor

[0127] comp_bspPM: Compensation current source pull-up bias transistor

[0128] PH1: Rising Transient Phase

[0129] PH2: High steady-state stage

[0130] PH3: Decreasing transient phase

[0131] PH4: Low steady-state stage

[0132] t1~t10: Time points

[0133] I comp_ref Compensation reference current

[0134] I comp_iq I comp_iq [1], I comp_iq [2], I comp_iq [3], I comp_iq [4]: Compensation current

[0135] Rout_ts, Rout_ts[1], Rout_ts[2], Rout_ts[3], Rout_ts[4]: Transistor path output impedance

[0136] ND Rout_ts ND Rout_ts [1], ND Rout_ts [2], ND Rout_ts [3], ND Rout_ts [4]: Transistor path output endpoint

[0137] Rout_cp: Output impedance of the capacitor path Detailed Implementation

[0138] To address the shortcomings of existing MIPI port physical layer drivers, this disclosure proposes the following embodiments of a layer driver. The driver portDRV of this disclosure can be applied to MIPI port physical drivers or other types of applications. As disclosed in the following embodiments, the driver portDRV of this disclosure does not require an additional low-dropout regulator, only an operational amplifier, only a single-stage drive circuit, and only needs to receive a reference voltage Vref (e.g., 1.2V).

[0139] Please see Figure 2This is a block diagram of a driver portDRV according to the present disclosure. The driver portDRV includes: a switching signal generation circuit swGenCKT, a port control module portCtrlMDL, a comparator circuit cfCKT, a drive circuit DRV, and a compensation circuit compCKT. The signals related to the switching signal generation circuit swGenCKT, the port control module portCtrlMDL, the comparator circuit cfCKT, the drive circuit DRV, and the compensation circuit compCKT are then described sequentially.

[0140] The switching signal generation circuit swGenCKT is electrically connected to the external controller extCTL (e.g., a MIPI controller), the port control module portCtrlMDL, the drive circuit DRV, and the compensation circuit compCKT. After receiving the driver enable signal EN and the driver input signal inDAT from the external controller extCTL, the switching signal generation circuit swGenCKT generates the pull-up path positive phase switching signal SW_P, the pull-up path negative phase switching signal SWB_P, the pull-down path positive phase switching signal SW_N, and the pull-down path negative phase switching signal SWB_N according to the logic level of the driver enable signal EN and the driver input signal inDAT. Figure 3 Details related to the switching signal generation circuit swGenCKT will be explained.

[0141] The port control module portCtrlMDL is electrically connected to the external controller extCTL, the supply voltage terminal Vcc, the ground voltage terminal Gnd, and the switching signal generation circuit swGenCKT. The port control module portCtrlMDL is biased via the NMOS current mirror terminal ND. mrr_nm ND, the gate control terminal of the pull-up transistor PG18 The comparator circuit cfCKT is electrically connected; the port control module portCtrlMDL is connected to the pull-up capacitor terminal ND. Cup ND terminal of pull-down capacitor Cdn ND, the gate control terminal of the pull-down transistor NG18 and the pull-up transistor gate control terminal ND PG18 The power is connected to the drive circuit DRV; and the port control module portCtrlMDL is biased to the compensation circuit terminal ND. mrr_comp The circuit is electrically connected to the compensation circuit compCKT. The supply voltage terminal Vcc and the ground voltage terminal Gnd have constant voltage values. For example, the supply voltage terminal Vcc is 1.8V; the ground voltage terminal Gnd is 0V.

[0142] The port control module portCtrlMDL receives the pull-up path positive phase switching signal SW_P, the pull-up path negative phase switching signal SWB_P, the pull-down path positive phase switching signal SW_N, and the pull-down path negative phase switching signal SWB_N from the self-switching signal generation circuit swGenCKT, and generates signals related to the comparator circuit cfCKT, the driver circuit DRV, and the compensation circuit compCKT. Figure 4 This section will explain the internal components of the port control module portCtrlMDL and its associated signals.

[0143] The comparator circuit cfCKT is electrically connected to the supply voltage terminal Vcc, the ground voltage terminal Gnd, the port control module portCtrlMDL, the driver circuit DRV, and the compensation circuit compCKT. The comparator circuit cfCKT has an inverting comparator output terminal cfout-, a non-inverting comparator output terminal cfout+, an inverting comparator input terminal cfin-, and a non-inverting comparator input terminal cfin+. The inverting comparator output terminal cfout- is electrically connected to the pull-up transistor gate terminal ND of the driver circuit DRV. PG18 Furthermore, the output terminal cfout+ of the positive comparator is electrically connected to the compensation circuit enable terminal ND of the compensation circuit compCKT. comp_en The comparator circuit cfCKT receives a reference voltage Vref (e.g., 1.2V) with a constant value at the inverting comparator input cfin-; and receives the value of the drive circuit DRV at the driver output ND at the non-inverting comparator input cfin+. out The resulting driver output signal is outSIG. Figure 5 The internal components and connection method of the comparator circuit cfCKT will be explained.

[0144] The drive circuit DRV is electrically connected to the supply voltage terminal Vcc, the ground voltage terminal Gnd, and the switching signal generation circuit swGenCKT. The drive circuit DRV is connected via a pull-up capacitor terminal ND. Cup ND terminal of pull-down capacitor Cdn ND, the gate control terminal of the pull-up transistor PG18 With pull-down transistor gate control terminal ND NG18 The port is electrically connected to the port control module portCtrlMDL; and the driver output terminal ND is also connected to it. out Electrically connected to the compensation circuit compCKT. According to the concept of this disclosure, the internal components of the drive circuit DRV are connected to the driver enable signal EN transmitted by the external controller extCTL, and the inverting comparator output Cfout- of the comparator circuit cfCKT (equivalent to the pull-up transistor gate terminal ND). PG18 The voltage and port control module portCtrlMD sets the pull-down transistor gate control endpoint ND.NG18 The voltage, along with the pull-up path positive-phase switching signal SW_P, pull-up path negative-phase switching signal SWB_P, pull-down path positive-phase switching signal SW_N, and pull-down path negative-phase switching signal SWB_N transmitted by the switching signal generation circuit swGenCKT, changes the driver output signal outSIG. Furthermore, the driver circuit DRV transmits the driver output signal outSIG to the positive-phase comparator input cfin+ of the comparator circuit cfCKT. Figure 6 The internal components of the drive circuit DRV and its associated signals will be explained.

[0145] The compensation circuit compCKT is electrically connected to the supply voltage terminal Vcc and the ground voltage terminal Gnd. The compensation circuit enable terminal ND of compCKT is... comp_en The voltage is electrically connected to the non-inverting comparator output terminal cfout+ of the comparator circuit cfCKT. Therefore, the voltage at the non-inverting comparator output terminal cfout+ of the comparator circuit cfCKT is equal to the enable terminal ND of the compensation circuit. comp_en The voltage. Additionally, the compensation circuit compCKT and the self-switching signal generation circuit swGenCKT receive the pull-up path inverting switching signal SWB_P; and the driver output terminal ND of the self-driving circuit DRV. out Receive the driver output signal outSIG. For information on the internal components of the compensation circuit compCKT and its related signals, please refer to [link to relevant documentation]. Figure 7 Explanation.

[0146] The additional current enable circuit (addEnCKT) is electrically connected to the external controller (extCTL), the switching signal generation circuit (swGenCKT), and the compensation circuit (compCKT). One input of the addEnCKT receives the external enable signal IQ_extEN from the external controller (extCTL), and the other input receives the pull-up path positive phase switching signal SW_P from the switching signal generation circuit (swGenCKT). The additional current path enable signal IQ_EN output by the switching signal generation circuit (swGenCKT) is further transmitted to the compensation circuit (compCKT).

[0147] Please see Figure 3 This is a schematic diagram illustrating how the switching signal generation circuit swGenCKT of the present disclosure concept can be implemented using logic circuits. Figure 3 In the circuit, the switching signal generation circuit swGenCKT includes NAND gates NAND1 and NAND2, and NOT gates NOT1a, NOT1b, and NOT1c. In practical applications, the implementation of the switching signal generation circuit swGenCKT is not limited to... Figure 3 Examples.

[0148] One input of NAND gate NAND1 receives the driver enable signal EN, and the other input receives the driver input signal inDAT. The output of NAND gate NAND1 is defined as the pull-up path inverting switch signal SWB_P. After receiving the pull-up path inverting switch signal SWB_P at the input of NOT gate NOT1b, it generates the pull-up path non-inverting switch signal SW_P. After receiving the driver input signal inDAT at the input of NOT gate NOT1a, it generates the inverting driver input signal inDAT'. One input of NAND gate NAND2 receives the driver enable signal EN, and the other input receives the inverting driver input signal inDAT' output from NOT gate NOT1a. The output of NAND gate NAND2 is defined as the pull-down path inverting switch signal SWB_N. After receiving the pull-down path inverting switch signal SWB_N at the input of NOT gate NOT1c, it generates the pull-down path non-inverting switch signal SW_N.

[0149] exist Figure 3 The relationship between the logic levels of the driver enable signal EN and the driver input signal inDAT and the logic levels of the pull-up path positive phase switching signal SW_P, the pull-up path negative phase switching signal SWB_P, the pull-down path positive phase switching signal SW_N, and the pull-down path negative phase switching signal SWB_N is shown in Table 1.

[0150] Table 1

[0151]

[0152]

[0153] As can be seen from Table 1, the logic level of the input signal inDAT does not necessarily affect the logic levels of the pull-up path positive switching signal SW_P, the pull-up path negative switching signal SWB_P, the pull-down path positive switching signal SW_N, and the pull-down path negative switching signal SWB_N, depending on the logic level of the driver enable signal EN.

[0154] When the driver enable signal EN is at a low logic level L (EN = L), the logic level of the driver input signal inDAT does not affect the logic levels of the pull-up path positive phase switching signal SW_P, the pull-up path negative phase switching signal SWB_P, the pull-down path positive phase switching signal SW_N, and the pull-down path negative phase switching signal SWB_N. More specifically, when the driver enable signal EN is at a low logic level L (EN = L), regardless of how the logic level of the driver input signal inDAT changes, the pull-up path positive phase switching signal SW_P and the pull-down path positive phase switching signal SW_N remain at a low logic level L (SW_P = SW_N = L); and the pull-up path negative phase switching signal SWB_P and the pull-down path negative phase switching signal SWB_N remain at a high logic level H (SWB_P = SWB_N = L).

[0155] Conversely, when the driver enable signal EN is at a high logic level H (EN = H), the logic levels of the pull-up path in-phase switching signal SW_P and the pull-down path in-phase switching signal SWB_N remain equal to the logic level of the driver input signal inDAT (SW_P = SWB_N = inDAT). Furthermore, the logic levels of the pull-up path in-phase switching signal SWB_P and the pull-down path in-phase switching signal SW_N remain equal to the logic level of the inverting driver input signal inDAT' (SWB_P = SW_N = inDAT').

[0156] Please see Figure 4 The diagram illustrates the internal components and related signals of the port control module portCtrlMDL according to the present disclosure. The port control module portCtrlMDL includes: a reference current source curSRC, a path selection circuit pathSelCKT, a PMOS current mirror disable transistor cfdisPM, an NMOS current mirror disable transistor cfdisNM, a pull-up path disable transistor updisPM, a pull-up path bypass transistor upbpPM, a pull-down path disable transistor dndisNM, a pull-down path bypass transistor dnbpNM, and a compensation disable transistor comp_disNM.

[0157] The reference current source curSRC is electrically connected to the supply voltage terminal Vcc and the path selection circuit pathSelCKT. The reference current source curSRC is used to provide a stable Iref (e.g., Iref = 10μA).

[0158] The path selection circuit pathSelCKT is electrically connected to the switching signal generation circuit swGenCKT, the comparator circuit cfCKT, and the gate control terminal ND of the pull-down transistor. NG18The path selection circuit pathSelCKT and the self-switching signal generation circuit swGenCKT receive the pull-up path positive phase switching signal SW_P and the pull-down path positive phase switching signal SW_N.

[0159] The PMOS current mirror disable transistor cfdisPM is electrically connected to the supply voltage terminal Vcc, the switching signal generation circuit swGenCKT, and the PMOS current mirror bias terminal ND. mrr_pm Furthermore, the PMOS current mirror disabled transistor cfdisPM is biased by the PMOS current mirror terminal ND. mrr_pm Simultaneously, it is electrically connected to the compensation circuit compCKT and the PMOS current mirror pMRR. The PMOS current mirror disable transistor cfdisPM receives the pull-up path positive phase switching signal SW_P from the self-switching signal generation circuit swGenCKT. When the PMOS current mirror disable transistor cfdisPM is turned on according to the logic level of the pull-up path positive phase switching signal SW_P, the PMOS current mirror disable transistor cfdisPM will conduct the supply voltage Vcc to the PMOS current mirror bias terminal ND. mrr_pm That is, ND mrr_pm =Vcc. Conversely, when the PMOS current mirror disable transistor cfdisPM is turned off according to the logic level of the pull-up path positive switching signal SW_P, the PMOS current mirror disable transistor cfdisPM does not affect the PMOS current mirror bias terminal ND. mrr_pm The voltage.

[0160] The NMOS current mirror disable transistor cfdisNM is electrically connected to the ground voltage terminal Gnd, the switching signal generation circuit swGenCKT, and the NMOS current mirror bias terminal ND. mrr_nm Furthermore, the NMOS current mirror disabled transistor cfdisNM is biased by the NMOS current mirror terminal ND. mrr_nm The NMOS current mirror nMRR is electrically connected. The NMOS current mirror disable transistor cfdisNM's self-switching signal generation circuit swGenCKT receives the pull-up path inverted switching signal SWB_P. When the NMOS current mirror disable transistor cfdisNM is turned on according to the logic level of the pull-up path positive switching signal SW_P, the NMOS current mirror disable transistor cfdisNM will conduct the ground voltage Gnd to the NMOS current mirror bias terminal ND. mrr_nm That is, ND mrr_nm =Gnd. Conversely, when the NMOS current mirror disable transistor cfdisNM is turned off according to the logic level of the pull-up path positive switching signal SW_P, the NMOS current mirror disable transistor cfdisNM does not affect the NMOS current mirror bias terminal ND. mrr_nm The voltage.

[0161] The pull-up path disable transistor updisPM is electrically connected to the supply voltage terminal Vcc, the switching signal generation circuit swGenCKT, and the gate control terminal ND of the pull-up transistor. PG18 Furthermore, the pull-up path disable transistor updisPM is controlled via the pull-up transistor gate terminal ND. PG18 The circuit is electrically connected to the drive circuit DRV. The pull-up path disable transistor updisPM receives the pull-up path positive phase switching signal SW_P from the self-switching signal generation circuit swGenCKT. When the pull-up path disable transistor updisPM is turned on according to the logic level of the pull-up path positive phase switching signal SW_P, the pull-up path disable transistor updisPM will conduct the supply voltage Vcc to the gate control terminal ND of the pull-up transistor according to the pull-up path positive phase switching signal SW_P. PG18 That is, ND PG18 =Vcc. Conversely, when the pull-up path disable transistor updisPM is turned off according to the logic level of the pull-up path positive switching signal SW_P, the pull-up path disable transistor updisPM does not affect the gate control terminal ND of the pull-up transistor. PG18 The voltage.

[0162] The pull-up path bypass transistor upbpPM is electrically connected to the supply voltage terminal Vcc, the switching signal generation circuit swGenCKT, and the pull-up capacitor terminal ND. Cup Furthermore, the pull-up path bypass transistor upbpPM is connected to the pull-up capacitor terminal ND. Cup The circuit is electrically connected to the drive circuit DRV. The pull-up path bypass transistor upbpPM receives the pull-up path positive phase switching signal SW_P from the self-switching signal generation circuit swGenCKT. When the pull-up path bypass transistor upbpPM is turned on according to the logic level of the pull-up path positive phase switching signal SW_P, the pull-up path bypass transistor upbpPM will conduct the supply voltage Vcc to the pull-up capacitor terminal ND. Cup That is, ND Cup =Vcc. Conversely, when the pull-up path bypass transistor upbpPM is turned off according to the logic level of the pull-up path positive switching signal SW_P, the pull-up path bypass transistor upbpPM does not affect the pull-up capacitor terminal ND. Cup The voltage.

[0163] The pull-down path bypass transistor dnbpNM is electrically connected to the ground voltage terminal Gnd, the switching signal generation circuit swGenCKT, and the gate control terminal ND of the pull-down transistor. NG18 Furthermore, the pull-down path bypass transistor dnbpNM passes through the pull-down capacitor terminal ND. CdnThe circuit is electrically connected to the drive circuit DRV. The pull-down path bypass transistor dnbpNM receives the pull-down path inverting switching signal SWB_N from the self-switching signal generation circuit swGenCKT. When the pull-down path bypass transistor dnbpNM is turned on according to the logic level of the pull-down path inverting switching signal SWB_N, the pull-down path bypass transistor dnbpNM will conduct the ground voltage Gnd to the gate control terminal ND of the pull-down transistor. NG18 That is, ND NG18 =Gnd. When the pull-down path bypass transistor dnbpNM is turned off according to the logic level of the pull-down path inverting switching signal SWB_N, the pull-down path bypass transistor dnbpNM does not affect the gate control terminal ND of the pull-down transistor. NG18 The voltage.

[0164] The pull-down path disable transistor dndisNM is electrically connected to the ground voltage terminal Gnd, the switching signal generation circuit swGenCKT, and the pull-down capacitor terminal ND. Cdn Furthermore, the pull-down path disable transistor dndisNM is controlled by the pull-down transistor gate terminal ND. NG18 The circuit is electrically connected to the drive circuit DRV. The pull-down path disable transistor dndisNM receives the pull-down path inverting switching signal SWB_N from the self-switching signal generation circuit swGenCKT. When the pull-down path disable transistor dndisNM is turned on according to the logic level of the pull-down path inverting switching signal SWB_N, the pull-down path disable transistor dndisNM will conduct the ground voltage Gnd to the gate control terminal ND of the pull-down transistor. NG18 That is, ND NG18 =Gnd. When the pull-down path disable transistor dndisNM is turned off according to the logic level of the pull-down path inverting switching signal SWB_N, the pull-down path disable transistor dndisNM does not affect the gate control terminal ND of the pull-down transistor. NG18 The voltage.

[0165] The compensation-disabled transistor comp_disNM is electrically connected to the ground voltage terminal Gnd, the switching signal generation circuit swGenCKT, and the compensation circuit bias terminal ND. mrr_comp Furthermore, the compensation-disabled transistor comp_disNM is biased through the compensation circuit's ND terminal. mrr_comp The compensation circuit compCKT is electrically connected to the compensation disable transistor comp_disNM. The self-switching signal generation circuit swGenCKT receives the pull-up path inverting switching signal SWB_P. When the compensation disable transistor comp_disNM is turned on according to the logic level of the pull-up path inverting switching signal SWB_P, the compensation disable transistor comp_disNM will conduct the ground voltage Gnd to the bias terminal ND of the compensation circuit. mrr_comp That is, ND mrr_comp=Gnd. When the compensation disable transistor comp_disNM is turned off according to the logic level of the pull-up path inverting switching signal SWB_P, the compensation disable transistor comp_disNM does not affect the bias terminal ND of the compensation circuit. mrr_comp The voltage.

[0166] Please see Figure 5 This is a schematic diagram of the internal components and related signals of the comparator circuit cfCKT according to the present disclosure. According to the present disclosure, the comparator circuit cfCKT is a single-stage CMOS operational amplifier.

[0167] The comparator circuit cfCKT includes: a PMOS current mirror pMRR, an NMOS current mirror nMRR, and a differential input circuit diffInCKT. The PMOS current mirror pMRR is electrically connected to the PMOS current mirror disable transistor cfdisPM and the differential input circuit diffInCKT. The NMOS current mirror nMRR is electrically connected to the NMOS current mirror disable transistor cfdisNM, the differential input circuit diffInCKT, and the path selection circuit pathSelCKT.

[0168] The PMOS current mirror pMRR further includes: a PMOS current mirror inverting transistor pmrr_pPM and a PMOS current mirror inverting transistor pmrr_nPM. The differential input circuit diffInCKT further includes: a non-inverting differential input transistor diffpNM and an inverting differential input transistor diffnNM. The NMOS current mirror nMRR further includes: an NMOS current mirror inverting transistor nmrr_pNM and an NMOS current mirror inverting transistor nmrr_nNM. Wherein, the PMOS current mirror inverting transistor pmrr_pPM and the PMOS current mirror inverting transistor pmrr_nPM are PMOS transistors; the non-inverting differential input transistor diffpNM, the inverting differential input transistor diffnNM, the NMOS current mirror inverting transistor nmrr_pNM, and the NMOS current mirror inverting transistor nmrr_nNM are NMOS transistors.

[0169] In the PMOS current mirror pMRR, the source of the PMOS current mirror inverting transistor pmrr_pPM is electrically connected to the supply voltage terminal Vcc, and the gate is electrically connected to the PMOS current mirror bias terminal ND. mrr_pm The drain of the PMOS current mirror inverting transistor pmrr_nPM is connected to the supply voltage terminal Vcc and the gate is connected to the PMOS current mirror bias terminal ND. mrr_pmThe drain is connected to the output terminal cfout- of the inverting comparator. Therefore, the conduction state of both the PMOS current mirror inverting transistor pmrr_pPM and the PMOS current mirror inverting transistor pmrr_nPM depends on the bias terminal ND of the PMOS current mirror. mrr_pm The voltage. Furthermore, the gate and drain of the PMOS current mirror inverting transistor pmrr_pPM are connected to each other. Therefore, the output terminal cfout+ of the inverting comparator is equal to the bias terminal ND of the PMOS current mirror. mrr_pm The voltage.

[0170] The PMOS current mirror disable transistor cfdisPM is electrically connected to the switching signal generation circuit swGenCKT, the supply voltage terminal Vcc, and the PMOS current mirror bias terminal ND. mrr_pm Furthermore, the PMOS current mirror disable transistor cfdisPM receives the pull-up path positive phase switching signal SW_P from the self-switching signal generation circuit swGenCKT. The PMOS current mirror disable transistor cfdisPM is selectively turned on according to the logic level of the pull-up path positive phase switching signal SW_P.

[0171] When the PMOS current mirror disable transistor cfdisPM is turned on, the PMOS current mirror disable transistor cfdisPM conducts the supply voltage Vcc to the PMOS current mirror bias terminal ND. mrr_pm That is, ND mrr_pm =Vcc. Consequently, the PMOS current mirror inverting transistor pmrr_pPM and the PMOS current mirror inverting transistor pmrr_nPM will be turned off because their gates receive the supply voltage Vcc. Conversely, when the PMOS current mirror disable transistor cfdisPM is turned off, the PMOS current mirror disable transistor cfdisPM does not affect the PMOS current mirror bias terminal ND. mrr_pm The voltage does not affect the state of the PMOS current mirror inverting transistor pmrr_pPM and the PMOS current mirror inverting transistor pmrr_nPM.

[0172] In the differential input circuit diffInCKT, the drain of the non-phase differential input transistor diffpNM is connected to the PMOS current mirror bias terminal ND. mrr_pmThe gate of the inverting differential input transistor diffnNM is connected to the input terminal cfin+ of the inverting comparator. The drain of the inverting differential input transistor diffnNM is electrically connected to the output terminal cfout- of the inverting comparator, and its gate is connected to the input terminal cfin- of the inverting comparator. The source of the inverting differential input transistor diffpNM and the source of the inverting differential input transistor diffnNM are both electrically connected to the NMOS current mirror nMRR. Therefore, whether the inverting differential input transistor diffpNM is turned on depends on the voltage at the input terminal cfin- of the inverting comparator; and whether the inverting differential input transistor diffnNM is turned on depends on the voltage at the input terminal cfin- of the inverting comparator.

[0173] According to the concept of this disclosure, the positive comparator input terminal cfin+ of the comparator circuit cfCKT is electrically connected to the driver output terminal ND. out Furthermore, the inverting comparator input terminal cfin- of the comparator circuit cfCKT receives the reference voltage Vref. Therefore, the voltage at the non-inverting comparator input terminal cfin+ is equal to the voltage of the driver output signal outSIG. Thus, it can be concluded that whether the non-inverting differential input transistor diffpNM is turned on depends on the voltage of the driver output signal outSIG.

[0174] In the NMOS current mirror nMRR, the drain and gate of the NMOS current mirror inverting transistor nmrr_pNM are electrically connected to the NMOS current mirror bias terminal ND. mrr_nm The source of the NMOS current mirror inverting transistor nmrr_nNM is connected to the ground voltage terminal Gnd; the drain of the NMOS current mirror inverting transistor nmrr_nNM is connected to the differential terminal ND. diff The gate is electrically connected to the NMOS current mirror bias terminal ND. mrr_nm The source is electrically connected to the ground voltage terminal Gnd. Therefore, whether the NMOS current mirror inverting transistor nmrr_pNM and the NMOS current mirror inverting transistor nmrr_nNM are turned on or off depends on the NMOS current mirror bias terminal ND. mrr_nm The voltage. Also, the NMOS current mirror bias terminal ND. mrr_nm The voltage changes depending on the conduction state of the path selection circuit pathSelCKT and the NMOS current mirror disabling transistor cfdisNM.

[0175] The path selection circuit pathSelCKT is electrically connected to the NMOS current mirror bias terminal ND. mrr_nmThe path selection circuit pathSelCKT and the self-switching signal generation circuit swGenCKT receive mutually inverted pull-up path positive phase switching signals SW_P and SW_N. When the path selection circuit pathSelCKT is turned on, it conducts the supply voltage Vcc to the NMOS current mirror bias terminal ND. mrr_nm This causes the NMOS current mirror inverting transistor nmrr_pNM and the NMOS current mirror inverting transistor nmrr_nNM to conduct. Conversely, when the path selection circuit pathSelCKT is disconnected, it does not affect the NMOS current mirror bias terminal ND. mrr_nm The voltage.

[0176] The NMOS current mirror disabling transistor cfdisNM is electrically connected to the NMOS current mirror bias terminal ND. mrr_nm Furthermore, the NMOS current mirror disable transistor cfdisNM's self-switching signal generation circuit swGenCKT receives the pull-up path inverted switching signal SWB_P. The NMOS current mirror disable transistor cfdisNM selectively conducts according to the logic level of the pull-up path inverted switching signal SWB_P. When the NMOS current mirror disable transistor cfdisNM is turned on, the NMOS current mirror bias terminal ND... mrr_nm Equal to ground voltage Gnd(ND) mrr_nm =Gnd), which in turn disconnects the NMOS current mirror inverting transistor nmrr_pNM and the NMOS current mirror inverting transistor nmrr_nNM. Conversely, when the NMOS current mirror disabling transistor cfdisNM is disconnected, the NMOS current mirror disabling transistor cfdisNM does not affect the state of the NMOS current mirror inverting transistor nmrr_pNM and the NMOS current mirror inverting transistor nmrr_nNM.

[0177] Based on the PMOS current mirror pMRR architecture, when the PMOS current mirror inverting transistor pmrr_pPM and the PMOS current mirror inverting transistor pmrr_nPM are turned on, the comparator reference current I flowing through the PMOS current mirror inverting transistor pmrr_pPM... pPM It will be equal to the comparator mirror current I flowing through the PMOS current mirror inverting transistor pmrr_nPM. nPM (I pPM =I nPM Furthermore, the comparator reference current I flowing through the PMOS current mirror inverting transistor pmrr_pPM pPM and the comparator mirror current I flowing through the PMOS current mirror inverting transistor pmrr_nPM nPM The current is collected into a bias mirror current I. nNM (IpPM +I nPM =I nNM After that, it flows through the NMOS current mirror inverting transistor nmrr_nNM. Furthermore, based on the NMOS current mirror nMRR architecture, when both the NMOS current mirror inverting transistor nmrr_pNM and the NMOS current mirror non-inverting transistor nmrr_nNM are turned on, the bias reference current I flowing through the NMOS current mirror non-inverting transistor nmrr_pNM... pNM Equal to the bias mirror current I flowing through the NMOS current mirror inverting transistor nmrr_nNM nNM (I pNM =I nNM ).

[0178] Please see Figure 6 This is a schematic diagram of the internal components and related signals of the drive circuit DRV according to the present disclosure. The drive circuit DRV includes: a pull-up circuit upCKT, a pull-down circuit dnCKT, a drive circuit enable transmission gate enTG, and an output impedance Rout. One end of the pull-up circuit upCKT, the pull-down circuit dnCKT, and the drive circuit enable transmission gate enTG are all electrically connected to the capacitor feedback terminal ND. Cfb The other end of the drive circuit enables the transmission gate enTG and is electrically connected to the output impedance Rout.

[0179] The drive circuit enable transmission gate enTG receives the driver enable signal EN from the external controller extCTL. The drive circuit enable transmission gate enTG is selectively turned on depending on the driver enable signal EN. When the driver enable signal EN is at a high logic level H (EN = H), the drive circuit enable transmission gate enTG will be turned on, and the driver output signal outSIG will be determined by either the pull-up circuit upCKT or the pull-down circuit dnCKT. When the driver enable signal EN is at a low logic level L (EN = L), the drive circuit enable transmission gate enTG will be turned off, and the driver output signal outSIG will be in a floating state.

[0180] The pull-up circuit upCKT includes: a pull-up transistor upPM, a pull-up path transmission gate upTG, and a pull-up path capacitor Cup. The source of the pull-up transistor upPM is electrically connected to the supply voltage terminal Vcc, and the gate is electrically connected to the pull-up transistor gate control terminal ND. PG18 The drain is connected to the capacitor feedback terminal ND. Cfb The pull-up path transmission gate upTG is electrically connected to the gate control terminal ND of the pull-up transistor. PG18 , and the pull-up capacitor terminal ND Cup The pull-up path capacitor Cup is electrically connected to the pull-up capacitor terminal ND. Cup With capacitor feedback endpoint ND CfbBetween. The pull-up circuit upCKT self-switching signal generation circuit swGenCKT receives the pull-up path positive phase switching signal SW_P. Among them, the pull-up path transmission gate upTG, the pull-up path disable transistor updisPM, and the pull-up path bypass transistor upbpPM are all selectively turned on with the pull-up path positive phase switching signal SW_P.

[0181] The pull-down circuit dnCKT includes: a pull-down transistor dnNM, a pull-down path transmission gate dnTG, and a pull-down path capacitor Cdn. The source of the pull-down transistor dnNM is electrically connected to the ground voltage terminal Gnd, and the gate is electrically connected to the gate control terminal ND of the pull-down transistor. NG18 The drain is connected to the capacitor feedback terminal ND. Cfb The pull-down path transmission gate dnTG is electrically connected to the gate control terminal ND of the pull-down transistor. NG18 With pull-down capacitor terminal ND Cdn The pull-down path capacitor Cdn is electrically connected to the pull-down capacitor terminal ND. Cdn With capacitor feedback endpoint ND Cfb Between them. The pull-down circuit dnCKT and the self-switching signal generation circuit swGenCKT receive the pull-down path positive phase switching signal SW_N and the pull-down path negative phase switching signal SWB_N, which are opposite to each other. Among them, the pull-down path transmission gate dnTG is selectively turned on with the pull-down path positive phase switching signal SW_N; the pull-down path disable transistor dndisPM and the pull-down path bypass transistor dpbpPM are selectively turned on with the pull-down path negative phase switching signal SWB_N.

[0182] According to the concept of this disclosure, the capacitance value of the pull-up path capacitor Cup is greater than the capacitance value of the pull-down path capacitor Cdn. For example, the pull-up path capacitor Cup is 330fF; the pull-down path capacitor Cdn is 80fF. The capacitance values ​​here are for illustrative purposes only and are not limited to these values ​​in actual applications.

[0183] Please see Figure 7 This is a schematic diagram of the internal components and related signals of the compensation circuit compCKT according to the present disclosure. The compensation circuit compCKT includes: a compensation reference current path comp_refPATH, K compensation current paths comp_curPATH[1] to comp_curPATH[K], and K additional current paths add_curPATH[1] to add_curPATH[K]. Wherein, K is a positive integer.

[0184] The compensation reference current path comp_refPATH is electrically connected to the supply voltage endpoint Vcc and the compensation circuit bias endpoint ND. mrr_compGround voltage endpoint Gnd. Compensation current path comp_curPATH[1]~comp_curPATH[K] is electrically connected to the supply voltage endpoint Vcc and the compensation circuit bias endpoint ND. mrr_comp Ground voltage endpoint Gnd. Additional current path add_curPATH[1]~add_curPATH[K] is electrically connected to the supply voltage endpoint Vcc, the additional current enable circuit addEnCKT, and the ground voltage endpoint Gnd.

[0185] The comp_disNM transistor of the compensation circuit selectively switches the bias terminal ND of the compensation circuit according to the logic level of the pull-up path inverting switching signal SWB_P. mrr_comp Pull down to ground voltage Gnd. Furthermore, the compensation reference current path comp_refPATH, compensation current path comp_curPATH[1]~comp_curPATH[K], and additional current path add_curPATH[1]~add_curPATH[K] should correspond to the compensation circuit bias endpoint ND. mrr_comp The voltage is deactivated or a compensation reference current I is generated respectively. comp_ref Compensation current I comp_iq Additional current I add_iq Among them, the compensation current I comp_iq With additional current I add_iq This is the quiescent current used to pull down the driver output signal outSIG. Additionally, the additional current paths add_curPATH[1] to add_curPATH[K] are selected.

[0186] When the compensation circuit disable transistor comp_disNM is turned on, the compensation circuit disable transistor comp_disNM will turn on the ND bias terminal of the compensation circuit. mrr_comp Pull down to ground voltage Gnd. Along with ground, the compensation reference current path comp_refPATH will stop generating the compensation reference current I. comp_ref The compensation current paths comp_curPATH[1] to comp_curPATH[K] will stop generating compensation current I. comp_iq Furthermore, the additional current paths add_curPATH[1] to add_curPATH[K] will stop generating additional current I. add_iq .

[0187] Conversely, when the disable transistor comp_disNM of the compensation circuit is turned off, does the compensation reference current path comp_refPATH generate the compensation reference current I? comp_refIt depends on the output terminal cfout+ of the inverting comparator (equivalent to the enable terminal ND of the compensation circuit). comp_en The voltage of the compensation current path (comp_curPATH); whether the compensation current I is generated. comp_iq This depends on the logic level of the pull-up path positive phase switching signal SW_P; and whether the additional current path add_curPATH generates an additional current I. add_iq This depends on the logic level of the additional current path enable signal IQ_EN.

[0188] The additional current path enable signal IQ_EN is output by the additional current enable circuit addEnCKT. Therefore, the additional current path enable signal IQ_EN depends on the input signal of the additional current enable circuit addEnCKT, that is, the logic level of the pull-up path positive phase switching signal SW_P and the logic level of the additional current path external enable signal IQ_extEN. For simplicity, the following explanation will assume that the additional current path enable signal IQ_EN is at a low logic level (IQ_EN = L), thus disabling the additional current paths add_curPATH[1] to add_curPATH[K].

[0189] According to the concept of this disclosure, the additional current enable circuit addEnCKT can be an AND gate. If the external controller extCTL does not enable the additional current paths add_curPATH[1] to add_curPATH[K], the external controller extCTL can set the external enable signal IQ_extEN of the additional current path to a low logic level L (IQ_extEN = L). At this time, no matter how the pull-up path positive phase switching signal SW_P changes, the additional current enable signal IQ_EN output by the additional current enable circuit addEnCKT remains equal to the low logic level L (IQ_EN = L). That is, when IQ_extEN = L, IQ_EN = L. Furthermore, if the external controller extCTL wants to enable the additional current paths add_curPATH[1] to add_curPATH[K], the external controller extCTL can continuously set the external enable signal IQ_extEN of the additional current path to a high logic level H (IQ_extEN = H). At this time, the additional current path enable signal IQ_EN output by the additional current enable circuit addEnCKT changes according to the pull-up path positive phase switching signal SW_P. That is, when IQ_extEN = H, IQ_EN = SW_P.

[0190] In the foregoing explanation, respectively, the following methods have been used: Figure 3 Explain how to use logic circuits to construct a switching signal generation circuit swGenCKT; Figure 4Explain the internal components and related signals of the port control module portCtrlMDL; Figure 5 Explain the internal components and related signals of the comparator circuit cfCKT; Figure 6 Explain the internal components and related signals of the drive circuit DRV; and, Figure 7 The internal components and related signals of the compensation circuit compCKT are explained. Next, this disclosure will use... Figure 8 Compilation Figures 4-7 The mentioned circuit components. Subsequently, based on... Figure 8 The circuit diagram shown is as follows: Figures 9-14 Explain how the driver portDRV presents different circuit states in response to the combination of changes in the logic level of the driver enable signal EN and the driver input signal inDAT.

[0191] Please see Figure 8 This is a circuit diagram of the driver portDRV according to the present disclosure. Figure 3 , Figure 5 , Figure 6 The circuit components of the switching signal generation circuit swGenCKT, the comparator circuit cfCKT, and the drive circuit DRV have been described in detail in the previous sections. Here, we will further explain how to implement them using transistors. Figure 4 The port control module portCtrlMDL and Figure 7 The compensation circuit compCKT.

[0192] First, let's explain how to implement the port control module portCtrlMDL using transistors. For example... Figure 4 The port control module portCtrlMDL includes: a reference current source curSRC, a path selection circuit pathSelCKT, a PMOS current mirror disable transistor cfdisPM, an NMOS current mirror disable transistor cfdisNM, a pull-up path disable transistor updisPM, a pull-up path bypass transistor upbpPM, a pull-down path disable transistor dndisNM, a pull-down path bypass transistor dnbpNM, and a compensation disable transistor comp_disNM. The composition and connection of these components are described below. Please also refer to... Figure 4 , Figure 8 .

[0193] The reference current source curSRC is electrically connected to the supply voltage terminal Vcc and the path selection terminal ND. pathSEL Between. The reference current source curSRC is used to provide the reference current Iref (e.g., 10 μA).

[0194] The path selection circuit pathSelCKT includes: an up-path selection transmission gate upselTG and a down-path selection transmission gate dnselTG. The up-path selection transmission gate upselTG is controlled by the up-path positive phase switching signal SW_P; and the down-path selection transmission gate dnselTG is controlled by the down-path positive phase switching signal SW_N.

[0195] The pull-up path uses a transmission gate UPSELTG electrically connected to the path selection endpoint ND. pathSEL With NMOS current mirror bias terminal ND mrr_nm When the pull-up path positive phase switching signal SW_P is at a high logic level H (SW_P = H), the pull-up path selection transmission gate upselTG is turned on. Conversely, when the pull-up path positive phase switching signal SW_P is at a low logic level L (SW_P = L), the pull-up path selection transmission gate upselTG is turned off.

[0196] The pull-down path uses the transmission gate dnselTG, which is electrically connected to the path selection endpoint ND. pathSEL With pull-down transistor gate control terminal ND NG18 When the pull-down path positive phase switching signal SW_N is at a high logic level H (SW_N = H), the pull-down path selection transmission gate dnselTG is turned on. Conversely, when the pull-down path positive phase switching signal SW_N is at a low logic level L (SW_N = L), the pull-down path selection transmission gate dnselTG is turned off.

[0197] When the pull-up path positive phase switching signal SW_P and the pull-down path positive phase switching signal SW_N are kept in opposite phase, the pull-up path transmission gate upselTG and the pull-down path transmission gate dnselTG will be turned on alternately.

[0198] When the upselTG transmission gate is turned on and the downselTG transmission gate is turned off, the reference current Iref flows through the upselTG transmission gate, and the upselTG transmission gate conducts the supply voltage Vcc to the NMOS current mirror bias terminal ND. mrr_nm When the pull-up path transmission gate upselTG is off and the pull-down path transmission gate dnselTG is on, the reference current Iref flows through the pull-down path transmission gate dnselTG, and the pull-down path transmission gate dnselTG conducts the supply voltage Vcc to the gate control terminal ND of the pull-down transistor. NG18 .

[0199] Next, the connection method of the transistors in the port control module portCtrlMDL will be explained. For example... Figure 8As shown, the pull-up path disable transistor updisPM and the pull-up path bypass transistor upbpPM are PMOS transistors; and the pull-down path disable transistor dndisNM and the pull-down path bypass transistor dnbpNM are NMOS transistors. Furthermore, the operation of the pull-up path disable transistor updisPM and the pull-up path bypass transistor upbpPM, which are PMOS transistors, is related to the operation of the pull-up circuit upCKT; and the operation of the pull-down path disable transistor dndisNM, the pull-down path bypass transistor dnbpNM, and the pull-down circuit dnCKT is related to their operation. The connection methods and related operating methods of these circuit elements will be explained one by one below.

[0200] The source of the pull-up path disable transistor updisPM is connected to the supply voltage terminal Vcc, the gate receives the pull-up path positive phase switching signal SW_P, and the drain is connected to the output terminal cfout- of the inverting comparator. Therefore, whether the pull-up path disable transistor updisPM is turned on or off depends on the logic level of the pull-up path positive phase switching signal SW_P. When the pull-up path positive phase switching signal SW_P is at a high logic level H (SW_P = H), the pull-up path disable transistor updisPM is turned off without affecting the voltage at the output terminal cfout- of the inverting comparator (equivalent to the gate terminal ND of the pull-up transistor). PG18 The voltage of the pull-up path. Conversely, when the pull-up path positive switching signal SW_P is at a low logic level L (SW_P = L), the pull-up path disable transistor updisPM is turned on, and the voltage at the output terminal cfout- of the inverting comparator is turned on (equivalent to the voltage at the gate terminal ND of the pull-up transistor). PG18 Let the voltage be the supply voltage Vcc. That is, cfout = ND. PG18 =Vcc.

[0201] The source of the pull-up path bypass transistor upbpPM is connected to the supply voltage terminal Vcc, the gate receives the pull-up path positive phase switching signal SW_P, and the drain is connected to the pull-up capacitor terminal ND. Cup Therefore, whether the pull-up path bypass transistor upbpPM is turned on or off depends on the logic level of the pull-up path positive switching signal SW_P. When the pull-up path positive switching signal SW_P is at a high logic level H (SW_P = H), the pull-up path bypass transistor upbpPM is turned off without affecting the pull-up capacitor terminal ND. Cup The voltage. Conversely, when the pull-up path positive switching signal SW_P is at a low logic level L (SW_P = L), the pull-up path bypass transistor upbpPM is turned on, and the pull-up capacitor terminal ND is switched off. Cup The voltage is set to the supply voltage Vcc. That is, ND Cup =Vcc.

[0202] The drain of the pull-down path disabled transistor dndisNM is connected to the gate terminal ND of the pull-down transistor. NG18 The gate receives the pull-down path inverting switching signal SWB_N, and the source is electrically connected to the ground voltage terminal Gnd. Therefore, whether the pull-down path disable transistor dndisNM is turned on or off depends on the logic level of the pull-down path inverting switching signal SWB_N. When the pull-down path inverting switching signal SWB_N is at a low logic level L (SWB_N = L), the pull-down path disable transistor dndisNM is turned off without affecting the gate control terminal ND of the pull-down transistor. NG18 The voltage. Conversely, when the pull-down path inverting switching signal SWB_N is at a high logic level H (SWB_N = H), the pull-down path disabling transistor dndisNM is turned on, and the gate control terminal ND of the pull-down transistor is turned on. NG18 Let ND be the ground voltage Gnd. NG18 =Gnd.

[0203] The drain of the pull-down path bypass transistor dnbpNM is connected to the ND terminal of the pull-down capacitor. Cdn The gate receives the pull-down path inverting switching signal SWB_N, and the source is electrically connected to the ground voltage terminal Gnd. Therefore, whether the pull-down path bypass transistor dnbpNM is turned on or off depends on the logic level of the pull-down path inverting switching signal SWB_N. When the pull-down path inverting switching signal SWB_N is at a low logic level L (SWB_N = L), the pull-down path bypass transistor dnbpNM is turned off without affecting the pull-down capacitor terminal ND. Cdn The voltage. Conversely, when the pull-down path inverting switching signal SWB_N is at a high logic level H (SWB_N = H), the pull-down path disabling transistor dndisNM is turned on, and the pull-down capacitor terminal ND is switched on. Cdn The voltage is set to the ground voltage Gnd. That is, ND Cdn =Gnd.

[0204] The connection relationship between the pull-up path disable transistor updisPM, the pull-up path bypass transistor upbpPM, the pull-up path transmission gate upTG, and the pull-up transistor upPM is further explained. From Figure 8 It can be seen that whether the pull-up path disable transistor updisPM, the pull-up path bypass transistor upbpPM, and the pull-up path transmission gate upTG are turned on or off all depend on the logic level of the pull-up path positive phase switching signal SW_P.

[0205] Therefore, when the pull-up path positive switching signal SW_P is at a low logic level L (SW_P = L), the pull-up path disable transistor updisPM and the pull-up path bypass transistor upbpPM will be turned on, and the pull-up path transmission gate upTG will be turned off. At this time, the voltage at the output terminal cfout- of the inverting comparator (equivalent to the voltage at the gate control terminal ND of the pull-up transistor) will be... PG18 The voltage of the pull-up path is set to the supply voltage Vcc, thereby turning off the pull-up transistor upPM. On the other hand, when the pull-up path inverting switching signal SW_P is at a high logic level H (SW_P = H), the pull-up path disable transistor updisPM and the pull-up path bypass transistor upbpPM will be turned off, and the pull-up path transmission gate upTG will be turned on. At this time, the voltage at the output terminal cfout- of the inverting comparator (equivalent to the voltage at the gate control terminal ND of the pull-up transistor) is... PG18 The voltage depends on the driver output signal outSIG and the reference voltage Vref received by the comparator circuit cfCKT.

[0206] The relationship between the pull-down path disable transistor dndisNM, the pull-down path bypass transistor dnbpNM, the pull-down path transmission gate dnTG, and the pull-down transistor dnNM is further explained. From Figure 8 It can be seen that whether the pull-down path disable transistor dndisNM and the pull-down path bypass transistor dnbpNM are turned on or off depends on the logic level of the pull-down path inverting switching signal SWB_N. On the other hand, whether the pull-down path transmission gate dnTG is turned on or off depends on the logic level of the pull-down path non-inverting switching signal SW_N.

[0207] Because the logic levels of the pull-down path inverting switching signal SWB_N and the pull-down path non-inverting switching signal SW_N are opposite to each other, in Figure 8 In the pull-down path disable transistor dndisNM and pull-down path bypass transistor dnbpNM, when both are turned on at the high logic level H (SWB_N = H) of the pull-down path inverting switching signal SWB_N, the pull-down path transmission gate dnTG is turned off at the low logic level L (SW_N = L) of the pull-down path positive switching signal SW_N. At this time, the gate control terminal ND of the pull-down transistor... NG18 The voltage of the pull-down path disabled transistor dndisNM becomes equal to the ground voltage Gnd when the pull-down path disabled transistor dndisNM is turned on, thereby causing the pull-down transistor dnNM to turn off.

[0208] Alternatively, when the pull-down path disable transistor dndisNM and the pull-down path bypass transistor dnbpNM are turned off at the low logic level L (SWB_N = L) of the pull-down path inverting switching signal SWB_N, the pull-down path transmission gate dnTG will be turned on at the high logic level H (SW_N = H) of the pull-down path positive switching signal SW_N. In this case, whether the pull-down transistor dnNM is turned on depends on the gate control terminal ND of the pull-down transistor. NG18 The voltage. Also, because the pull-down path uses a transmission gate dnselTG that conducts with the high logic level H (SW_N = H) of the pull-down path positive phase switching signal SW_N, the gate control terminal ND of the pull-down transistor at this time... NG18 The voltage is equal to the path selection endpoint ND. pathSEL The voltage (equivalent to the supply voltage Vcc), i.e., ND NG18 =ND pathSEL =Vcc. Therefore, it can be concluded that the pull-down transistor dnNM will be turned on under this condition.

[0209] As can be seen from the foregoing description, under the premise that the driver enable signal EN is at a high logic level H (EN=H), the pull-up path disable transistor updisPM and the pull-up path bypass transistor upbpPM are in the same conduction state, and are opposite to the conduction state of the pull-up path transmission gate upTG; and the pull-down path disable transistor dndisNM and the pull-down path bypass transistor dnbpNM are in the same conduction state, and are opposite to the conduction state of the pull-down path transmission gate dnTG.

[0210] The disable transistor comp_disNM in the compensation circuit is an NMOS transistor. The drain of the disable transistor comp_disNM is connected to the control terminal NMcomp of the compensation circuit, the gate receives the pull-up path inverting switching signal SWB_P, and the source is connected to the ground voltage terminal Gnd.

[0211] Therefore, when the pull-up path inverting switching signal SWB_P is at a high logic level H (SWB_P = H), the compensation circuit's disable transistor comp_disNM will be turned on, and the compensation circuit's bias terminal ND will be turned on. mrr_comp It equals the ground voltage Gnd. Once the compensation circuit bias terminal ND... mrr_compWhen the voltage is equal to the ground voltage Gnd, the compensation reference current path comp_refPATH, the compensation current path comp_curPATH, and the additional current path add_curPATH are all disabled, and no current flows through them. Conversely, when the pull-up path inverting switch signal SWB_P is at a low logic level L (SWB_P = L), the compensation circuit disable transistor comp_disNM will be turned off. In this case, the compensation circuit disable transistor comp_disNM does not affect the operation of the compensation reference current path comp_refPATH, the compensation current path comp_curPATH, and the additional current path add_curPATH.

[0212] Next, we will explain how to implement the compensation circuit compCKT using transistors. Please also refer to... Figure 7 , Figure 8 To simplify the explanation, Figure 8 Assume that K = 1 in the compensation circuit compCKT. That is, the compensation circuit compCKT includes: the compensation reference current path comp_refPATH, the compensation current path comp_curPATH, and the additional current path add_curPATH.

[0213] The compensation reference current path `comp_refPATH` consists of two transistors: `comp_bspPM`, a compensation current source pull-up bias transistor, and `comp_bsnNM`, a compensation current source pull-down bias transistor. `comp_bspPM` is a PMOS transistor, and `comp_bsnNM` is an NMOS transistor. The source of `comp_bspPM` is electrically connected to the supply voltage terminal Vcc, and its gate is electrically connected to the PMOS current mirror bias terminal ND. mrr_pm And the drain is connected to the bias terminal ND of the compensation circuit. mrr_comp The drain and gate of the compensating current source pull-down bias transistor comp_bsnNM are both electrically connected to the bias terminal ND of the compensation circuit. mrr_comp The source is electrically connected to the ground voltage terminal Gnd. Therefore, when the disable transistor comp_disNM of the compensation circuit is off, the compensation reference current I... comp_ref Whether the current flows through the compensated reference current path comp_refPATH will depend on the voltage at the output terminal cfout+ of the positive comparator.

[0214] The current compensation path `comp_curPATH` includes: the current compensation path enable transistor `comp_iqenNM` and the current compensation path transistor `comp_iqNM`. Both the current compensation path enable transistor `comp_iqenNM` and the current compensation path transistor `comp_iqNM` are NMOS transistors. The drain of the current compensation path enable transistor `comp_iqenNM` is connected to the driver output terminal ND. out The gate receives the positive phase switching signal SW_P from the pull-up path, and the source is electrically connected to the drain of the current compensation path transistor comp_iqNM. The gate of the current compensation path transistor comp_iqNM is electrically connected to the bias terminal ND of the compensation circuit. mrr_comp The source is electrically connected to the ground voltage terminal Gnd. Therefore, when the disable transistor comp_disNM of the compensation circuit is off, the compensation current I... comp_iq Whether the current flows through the compensation current path comp_curPATH depends on the logic level of the pull-up path positive phase switching signal SW_P.

[0215] The additional current path add_curPATH includes: the additional current path enable transistor add_iqenNM and the additional current path transistor add_iqNM. Both the additional current path enable transistor add_iqenNM and the additional current path transistor add_iqNM are NMOS transistors.

[0216] The drain of the additional current path enabling transistor add_iqenNM is connected to the driver output terminal ND. out The gate receives the additional current path enable signal IQ_EN, and the source is electrically connected to the drain of the additional current path transistor add_iqNM. The gate of the additional current path transistor add_iqNM is electrically connected to the bias terminal ND of the compensation circuit. mrr_comp The source is electrically connected to the ground voltage terminal Gnd. Therefore, when the disable transistor comp_disNM of the compensation circuit is off, the additional current I... add_iq Whether the current flows through the additional current path add_curPATH will depend on the logic level of the additional current path enable signal IQ_EN.

[0217] Table 2 shows the current paths included in the compensation circuit compCKT, the transistors included in each current path, and the current when the current path is turned on.

[0218] Table 2

[0219]

[0220] Please see Figure 9This is a schematic diagram of the circuit state of the driver portDRV according to the present disclosure when the drive circuit enable signal EN is at a low logic level L (EN = L). As shown in Table 1, when the drive circuit enable signal EN is at a low logic level L (EN = L), both the pull-up path positive phase switching signal SW_P and the pull-down path positive phase switching signal SW_N remain at a low logic level L (SW_P = SW_N = L); and both the pull-up path negative phase switching signal SWB_P and the pull-down path negative phase switching signal SWB_N remain at a high logic level H (SWB_P = SWB_N = H). The following describes the circuit state of the driver portDRV according to the present disclosure. Figure 9 In this context, the circuit behavior related to pull-up paths, pull-down paths, and the compCKT compensation circuit is discussed.

[0221] In the pull-up path, because the pull-up path positive switching signal SW_P is at a low logic level L (SW_P = L), the pull-up path transmission gate upselTG is off, the PMOS current mirror disable transistor cfdisPM is on, the pull-up path disable transistor updisPM is on, the pull-up path bypass transistor upbpPM is on, and the pull-up path transmission gate upTG is on. Furthermore, because the pull-up path inverting switching signal SWB_P is at a high logic level H (SWB_P = H), the NMOS current mirror disable transistor cfdisNM is on.

[0222] In the comparator circuit cfCKT, because the NMOS current mirror disable transistor cfdisNM is turned on, the NMOS current mirror disable transistor cfdisNM conducts the ground voltage Gnd to the NMOS current mirror bias terminal ND. mrr_nm That is, ND mrr_nm =Gnd. Consequently, the NMOS current mirror inverting transistor nmrr_pNM and the NMOS current mirror inverting transistor nmrr_nNM in the NMOS current mirror will be disconnected.

[0223] Additionally, because the PMOS current mirror disable transistor cfdisPM is turned on, cfdisPM conducts the supply voltage Vcc to the PMOS current mirror bias terminal ND. mrr_pm That is, ND mrr_pm =cfout+=Vcc. Consequently, the PMOS current mirror inverting transistor pmrr_pPM and the PMOS current mirror inverting transistor pmrr_nPM will be disconnected.

[0224] In the pull-up circuit upCKT, the gate of the pull-up transistor upPM is controlled by the gate control terminal ND of the pull-up transistor. PG18 Voltage control. Due to the conduction of the pull-up path disable transistor updisPM, the gate terminal ND of the pull-up transistor is... PG18The voltage of ND is equal to the supply voltage Vcc. That is, ND PG18 =Vcc. Therefore, the pull-up transistor upPM is turned off. Therefore, in Figure 9 In this context, the pull-up transistor upPM does not affect the driver output signal outSIG.

[0225] In the pull-down path, because the pull-down path positive switching signal SW_N is at a low logic level L (SW_N = L), the pull-down path transmission gate dnselTG and the pull-down path transmission gate dnTG are disconnected; because the pull-down path negative switching signal SWB_N is at a high logic level H (SWB_N = H), the pull-down path bypass transistor dnbpNM and the pull-down path disable transistor dndisNM are turned on.

[0226] Because the pull-down path disable transistor dndisNM is turned on, it conducts the ground voltage Gnd to the gate terminal ND of the pull-down transistor. NG18 This causes the pull-down transistor's gate control terminal ND to... NG18 It equals the ground voltage Gnd. That is, ND NG18 =Gnd. Consequently, the pull-down transistor dnNM is connected to the gate control terminal ND of the pull-down transistor. NG18 It is disconnected because it equals the ground voltage Gnd. Therefore, in Figure 9 In this context, the pull-down transistor dnNM does not affect the driver output signal outSIG.

[0227] In the compensation circuit compCKT, because the pull-up path positive switching signal SW_P is at a low logic level L (SW_P = L), the compensation current path enabling transistor comp_iqenNM is turned off. Conversely, because the pull-up path inverting switching signal SWB_P is at a high logic level L (SWB_P = H), the compensation circuit disabling transistor comp_disNM is turned on. The turned-on disabling transistor comp_disNM conducts the ground voltage Gnd to the NMOS current mirror bias terminal ND. mrr_nm That is, ND mrr_nm =Gnd. Consequently, the pull-down bias transistor comp_bsnNM of the compensation current source and the transistor comp_iqNM of the compensation current path are also disconnected. Therefore, in Figure 9 In this circuit, the compCKT compensation circuit will not affect the driver output signal outSIG.

[0228] On the other hand, because the voltage at the positive comparator output terminal cfout+, which is electrically connected to the gate of the compensation current source pull-up bias transistor comp_bspPM, is equal to the supply voltage Vcc, the compensation current source pull-up bias transistor comp_bspPM is also in the off state.

[0229] exist Figure 9 In the middle, the drive circuit enable transmission gate enTG is opened because the drive circuit enable signal EN is at a low logic level (EN=L). Therefore, in Figure 9 In this configuration, the output signal outSIG is in a floating state. Consequently, the positive differential input transistor diffpNM and the negative differential input transistor diffnNM are also in an off state.

[0230] As mentioned earlier, when the drive circuit enable signal EN is at a low logic level L (EN = L), the output signal outSIG is in a floating state. Further details will follow... Figures 10-21 In the description of how the circuit state of the driver portDRV changes with the driver input signal inDAT, it is assumed that the driver circuit enable signal EN is a high logic level H (EN = H).

[0231] Please see Figure 10 This is a schematic diagram illustrating how the port control module portCtrlMDL, according to the present disclosure, controls the driver portDRV to change its circuit state in response to changes in the driver input signal inDAT when the driver enable signal EN is at a high logic level H (EN = H). With changes in the driver input signal inDAT, the driver portDRV may operate in the rising transient phase PH1, the high stable phase PH2, and the low stable phase PH4. The following describes how the driver portDRV changes its operating state according to the level of the driver input signal inDAT, and the logic levels of the pull-up path positive phase switching signal SW_P, the pull-up path negative phase switching signal SWB_P, the pull-down path positive phase switching signal SW_N, and the pull-down path negative phase switching signal SWB_N, as well as the voltage of the driver output signal outSIG, when the driver portDRV is in the rising transient phase PH1, the high stable phase PH2, and the low stable phase PH4.

[0232] When the driver input signal inDAT is in the transient process of transitioning from a low logic level L to a high logic level H, the driver portDRV is in the rising transient phase PH1. At this time, the pull-up path positive switching signal SW_P and the pull-down path negative switching signal SWB_N are at high logic level H (SW_P = SWB_N = H); and the pull-up path negative switching signal SWB_P and the pull-down path positive switching signal SW_N are at low logic level L (SWB_P = SW_N = L). On the other hand, the voltage of the driver output signal outSIG gradually rises from the ground voltage Gnd to the reference voltage Vref (outSIG = Gnd → Vref). Figure 11 The driver portDRV is in the rising transient phase PH1.

[0233] When the driver input signal inDAT is in a stable state at high logic level H, the driver portDRV is in a high stable state phase PH2. At this time, the pull-up path positive phase switching signal SW_P and the pull-down path negative phase switching signal SWB_N are at high logic level H (SW_P = SWB_N = H); and the pull-up path negative phase switching signal SWB_P and the pull-down path positive phase switching signal SW_N are at low logic level L (SWB_P = SW_N = L). On the other hand, the voltage of the driver output signal outSIG remains at the reference voltage Vref. That is, outSIG = Vref. Figure 12 The driver portDRV is PH2 in a high steady-state phase.

[0234] When the driver input signal inDAT is in the transient process of transitioning from high logic level H to low logic level L, the driver portDRV is in the falling transient phase PH3. At this time, the pull-up path positive phase switching signal SW_P and the pull-down path negative phase switching signal SWB_N are at low logic level L (SW_P = SWB_N = L); and the pull-up path negative phase switching signal SWB_P and the pull-down path positive phase switching signal SW_N are at high logic level H (SWB_P = SW_N = H). On the other hand, the voltage of the driver output signal outSIG gradually decreases from the reference voltage Vref to the ground voltage Gnd (outSIG = Vref → Gnd). Figure 13 The driver portDRV is PH3 in the descent transient phase.

[0235] When the driver input signal inDAT is in a stable state at low logic level L, the driver portDRV is in a low stable state phase PH4. At this time, the pull-up path positive phase switching signal SW_P and the pull-down path negative phase switching signal SWB_N are at low logic level L (SW_P = SWB_N = L); and the pull-up path negative phase switching signal SWB_P and the pull-down path positive phase switching signal SW_N are at high logic level H (SWB_P = SW_N = H). On the other hand, the voltage of the driver output signal outSIG remains at the ground voltage Gnd (outSIG = Gnd). Figure 14 The driver portDRV is PH4 in a low steady-state phase.

[0236] according to Figure 10 Of the four stages listed, the drive circuit DRV may exhibit two types of situations. Please also refer to... Figure 6 , Figure 10 .

[0237] The first case is when the pull-up path positive switching signal SW_P is at a high logic level H (SW_P = H); the pull-down path positive switching signal SW_N is at a low logic level L (SW_N = L); and the pull-down path negative switching signal SWB_N is at a high logic level H (SWB_N = H). In other words, the first case corresponds to the rising transient phase PH1 and the high steady-state phase PH2. The states of the components of the pull-up circuit upCKT and the pull-down circuit dnCKT in the first case are described below.

[0238] In the pull-up circuit upCKT in the first case, the pull-up path transmission gate upTG will be turned on, and the pull-up path disable transistor updisPM and the pull-up path bypass transistor upbpPM will be turned off. Therefore, the pull-up path disable transistor updisPM will not affect the gate control terminal ND of the pull-up transistor. PG18 The voltage, the bypass transistor upbpPM in the pull-up path will not affect the ND terminal of the pull-up capacitor. Cup The voltage. At the same time, the pull-up path transmission gate upTG will pull up the gate control terminal ND of the pull-up transistor. PG18 The voltage is conducted to the ND terminal of the pull-up capacitor. Cup On the other hand, in the pull-down circuit dnCKT in the first case, the pull-down path transmission gate dnTG will be open, and the pull-down path disable transistor dndisPM and the pull-down path bypass transistor dnbpPM will be turned on. The turned-on pull-down path disable transistor dndisPM will conduct the ground voltage Gnd to the gate control terminal ND of the pull-down transistor. NG18 Furthermore, the pull-down path bypass transistor dnbpPM in the on state will conduct the ground voltage Gnd to the pull-down capacitor terminal ND. Cdn .

[0239] The second case is when the pull-up path positive switching signal SW_P is at a low logic level L (SW_P = L); the pull-down path positive switching signal SW_N is at a high logic level H (SW_N = H); and the pull-down path inverting switching signal SWB_N is at a low logic level L (SW_B = L). In other words, the second case corresponds to the falling transient phase PH3 and the low steady-state phase PH4. The states of the components of the pull-up circuit upCKT and the pull-down circuit dnCKT in the second case are described below.

[0240] In the second type of pull-up circuit upCKT, the pull-up path transmission gate upTG will be disconnected, and the pull-up path disable transistor updisPM and the pull-up path bypass transistor upbpPM will be turned on. At this time, the turned-on pull-up path disable transistor updisPM will conduct the supply voltage Vcc to the gate control terminal ND of the pull-up transistor. PG18Furthermore, the conducting pull-up bypass transistor upbpPM will conduct the supply voltage Vcc to the pull-up capacitor terminal ND. Cup On the other hand, in the pull-down circuit dnCKT in the second case, the pull-down path transmission gate dnTG will be turned on, and the pull-down path disable transistor dndisPM and the pull-down path bypass transistor dnbpPM will be turned off. In this case, the pull-down path disable transistor updisPM will not affect the pull-down transistor gate control terminal ND. NG18 The voltage, the bypass transistor dnbpPM in the pull-down path will not affect the ND terminal of the pull-down capacitor. Cdn The voltage. At the same time, the pull-down path transmission gate dnTG will pull the pull-down transistor gate control terminal ND. NG18 The voltage is conducted to the ND terminal of the pull-down capacitor. Cdn .

[0241] Next, this article will focus on Figures 11-14 Describe the states of the circuit elements in the driver portDRV during the rising transient phase PH1, the high steady-state phase PH2, the falling transient phase PH3, and the low steady-state phase PH4. Figures 11-14 In this text, a cross symbol represents a transistor and / or transmission gate in the off state; and a dashed arrow represents the signal conduction direction. Furthermore, this text defines a pull-up path as a combination of a transmission gate upselTG, components within the comparator circuit cfCKT, components within the pull-up circuit upCKT, a pull-up path disable transistor updisPM, and a pull-up path bypass transistor upbpPM; and defines a pull-down path as a combination of a transmission gate dnselTG, components within the pull-down circuit dnCKT, a pull-down path disable transistor dndisNM, and a pull-down path bypass transistor dnbpNM.

[0242] Please see Figure 11 This is a schematic diagram of the circuit state of the driver portDRV according to the present disclosure during the rising transient phase PH1. During the rising transient phase PH1, the driver circuit enable signal EN is at a high logic level H (EN = H); and the driver input signal inDAT changes from a low logic level L to a high logic level L (inDAT = L → H). Figure 15 This will explain the driver portDRV in Figure 11 Component and signal states (during the rising transient phase PH1).

[0243] Please see Figure 12 This is a schematic diagram of the circuit state of the driver portDRV according to the present disclosure during the high steady-state phase PH2. Please also refer to... Figure 10 , Figure 12During the high steady-state phase PH2, the drive circuit enable signal EN is at a high logic level H (EN = H); and the driver input signal inDAT remains equal to the high logic level H (inDAT = H). Figure 15 This will explain the driver portDRV in Figure 12 Component and signal states (during the high steady-state phase PH2).

[0244] Please see Figure 13 This is a schematic diagram of the circuit state of the driver portDRV according to the present disclosure during the descent transient phase PH3. Please also refer to... Figure 10 , Figure 13 During the descent transient phase PH3, the drive circuit enable signal EN is at a high logic level H (EN = H); and the driver input signal inDAT changes from a high logic level H to a low logic level L (inDAT = H → L). Figure 15 This will explain the driver portDRV in Figure 13 Component and signal states (during the transient phase PH3).

[0245] Please see Figure 14 This is a schematic diagram of the circuit state of the driver portDRV according to the present disclosure during the low steady-state phase PH4. Please also refer to... Figure 10 , Figure 14 During the low steady-state phase PH4, the drive circuit enable signal EN is at a high logic level H (EN = H); and the driver input signal inDAT remains equal to a low logic level L (inDAT = L). Figure 15 This will explain the driver portDRV in Figure 14 Component and signal states (during the low steady-state phase PH4).

[0246] Next, with Figure 15 , Figure 16 The waveforms illustrate the operation of the portDRV driver at each stage. To simplify the diagram, Figure 15 , Figure 16 The waveform does not list the supply voltage terminal Vcc with a constant voltage value, the ground voltage terminal Gnd, and the inverting comparator input cfin- (received reference voltage Vref).

[0247] Please see Figure 15 The waveform diagram shows how the internal endpoints of the driver portDRV according to the present disclosure change with the driver input signal inDAT when the driver circuit enable signal EN is at a high logic level H (EN = H) and the external enable signal IQ_extEN of the additional current path is set to a low logic level L (IQ_extEN = L) and the additional current path add_curPATH is disabled. Figure 15 The waveforms illustrate the driver input signals inDAT, outSIG, pull-up path inverting signal SW_P, pull-down path inverting signal SWB_N, pull-up path inverting signal SWB_P, pull-down path inverting signal SW_N, inverting comparator output cfout+, and pull-up transistor gate control terminal ND, all related to the driver portDRV. PG18 ND, the gate control terminal of the pull-down transistor NG18 , pull-up capacitor terminal ND Cup ND terminal of pull-down capacitor Cdn Compensation reference current I comp_ref Compensation current I comp_iq ND, the bias terminal of the compensation circuit mrr_comp The process changes depending on the different stages of the rising transient phase PH1, the high steady-state phase PH2, the falling transient phase PH3, and the low steady-state phase PH4.

[0248] Table 3 Summary Figure 15 The waveform changes are shown. The voltage and current values ​​listed here are approximate values ​​for reference only. Furthermore, the voltage and current values ​​used in actual applications are not limited to these.

[0249] Table 3

[0250]

[0251]

[0252]

[0253] exist Figure 15 In the diagram, the time periods t2~t3 and t6~t7 correspond to the rising transient phase PH1 (for information on the state of the driver portDRV during the rising transient phase PH1, please refer to...). Figure 11 The time points t3~t4 and t7~t8 correspond to the high steady-state phase PH2 (for information on the state of the driver portDRV during the high steady-state phase PH2, please refer to...). Figure 12 The time points t4~t5 and t9~t10 correspond to the descent transient phase PH3 (for information on the state of the driver portDRV during the descent transient phase PH3, please refer to...). Figure 13 Furthermore, the time periods t1~t2, t5~t6, and t9~t10 correspond to the low steady-state phase PH4 (for information on the state of the driver portDRV during the low steady-state phase PH4, please refer to...). Figure 14 Since the state of the driver portDRV cycles through the rising transient phase PH1, the high steady-state phase PH2, the falling transient phase PH3, and the low steady-state phase PH4, the following description of the waveform is based on time points t2 to t6.

[0254] Please also see Figure 11 , Figure 12 , Figure 15 During the rising transient phase PH1 between time points t2 and t3 (see...),... Figure 11 The driver input signal inDAT transitions from a low logic level L to a high logic level H (inDAT = L → H); during the high steady-state phase PH2 from time t3 to t4, the driver input signal inDAT remains equal to the high logic level H (inDAT = H) (see...). Figure 12 ).

[0255] During the rising transient phase PH1 and the high steady-state phase PH2, the switching signal generation circuit swGenCKT generates a high logic level H pull-up path positive phase switching signal SW_P and a pull-down path negative phase switching signal SWB_N (SW_P = SWB_N = H), and a low logic level L pull-up path negative phase switching signal SWB_P and a pull-down path positive phase switching signal SW_N (SWB_P = SW_N = L).

[0256] Please also see Figure 11 , Figure 15 During the period from time t2 to t3, in the pull-up path, because the pull-up path positive phase switching signal SW_P is at a high logic level H (SW_P = H), the pull-up path transmission gate upselTG is turned on, the PMOS current mirror disable transistor cfdisPM is turned off, the pull-up path disable transistor updisPM is turned off, the pull-up path bypass transistor upbpPM is turned off, and the pull-up path transmission gate upTG is turned on.

[0257] During the period from time t2 to t3, because the pull-up path inverting switching signal SWB_P is at a low logic level L (SWB_P = L), the NMOS current mirror disable transistor cfdisNM is turned off. Therefore, during the rising transient phase, PH1 of the NMOS current mirror disable transistor cfdisNM does not affect the NMOS current mirror bias terminal ND. mrr_nm The voltage. At this time, the pull-up path selected by the conduction gate upselTG conducts the supply voltage Vcc to the NMOS current mirror bias terminal ND. mrr_nm That is, ND mrr_nm =Vcc.

[0258] Because the gate is electrically connected to the NMOS current mirror bias terminal ND mrr_nm Because of this, the NMOS current mirror inverting transistor nmrr_pNM and the NMOS current mirror inverting transistor nmrr_nNM in the NMOS current mirror nMRR will change with the NMOS current mirror bias terminal ND. mrr_nm Set to supply voltage Vcc (ND)mrr_nm =Vcc) and thus conduct. Furthermore, the reference current Iref (e.g., 10μA) provided by the reference current source curSRC will become the bias reference current I flowing through the NMOS current mirror inverting transistor nmrr_pNM to the ground voltage Gnd. pNM Based on the current mirror architecture, the NMOS current mirror inverting transistor nmrr_nNM also has a bias mirror current I. nNM (For example: 40μA) flows through.

[0259] On the other hand, because the PMOS current mirror disable transistor cfdisPM is turned off with the positive phase switching signal SW_P (SW_P = H) of the pull-up path, the PMOS current mirror disable transistor cfdisPM does not affect the PMOS current mirror bias terminal ND. mrr_pm (Also, the voltage at the output terminal cfout+ of the non-inverting comparator). At this time, whether the PMOS current mirror non-inverting transistor pmrr_pPM and the PMOS current mirror inverting transistor pmrr_nPM in the PMOS current mirror pMRR are turned on or off depends on the bias terminal ND of the PMOS current mirror. mrr_pm (Also, the voltage at the output terminal cfout+ of the positive comparator).

[0260] In the comparator circuit cfCKT, the gate of the inverting differential input transistor diffnNM (equivalent to the inverting comparator input terminal cfin-) is turned on due to receiving the reference voltage Vref, which in turn causes the output terminal cfout- of the inverting comparator (also the pull-up transistor gate terminal ND) to be turned on. PG18 The voltage is gradually reduced from the supply voltage Vcc to approximately 1.3V (cfout - ND). PG18 =Vcc↓).

[0261] Consequently, during time points t2 to t3, the PMOS current mirror bias terminal ND, which is symmetrical to the output terminal cfout of the inverting comparator, is... mrr_pm The voltage at the output terminal cfout+ of the non-inverting comparator (i.e., the voltage at cfout+) gradually decreases from the supply voltage Vcc to approximately 1.4V (cfout+ = ND) as the non-inverting differential input transistor diffpNM and the NMOS current mirror inverting transistor nmrr_nNM are turned on. mrr_pm =ND comp_en =Vcc→1.4V).

[0262] As the voltage at the output terminal cfout+ of the non-inverting comparator decreases, the PMOS current mirror non-inverting transistor pmrr_pPM gradually turns on, generating a current (e.g., 20 μA) flowing through the PMOS current mirror non-inverting transistor pmrr_pPM and the non-inverting differential input transistor diffpNM. This current is due to the bias terminal ND of the PMOS current mirror. mrr_pm Because it is electrically connected to the output terminal cfout+ of the inverting comparator, the PMOS current mirror inverting transistor pmrr_nPM gradually turns on. The PMOS current mirror inverting transistor pmrr_nPM, now in the on state, will then pull up the output terminal cfout- of the inverting comparator (which is also the gate terminal ND of the transistor). PG18 The voltage is slightly increased from 1.3V to 1.5V. Subsequently, the PMOS current mirror inverting transistor pmrr_nPM, the inverting differential input transistor diffnNM, and the NMOS current mirror inverting transistor nmrr_nNM, in their on-state, will cause the pull-up transistor gate terminal ND to... PG18 It remains roughly at 1.5V.

[0263] Simultaneously, a current (e.g., 20 μA) is generated flowing through the PMOS current mirror inverting transistor pmrr_nPM and the non-phase differential input transistor diffpNM. Furthermore, the current flowing through the NMOS current mirror inverting transistor nmrr_nNM is equivalent to the sum of the currents flowing through the inverting differential input transistor diffnNM and the non-phase differential input transistor diffpNM (e.g., 40 μA).

[0264] In the pull-up circuit upCKT, the gate of the pull-up transistor upPM is controlled by the gate control terminal ND of the pull-up transistor. PG18 Voltage control. As mentioned earlier, the pull-up transistor gate terminal ND... PG18 The voltage is equal to the voltage at the output terminal cfout- of the inverting comparator (ND). PG18 =cfout-). Therefore, the pull-up transistor gate endpoint ND PG18 The voltage first gradually decreases from the supply voltage Vcc to 1.3V, then slightly increases to 1.5V. That is, ND... PG18 =cfout-=1.8V→1.3V→1.5V.

[0265] With the pull-up transistor gate control terminal ND PG18 The voltage change causes the pull-up transistor upPM to switch from an off state to a conducting state, which in turn pulls up the voltage of the driver output signal outSIG during the period t2 to t3, thus gradually increasing it from the ground voltage Gnd. Furthermore, because the compensation current path comp_curPATH generates a compensation current I... comp_iqAs a result, the voltage of the driver output signal outSIG is simultaneously pulled down by the compensation current path comp_curPATH. Therefore, at time t3, the driver output signal outSIG will not rise to the supply voltage Vcc, but will rise to the reference voltage Vref. That is, outSIG = Gnd → Vref.

[0266] Because the pull-up path transmission gate upTG is turned on by the pull-up path positive phase switching signal SW_P (SW_P = H) of the high logic level H, during the period t2 to t3, the pull-up capacitor terminal ND Cup The voltage at the output terminal cfout- of the inverting comparator is equal to the voltage at that terminal. Therefore, the voltage at the pull-up capacitor terminal ND... Cup The voltage also drops from 1.8V to 1.3V during the time interval t2 to t3, and then rises from 1.3V to 1.5V. That is, ND... Cup = 1.8V→1.3V→1.5V. During this period, the pull-up path capacitor Cup also flows through the PMOS current mirror inverting transistor pmrr_nPM and the gate terminal ND of the pull-up transistor. PG18 The pull-up path transmission gate upTG and the pull-up capacitor terminal ND Cup And then it was charged.

[0267] In the pull-down path, because the pull-down path positive switching signal SW_N is at a low logic level L (SW_N = L), the pull-down path transmission gate dnselTG and the pull-down path transmission gate dnTG are disconnected; because the pull-down path negative switching signal SWB_N is at a high logic level H (SWB_N = H), the pull-down path bypass transistor dnbpNM and the pull-down path disable transistor dndisNM are turned on.

[0268] Because the pull-down path disable transistor dndisNM is turned on, it conducts the ground voltage Gnd to the gate terminal ND of the pull-down transistor. NG18 This causes the pull-down transistor's gate control terminal ND to... NG18 The voltage ND is equal to the ground voltage Gnd. That is, ND NG18 =Gnd. Consequently, the pull-down transistor dnNM is connected to the gate control terminal ND of the pull-down transistor. NG18 The voltage is equal to the ground voltage Gnd(ND) NG18 =Gnd) and disconnected. Therefore, in Figure 11 In this context, the pull-down transistor dnNM does not affect the driver output signal outSIG. Furthermore, because the pull-down path bypass transistor dnbpNM is turned on, the pull-down capacitor terminal ND... Cdn As the pull-down path bypass transistor dnbpNM is turned on, it is pulled down to the ground voltage Gnd.

[0269] exist Figure 11 In the compensation circuit compCKT, because the pull-up path positive switching signal SW_P is at a high logic level H (SW_P = H), the compensation current path enabling transistor comp_iqenNM is turned on. Conversely, because the pull-up path inverting switching signal SWB_P is at a low logic level L (SWB_P = L), the compensation circuit disabling transistor comp_disNM is turned off. The off state of the compensation circuit disabling transistor comp_disNM does not affect the NMOS current mirror bias terminal ND. mrr_nm The voltage.

[0270] On the other hand, because the gate of the compensation current source pull-up bias transistor comp_bspPM is electrically connected to the output terminal cfout+ of the positive comparator, whether the compensation current source pull-up bias transistor comp_bspPM is turned on depends on the voltage at the output terminal cfout+ of the positive comparator (cfout+ = ND). mrr_pm =ND comp_en ).

[0271] Because the output terminal cfout+ of the inverting comparator gradually decreases from the supply voltage Vcc to 1.4V (cfout+ = ND), mrr_pm =ND comp_en Because of the voltage Vcc → 1.4V, the compensation current source pull-up bias transistor comp_bspPM will gradually change from the off state to the on state. Furthermore, the on-state compensation current source pull-up bias transistor comp_bspPM will conduct the supply voltage Vcc to the bias terminal ND of the compensation circuit. mrr_comp The bias terminal ND of the compensation circuit mrr_comp The voltage gradually increases.

[0272] With the bias terminal ND of the compensation circuit mrr_comp As the voltage rises, the compensation current source pull-down bias transistor comp_bsnNM and the compensation current path transistor comp_iqNM also turn on. As the compensation current source pull-up bias transistor comp_bspPM gradually turns on, a compensation reference current I will be generated in the compensation reference current path comp_refPATH, flowing through the compensation current source pull-up bias transistor comp_bspPM and the compensation current source pull-down bias transistor comp_bsnNM. comp_ref (For example, 10μA). Because both the compensation current source pull-up bias transistor comp_bspPM and the compensation current source pull-down bias transistor comp_bsnNM are turned on, during time points t2 to t3, the bias terminal ND of the compensation circuit... mrr_comp The voltage will rise from the ground voltage Gnd to approximately 0.5V.

[0273] Meanwhile, the compensation current path transistor comp_iqNM, which forms a current mirror with the compensation current source pull-down bias transistor comp_bsnNM, also follows the bias terminal ND of the compensation circuit connected to its gate. mrr_comp Equal to the supply voltage Vcc(ND) mrr_comp =Vcc) is the reason for conduction. Also, because the compensation current path enabling transistor comp_iqenNM is turned on by the high logic level pull-up path positive phase switching signal SW_P (SW_P=H), a compensation current I is generated in the compensation current path comp_curPATH, flowing through the compensation current path enabling transistor comp_iqenNM and the compensation current path transistor comp_iqNM. comp_iq (e.g., 20μA). Because the drain of the compensation current path enabling transistor comp_iqenNM is connected to the driver output terminal ND... out Because of this, the compensation current path enabling transistor comp_iqenNM conducts the ground voltage Gnd to the driver output terminal ND. out This causes the voltage of the driver output signal outSIG to vary with the compensation current I. comp_iq The dropdown was triggered by the generation of [something].

[0274] As mentioned earlier, in Figure 11 In this configuration, the driver output signal outSIG is simultaneously pulled up by the conduction of the pull-up transistor upPM and pulled down by the conduction of the compensation current path enable transistor comp_iqenNM and the compensation current path transistor comp_iqNM. Consequently, the driver output signal outSIG will be between the ground voltage Gnd and the supply voltage Vcc. At this time, based on the symmetrical structure of the PMOS current mirror pMRR, the voltage of the driver output signal outSIG is equal to the reference voltage Vref.

[0275] Following on, Figure 11 In this process, the driver output signal outSIG rises from the ground voltage Gnd to the reference voltage Vref. That is, outSIG = Gnd → Vref = 0V → 1.2V. Additionally, in... Figure 11 In the middle, the drive circuit enable transmission gate enTG is turned on by the drive circuit enable signal EN (EN = H) at the high logic level H. Therefore, the capacitor feedback terminal ND Cfb The voltage changes with the output signal outSIG. That is, ND Cfb =0V→1.2V.

[0276] When the driver portDRV is in the rising transient phase PH1, in addition to using the pull-up transistor upPM to pull up the voltage of the output signal outSIG, the pull-up path capacitor Cup is also charged simultaneously through the pull-up path transmission gate upTG. Simultaneously, the pull-up transistor gate control terminal ND... PG18 It will also be affected by this voltage conduction path. Accordingly, the setting of the pull-up path capacitor Cup can compensate for the AC response of the driver output signal outSIG during time points t2 to t3.

[0277] As mentioned above, the pull-up path capacitor (Cup) exhibits the Miller effect, affecting the slew rate of the driver's output signal (outSIG). A larger pull-up path capacitor (Cup) results in a lower slew rate of the driver's output signal (outSIG), meaning a smoother voltage rise. Conversely, a smaller pull-up path capacitor (Cup) results in a higher slew rate of the driver's output signal (outSIG), meaning a sharper voltage rise during the rising transient phase (PH1). In practical applications, the selected value of the pull-up path capacitor (Cup) depends on the specifications required by the driver's portDRV.

[0278] During the period from time t3 to t4 (high steady-state stage PH2, see...), see... Figure 12 The driver input signal inDAT remains equal to the high logic level H (inDAT = H). Therefore, in Figure 12 In the process, the on / off state of the transistors within the driver portDRV remains consistent with... Figure 11 The state of the latter part is the same. Furthermore, the driver output signal outSIG, the pull-up path positive phase switching signal SW_P, the pull-down path negative phase switching signal SWB_N, the pull-up path negative phase switching signal SWB_P, the pull-down path positive phase switching signal SW_N, the positive phase comparator output cfout+, and the pull-up transistor gate control terminal ND are all present. PG18 ND, the gate control terminal of the pull-down transistor NG18 , pull-up capacitor terminal ND Cup ND terminal of pull-down capacitor Cdn Compensation reference current I comp_ref Compensation current I comp_iq ND, the bias terminal of the compensation circuit mrr_comp The waveforms during the period from time t3 to t4 remain unchanged, identical to those at time t3. Therefore, the explanation will not be repeated here. Figure 12 In this context, the on / off state of the transistors within the driver portDRV is related to the voltage at each terminal.

[0279] Please also see Figure 13 , Figure 14 , Figure 15 During the transient falling phase PH3, the driver input signal inDAT transitions from a high logic level H to a low logic level L (inDAT = H → L); during the steady-state falling phase PH4, the driver input signal inDAT remains equal to the low logic level L (inDAT = L). During the transient falling phase PH3 and the steady-state falling phase PH4, the switching signal generation circuit swGenCKT generates a positive-phase pull-up path switching signal SW_P and a negative-phase pull-down path switching signal SWB_N (SW_P = SWB_N = L) for the low logic level L, and a negative-phase pull-up path switching signal SWB_P and a positive-phase pull-down path switching signal SW_N (SWB_P = SW_N = H) for the high logic level H. The circuit behavior related to the pull-up path, pull-down path, and compensation circuit compCKT is described below in sequence.

[0280] Please also see Figure 13 , Figure 15 During time points t4 to t5, in the pull-up path, because the pull-up path positive switching signal SW_P is at a low logic level L (SW_P = L), the pull-up path transmission gate upselTG is off, the PMOS current mirror disable transistor cfdisPM is on, the pull-up path disable transistor updisPM is on, and the pull-up path bypass transistor upbpPM is on, while the pull-up path transmission gate upTG is off. Furthermore, because the pull-up path inverting switching signal SWB_P is at a high logic level H (SWB_P = H), the NMOS current mirror disable transistor cfdisNM is on.

[0281] Because the NMOS current mirror disable transistor cfdisNM is turned on, it conducts the ground voltage Gnd to the reference bias terminal and the NMOS current mirror bias terminal ND. mrr_nm That is, ND mrr_nm =Gnd. Therefore, the NMOS current mirror inverting transistor nmrr_pNM and the NMOS current mirror inverting transistor nmrr_nNM are connected to the gate of the NMOS current mirror bias terminal ND. mrr_nm Equal to ground voltage Gnd(ND) mrr_nm It was disconnected because of =Gnd).

[0282] In the comparator circuit cfCKT, as the NMOS current mirror bias terminal ND... mrr_nm Set as ground voltage Gnd(ND) mrr_nm=Gnd), the NMOS current mirror inverting transistor nmrr_pNM and the NMOS current mirror inverting transistor nmrr_nNM will be turned off. Additionally, because the PMOS current mirror disable transistor cfdisPM is turned on, cfdisPM will conduct the supply voltage Vcc to the PMOS current mirror bias terminal ND. mrr_pm Make the output terminal cfout+ of the non-inverting comparator equal to the supply voltage Vcc (cfout+ = ND) mrr_pm =ND comp_en =Vcc). At this time, the PMOS current mirror inverting transistor pmrr_pPM and the PMOS current mirror inverting transistor pmrr_nPM are disconnected due to the supply voltage Vcc received at their gates.

[0283] like Figure 13 As shown, the pull-up path disabled transistor updisPM is turned on when SW_P = L. The supply voltage Vcc of the pulled-up path disabled transistor updisPM in the on-state is conducted to the gate terminal ND of the pull-up transistor. PG18 That is, ND PG18 =Vcc. Simultaneously, the pull-up transistor upPM, along with the pull-up transistor's gate terminal ND,... PG18 The voltage equals the supply voltage Vcc, causing it to disconnect. At this time, the pull-up transistor upPM does not affect the driver output signal outSIG. Additionally, during time points t4 to t5, due to the conduction of the pull-up path bypass transistor upbpPM, the pull-up capacitor terminal ND... Cup It equals the supply voltage Vcc. That is, ND Cup =1.8V. Furthermore, during time points t4 to t5, the pull-up path capacitor Cup passes through the pull-up path bypass transistor upbpPM and the pull-up capacitor terminal ND. Cup It continues to be charged to 1.8V.

[0284] In the pull-down path, because the pull-down path positive switching signal SW_N is at a high logic level H (SW_N = H), the pull-down path transmission gate dnselTG and the pull-down path transmission gate dnTG are turned on; because the pull-down path negative switching signal SWB_N is at a low logic level L (SWB_N = L), the pull-down path bypass transistor dnbpNM and the pull-down path disable transistor dndisNM are turned off.

[0285] Because the pull-down path disable transistor dndisNM is off, the pull-down path disable transistor dndisNM does not affect the gate control terminal ND of the pull-down transistor. NG18 The voltage. At this time, the conducting pull-down path uses the transmission gate dnselTG to conduct the supply voltage Vcc to the gate control terminal ND of the pull-down transistor.NG18 The pull-down transistor gate terminal ND NG18 During the period from time t4 to t5, the self-grounding voltage Gnd rises to the supply voltage Vcc. That is, ND NG18 =Gnd→Vcc. Consequently, the pull-down transistor dnNM is affected by the gate control terminal ND of the pull-down transistor. NG18 The driver turns on because its voltage equals the supply voltage Vcc, causing the driver output signal outSIG to drop from the supply voltage Vcc to the ground voltage Gnd. That is, outSIG = Vcc → Gnd.

[0286] During the period from time t4 to t5, due to the conduction of the pull-down path transmission gate dnTG, the pull-down capacitor terminal ND... Cdn With the pull-down transistor gate control terminal ND NG18 The voltage rises synchronously to the supply voltage Vcc.

[0287] In the compensation circuit compCKT, because the pull-up path inverting switching signal SWB_P is at a high logic level H (SWB_P = H), the compensation circuit disable transistor comp_disNM is turned on. Furthermore, the compensation circuit disable transistor comp_disNM turns on the ND bias terminal of the compensation circuit. mrr_comp Set as ground voltage Gnd(ND) mrr_comp =Gnd). Consequently, the compensating current source pull-down bias transistor comp_bsnNM and the compensating current path transistor comp_iqNM remain off during time points t4 to t5.

[0288] Whether the compensating current source pull-up bias transistor comp_bspPM is turned on depends on the PMOS current mirror bias terminal ND. mrr_pm (Equivalent to the voltage at the output terminal cfout+ of the non-inverting comparator, where cfout+ = ND) mrr_pm =ND comp_en Also, because Figure 13 Because the output of the positive comparator, cfout+, equals the supply voltage Vcc, the pull-up bias transistor comp_bspPM of the compensation current source remains off during time points t4 to t5. Therefore, during time points t4 to t5, there is no compensation reference current I. comp_refThe compensation reference current path `comp_refPATH` is generated. On the other hand, in the compensation current path `comp_curPATH`, the compensation current path enabling transistor `comp_iqenNM` is turned off because the pull-up path positive phase switching signal `SW_P` is at a low logic level L (SW_P = L). Therefore, in the compensation current path `comp_curPATH`, both the compensation current path enabling transistor `comp_iqenNM` and the compensation current path transistor `comp_iqNM` are turned off. At this time, there is no compensation current `I` in the compensation current path `comp_curPATH`. comp_iq produce.

[0289] In addition, Figure 13 In this circuit, the driver output signal outSIG is pulled down to ground voltage Gnd when the pull-down transistor dnNM is turned on. Therefore, the non-inverting differential input transistor diffpNM in the differential input circuit diffInCKT is turned off because the driver output signal outSIG received at its gate is equal to the ground voltage Gnd. Consequently, the inverting differential input transistor diffnNM, located on the other side of the differential input circuit diffInCKT, is also turned off during the falling transient phase of PH3.

[0290] When the driver portDRV is in the falling transient phase PH3, in addition to using the pull-down transistor dnNM to pull down the voltage of the driver output signal outSIG, the pull-down path capacitor Cdn is also charged simultaneously through the pull-down path transmission gate dnTG. Simultaneously, the pull-down transistor gate control terminal ND... NG18 It will also be affected by this voltage conduction path. Accordingly, the setting of the pull-down path capacitor Cdn can compensate for the AC response of the driver output signal outSIG during time points t4 to t5.

[0291] As mentioned above, the pull-down path capacitor Cdn exhibits the Miller effect, affecting the slew rate of the driver's output signal outSIG. A larger value for the pull-down path capacitor Cdn results in a lower slew rate for the driver's output signal outSIG. That is, during the transient hysteresis phase PH3, the voltage drop of the driver's output signal outSIG is more gradual. Conversely, a smaller value for the pull-down path capacitor Cdn results in a higher slew rate for the driver's output signal outSIG. That is, the voltage drop of the driver's output signal outSIG is steeper. In practical applications, the capacitance value of the pull-down path capacitor Cdn depends on the specifications required by the driver's portDRV.

[0292] During the period from time t5 to t6 (low steady-state stage PH4, see...) Figure 14 Because the driver input signal inDAT remains equal to the low logic level L (inDAT = L), in Figure 14In the process, the on / off state of the transistors within the driver portDRV remains consistent with... Figure 13 The states described in the latter part are the same. Furthermore, the driver output signal outSIG, the pull-up path positive phase switching signal SW_P, the pull-down path inverting phase switching signal SWB_N, the pull-up path inverting phase switching signal SWB_P, the pull-down path positive phase switching signal SW_N, the positive phase comparator output cfout+, and the pull-up transistor gate control terminal ND are all present. PG18 ND, the gate control terminal of the pull-down transistor NG18 , pull-up capacitor terminal ND Cup ND terminal of pull-down capacitor Cdn Compensation reference current I comp_ref Compensation current I comp_iq ND, the bias terminal of the compensation circuit mrr_comp The waveforms during the period from time t5 to t6 remain consistent with the state at time t5 without change. Therefore, the explanation will not be repeated here. Figure 14 In this context, the on / off state of the transistors within the driver portDRV is related to the voltage at each terminal.

[0293] As mentioned earlier, the external enable signal IQ_extEN for the additional current path is one input to the additional current enable circuit addEnCKT. The other input to addEnCKT is the pull-up path positive phase switching signal SW_P. Here, it can be assumed that addEnCKT is an AND gate.

[0294] When the external enable signal IQ_extEN of the additional current path is at a low logic level L (IQ_extEN = L), the additional current path enable signal IQ_EN output by the AND gate remains at a low logic level L (IQ_EN = L) regardless of the logic level of the positive phase switching signal SW_P of the pull-up path. Figure 15 The waveform is equivalent to, energy-forbidden. Figure 5 The case of the additional current path add_curPATH in the context of [the application / process]. That is to say, Figure 15 The waveform change corresponds to Figures 11-14 The status of the driver portDRV.

[0295] On the other hand, when the external enable signal IQ_extEN for the additional current path is at a high logic level H (IQ_extEN = H), the additional current path enable signal IQ_EN output by the AND gate changes according to the logic level of the pull-up path positive phase switching signal SW_P. When the pull-up path positive phase switching signal SW_P is at a high logic level H (SW_P = H), the additional current path enable signal IQ_EN is also at a high logic level H (IQ_EN = (IQ_extEN AND SW_P) = H). When the pull-up path positive phase switching signal SW_P is at a low logic level L (SW_P = L), the additional current path enable signal IQ_EN is also at a low logic level H (IQ_EN = L). Figure 16 Assuming that the external enable signal IQ_extEN of the additional current path is maintained at a high logic level H (IQ_extEN = (IQ_extEN AND SW_P) = H), the waveform of the additional current path is enabled by the additional current path enable signal IQ_EN being at a high logic level H (IQ_EN = H) during the rising transient phase PH1 and the high steady-state phase PH2.

[0296] Please see Figure 16 It is a waveform diagram showing how the internal endpoints of the driver portDRV according to the present disclosure change with the driver input signal inDAT when the driver circuit enable signal EN is at a high logic level H (EN = H) and the external enable signal IQ_extEN of the additional current path is set to a high logic level H (IQ_extEN = H) to enable the additional current path add_curPATH.

[0297] Figure 15 , Figure 16 The listed signal waveforms are largely similar. The difference between the two is that... Figure 16 Assuming the external enable signal IQ_extEN for the additional current path is at a high logic level H (IQ_extEN = H), Figure 16 Comparison Figure 15 Additional current I add_iq The waveform of the additional current path enable signal IQ_EN. In other words, Figure 15 This is equivalent to assuming an additional current I add_iq The current path enable signal IQ_EN remains at 0 μA and remains at a low logic level L (IQ_EN = L).

[0298] With the additional current I add_iq The generation of this effect makes the change process of some signals smoother. For example, the bias terminal ND of the comparator compensation circuit... mrr_comp exist Figure 15 , Figure 16 The waveform shows that although the bias terminal ND of the compensation circuit...mrr_comp exist Figure 15 , Figure 16 During the time points t2 to t3, the voltage rises from 0V to 0.5V, but the bias terminal ND of the compensation circuit... mrr_comp exist Figure 16 The waveform during the time point t2 to t3 (the rising transient phase PH1) is relatively... Figure 15 The waveform during the time points t2 to t3 is slightly smoother.

[0299] Other terminals include the output of the inverting comparator (cfout+), the output of the inverting comparator (cfout-), and the pull-up capacitor (ND). Cup exist Figure 15 , Figure 16 The waveforms also all show Figure 16 The waveform inside is relatively Figure 15 The waveform tends to be smoother or have a slightly smaller variation amplitude. Therefore, it can be inferred that the additional current I... add_iq The generation of this does not change the way the signal changes; it simply makes the change in the signal during the rising transient phase PH1 smoother. Therefore, the following explanation... Figure 16 When the signal is given, it will not be explained again. Figure 15 Other signals that are repeatedly plotted.

[0300] Table 5 Summary Figure 16 It did not appear in the middle. Figure 15 The waveform of the signal changes as the stage progresses. The voltage and current values ​​listed here are approximate and for reference only. Furthermore, the voltage and current values ​​used in actual applications are not limited to these.

[0301] Table 5

[0302]

[0303] Please also see Figure 16 As per Table 5, because the pull-up path positive phase switching signal SW_P is at a high logic level H (SW_P = H) during the rising transient phase PH1 and the high steady-state phase PH2, the additional current path enable signal IQ_EN is also at a high logic level H (IQ_EN = H) during the rising transient phase PH1 and the high steady-state phase PH2. Furthermore, the additional current I... add_iq The current value rises from 0 μA to 20 μA during the rising transient phase PH1, and remains at 20 μA during the high steady-state phase PH2. During the falling transient phase PH3 and the low steady-state phase PH4, the additional current path enable signal IQ_EN is at a low logic level L (IQ_EN = L), and no additional current I is generated at this time. add_iq .

[0304] Please see Figure 17This is a schematic diagram showing the addition of transistor path output impedance Rout_ts and capacitor path output impedance Rout_cp to the driver portDRV. In this diagram, the transistor path output impedance Rout_ts (e.g., Rout_ts = 500Ω) is electrically connected to the transistor path output terminal ND. Rout_ts With the driver output terminal ND out Between; the capacitor path output impedance Rout_cp (e.g., Rout_cp = 250Ω) is electrically connected to the drive circuit enable transmission gate enTG and the driver output terminal ND. out Between. Specifically, the transistor path output impedance Rout_ts is greater than the capacitor path output impedance Rout_cp. In practical applications, the impedance values ​​of the transistor path output impedance Rout_ts and the capacitor path output impedance Rout_cp are not limited to the examples given here.

[0305] Please see Figure 18A This diagram illustrates the calculation of the equivalent output impedance Rout_eq when a pull-up path is selected during the rising transient phase PH1 and the high steady-state phase PH2 after adding the transistor path output impedance Rout_ts and the capacitor path output impedance Rout_cp to the driver portDRV. Please also refer to... Figure 11 , Figure 12 , Figure 18A .

[0306] When the driver portDRV is in the rising transient phase PH1 or the high steady-state phase PH2, the calculation of the equivalent output impedance Rout_eq must consider the pull-up path output impedances Rout_up1 and Rout_up2 on two signal pull-up transmission paths. The first is the pull-up path output impedance Rout_up1 on the signal pull-up transmission path (Rout_ts+upPM) of the transistor path connected in series with each other; the second is the path output impedance Rout_up2 on the signal pull-up transmission path (Rout_cp+Cup) of the capacitor path connected in series with each other.

[0307] Because the signal pull-up transmission paths (Rout_ts+upPM) and (Rout_cp+Cup) are parallel to each other, Figure 18AThe equivalent output impedance Rout_eq of the driver portDRV is equivalent to the parallel connection of the pull-up path output impedances Rout_up1 and Rout_up2. That is, Rout_eq = Rout_up1 / / Rout_up2. In the signal pull-up transmission path (Rout_ts + upPM), because the pull-up transistor upPM has only a very small turn-on resistance when it is turned on, the pull-up path output impedance Rout_up1 is approximately equal to the transistor path output impedance Rout_ts. That is, Rout_up1 ≈ Rout_ts. Furthermore, because the impedance of the pull-up path capacitor Cup is approximately infinite (∞), the pull-up path output impedance Rout_up2 in the signal pull-up transmission path (Rout_cp + Cup) is approximately infinite (∞). That is, Rout_up2 ≈ ∞. Based on this, in Figure 18A In this context, the equivalent output impedance Rout_eq is equivalent to the parallel connection of the pull-up path output impedances Rout_up1 and Rout_up2 on the signal pull-up transmission paths (Rout_ts+upPM) and (Rout_cp+Cup). In this case, the equivalent output impedance Rout_eq approximates the transistor path output impedance Rout_ts. That is, Rout_eq = Rout_up1 / / Rout_up2 ≈ Rout_ts.

[0308] Please see Figure 18B This diagram illustrates the calculation of the equivalent output impedance Rout_eq when a pull-down path is selected during the transient phase PH3 and the low steady-state phase PH4 after adding the transistor path output impedance Rout_ts and the capacitor path output impedance Rout_cp to the driver portDRV. Please also refer to... Figure 13 , Figure 14 , Figure 18B .

[0309] When the driver portDRV is in the transient PH3 or the low steady-state PH4, the calculation of the equivalent output impedance Rout_eq must consider the pull-down path output impedances Rout_dn1 and Rout_dn2 on two signal pull-down transmission paths. The first is the pull-down path output impedance Rout_dn1 on the signal pull-down transmission path (Rout_ts+dnNM) of the series-connected transistor path Rout_ts and pull-down transistor dnNM. The second is the pull-down path output impedance Rout_dn2 on the signal pull-down transmission path (Rout_cp+Cdn) of the series-connected capacitor path Rout_cp and pull-down capacitor Cdn. Because the signal pull-down transmission paths (Rout_ts+dnNM) and (Rout_cp+Cdn) are parallel, Figure 18BThe equivalent output impedance Rout_eq of the driver portDRV can be expressed as the parallel connection of the pull-down path output impedances Rout_dn1 and Rout_dn2. That is, Rout_eq = Rout_dn1 / / Rout_dn2.

[0310] In the signal pull-down transmission path (Rout_ts+dnNM), because the pull-down transistor dnNM has only a very small turn-on resistance when it is turned on, the pull-down path output impedance Rout_dn1 is approximately equal to the transistor path output impedance Rout_ts. That is, Rout_dn1≈Rout_ts. Furthermore, because the impedance of the pull-down path capacitor Cdn is approximately infinite (∞), the pull-down path output impedance Rout_dn2 in the signal pull-down transmission path (Rout_cp+Cdn) is approximately infinite (∞). That is, Rout_dn2≈∞. Therefore, in Figure 18B In this context, the equivalent output impedance Rout_eq is equivalent to the parallel connection of the pull-down path output impedances Rout_dn1 and Rout_dn2 on the parallel-connected signal pull-down transmission paths (Rout_ts+dnNM) and (Rout_cp+Cdn). At this point, the equivalent output impedance Rout_eq approximates the transistor path output impedance Rout_ts. That is, Rout_eq = Rout_dn1 / / Rout_dn2 ≈ Rout_ts.

[0311] In practical applications, the driver portDRV of this disclosure can be configured with multiple pull-up transistors upPM[1] to upPM[K] in the pull-up circuit upCKT and K pull-down transistors dnNM[1] to dnNM[K] in the pull-down circuit dnCKT, based on electrostatic discharge (ESD) protection considerations. K is a positive integer. The following example assumes K = 4.

[0312] Please see Figure 19 The above is a schematic diagram of a pull-up circuit upCKT containing pull-up transistors upPM[1]~upPM[4] in parallel, pull-down transistors dnNM[1]~dnNM[4] in parallel, and a transistor path output impedance Rout_ts[1]~Rout_ts[4] in parallel. The pull-up circuit upCKT contains pull-up transistors upPM[1]~upPM[4] connected in parallel; the pull-down circuit dnCKT contains pull-down transistors dnNM[1]~dnNM[4] connected in parallel.

[0313] The sources of pull-up transistors upPM[1] to upPM[4] are all electrically connected to the supply voltage Vcc, and their gates are all electrically connected to the gate control terminal ND of the pull-up transistors.PG18 Therefore, the on / off states of the pull-up transistors upPM[1] to upPM[4] remain consistent. The sources of the pull-down transistors dnNM[1] to dnNM[K] are all electrically connected to the ground voltage terminal Gnd, and the gates are all electrically connected to the gate control terminal ND of the pull-down transistor. NG18 Therefore, the on / off states of pull-down transistors dnNM[1] to dnNM[4] remain consistent.

[0314] The drain of the pull-up transistor upPM[k] and the drain of the pull-down transistor dnNM[k] are electrically connected to the output terminal ND of the transistor path. Rout_ts [k]. Furthermore, the transistor path output impedance Rout_ts[k] is electrically connected to the transistor path output terminal ND. Rout_ts [k] and driver output endpoint ND out Between. k and K are positive integers, and k≤K. For example, the drain of the pull-up transistor upPM[1] and the drain of the pull-down transistor dnNM[1] are electrically connected to the transistor path output terminal ND. Rout_ts [1]. Furthermore, the transistor path output impedance Rout_ts[1] is electrically connected to the transistor path output terminal ND. Rout_ts [1] and driver output terminal ND out between.

[0315] Because the output impedances Rout_ts[1] to Rout_ts[K] of the transistor path are connected in parallel, by analogy... Figure 18A , Figure 18B As can be seen from the description, the equivalent output impedance Rout_eq is approximately the result of the transistor path output impedances Rout_ts[1]~Rout_ts[K] in parallel. That is, the equivalent output impedance Rout_eq=(Rout_ts[1] / / Rout_ts[2] / / ... / / Rout_ts[K]).

[0316] Based on the consideration of maintaining the resistance value of the equivalent output impedance Rout_eq, if K is larger, then transistor path output impedances Rout_ts[1]~Rout_ts[K] with larger resistance values ​​need to be used. In this way, the resistance value of the equivalent output impedance Rout_eq can be maintained while increasing K. However, using transistor path output impedances Rout_ts[1]~Rout_ts[K] with larger resistance values ​​also means that a larger circuit area is required.

[0317] Therefore, in practical applications, electrostatic discharge protection can be provided by increasing the number of pull-up transistors upPM[1]~upPM[K] and pull-down transistors dnNM[1]~dnNM[K]. However, the value of K still needs to be determined by referring to the total area occupied by the pull-up transistors upPM[1]~upPM[K], pull-down transistors dnNM[1]~dnNM[K], capacitor path output impedance Rout_cp, and transistor path output impedance Rout_ts[1]~Rout_ts[K].

[0318] If the driver portDRV is based on electrostatic discharge (ESD) protection considerations, then... Figure 19 When adding pull-up transistors upPM[1]~upPM[K] and pull-down transistors dnNM[1]~dnNM[K], the number of compensation current paths comp_curPATH[1]~comp_curPATH[K] and additional current paths add_curPATH[1]~add_curPATH[K] must also be adjusted synchronously. Figure 20 Assuming that when K=4, it is necessary to set the compensation current path comp_curPATH[1]~comp_curPATH[4] and the additional current path add_curPATH[1]~add_curPATH[4].

[0319] Please see Figure 20 It is in response to Figure 19 The diagram shows the parallel compensation current paths comp_curPATH[1]~comp_curPATH[4] and parallel additional current paths add_curPATH[1]~add_curPATH[4] set by the driver portDRV. For simplicity, Figure 20 Only the compensation circuit compCKT is shown.

[0320] exist Figure 20 In the compensation circuit compCKT, there are two current paths: comp_refPATH and comp_curPATH[1] to comp_curPATH[4]. The comp_refPATH includes the compensating reference current path comp_refPATH and the compensating current source pull-up bias transistor comp_bspPM and the compensating current source pull-down bias transistor comp_bsnNM. The compensating current path comp_curPATH[k] (k = 1 to 4) includes the compensating current path enable transistor comp_iqenNM[k] and the compensating current path transistor comp_iqNM[k]. When the compensating reference current I... comp_refWhen a compensation current Icomp_iq[k] (e.g., 20μA) is generated (e.g., 10μA), a corresponding compensation current Icomp_iq[k] is also generated on the compensation current path comp_curPATH[k].

[0321] When the pull-up path capacitor Cup has a small capacitance value, the AC stability of the driver portDRV will be poor. In this case, an additional current path add_curPATH can be used to improve the AC stability of the driver portDRV.

[0322] exist Figure 20 The architecture is illustrated when K=4 and additional current paths add_curPATH[1] to add_curPATH[K] are selected. The additional current paths add_curPATH[k] (k=1 to 4) include: the additional current path enable transistor add_iqenNM[k] and the additional current path transistor add_iqNM[k]. Both the additional current path enable transistor add_iqenNM[k] and the additional current path transistor add_iqNM[k] are NMOS transistors.

[0323] Please also see Figure 16 , Figure 20 .Depend on Figure 16 The waveforms show that the additional current path enable signal IQ_EN is at a high logic level H (IQ_EN = H = 1.8V) when the driver portDRV is in the rising transient phase PH1 and the high steady-state phase PH2. Therefore, the additional current path add_curPATH[k] will generate an additional current I during the rising transient phase PH1 and the high steady-state phase PH2. add_iq [k] (e.g., 20 μA). The value of K here refers to the compensation reference current I. comp_ref The current value of the compensation current Icomp_iq[k], the current value of the additional current I add_iq The current values ​​for [k] are examples and are not limited to these values ​​in actual applications.

[0324] Please see Figure 21 This is a schematic diagram of a low-dropout regulator (LDO) formed by a comparator circuit cfCKT, a pull-up transistor upPM, and a compensation circuit compCKT according to the present disclosure. Please also see... Figure 8 , Figure 21 . Figure 21 The circuit elements and connections shown are all consistent with... Figure 8 same.

[0325] exist Figure 21In the diagram, the circuit elements and connections within the comparator circuit cfCKT, pull-up transistor upPM, and compensation circuit compCKT are indicated by thick black lines. These components and connections constitute a low-dropout regulator (LDO). When the driver portDRV is in the high steady-state phase PH2, this LDO architecture can stably maintain the driver output signal outSIG equal to the reference voltage Vref. Therefore, it can be seen that the driver portDRV of this disclosure utilizes existing circuitry to incorporate the functionality of a low-dropout regulator (LDO), thus reducing the required circuit area.

[0326] Compared with existing technologies, the portDRV driver disclosed herein has at least the following advantages: it eliminates the need for an additional low-dropout regulator, requires only one operational amplifier, necessitates only a single-stage drive circuit, and requires only a reference voltage Vref. Compared with existing technologies, the portDRV driver disclosed herein can be implemented with a simpler circuit, thereby saving power and occupying a smaller area, thus reducing product manufacturing costs. In practical applications, the power-saving portDRV driver proposed in this disclosure has no limited uses. For example, in addition to being used in MIPI port physical layer drivers, it can also be used in display driver circuits, etc. The scope of practical applications in this section will not be detailed herein.

[0327] In summary, although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A driver comprising: A switching signal generation circuit generates a pull-up path positive phase switching signal, a pull-up path negative phase switching signal, a pull-down path positive phase switching signal, and a pull-down path negative phase switching signal based on a drive circuit enable signal and a driver input signal. A comparator circuit, electrically connected to a first constant voltage terminal and a second constant voltage terminal, includes: A positive phase comparator input is electrically connected to a driver output terminal of the driver; An inverting comparator input receives a reference voltage, wherein the reference voltage is greater than the voltage at the second constant voltage terminal and less than the voltage at the first constant voltage terminal. The output of a positive phase comparator; and, The output of an inverting comparator is electrically connected to the gate terminal of a pull-up transistor. A driving circuit, comprising: A pull-up circuit, electrically connected to the switching signal generation circuit and the comparator circuit, selectively adjusts the voltage at the driver output terminal based on the voltage of the positive-inverting switching signal of the pull-up path and the voltage at the gate control terminal of the pull-up transistor; and, A pull-down circuit, electrically connected to the switching signal generation circuit, selectively adjusts the voltage at the driver output terminal based on the voltage at the gate control terminal of the pull-down path inverted switching signal and the voltage at the pull-down transistor; and A one-port control module is electrically connected to the switching signal generation circuit, the comparison circuit, and the driving circuit. It sets the voltage of the gate control terminal of the pull-up transistor and the voltage of the gate control terminal of the pull-down transistor according to the pull-up path positive switching signal, the pull-up path negative switching signal, the pull-down path positive switching signal, and the pull-down path negative switching signal.

2. The driver as claimed in claim 1, wherein The pull-up circuit includes: K pull-up transistors are electrically connected to the gate control terminal of the pull-up transistor and the first constant voltage terminal. The output terminal of the driver is selectively set to the voltage of the first constant voltage terminal according to the voltage of the gate control terminal of the pull-up transistor. A pull-up path transmission gate, electrically connected to the switching signal generation circuit and the gate control terminal of the pull-up transistor, is selectively turned on according to the positive phase switching signal of the pull-up path; and A pull-up path capacitor is electrically connected to the pull-up path transmission gate, wherein The pull-down circuit includes: K pull-down transistors are electrically connected to the gate control terminal of the pull-down transistor and the second constant voltage terminal. The output terminal of the driver is selectively set to the voltage of the second constant voltage terminal according to the voltage of the gate control terminal of the pull-down transistor. A pull-down path transmission gate is electrically connected to the switching signal generation circuit and the gate control terminal of the pull-down transistor, and is selectively turned on according to the positive phase switching signal of the pull-down path; as well as A pull-down path capacitor is electrically connected to the pull-up path capacitor and the pull-down path transmission gate, wherein the kth pull-up transistor among the K pull-up transistors is electrically connected to the kth pull-down transistor among the K pull-down transistors, where k and K are positive integers, and k is less than or equal to K.

3. The driver as claimed in claim 2, wherein When the pull-up path transmission gate is turned on according to the pull-up path positive phase switching signal, the pull-down path transmission gate is turned off according to the pull-down path positive phase switching signal; and When the pull-up path transmission gate is disconnected according to the pull-up path positive phase switching signal, the pull-down path transmission gate is turned on according to the pull-down path positive phase switching signal.

4. The driver of claim 2, wherein the port control module comprises: A reference current source, electrically connected to the first constant voltage terminal, provides a reference current; and, A path selection circuit includes: A pull-up path uses a transmission gate, electrically connected to the reference current source and the comparator circuit. It is selectively turned on according to the positive-inverting switching signal of the pull-up path, thereby allowing the reference current to flow to the comparator circuit; and... One pull-down path uses a transmission gate, which is electrically connected to the reference current source and the pull-down circuit. It is selectively turned on according to the positive phase switching signal of the pull-down path, thereby allowing the reference current to flow to the pull-down circuit.

5. The driver as claimed in claim 4, wherein When the enable signal of the drive circuit is equal to a first logic level, the pull-up path transmission gate and the pull-down path transmission gate are synchronously disconnected; and When the enable signal of the drive circuit is equal to a second logic level, the pull-up path transmission gate and the pull-down path transmission gate are turned on alternately.

6. The driver of claim 4, wherein the port control module further comprises: A pull-up path disable transistor is electrically connected to the first constant voltage terminal and the gate control terminal of the pull-up transistor. It is selectively turned on according to the positive phase switching signal of the pull-up path. When the pull-up path disable transistor is turned on, it sets the gate control terminal of the pull-up transistor to the voltage of the first constant voltage terminal, thereby turning off the K pull-up transistors; and... A pull-up path bypass transistor is electrically connected to the first constant voltage terminal, the pull-up path transmission gate, and the pull-up path capacitor, and is selectively turned on according to the pull-up path positive switching signal.

7. The driver as claimed in claim 6, wherein When the enable signal of the driving circuit is equal to a first logic level, both the pull-up path disable transistor and the pull-up path bypass transistor are turned on, and both the K pull-up transistors and the pull-up path transmission gate are turned off; and When the enable signal of the driving circuit is equal to a second logic level, the pull-up path disable transistor and the pull-up path bypass transistor are selectively turned on, wherein... When the enable signal of the drive circuit is equal to the second logic level, and when both the pull-up path disable transistor and the pull-up path bypass transistor are turned on, the K pull-up transistors and the pull-up path transmission gate are all turned off, and When the enable signal of the drive circuit is equal to the second logic level, and when both the pull-up path disable transistor and the pull-up path bypass transistor are turned off, the K pull-up transistors and the pull-up path transmission gate are all turned on.

8. The driver of claim 4, wherein the port control module further comprises: A pull-down path disable transistor is electrically connected to the second constant voltage terminal and the gate control terminal of the pull-down transistor. It is selectively turned on according to the pull-down path inverting switching signal. When the pull-down path disable transistor is turned on, it sets the gate control terminal of the pull-down transistor to the voltage of the second constant voltage terminal, thereby turning off the K pull-down transistors; and A pull-down path bypass transistor is electrically connected to the second constant voltage terminal, the pull-down path transmission gate, and the pull-down path capacitor. It is selectively turned on according to the pull-down path inverting switching signal.

9. The driver as claimed in claim 8, wherein When the enable signal of the driving circuit is equal to a first logic level, both the pull-down path disable transistor and the pull-down path bypass transistor are turned on, and both the K pull-down transistors and the pull-down path transmission gate are turned off; and When the enable signal of the driving circuit is equal to a second logic level, the pull-down path disable transistor and the pull-down path bypass transistor are selectively turned on, wherein... When the enable signal of the driving circuit is equal to the second logic level, and when both the pull-down path disable transistor and the pull-down path bypass transistor are turned on, the K pull-down transistors and the pull-down path transmission gate are all turned off, and When the enable signal of the drive circuit is equal to the second logic level, and when both the pull-down path disable transistor and the pull-down path bypass transistor are turned off, the K pull-down transistors and the pull-down path transmission gate are all turned on.

10. The driver of claim 2, wherein the driving circuit further comprises: A drive circuit enables a transmission gate, which is electrically connected to the pull-up path capacitor and the pull-down path capacitor, and is selectively turned on according to the drive circuit enable signal. A capacitor path output impedance; electrically connected to the enable transmission gate of the drive circuit and the output terminal of the driver; and, There are K transistor path output impedances, wherein the kth transistor path output impedance is electrically connected to the kth pull-up transistor and the kth pull-down transistor.

11. The driver of claim 10, wherein When the enable transmission gate of the drive circuit is turned off, the pull-up circuit and the pull-down circuit stop setting the voltage of the driver output terminal, and the driver output terminal is in a floating state.

12. The driver of claim 10, wherein When the drive circuit enables the transmission gate to conduct, the voltage at the output terminal of the driver changes according to the input signal of the driver, wherein, When the driver input signal changes from a first logic level to a second logic level, the voltage at the driver output terminal rises from the voltage at the second constant voltage terminal to the reference voltage. When the voltage of the driver input signal remains equal to the second logic level, the voltage of the driver output terminal remains equal to the reference voltage. When the driver input signal changes from the second logic level to the first logic level, the voltage at the driver output terminal drops from the reference voltage to the voltage at the second constant voltage terminal. as well as When the driver input signal is maintained at the first logic level, the voltage at the driver output terminal is maintained at the second constant voltage terminal.

13. The driver of claim 2, further comprising: A compensation circuit, comprising: A compensation reference current path, electrically connected to the port control module, the output of the inverting comparator, the first constant voltage terminal, and the second constant voltage terminal, selectively generates a compensation reference current between the first constant voltage terminal and the second constant voltage terminal based on the voltage at the output of the inverting comparator and the inverting switching signal of the pull-up path; and, K compensation current paths are electrically connected to the switching signal generation circuit, the port control module, the driver output terminal, and the second constant voltage terminal. They selectively and synchronously generate K compensation currents between the driver output terminal and the second constant voltage terminal based on the positive phase switching signal and the negative phase switching signal of the pull-up path.

14. The driver of claim 13, wherein the port control module further comprises: A compensation circuit disable transistor is electrically connected to the switching signal generation circuit, the compensation reference current path, and the K compensation current paths. It selectively disconnects the compensation reference current path and the K compensation current paths according to the pull-up path inverted switching signal.

15. The driver of claim 14, wherein the compensation circuit further comprises: K additional current paths are electrically connected to the compensation reference current path, the K compensation current paths, and the compensation circuit disable transistor. These paths selectively and synchronously generate the K additional currents based on the logic level of an additional current path enable signal. The power-off transistor in the compensation circuit selectively disconnects the K additional current paths based on the inverted switching signal of the pull-up path.

16. The driver of claim 15, further comprising: An additional current enable circuit is electrically connected to the switching signal generation circuit and the K additional current paths. It receives the pull-up path positive phase switching signal from the switching signal generation circuit and an external enable signal for the additional current paths from an external controller. The additional current enable circuit determines the logic level of the additional current path enable signal based on the positive phase switching signal of the pull-up path and the external enable signal of the additional current path.

17. The driver of claim 13, wherein the comparator circuit, the K pull-up transistors, and the compensation circuit together form a low-dropout regulator.

18. The driver of claim 1, wherein the comparator circuit further comprises: A first current mirror, comprising: A first current mirror inverting transistor is electrically connected to the output of the inverting comparator, the port control module, and the first constant voltage terminal; and, A first current mirror inverting transistor is electrically connected to the output of the inverting comparator, the port control module and the first constant voltage terminal; A differential input circuit, comprising: A positive differential input transistor is electrically connected to the output and input of the positive comparator; and An inverting differential input transistor is electrically connected to the output and input of the inverting comparator; and A second current mirror, comprising: A second current mirror inverting transistor is electrically connected to the port control module and the second constant voltage terminal; and, A second current mirror inverting transistor is electrically connected to the port control module, the positive differential input transistor, the inverting differential input transistor, and the second constant voltage terminal.

19. The driver of claim 18, wherein the port control module further comprises: A first current mirror disable circuit, electrically connected to the first fixed voltage endpoint, the switching signal generation circuit, the first current mirror inverting transistor, and the first current mirror inverting transistor, selectively conducts the voltage of the first fixed voltage endpoint to the output of the inverting comparator according to the pull-up path inverting switching signal, thereby disconnecting the first current mirror inverting transistor and the first current mirror inverting transistor; and A second current mirror disable circuit is electrically connected to the second constant voltage terminal, the switching signal generation circuit, the second current mirror inverting transistor, and the second current mirror non-inverting transistor. Based on the pull-up path inverting switching signal, it selectively conducts the voltage of the second constant voltage terminal to the second current mirror inverting transistor and the second current mirror non-inverting transistor, thereby disconnecting the second current mirror non-inverting transistor and the second current mirror inverting transistor. The first current mirror disabling circuit and the second current mirror disabling circuit are synchronously turned on or synchronously turned off.

20. The driver as claimed in claim 1, wherein, When the enable signal of the driving circuit is a first logic level, the switching signal generating circuit sets the positive phase switching signal of the pull-up path and the positive phase switching signal of the pull-down path to the first logic level, and sets the negative phase switching signal of the pull-up path and the negative phase switching signal of the pull-down path to a second logic level; and, When the enable signal of the driving circuit is the second logic level, the switching signal generating circuit sets the pull-up path positive switching signal and the pull-down path negative switching signal according to the logic level of the driver input signal, and sets the pull-up path negative switching signal and the pull-down path positive switching signal according to the negative logic level of the driver input signal.

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