Method for starting a phase-locked loop and corresponding integrated circuit

Abstract

The present disclosure relates to a method for starting a phase-locked loop and a corresponding integrated circuit. In a start-up sequence of the phase-locked loop, a voltage-controlled oscillator is operated in a linear region by a first voltage, and a first count of a register of a frequency divider is read. Then, the voltage-controlled oscillator is controlled by a second voltage having a second voltage offset from the first voltage, and a second count of the register is read. A slope of the linear region is then determined from a difference between the first and second counts and the offset of the first and second voltages. A determination of a third voltage required to reach a target frequency of an output signal is made in dependence on the slope and a deviation between a current value of the register count and a target value corresponding to the target frequency. The voltage-controlled oscillator is then controlled with the third voltage.

Description

Cross-reference to related applications

[0001] This application claims priority to French patent application No. FR2500714, filed on January 23, 2025, the contents of which are incorporated herein by reference in their entirety to the fullest extent permitted by law. Technical Field

[0002] The implementations and embodiments of this invention relate to integrated circuits, and more particularly to phase-locked loop (PLL) circuits. More specifically, the embodiments herein relate to the management of PLL circuit startup. Background Technology

[0003] Phase-locked loop (PLL) circuits are typically used in digital systems that require high internal operating frequencies, such as those in the hundreds of megahertz or gigahertz range.

[0004] Therefore, phase-locked loop circuits are particularly useful for delivering internal clock signals with high operating frequencies to these digital systems, such as programmable cores or microprocessors.

[0005] However, the start-up duration (i.e., the time it takes for the loop to stabilize after the reference signal and the oscillator output signal are nearly synchronized) can be very long, for example, between 90 μs and 150 μs or even several hundred microseconds in some cases.

[0006] Conventional techniques for accelerating startup have made it possible to reduce this duration to about 30 μs, for example, by using a setpoint derived from the frequency variation to a transfer of a pre-charge current controlled by the setpoint, and by making it possible to modulate the frequency through the analog components to get closer to the operating frequency.

[0007] Although this type of technology is relatively efficient from a speed point of view under nominal conditions, its operation in the analog section can be difficult within the range of technology and possible configurations, and it is also very sensitive to variations in process voltage-temperature (PVT) (variations (or hazards) in the manufacturing process), possible variations in supply voltage, and temperature variations, which can negatively impact the effective start-up duration of the circuit.

[0008] However, the duration of a low and stable start-up is generally an important parameter in relation to operating conditions and other external hazards.

[0009] Therefore, there is a need to obtain even faster, more stable and reproducible start-up durations for phase-locked loops, regardless of any changes in the PVT. Summary of the Invention

[0010] By indirectly determining the oscillator gain in a linear mode, and quantizing the distance between the signal frequency and the target frequency using gain determination, and thus controlling the oscillator with voltage to directly reach the target frequency, the implementation and examples defined below enable these needs to be met while benefiting from other advantages. This technique allows for direct attainment of the target frequency with single-step quantization of the distance (in most cases) and in a manner suitable for PVT drift. In particular, the fast-start technique of the phase-locked loop is based on minimal analog considerations but is largely implemented digitally, and is therefore suitable for any existing technology.

[0011] In fact, according to one aspect, a method for managing the operation of a phase-locked loop is provided, the loop including a voltage-controlled oscillator (VCO) for generating an output signal and a frequency divider for maintaining a count of pulses of the output signal in a register. The method includes a startup sequence comprising: controlling the oscillator with a first voltage configured to place the oscillator directly in the linear region and reading a first count from the register; controlling the oscillator with a second voltage having an offset relative to the first voltage and reading a second count from the register; measuring the slope of the linear region of the oscillator based on the difference between the first and second counts and the offset between the first and second voltages; and controlling the oscillator with a third voltage determined based on the measured slope and the deviation between the current value of the register count and a target value corresponding to a target frequency, so as to achieve a target frequency for the output signal.

[0012] Therefore, in other words, the effective slope of the oscillator is measured under effective PVT conditions in order to determine immediately or almost immediately the final voltage that will allow the target frequency to be obtained under these PVT conditions. Determining the final voltage based on the measured value of the effective slope is particularly accurate and relevant because when measuring the slope, the oscillator is intentionally placed in the linear region by the first voltage.

[0013] This mechanism eliminates the time required for iterative steps to achieve the voltage-frequency pair (target voltage - target frequency), and thus benefits from very fast, reproducible, and stable locking times regardless of method variations or temperature. Furthermore, this mechanism is as independent of simulation considerations as possible and facilitates technological portability (i.e., easy adaptation to different phase-locked loop techniques).

[0014] According to one implementation, the phase-locked loop includes a phase comparator that generates a control signal for a voltage-controlled oscillator, the control signal representing a comparison between an output signal divided by a frequency divider and a reference signal; the start sequence is controlled by a digital control circuit whose timing is supplied by a clock signal that can switch between the reference signal and the output signal.

[0015] According to one implementation, a reference signal is used to supply timing to the control circuit until the oscillator is controlled by a first voltage, and thereafter the oscillator is controlled by an output signal.

[0016] According to one implementation, the phase-locked loop includes a low-pass filter circuit for filtering control signals for a voltage-controlled oscillator; the control of the oscillator utilizing the first voltage is performed by a first pre-charge circuit by injecting a first pre-charge current at a first internal node of the filter and measuring the pre-charge voltage at a second internal node of the filter until a first voltage is reached.

[0017] For example, the first pre-charge circuit transmits the first voltage to the control circuit to control the oscillator so as to switch the timing supply of the control circuit to the output signal.

[0018] According to one implementation, a first internal node of the filter is selected to attenuate the filter's output response to the injection of a first pre-charge current.

[0019] According to one implementation, if the current value of the register differs from the target value by more than a tolerance (e.g., 5%) when the oscillator is controlled by a third voltage, a new third voltage is determined based on the new deviation between the current value and the target value.

[0020] Furthermore, for example, if two consecutive current values ​​of the register differ by more than the tolerance of the target value when the oscillator is controlled by the third voltage, and are below and above the target value respectively, the newly determined third voltage becomes closer to the basic amount of the previous value of the third voltage.

[0021] According to another aspect, an integrated circuit is also provided, comprising: a phase-locked loop (PLL) including a voltage-controlled oscillator (VCO) for generating an output signal and a frequency divider for holding a count of pulses of the output signal in a register; and a digital control circuit configured to, during a startup sequence: control the oscillator with a first voltage configured to place the oscillator directly in the linear region and read a first count from the register; control the oscillator with a second voltage having an offset relative to the first voltage and read a second count from the register; measure the slope of the linear region of the oscillator based on the difference between the first count and the second count and the offset between the first voltage and the second voltage; and control the oscillator with a third voltage determined based on the measured slope and the deviation between the current value of the register count and a target value corresponding to a target frequency, so as to achieve a target frequency for the output signal.

[0022] According to one embodiment, the phase-locked loop includes a phase comparator configured to generate a control signal for a voltage-controlled oscillator, the control signal representing a comparison between an output signal divided by a frequency divider and a reference signal; and a digital control circuit, timed by a clock signal, configured in a startup sequence to switch the clock signal between the reference signal and the output signal.

[0023] According to one embodiment, the control circuit is configured to switch the clock signal to a reference signal until the oscillator is controlled by a first voltage, and then switch to the output signal.

[0024] According to one embodiment, the phase-locked loop includes: a low-pass filter circuit configured to filter a control signal for a voltage-controlled oscillator; and a first pre-charge circuit configured to control the oscillator with the first voltage by injecting a first pre-charge current at a first internal node of the filter and measuring a pre-charge voltage at a second internal node of the filter until the first voltage is reached.

[0025] According to one embodiment, a first pre-charge circuit is configured to pass the first voltage to a control circuit to control an oscillator, and the control circuit is configured to switch their timing supply to an output signal.

[0026] According to one embodiment, the first internal node of the filter is configured to attenuate the output response of the filter to the injection of a first pre-charge current.

[0027] According to one embodiment, the control circuit is configured to test whether the difference between the current value of the register and the target value when the oscillator is controlled with a third voltage is greater than a tolerance (e.g., 5%), and if so, to determine a new third voltage based on the new deviation between the current value and the target value.

[0028] Furthermore, for example, the control circuit is configured to monitor whether two consecutive current values ​​of the register differ by more than a tolerance of the target value when the oscillator is controlled with a third voltage, and are respectively below and above the target value, and if so, to make the newly determined third voltage closer to the basic amount of the previous value of the third voltage. Attached Figure Description

[0029] Further advantages and features of the invention will become apparent after reviewing the detailed description of the non-limiting embodiments and implementations and with reference to the accompanying drawings, in which:

[0030] Figure 1 This is a block diagram of a phase-locked loop (PLL) circuit;

[0031] Figure 2 It is a flowchart of a method for managing the operation of a phase-locked loop, particularly for implementing a start sequence;

[0032] Figure 3 The graph of the transfer function of the oscillator is illustrated schematically.

[0033] Figure 4 The implementation of the second step is schematically illustrated in the graph of the oscillator's transfer function;

[0034] Figure 5 The implementation of the third step in the graph of the oscillator's transfer function is illustrated schematically;

[0035] Figure 6 It is based on Figures 1 to 5 The signal timing diagram for the startup sequence; and

[0036] Figure 7 The filter circuit of the PLL loop is schematically illustrated. Detailed Implementation

[0037] Figure 1 This is a block diagram of a phase-locked loop (PLL) circuit.

[0038] The PLL circuit enables the generation of an output clock signal with a relatively high output frequency fcvo (on the order of one megahertz (kHz) or one megahertz (MHz)) from a reference signal with a relatively low reference frequency fosc (on the order of one megahertz (MHz) or one megahertz (GHz)).

[0039] For the sake of brevity, the term type “output signal with output frequency” can be simplified to the term “output frequency”, which implies that the frequency is carried by an electrical signal within the scope of this description.

[0040] Therefore, the PLL loop includes a voltage-controlled oscillator (VCO) that generates the output frequency fvco, an input oscillator (OSC) configured to generate the reference frequency fosc, and a feedback loop for the output frequency fvco (to perform frequency multiplication). In the feedback loop, the output frequency is divided by a frequency divider DIVf, and if the divided frequency is lower or higher than the reference frequency, the phase comparator PD of the VCO is used to compare the divided output frequency fdiv with the reference frequency fosc to speed up or slow down the output frequency.

[0041] For example, to generate the divided frequency (fdiv = fvco / N), the divider DIVf can typically increment a counter in a register periodically at each pulse (e.g., the rising edge) of the output signal fvco. When the counter reaches the divided value N, a transition is generated in the signal fdiv (which rises or falls depending on the previous level of the signal fdiv), and its new level (1 or 0) is maintained until the next transition.

[0042] The phase comparator PD is configured, for example, to generate two “down” and “up” signals, where different binary states representing the positive or negative phase difference between the input signal fpd (or fosc / R) and the frequency-divided output signal fdiv allow control of the downstream of the loop to accelerate or decelerate the output fvco generated by the oscillator VCO, for example, via the filter FLT.

[0043] For example, a filter FLT can implement low-pass filtering and convert current (from a phase comparator PD) into voltage, thereby controlling an oscillator VCO.

[0044] Furthermore, the PLL circuit can advantageously include a first pre-charge circuit PPC configured to inject a first pre-charge current ippc into the filter FLT and measure the pre-charge voltage VC1. Combined with Figure 7 See below.

[0045] Alternatively, a divider 1 / R can be provided to divide the reference frequency fosc, and the input frequency fpd = fosc / R can be provided to the phase comparator PD to implement the multiplication factor based on a more complex fraction. In the following text, we will consider dividing by 1 (R = 1) and the input frequency fpd of the phase comparator PD being equal to the reference frequency fosc (i.e., fpd = fosc).

[0046] The operation of the PLL loop is timed by a state (or finite state) machine type control circuit, FSM. The state machine FSM is a digital circuit whose timing is supplied by a clock signal ck.

[0047] Once the loop is started, and at least at the very beginning of the start sequence Srt, the state machine FSM can advantageously be supplied with the reference frequency fosc. Then, when the output frequency fvco is present, the state machine FSM can advantageously switch its clock signal so that it is supplied with the output frequency fvco.

[0048] For example, the first precharge circuit PPC is configured to generate a signal for passing the generated output signal fvco to the state machine FSM.

[0049] In particular, the mechanism implemented by the first pre-charge circuit PPC for establishing the first voltage Vctrl1 can be advantageously used twice, on the one hand to generate the first voltage Vctrl1, and on the other hand to pass the signal notifying the existence of the output frequency fvco to the state machine FSM.

[0050] In this respect, especially combined Figure 3 and 7 See below.

[0051] This allows the clock frequency ck = fvco to benefit from the Fast State Machine (FSM), which not only enables the implementation of startup sequences but also allows for the execution of relatively complex operations, such as frequency division, without specific time constraints.

[0052] Now for reference Figure 2 .

[0053] Figure 2 The illustration shows an example method for managing the operation of a phase-locked loop, particularly the implementation of the advantageous start sequence SLT.

[0054] For example, as mentioned above... Figure 1 The described phase-locked loop (PLL) specifically includes a voltage-controlled oscillator (VCO) that generates an output signal fvco and a frequency divider (DIVf) for the output signal, holding counts N1, N2, and N3 in a register of pulses of the output signal fvco.

[0055] The method Srt includes a first step Stp1, in which the oscillator VCO is controlled with a first voltage Vctrl1 configured to place the oscillator directly in the linear region, and a first count N1 of the register of the divider DIVf is read.

[0056] Also combined Figure 3 See below.

[0057] The method Srt includes a second step Stp2, in which the oscillator VCO is controlled with a second voltage Vctrl2 having an offset of +ΔVctrl relative to the first voltage Vctrl1, and the second count N2 of the register is read.

[0058] In the second step Stp2, the slope of the linear region of the oscillator is measured based on the difference ΔN = N2 - N1 between the first count N1 and the second count N2, and the offset ΔVctrl between the first voltage Vctrl1 and the second voltage Vctrl2.

[0059] Also combined Figure 4 See below.

[0060] The method Srt includes a third step Stp3, in which the oscillator VCO is controlled by a third voltage Vctrl3, which is determined based on the deviation between the measured slope ΔN / Vctrl1 and the current value of the count in register N3 (initially N3=N2) and the target value NTg corresponding to the target frequency in order to achieve the target frequency of the output signal.

[0061] For example, a tolerance can be defined at frequencies greater than + / - 5% of the target frequency FreqTg, such that if |NTg-N3| ≤ 5% of NTg, the start sequence ends at End_Strt; otherwise, the third step Stp3 is repeated from the deviation between the current value of register N3 and the target value NTg.

[0062] Also combined Figure 5 See below.

[0063] For a detailed implementation of the example of the startup sequence SLT, it also combines Figure 6 See below.

[0064] Figure 3 The diagram illustrates the transfer function of the oscillator VCO (i.e., the frequency Freq of the output signal fvco, which controls the input voltage Vin, is also known as the "S-characteristic" due to its stretched "S" shape).

[0065] The transfer function of an oscillator VCO typically includes a linear region Lnr, where the output frequency fvco is substantially proportional to the input voltage Vin.

[0066] Therefore, the first step Stp1 of the startup method includes controlling the oscillator at the first operating point 1 at a first frequency Freq1, which is obtained by a first voltage Vctrl1 located in the linear region Lnr.

[0067] The first voltage Vctrl1 is, for example, located essentially at the center of the linear region Lnr, and can be advantageously achieved by means of an analog first precharge circuit PPC (in combination with...). Figure 7 (See below) is determined by a fixed voltage (such as 500mV) suitable for the circuit.

[0068] Reading the first count N1, which increments in the register of the divider DIVf during the cycle of the reference signal fosc (i.e., the entire cycle), gives a measurement of the first frequency Freq1 relative to the reference frequency fosc. Alternatively, reading the first count N1 can be performed during several cycles of the reference signal fosc, also giving a relative measurement of the output frequency fvco.

[0069] For example, reading the first count N1 takes less than 1 μs (microseconds), while controlling the oscillator VCO with the first voltage Vctrl1 takes less than 2 μs.

[0070] Figure 4 The implementation of the second step, Stp2, is schematically illustrated in the transfer function graph of the oscillator VCO.

[0071] The second step of the startup method, Stp2, involves controlling the oscillator at the second operating point 2 at a second frequency Freq2, which is obtained from a second voltage Vctrl2 that is also located in the linear region Lnr.

[0072] The second count N2, which is incremented in the register of the frequency divider DIVf within at least one cycle of the reference signal fosc, gives the measured value of the second frequency Freq2 relative to the reference frequency fosc.

[0073] Therefore, in the second step Stp2, the slope Kvco of the linear region of the oscillator VCO can be measured. The slope is approximately the ratio ΔFreq / ΔVctrl of the frequency difference ΔFreq to the voltage difference ΔVctrl between the first operating point 1 and the second operating point 2 (where: ΔFreq = Freq2 - Freq1; and ΔVctrl = Vctrl2 - Vctrl1).

[0074] It should be noted that the above approximation is particularly accurate and reliable because the oscillator is intentionally placed in the linear region and far from the inflection point of the “S” characteristic during the first step Stp1.

[0075] The frequency difference ΔFreq is obtained from the difference ΔN = N2 - N1 between the first count N1 and the second count N2.

[0076] As for the offset ΔVctrl between the first voltage Vctrl1 and the second voltage Vctrl2, it is known because it is "hard-coded" due to the fact that it comes from the control of the PLL loop.

[0077] In this regard, the added offset ΔVctrl is advantageously provided to be large enough to avoid the risk of generating errors in the calculation, and small enough to be considered as the basic injection (one step) to be reproduced multiple times to get closer to the target frequency.

[0078] In other words, in the second step Stp2, an indirect measurement of the oscillator's effective gain is obtained, including its dependence on the PVT variation.

[0079] Figure 5 The implementation of the third step, Stp3, is schematically illustrated in the transfer function graph of the oscillator VCO.

[0080] The third step of the startup method, Stp3, involves controlling the oscillator at a third operating point 3 (3b) with a third frequency Freq3, which is obtained from a third voltage Vctrl3, which is also located in the linear region Lnr.

[0081] More specifically, a third function Vctrl3 is determined in order to reach or become closer to the target frequency FreqTg.

[0082] In fact, the slope K from the first operation point 1 and the second operation point 2 is known. VCO (i.e., K) VCO =ΔFreq / ΔVctrl), which gives the value of the third voltage Vctrl3 that positions the frequency Freq3 on the (linear) curve at the target value FreqTg.

[0083] In fact, K VCO =ΔFreq / ΔVctrl and K VCO =ΔF / ΔV, where ΔF =FreqTg-Freq2 is the difference between the target frequency FreqTg and Ia and the current frequency (i.e., the second frequency Freq2); and ΔV=Vctrl3-Vctrl2 is the difference between the third voltage Vctrl3, which aims to obtain the target frequency, and the current voltage (i.e., the second voltage Vctrl2).

[0084] Therefore, there exists ΔV = ΔVctrl ΔFreq.

[0085] Furthermore, the frequency difference ΔF is obtained from the difference ΔN' = NTg - N2 between the second count N2 and the target count NTg (i.e., the target value NTg of the counter DIVf corresponding to the target frequency FreqTg).

[0086] Therefore, ΔV = ΔVctrl That is, Vctrl3 = Vctrl2 + ΔVctrl (NTg-N2) / (N2-N1).

[0087] In theory, this calculation allows the target operating point Tg to be reached directly and precisely at the target frequency FreqTg using the corresponding control voltage VctrlTg.

[0088] However, due to possible nonlinearity of the gain and possible quantization errors in the calculation (the latter is performed on integer counts N2, N3, and Euclidean frequency division is implemented), the calculated result of the third voltage Vctrl3 may result in an operating point 3b at a distance greater than the tolerance relative to the target operating point Tg. For example, the tolerance can be defined at a frequency greater than + / - 5% of the target frequency FreqTg.

[0089] Therefore, for example, it is possible to test the difference between the current value N3 of the register (i.e., the value incremented in the register of the divisor DIVf over the duration of the loop of the reference signal fosc) and the target value NTg corresponding to the target frequency FreqTg.

[0090] For example, refer to Figure 2 The following can be defined as a test: if |NTg-N3| If NTg, then the start sequence ends at End_Strt; otherwise, it starts from operation point 3b ( Figure 5 Repeat step 3 (Stp3).

[0091] In this case, a new calculation of Vctrl3' is performed from the third operating point 3b, where ΔF'=FreqTg-Freq3 is the difference between the target frequency FreqTg and Ia and the current frequency (i.e., the third frequency Freq3); and ΔV'=Vctrl3'-Vctrl3 is the difference between the new third voltage Vctrl3' aimed at obtaining the target frequency and the current voltage (i.e., the third voltage Vctrl3).

[0092] Therefore, according to K VCO =ΔFreq / ΔVctrl=ΔF' / ΔV', there is ΔV'=ΔVctrl ΔFreq.

[0093] Furthermore, the frequency difference ΔF' is obtained from the difference ΔN' = NTg - N3 between the current count value N3 and the target count NTg.

[0094] Therefore, ΔV'=ΔVctrl That is, Vctrl3' = Vctrl3 + ΔVctrl (NTg-N3) / (N2-N1).

[0095] The third step, Stp3, can be repeated as many times as necessary from the last operating point where the stopping condition is not met (which is a test of tolerance tolerance, for example, at 5% of the target frequency) until the stopping condition is met.

[0096] Now for reference Figure 6 .

[0097] Figure 6 The diagram illustrates the combination based on previous data. Figures 1 to 5 The time progression of the output frequency fvco of the described startup sequence Srt is illustrated, and more particularly, the control signals of the state machine FSM are shown to time the sequence and the values ​​of the registers used.

[0098] In this example, the state machine FSM uses the reference frequency fosc, which is available before starting the PLL loop, as the clock signal ck, for example, once the operation signal Rdy is received from the reference oscillator OSC.

[0099] For example, the reference frequency fosc is 16MHz, and the target frequency of the output signal fvco is 1.6GHz, i.e., NTg = 100 (fvco = fosc). NTg).

[0100] The first activation signal of the first step Stp1 enables the implementation of the first step to be controlled at the binary level "1", that is, to activate the first precharge circuit PPC configured to inject current ippc, so that a first voltage Vctrl1 can be established in the filter FLT of the PLL loop to reach the center part of the linear region of the PLL loop.

[0101] When the first voltage Vctrl1 is reached at time 101, the output frequency fvco is, for example, at 625MHz, and the first activation signal Stp1 is controlled to the binary value "0".

[0102] The first count N1 can be incremented starting at time 102 during the next cycle of the reference frequency fosc, and continues until time 103 when the first count N1 = 39 is recorded.

[0103] Starting at time 103, the second step is achieved by changing the second activation signal Stp2 to the binary value "1" through the state machine FSM.

[0104] Therefore, in the second step, the voltage deviation ΔVctrl is introduced into the control of the oscillator VCO until the second voltage Vctrl2 is reached and the output frequency fvco is, for example, at 820MHz and the second activation signal Stp2 is controlled at the moment 104 when the binary value is "0".

[0105] In this example, the offset ΔVctrl will be introduced using q=4 cycles from time 103 to time 104.

[0106] Before controlling the third step Stp2 by changing the third activation signal Stp3 to the binary value "1" through the state machine FSM, waiting until time 105 in a loop ensures the stability of the second output frequency fvco.

[0107] During the loop, the second count N2 is incremented starting at time 105 until time 106 when the second count N2 = 51 is recorded.

[0108] At the same time 106, the value of the difference N2-N1=12 is recorded, and the value of the third counter N3 is initialized at N3=N2=51 to calculate the coefficient p.

[0109] Still at the same time 106, the calculation of the coefficient p = NTg / (N2-N1) - N3 / (N2-N1) is recorded, that is, p = 4 (where NTg = 100 in this example).

[0110] Therefore, starting from time 106, the third step introduces an offset ΔV that allows direct attainment of the target frequency, such as... ΔVctrl, this is actually The duration of each cycle continues until the third voltage Vctrl3 is reached and the output frequency fvco is, for example, at 1320MHz at time 107.

[0111] Waiting until time 108 cycles again ensures the stability of the third output frequency fvco.

[0112] The increment of the third count N3 begins at time 108 during the loop and continues until time 109 when the third count N3 = 83 is recorded.

[0113] At the same time 109, for example at 5% of the target count NTg, the calculation of the convergence criterion is performed on N3, for example by means of a hard-coded bit offset operator.

[0114] In this example, since |100-83|>5 (5% of NTg = 100), the third step Stp3 is repeated.

[0115] Therefore, in this case, with the current count N3=82, a new value for coefficient p is obtained ( Figure 5 The calculation of p' in the middle is performed, and p=2 is recorded again at time 109.

[0116] Therefore, from time 109 to time 110, for Each cycle introduces a new offset ΔV' until the third voltage Vctrl3 is reached and the output frequency fvco is at 1600MHz at moment 110.

[0117] The waiting loop (not shown) ensures the stability of the third output frequency fvco.

[0118] During the cycle up to time 111, the third count N3 was incremented, recording count N3 = 101.

[0119] At the same time 111, the calculation of the convergence criterion is verified, because in this example, |100-101|≤5.

[0120] Once the start sequence Strt is complete, the state machine FSM sets the end sequence signal End_Strt to the binary value "1".

[0121] Recall that, although in most cases the stopping condition (i.e., the target is reached within the tolerance) can be met once the third step Stp3 is first implemented, the third step Stp3 can be repeated as many times as needed from the last operating point where the stopping condition is not met.

[0122] Furthermore, in this context of repeating the third step Stp3, the initiation sequence can advantageously include detecting oscillations on either side of the target, i.e., operating points alternating between frequencies below and above the target frequency and outside the tolerance. For example, this could be due to the potential amplification of (non-zero risk) errors, causing the frequency to increase too much and then decrease too much without satisfying the stopping condition.

[0123] In this regard, oscillation detection involves monitoring the last two operating points obtained consecutively by this method. When switching from an operating point below (or above) the target frequency to an operating point above (or below) the target frequency without meeting the stopping condition, the next fundamental current injection q then occurs on a cycle smaller than the previous cycle (i.e., (q-1) loops, where p=1). This can be repeated until an injection occurs in one loop.

[0124] Now for reference Figure 7 .

[0125] Figure 7 The previous combination is illustrated schematically. Figure 1 The filter circuit FLT of the described PLL loop.

[0126] The filter FLT includes, for example, a resistor-capacitor (RC) connection arranged to perform low-pass filtering on a signal leaving the phase comparator PD (e.g., the current at node Vpd), which is then converted into the control voltage V of the oscillator VCO. VCO .

[0127] The RC circuit includes a main branch between the input node Vpd and ground, in which the first resistor R1, the second resistor R2 and the main capacitor C1 are coupled in series.

[0128] Furthermore, the input secondary capacitor C2 is coupled between the input node Vpd and ground, and the output secondary circuitry includes the input node Vpd and the output node Vpd. VCO The third resistor R3 between and at the output node V VCO The output secondary capacitor C3 is located between the capacitor and ground.

[0129] Furthermore, the RC circuit of the filter FLT advantageously includes a first internal node between the first resistor R1 and the second resistor R2 for receiving the injection of the first precharge current ippc, and a second internal precharge voltage readout node VC1 at the terminal of the main capacitor C1.

[0130] The first precharge circuit PPC is configured to inject a first precharge current ippc into the injection node ippc of the filter FLT in order to place the oscillator VCO in the linear region in a controlled manner relative to a measured value of the precharge voltage VC1 on the read node.

[0131] The operation of the first pre-charge circuit therefore includes, for example, controlling the activation of the current injector when the input is less than 500mV, and controlling the deactivation of the current injector when the input is greater than or equal to 500mV. Voltage comparison is performed by analog circuitry in a manner that supports PVT variations substantially the same as those in the PLL loop.

[0132] A first pre-charge current ippc is injected into the injection node, such that it can be balanced with the resistance value (such as the capacitance value) relative to the capacitance value. (C2 + C3) are attenuated together in filter V VCO The response of the output (which is amplified) to this current ippc.

[0133] Therefore, the intensity of the first pre-charge current ippc can be increased, for example, by the order of 100 μA (which is large compared to conventional use) without risking exceeding the safe limit of the output frequency fvco.

[0134] On the other hand, the measured voltage VC1 at the terminal of capacitor C1 is higher than that at the output node V. VCO The measurements are faster and more stable, and furthermore, it allows for measurements to be taken at the latter V. VCO The drift of the output frequency fvco is reduced by 80%, for example simply because the primary capacitor value C1 is very large relative to the secondary capacitor values ​​C2 and C3.

[0135] Finally, when the first voltage Vctrl1 is established by the first precharge circuit PPC, the first precharge circuit PPC can be advantageously configured to transmit information to the control circuit that the oscillation of the output signal fvco has begun.

Claims

1. A method for managing the operation of a phase-locked loop, the phase-locked loop including a voltage-controlled oscillator (VCO) and a frequency divider, the VCO generating an output signal, the frequency divider being configured to count pulses of the output signal in a register, the method including a startup sequence comprising: The voltage-controlled oscillator is controlled by a first voltage, which directly places the voltage-controlled oscillator in the linear region. Then read the first count from the register; The voltage-controlled oscillator is controlled by a second voltage, which is offset relative to the first voltage. Then read the second count from the register; The slope of the linear region is measured using the difference between the first count and the second count, and the offset between the first voltage and the second voltage. Based on the slope and the deviation between the current value of the register count and the target value corresponding to the target frequency, a third voltage required to reach the target frequency of the output signal is determined; and The voltage-controlled oscillator is controlled by the third voltage.

2. The method of claim 1, wherein the phase-locked loop includes a phase comparator configured to generate a control signal for the voltage-controlled oscillator, wherein the control signal represents a comparison between the output of the frequency divider and a reference signal; and further includes timing a digital control circuit for controlling the start sequence with a clock signal, and switching the clock signal of the digital control circuit between the reference signal and the output signal.

3. The method according to claim 2, wherein timing the digital control circuit comprises: The reference signal is supplied as the clock signal until the voltage-controlled oscillator is controlled by the first voltage, and thereafter the output signal is supplied as the clock signal.

4. The method of claim 1, wherein the phase-locked loop includes a low-pass filter circuit that filters the control signal for the voltage-controlled oscillator; wherein controlling the voltage-controlled oscillator with the first voltage includes: A first pre-charge current is injected into the first internal node of the low-pass filter by the first pre-charge circuit; as well as The pre-charge voltage on the second internal node of the low-pass filter is measured until the first voltage is reached.

5. The method of claim 4, further comprising timing a digital control circuit controlling the start sequence with a clock signal; supplying the reference signal as the clock signal until the voltage-controlled oscillator is controlled by the first voltage; thereafter supplying the output signal as the clock signal; and transmitting from the first precharge circuit to the digital control circuit that the voltage-controlled oscillator is controlled by the first voltage so as to switch to supplying the output signal as the clock signal.

6. The method of claim 4, wherein the first internal node of the low-pass filter is selected to attenuate the output response of the low-pass filter to the injection of the first pre-charge current.

7. The method according to claim 1, further comprising: When the voltage-controlled oscillator is controlled by the third voltage, if the difference between the current value of the register and the target value is greater than the tolerance, a new third voltage is determined based on the new deviation between the current value and the target value.

8. The method according to claim 7, further comprising: When two consecutive current values ​​of the register of the voltage-controlled oscillator controlled by the third voltage differ from the target value by a tolerance, and are respectively lower and higher than the target value, a fundamental amount is determined to make the new third voltage closer to the previous value of the third voltage.

9. An integrated circuit, comprising: A phase-locked loop includes a voltage-controlled oscillator and a frequency divider, wherein the voltage-controlled oscillator generates an output signal and the frequency divider is configured to count pulses of the output signal in a register; as well as The digital control circuit is configured to: The voltage-controlled oscillator is controlled by a first voltage, which is configured to place the voltage-controlled oscillator directly in the linear region. Then read the first count from the register; The voltage-controlled oscillator is controlled by a second voltage, which is offset relative to the first voltage. Then read the second count from the register; The slope of the linear region is measured using the difference between the first count and the second count, and the offset between the first voltage and the second voltage. Based on the slope and the deviation between the current value of the register count and the target value corresponding to the target frequency, a third voltage required to reach the target frequency of the output signal is determined; and The voltage-controlled oscillator is controlled by the third voltage.

10. The integrated circuit of claim 9, wherein the phase-locked loop includes a phase comparator configured to generate a control signal for the voltage-controlled oscillator, the control signal representing a comparison between the output of the frequency divider and a reference signal; and wherein the digital control circuit is timed by a clock signal and configured in the start sequence to switch the clock signal between the reference signal and the output signal.

11. The integrated circuit of claim 10, wherein the clock signal for the control circuit is the reference signal until the voltage-controlled oscillator is controlled by the first voltage, and wherein the clock signal for the control circuit is the output signal thereafter.

12. The integrated circuit of claim 9, wherein the phase-locked loop comprises: A low-pass filter circuit is configured to filter the control signal used for the voltage-controlled oscillator; as well as A first pre-charge circuit is configured to control the voltage-controlled oscillator with the first voltage by injecting a first pre-charge current at a first internal node of the low-pass filter and measuring the pre-charge voltage at a second internal node of the filter until the first voltage is reached.

13. The integrated circuit of claim 12, wherein the digital control circuit is timed by a clock signal, wherein the clock signal for the control circuit is the reference signal until the voltage-controlled oscillator is controlled by the first voltage, and wherein the clock signal for the control circuit is the output signal thereafter, and wherein the first pre-charge circuit is configured to transmit to the control circuit that the voltage-controlled oscillator is controlled by the first voltage, and the control circuit is configured to switch the clock signal to the output signal.

14. The integrated circuit of claim 12, wherein the first internal node of the filter is configured to attenuate the output response of the filter to the injection of the first pre-charge current.

15. The integrated circuit of claim 9, wherein the control circuit is configured to identify when the current value of the register having the voltage-controlled oscillator controlled by the third voltage differs from the target value by more than a tolerance, and then determine a new third voltage based on the new deviation between the current value and the target value.

16. The integrated circuit of claim 15, wherein the control circuit is configured to monitor whether two consecutive current values ​​of the register of the voltage-controlled oscillator controlled by the third voltage differ from the target value by a tolerance, and are respectively below and above the target value, and then make the newly determined third voltage closer to the basic amount of the previous value of the third voltage.

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