Method for processing a circuit board and circuit board
By embedding components sequentially along the thickness of the circuit board, and combining through-slot and blind slot designs, the problems of insufficient space utilization and integration in embedded packaging processes are solved, achieving high-density packaging and improved stability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHENNAN CIRCUITS
- Filing Date
- 2026-04-17
- Publication Date
- 2026-07-24
AI Technical Summary
Existing embedded packaging technologies have shortcomings in terms of space utilization and integration, resulting in large package size, low stability, and high cost.
By sequentially embedding first and second embedded devices in the thickness direction of the circuit board, and utilizing the structural design of through slots and blind slots, combined with technologies such as adhesive layers, dielectric layers and laser engraving, the devices are fixed and signals are fanned out, forming a multi-layer embedded package.
It improves the packaging density and performance of circuit boards, reduces unit costs, and enhances space utilization and stability.
Smart Images
Figure CN122458338A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of circuit board packaging technology, and in particular to a method for processing a circuit board and a circuit board. Background Technology
[0002] Traditional packaging processes achieve electrical connections between devices through soldering or wire bonding. Products manufactured using traditional packaging methods are large and lack stability. Based on this, embedded packaging has gradually developed. Because embedded packaging requires matching the properties of various materials, its unit cost is significantly higher than that of traditional packaging. However, embedded packaging products are smaller and more stable, thus it has still achieved considerable development in the packaging field.
[0003] In the field of embedded packaging, planar packaging is commonly used, where all embedded components are on a single plane. The number of components that can be embedded is limited by the overall design size. Therefore, it has low space utilization and low package integration.
[0004] Therefore, there is an urgent need to improve existing embedded packaging technology in order to enhance the integration of embedded packaging. Summary of the Invention
[0005] This application provides a method for processing a circuit board and a circuit board in which a first embedded device and a second embedded device can be sequentially embedded along the thickness direction of the circuit board, thereby improving the packaging density and performance of the circuit board.
[0006] This application provides a method for processing a circuit board, including: Double-sided copper-clad laminates are available; A through groove is processed on the double-sided copper-clad board, a first embedded device is placed in the through groove, and the first embedded device is fixed and the signal is fanned out. A third dielectric layer is laminated on the non-signal fan-out side of the first embedded device, and a blind groove is processed on the third dielectric layer; A second embedded device is installed in the blind slot, and signal fan-out is performed on the second embedded device.
[0007] In some embodiments, the provisioning of the first embedded device within the through groove includes: A first adhesive layer is provided on one side of the double-sided copper-clad laminate, and the first adhesive layer covers the opening on one side of the through groove; The first embedded device is placed in the through groove and attached to the first adhesive layer; After fixing the first embedded device, the process further includes: removing the first adhesive layer.
[0008] In some embodiments, fixing the first embedded device includes: A first dielectric layer is pressed onto the non-signal fan-out side of the first embedded device; The first dielectric layer is heated and pressurized, causing the colloidal portion of the first dielectric layer to flow into the gap between the first embedded device and the through groove, and the colloidal portion of the first dielectric layer is cured.
[0009] In some embodiments, signal fan-out is performed on the first embedded device, including: A second dielectric layer is pressed onto the signal fan-out side of the first embedded device; Laser etching is performed on the position where the second dielectric layer is directly opposite the pad of the first embedded device, so that the pad of the first embedded device is exposed. Laser etching is performed on the position where the first dielectric layer is directly opposite the non-signal fan-out surface of the first embedded device, so that at least part of the non-signal fan-out surface of the first embedded device is exposed.
[0010] In some embodiments, signal fan-out of the first embedded device further includes: Sputtering is performed on the surfaces of the first dielectric layer and the second dielectric layer to form a copper seed layer; An electroplated copper layer is formed on the copper seed layer by electroplating. A circuit pattern is formed on the electroplated copper layer.
[0011] In some embodiments, the provisioning of the second embedded device within the blind slot includes: A second adhesive layer is provided at the bottom of the blind groove; The second embedded device is placed in the blind groove and attached to the second adhesive layer.
[0012] In some embodiments, providing a second adhesive layer at the bottom of the blind groove includes: When the blind groove satisfies H≤100μm, silicone is coated on the bottom of the blind groove by screen printing; When the blind groove satisfies H>100μm, a pre-made silicone film is placed at the bottom of the blind groove using a pick-and-place machine; Where H is the depth of the blind groove.
[0013] In some embodiments, the signal fan-out of the second embedded device includes: A fourth medium layer is pressed onto the opening side of the blind groove; Laser etching is performed on the position where the fourth dielectric layer is directly opposite the pad of the second embedded device, so that the pad of the second embedded device is exposed. The surface of the fourth dielectric layer is sputtered to form a copper seed layer, and an electroplated copper layer is formed on the copper seed layer, and a circuit pattern is formed on the electroplated copper layer.
[0014] In some embodiments, there are multiple first embedded devices, and each first embedded device includes a chip. The second embedded device is multiple, and the second embedded device includes a chip and a copper base.
[0015] This application also provides a circuit board, which is prepared by the circuit board processing method of any of the above embodiments.
[0016] The circuit board processing method of this application embodiment involves setting a first embedded device in a through groove of a double-sided copper-clad board, pressing a third dielectric layer on the non-signal fan-out side of the first embedded device, and setting a second embedded device in a blind groove of the third dielectric layer. Therefore, the first embedded device and the second embedded device can be embedded sequentially along the thickness direction of the circuit board, thereby improving the packaging density and performance of the circuit board. Attached Figure Description
[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0018] Figure 1 This is a schematic flowchart illustrating the circuit board processing method according to an embodiment of this application.
[0019] Figure 2 This is a schematic diagram of the first state of the circuit board in the processing method of this application embodiment.
[0020] Figure 3 This is a schematic diagram of the second state of the circuit board in the processing method of this application embodiment.
[0021] Figure 4 This is a schematic diagram of the third state of the circuit board in the processing method of this application embodiment.
[0022] Figure 5 This is a schematic diagram of the fourth state of the circuit board in the processing method of this application embodiment.
[0023] Figure 6 This is a schematic diagram of the fifth state of the circuit board in the processing method of this application embodiment.
[0024] Figure 7This is a schematic diagram of the sixth state of the circuit board in the processing method of this application embodiment.
[0025] Figure 8 This is a schematic diagram of the seventh state of the circuit board in the processing method of this application embodiment.
[0026] Figure 9 This is a schematic diagram of the eighth state of the circuit board in the processing method of this application embodiment.
[0027] Figure 10 This is a schematic diagram of the ninth state of the circuit board in the processing method of this application embodiment. Detailed Implementation
[0028] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.
[0029] This application provides a method for processing a circuit board, in which a first embedded device and a second embedded device are sequentially embedded along the thickness direction of the circuit board, thereby improving the packaging density and performance of the circuit board.
[0030] refer to Figure 1 , Figure 1 This is a schematic flowchart illustrating a circuit board fabrication method according to an embodiment of this application. The fabrication method includes the following steps 110-140: 110, providing double-sided copper-clad laminates; 120. A through groove is processed on a double-sided copper-clad board, a first embedded device is set in the through groove, and the first embedded device is fixed and the signal is fanned out. 130. A third dielectric layer is pressed onto the non-signal fan-out side of the first embedded device, and a blind groove is machined on the third dielectric layer. 140. A second embedded device is installed in the blind slot, and signal fan-out is performed on the second embedded device.
[0031] First, in step 110, a double-sided copper-clad laminate is provided. See also... Figure 2 , Figure 2 This is a schematic diagram of the first state of the circuit board in the processing method of this application embodiment. The double-sided copper-clad laminate includes a core board and copper layers respectively disposed on both sides of the core board. In practical applications, a copper-clad laminate of appropriate thickness can be selected according to application requirements (e.g., the thickness of the device). The thickness of the copper-clad laminate includes the thickness of the core board and the thickness of the copper layers on both sides.
[0032] In practical applications, through holes with a preset diameter can be machined on a double-sided copper-clad laminate. The through holes are then electroplated to form copper walls, followed by resin plugging and copper plating on the resin surface. Figure 2 As shown. This achieves electrical conductivity between the copper layers on both sides of the core board, enabling the transmission of electrical signals between them. Understandably, after hole wall electroplating, resin plugging, and surface copper plating, circuit patterns can be further fabricated on the copper layers. In practical applications, circuit patterns can be created by methods such as applying dry film to the copper layer surface, exposure, development, etching, and film removal, ultimately forming the circuit pattern on the circuit board (PCB).
[0033] In step 120, through-grooves are first machined on the double-sided copper-clad board. The machined through-grooves are as follows: Figure 2 As shown, the through-slot extends along the thickness direction of the double-sided copper-clad laminate. It is understood that there can be multiple through-slots, spaced apart. In practical applications, the through-slots can be machined by milling using methods such as machining or laser engraving. Subsequently, a first embedded device is placed within the through-slot, and the first embedded device is fixed and its signal fan-out is implemented.
[0034] In some embodiments, the first embedded device is disposed within the through groove, including the following steps: A first adhesive layer is provided on one side of the double-sided copper-clad laminate, and the first adhesive layer covers the opening on one side of the through groove; The first embedded device is placed in the through groove and attached to the first adhesive layer; After fixing the first embedded device, the process also includes: removing the first adhesive layer.
[0035] refer to Figure 3 and Figure 4 , Figure 3 This is a schematic diagram of the second state of the circuit board in the processing method of this application embodiment. Figure 4 This is a schematic diagram of the third state of the circuit board in the processing method of this application embodiment. In this case, after a through-groove is processed on the double-sided copper-clad board, a first adhesive layer is formed on one side of the double-sided copper-clad board. The first adhesive layer covers the opening on one side of the through-groove, as shown below. Figure 3 As shown. In some embodiments, the first adhesive layer is a tape, such as a high-temperature tape, with the adhesive side of the tape facing into the through groove.
[0036] Subsequently, the first embedded device is placed in the through groove and adhered to the first adhesive layer, such as Figure 4As shown. The first embedded device is designated as device 1. In some embodiments, there are multiple first embedded devices, which may include chips, such as logic chips, memory chips, radio frequency chips, optoelectronic chips, etc. In practical applications, the depth (longitudinal dimension) of the through-groove is slightly larger than the thickness of the first embedded device, and the lateral dimension (dimension perpendicular to the longitudinal direction) of the through-groove is slightly larger than the dimension of the first embedded device, creating a gap between the first embedded device and the through-groove. At this time, the first embedded device is adhered and fixed using a first adhesive layer to prevent movement. After the first embedded device is subsequently fixed, the first adhesive layer can be removed, for example, by peeling off tape.
[0037] In some embodiments, fixing the first embedded device includes the following steps: A first dielectric layer is pressed onto the non-signal fan-out side of the first embedded device; The first dielectric layer is heated and pressurized, causing the colloidal portion of the first dielectric layer to flow into the gap between the first embedded device and the through groove, and the colloidal portion of the first dielectric layer is cured.
[0038] refer to Figure 5 , Figure 5 This is a schematic diagram of the fourth state of the circuit board in the processing method of this application embodiment. The first embedded device has a signal fan-out surface and a non-signal fan-out surface. The signal fan-out surface is used for signal fan-out from the first embedded device to realize electrical signal transmission with other devices. The non-signal fan-out surface is the opposite side to the signal fan-out surface.
[0039] After setting up the first embedded device, a first dielectric layer is pressed onto the non-signal fan-out side of the first embedded device, such as... Figure 5 As shown. The first dielectric layer can be a prepreg (PP). The prepreg is a base material for manufacturing printed circuit boards and is made of polyimide, epoxy resin, or bismaleimide-triazine resin, or a blend of these with glass fiber.
[0040] Subsequently, the first dielectric layer is heated and pressurized, causing the colloidal portion of the first dielectric layer to flow into the gap between the first embedded device and the through groove, and the colloidal portion of the first dielectric layer to solidify. In practical applications, when the environment of PP reaches a certain temperature, the colloidal content within it will become fluid. When a certain pressure is applied, the colloidal content will flow into the gap between the first embedded device and the through groove. As the temperature continues to rise, the colloidal content will solidify, thereby fixing the first embedded device in place. At this point, the first adhesive layer can be removed, for example, by peeling off the tape.
[0041] In some embodiments, signal fan-out of the first embedded device includes the following steps: A second dielectric layer is pressed onto the signal fan-out side of the first embedded device; Laser etching is performed on the position where the pads of the second dielectric layer and the first embedded device are directly opposite each other, so that the pads of the first embedded device are exposed. Laser etching is performed on the position where the first dielectric layer and the non-signal fan-out surface of the first embedded device are directly opposite each other, so that at least part of the non-signal fan-out surface of the first embedded device is exposed.
[0042] refer to Figure 6 , Figure 6 This is a schematic diagram of the fifth state of the circuit board in the processing method of this application embodiment. The signal fan-out surface of the first embedded device has pads. After fixing the first embedded device, a second dielectric layer is pressed onto one side of the signal fan-out surface of the first embedded device. The second dielectric layer can also be a prepreg (PP). Subsequently, laser etching is performed on the position of the second dielectric layer opposite to the pads to expose the pads, facilitating electrical connection between the pads and the circuit board lines. Furthermore, laser etching is also performed on the position of the first dielectric layer opposite to the non-signal fan-out surface of the first embedded device, exposing at least part of the non-signal fan-out surface. The exposed non-signal fan-out surface can serve as a heat dissipation surface for the first embedded device, used for connection with a heat dissipation structure, improving the heat dissipation performance of the first embedded device.
[0043] It should be noted that, Figure 6 The diagram shown illustrates the device after further processing. The pads of the first embedded device are exposed relative to the second dielectric layer, and a portion of the non-signal fan-out surface is also exposed relative to the first dielectric layer.
[0044] In some embodiments, signal fan-out of the first embedded device further includes the following steps: Sputtering is performed on the surfaces of the first dielectric layer and the second dielectric layer to form a copper seed layer; Electroplating is performed on the copper seed layer to form an electroplated copper layer; Circuit patterns are formed on the electroplated copper layer.
[0045] It should be noted that sputtering is a highly efficient and controllable physical vapor deposition technique that uses plasma to bombard a target, causing its atoms to sputter and deposit on a substrate to form a thin film, which serves as a seed layer for subsequent processing.
[0046] In this process, sputtering can be used to sputter the surfaces of the first and second dielectric layers, forming copper seed layers on both surfaces. The copper seed layers are thin films of copper. Subsequently, electroplating is performed on the copper seed layers to form electroplated copper layers, such as... Figure 6As shown. Understandably, since the pads and part of the non-signal fan-out surface of the first embedded device are exposed, a copper seed layer will also form on the pad surface and the non-signal fan-out surface during sputtering. During subsequent electroplating, the plated copper will fill the depressions in the pads and non-signal fan-out surface, forming... Figure 6 The structure shown is an electroplated copper layer. Subsequently, circuit patterns can be formed on the electroplated copper layer through processes such as dry film application, exposure, development, etching, and film removal. This allows for the fixation, protection, and signal extraction of the first embedded device.
[0047] Understandably, the pads of the first embedded device are connected to the plated copper layer on the surface of the second dielectric layer. Therefore, the pads can transmit electrical signals to the outside through the circuit pattern formed by the plated copper layer on the surface of the second dielectric layer. The non-signal fan-out side of the first embedded device is connected to the plated copper layer on the surface of the first dielectric layer. Therefore, the non-signal fan-out side can dissipate heat through the plated copper layer on the surface of the first dielectric layer, thereby improving the heat dissipation performance of the first embedded device.
[0048] Subsequently, in step 130, a third dielectric layer is laminated on the non-signal fan-out side of the first embedded device. For example, refer to... Figure 7 , Figure 7 This is a schematic diagram of the sixth state of the circuit board in the processing method of this application embodiment. A third dielectric layer can be further laminated on the first dielectric layer, or a third dielectric layer can be further laminated on the electroplated copper layer formed after laminating the first dielectric layer. The third dielectric layer can also be a prepreg (PP).
[0049] After laminating the third dielectric layer, blind grooves are machined on the third dielectric layer, such as... Figure 7 As shown. Blind slots can be fabricated using methods such as machining or laser milling. For example, controlled-depth milling can be used to mechanically remove the PP at the location where the subsequent device will be embedded to create a blind slot. Understandably, multiple blind slots can be created, spaced apart. In practical applications, the thickness of the third dielectric layer matches the height of the device to be embedded, typically being 20μm~30μm thicker than the embedded device. Furthermore, in practical applications, to ensure no residual resin remains at the bottom of the blind slots due to manufacturing processes, plasma cleaning can be used to remove residual resin from the blind slots. This completes the blind slots required for the subsequent installation of the second embedded device.
[0050] Subsequently, in step 140, a second embedded device is installed in the blind slot, and signal fan-out is performed on the second embedded device.
[0051] In some embodiments, the second embedded device is disposed within the blind slot, comprising the following steps: A second adhesive layer is applied to the bottom of the blind groove; The second embedded device is placed in the blind slot and attached to the second adhesive layer.
[0052] refer to Figure 8 and Figure 9 , Figure 8 This is a schematic diagram of the seventh state of the circuit board in the processing method of this application embodiment. Figure 9 This is a schematic diagram of the eighth state of the circuit board in the processing method of this application embodiment. First, a second adhesive layer is formed at the bottom of the blind slot, such as... Figure 8 As shown. Subsequently, the second embedded device is placed within the blind groove and adhered to the second adhesive layer, as shown. Figure 9 As shown.
[0053] In practical applications, the second adhesive layer can be silicone, which is used to adhere and fix the second embedded device. In some embodiments, there are multiple second embedded devices, for example, the second embedded devices include... Figure 9 Devices 2A and 2B are shown. Device 2A can be a chip, such as a logic chip, memory chip, RF chip, optoelectronic chip, etc. Device 2B can be a copper-based device, formed of copper. Understandably, the copper base is connected to the first embedded device (device 1) through a bottom-plated copper layer. Therefore, device 1 can dissipate heat externally through the copper base, improving the heat dissipation performance of the first embedded device, thereby improving the overall heat dissipation performance of the circuit board.
[0054] In practical applications, different adhesive application processes are required to set the second adhesive layer for blind grooves of different depths in order to match the processing capabilities.
[0055] For example, in some embodiments, when the blind groove depth H ≤ 100 μm, silicone is applied to the bottom of the blind groove via screen printing, where H is the depth of the blind groove. In practical applications, the amount of silicone applied to the bottom of the blind groove can be controlled by using screens with different mesh sizes. The advantages of screen printing are high processing efficiency, the ability to coat the entire board with silicone, and good uniformity of the silicone layer. However, when the blind groove depth is too large, silicone buildup can occur, affecting subsequent processing.
[0056] In some embodiments, when the blind groove depth (H > 100 μm) is satisfied, a pre-made silicone adhesive film is placed at the bottom of the blind groove using a pick-and-place machine, where H is the depth of the blind groove. In practical applications, a pick-and-place machine can be used to place the pre-made silicone adhesive film at the bottom of the blind groove to achieve adhesive application. The advantage of this process is that the adhesive layer thickness is precisely controlled, and no solvent is involved in the processing. The silicone adhesive film is usually a UV-curable adhesive, which contains a photoinitiator. After absorbing ultraviolet light of a specific wavelength, it initiates the polymerization of oligomers and monomers to undergo a cross-linking reaction, thereby achieving pre-curing of the adhesive. In practical applications, different silicone adhesives are required to meet different product needs. For example, for products with high heat dissipation requirements, a layer of high thermal conductivity silicone adhesive can be applied.
[0057] In some embodiments, signal fan-out of the second embedded device includes the following steps: A fourth dielectric layer is pressed onto the opening side of the blind groove; Laser etching is performed on the position where the pads of the fourth dielectric layer and the second embedded device are directly opposite each other, so that the pads of the second embedded device are exposed. The surface of the fourth dielectric layer is sputtered to form a copper seed layer, and an electroplated copper layer is formed on the copper seed layer, and a circuit pattern is formed on the electroplated copper layer.
[0058] refer to Figure 10 , Figure 10 This is a schematic diagram of the ninth state of the circuit board in the processing method of this application embodiment. First, a fourth dielectric layer is pressed onto one side of the opening of the blind slot; for example, the fourth dielectric layer can be further pressed onto the third dielectric layer. The fourth dielectric layer can also be a prepreg (PP). It is understood that the second embedded device includes a chip with pads. Therefore, laser engraving can be performed on the position where the fourth dielectric layer and the pads of the second embedded device are directly opposite, exposing the pads and facilitating electrical connection between the chip pads and the circuit board lines. It should be noted that... Figure 10 The diagram shown illustrates the subsequent processing. The pads of the second embedded device are exposed relative to the fourth dielectric layer.
[0059] In practical applications, for the copper base included in the second embedded device, the position of the fourth dielectric layer opposite to the copper base can be laser-etched to expose the copper base, which facilitates the connection between the copper base and other devices, thereby enhancing heat dissipation performance.
[0060] Subsequently, sputtering is performed on the surface of the fourth dielectric layer to form a copper seed layer, which is a thin film of copper formed on the surface of the fourth dielectric layer. Then, electroplating is performed on the copper seed layer to form an electroplated copper layer, such as... Figure 10As shown. Understandably, since the pads of the second embedded device are exposed, a copper seed layer will also form on the pad surface during sputtering. During subsequent electroplating, the plated copper will fill the depressions in the pad locations, forming... Figure 10 The structure shown illustrates an electroplated copper layer. Similarly, since the copper base is partially exposed, a copper seed layer forms on the copper base surface during sputtering. During subsequent electroplating, the electroplated copper fills the depressions where the copper base is located, forming... Figure 10 The structure shown is an electroplated copper layer. Subsequently, circuit patterns can be formed on the electroplated copper layer through processes such as dry film bonding, exposure, development, etching, and film stripping.
[0061] The circuit board processing method of this application embodiment involves setting a first embedded device in a through groove of a double-sided copper-clad board, pressing a third dielectric layer on the non-signal fan-out side of the first embedded device, and setting a second embedded device in a blind groove of the third dielectric layer. Therefore, the first embedded device and the second embedded device can be embedded sequentially along the thickness direction of the circuit board, thereby improving the packaging density and performance of the circuit board.
[0062] This application also provides a circuit board, which is prepared by the processing method of any of the above embodiments.
[0063] In the description of this application, it should be understood that terms such as “first” and “second” are used only to distinguish similar objects and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated.
[0064] It should be noted that in the embodiments of this application, "connection" can be understood as electrical connection. The connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be a direct connection between A and B, or an indirect connection between A and B through one or more other electrical components.
[0065] The foregoing has provided a detailed description of the circuit board processing method and the circuit board itself, as provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are merely for the purpose of helping to understand this application. Furthermore, those skilled in the art will recognize that, based on the ideas of this application, there may be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this application.
Claims
1. A method for processing a circuit board, characterized in that, include: Double-sided copper-clad laminates are available; A through groove is processed on the double-sided copper-clad board, a first embedded device is placed in the through groove, and the first embedded device is fixed and the signal is fanned out. A third dielectric layer is laminated on the non-signal fan-out side of the first embedded device, and a blind groove is processed on the third dielectric layer; A second embedded device is installed in the blind slot, and signal fan-out is performed on the second embedded device.
2. The circuit board processing method according to claim 1, characterized in that, The provision of the first embedded device within the through groove includes: A first adhesive layer is provided on one side of the double-sided copper-clad laminate, and the first adhesive layer covers the opening on one side of the through groove; The first embedded device is placed in the through groove and attached to the first adhesive layer; After fixing the first embedded device, the process further includes: removing the first adhesive layer.
3. The circuit board processing method according to claim 1, characterized in that, Fixing the first embedded device includes: A first dielectric layer is pressed onto the non-signal fan-out side of the first embedded device; The first dielectric layer is heated and pressurized to allow the colloidal portion of the first dielectric layer to flow into the gap between the first embedded device and the through groove, and to solidify the colloidal portion of the first dielectric layer.
4. The circuit board processing method according to claim 3, characterized in that, Signal fan-out of the first embedded device includes: A second dielectric layer is pressed onto the signal fan-out side of the first embedded device; Laser etching is performed on the position where the second dielectric layer is directly opposite the pad of the first embedded device, so that the pad of the first embedded device is exposed. Laser etching is performed on the position where the first dielectric layer is directly opposite the non-signal fan-out surface of the first embedded device, so that at least part of the non-signal fan-out surface of the first embedded device is exposed.
5. The circuit board processing method according to claim 4, characterized in that, The signal fan-out for the first embedded device further includes: Sputtering is performed on the surfaces of the first dielectric layer and the second dielectric layer to form a copper seed layer; An electroplated copper layer is formed on the copper seed layer by electroplating. A circuit pattern is formed on the electroplated copper layer.
6. The circuit board processing method according to claim 1, characterized in that, The provision of a second embedded device within the blind slot includes: A second adhesive layer is provided at the bottom of the blind groove; The second embedded device is placed in the blind groove and attached to the second adhesive layer.
7. The method for processing a circuit board according to claim 6, characterized in that, The provision of a second adhesive layer at the bottom of the blind groove includes: When the blind groove satisfies H≤100μm, silicone is coated on the bottom of the blind groove by screen printing; When the blind groove satisfies H>100μm, a pre-made silicone film is placed at the bottom of the blind groove using a pick-and-place machine; Where H is the depth of the blind groove.
8. The method for processing a circuit board according to claim 1, characterized in that, The signal fan-out of the second embedded device includes: A fourth medium layer is pressed onto the opening side of the blind groove; Laser etching is performed on the position where the fourth dielectric layer is directly opposite the pad of the second embedded device, so that the pad of the second embedded device is exposed. The surface of the fourth dielectric layer is sputtered to form a copper seed layer, and an electroplated copper layer is formed on the copper seed layer, and a circuit pattern is formed on the electroplated copper layer.
9. The method for processing a circuit board according to any one of claims 1 to 8, characterized in that: The first embedded device is multiple, and the first embedded device includes a chip; The second embedded device is multiple, and the second embedded device includes a chip and a copper base.
10. A circuit board, characterized in that, The circuit board is prepared by the circuit board processing method according to any one of claims 1 to 9.