Memory integrated circuit and method of manufacturing the same
By setting test structures in the dicing area of DRAM chips and employing self-aligned dual or reverse patterning technology to adjust the pitch and position of the insulation structure, the pattern alignment problem during DRAM miniaturization was solved, thereby improving the reliability and manufacturing precision of DRAM.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- WINBOND ELECTRONICS CORP
- Filing Date
- 2025-02-25
- Publication Date
- 2026-07-24
AI Technical Summary
As DRAM cells are miniaturized, limitations in photolithography processes lead to alignment issues between patterns, affecting DRAM reliability. Existing technologies struggle to effectively verify and adjust the relative positions of the insulating structure and character lines.
Test structures are set in the dicing area of a semiconductor chip. Self-aligned dual or reverse patterning technology is used to ensure that the insulation structure and the character lines are kept at an appropriate distance by adjusting the pitch and position relationship of the insulation structure. The test structures are used to observe and verify the relative position of the insulation structure and the character lines in the chip area.
Effective verification and adjustment of the relative positions of the insulation structure and the character lines avoid leakage or parasitic capacitance problems in the capacitor contact structure, thereby improving the reliability and manufacturing precision of DRAM.
Smart Images
Figure CN122458409A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to an integrated circuit and a method for manufacturing the same, and more particularly to a memory integrated circuit and a method for manufacturing the same. Background Technology
[0002] As a type of semiconductor memory, dynamic random access memory (DRAM) is frequently used as the main memory in memory systems due to its advantages such as high storage density and fast operation speed. To further increase storage density, DRAM cells are continuously miniaturized. However, limitations in photolithography processes cause many side effects during DRAM cell miniaturization, such as alignment problems between patterns. While further improving photolithography technology, verification mechanisms must also be designed to ensure the reliability of DRAM. Summary of the Invention
[0003] One embodiment of this disclosure provides a memory integrated circuit, including: a plurality of memory arrays located in a plurality of chip regions of a semiconductor chip; and a plurality of test structures located in a dicing region of the semiconductor chip, wherein the plurality of memory arrays and the plurality of test structures each include a plurality of character lines extending in the same direction and a plurality of insulating structures, wherein the plurality of insulating structures in each memory array are configured to define a plurality of capacitive contact structures, the plurality of insulating structures in each memory array are arranged with a first pitch, and the plurality of insulating structures in each test structure are arranged with a second pitch greater than the first pitch.
[0004] Another embodiment of this disclosure provides a memory integrated circuit, including: a plurality of functional pattern arrays located in a plurality of chip regions of a semiconductor chip; and a plurality of test structures located in a dicing region of the semiconductor chip, wherein the plurality of functional pattern arrays and the plurality of test structures each include a plurality of first patterns and a plurality of second patterns extending in the same direction, wherein the plurality of second patterns in each functional pattern array are configured to define the positions of a plurality of third patterns, the plurality of second patterns in each functional pattern array are arranged with a first pitch, and the plurality of second patterns in each test structure are arranged with a second pitch greater than the first pitch.
[0005] Another embodiment of this disclosure provides a method for manufacturing a memory integrated circuit, comprising: forming a plurality of memory arrays in a plurality of chip regions of a semiconductor chip; and forming a plurality of test structures in a dicing region of the semiconductor chip, wherein the plurality of memory arrays and the plurality of test structures each include a plurality of character lines extending in the same direction and a plurality of insulating structures, wherein the plurality of insulating structures in each memory array are configured to define a plurality of capacitive contact structures, the plurality of insulating structures in each memory array are arranged with a first pitch, and the plurality of insulating structures in each test structure are arranged with a second pitch greater than the first pitch.
[0006] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description
[0007] Figure 1A and Figure 1B This is a plan view of an intermediate structure of a memory integrated circuit during the manufacturing process, as shown in some embodiments of this disclosure;
[0008] Figures 2A to 2F This is a cross-sectional schematic diagram of a series of intermediate structures during a self-aligned dual patterning process for forming a capacitive contact structure, as shown in some embodiments of this disclosure.
[0009] Figure 3A This is a cross-sectional schematic diagram showing an intermediate structure during the stage of forming a first insulating structure for defining a capacitor contact structure, according to some embodiments of this disclosure;
[0010] Figure 3B This illustrates the situation where the character line exhibits pitch walking. Figure 3A A planar schematic diagram of the test structure shown;
[0011] Figures 4A to 4D This is a cross-sectional schematic diagram of a series of intermediate structures during a self-aligned reverse patterning process for forming a capacitive contact structure, as shown in some embodiments of this disclosure.
[0012] Figure 5 This is a cross-sectional schematic diagram illustrating an intermediate structure during the stage of forming a second insulating structure for defining a capacitor contact structure, according to some embodiments of this disclosure.
[0013] Explanation of reference numerals in the attached figures:
[0014] 100: Access transistor
[0015] 102: Active Zone
[0016] 104: Bit line contact structure
[0017] 106, 106a: Insulation structure
[0018] 200: Substrate structure
[0019] 202: First insulating material layer
[0020] 204: Core Pattern
[0021] 206: Lining
[0022] 208: Shell
[0023] 208a, 208c: Lateral extension section
[0024] 208b: Longitudinal extension
[0025] 210: Block
[0026] 212: Second insulating material
[0027] 300: Semiconductor chip
[0028] 302: Chip Area
[0029] 304: Cutting Road Area
[0030] 306, 606: Test Structure
[0031] 500: Dielectric layer
[0032] 502: Second insulating material layer
[0033] 504: Insulation Structure
[0034] BL: Bitline
[0035] D1, D2, D3: Direction
[0036] F1, F2: Far side
[0037] N1, N2: Near edge
[0038] P204: Pitch
[0039] P1, P2: Pitch
[0040] T: Opening
[0041] W204: Width
[0042] WL, WL1, WL2: Character lines Detailed Implementation
[0043] The following description uses DRAM integrated circuits to illustrate the memory integrated circuit disclosed herein. Nevertheless, after understanding the photolithography verification mechanism disclosed herein, it should be understood that this photolithography verification mechanism can also be applied to other memory integrated circuits or any integrated circuit with periodic patterns.
[0044] DRAM integrated circuits comprise multiple memory cells arranged in an array, each including access transistors and memory capacitors coupled to the access transistors. In terms of process sequence, access transistors can be formed on the semiconductor chip first, followed by memory capacitors. Furthermore, after forming the access transistors but before forming the memory capacitors, various components, including bit line contact structures and bit line-capacitor contact structures, can be formed on the semiconductor chip.
[0045] exist Figure 1A In the intermediate stage shown, access transistors 100 have been formed in a semiconductor substrate. Specifically, each access transistor 100 is defined at the intersection of an active region 102 and a character line WL. The character line WL serves as the gate of the access transistor 100, while the portions of the active region 102 located on both sides of the character line WL serve as the drain and source of the access transistor.
[0046] Each active region 102 is shared by two access transistors 100. In these embodiments, each active region 102 is interleaved across two character lines WL. The two access transistors 100 are defined with the portion of their active regions 102 located between the two character lines WL as a shared drain / source.
[0047] The character lines WL extend along direction D1 and are arranged along direction D2, which is perpendicular to direction D1. On the other hand, the active areas 102 may extend along direction D3, which intersects with directions D1 and D2, and are arranged in an array. The active areas 102 in each row are arranged along direction D1, while the active areas 102 in each column are arranged along direction D2. In some embodiments, the active areas 102 in each column are shifted towards direction D2 relative to the two adjacent columns, and the active areas 102 in each row are shifted towards direction D1 relative to the two adjacent rows.
[0048] In addition to access transistor 100, Figure 1A The intermediate stage shown further forms a bit line BL and a bit line contact structure 104 on the semiconductor substrate. One drain / source of each access transistor 100 is connected to a bit line BL through a bit line contact structure 104. The extension direction of the bit line BL may be perpendicular to the extension direction of the character line WL. In an example where the character line WL extends along direction D1, the bit line BL may extend along direction D2. In an embodiment where each active region 102 is shared by two access transistors 100, the bit line BL may be connected to the portion of the active region 102 that serves as a common drain / source through the bit line contact structure 104.
[0049] In addition to connecting one drain / source to the bit line BL, each access transistor 100 also connects its other drain / source to the storage capacitor to be formed subsequently. In an embodiment where each active region 102 is interleaved across two character lines WL and shared by two access transistors 100, each active region 102 uses the middle portion located between the two interleaved character lines WL as the common drain / source of the two access transistors 100 and connects to the bit line BL, while its end portions on both sides are connected to the storage capacitor to be formed subsequently. Figure 1A As shown, the end portions of the active region 102 are each located between the two character lines WL.
[0050] Next, according to some embodiments, an insulating structure will be formed between the character lines WL, which defines a capacitor contact structure for connecting the end portion of the active region 102 to the storage capacitor.
[0051] Please refer to Figure 1B An insulating structure 106 is formed between character lines WL and defines the location of the subsequently formed capacitive contact structure. In some embodiments, the location of the capacitive contact structure is defined using a self-aligned double patterning (SADP) technique. In these embodiments, after forming the insulating structure 106, a filler material is formed around the insulating structure 106, and then the insulating structure 106 is removed to expose the opening defined by the insulating structure 106. The opening is used to accommodate the capacitive contact structure.
[0052] Please refer to Figure 2A First, a first insulating material layer 202 is formed on the substrate structure 200, and a core pattern 204 is formed on the first insulating material layer 202. Although not specifically shown, the substrate structure 200 includes at least Figure 1A The structure is shown. The first insulating material layer 202 completely covers the substrate structure 200 and will be patterned in subsequent steps. Figure 1B The insulating structure 106 is shown. The core pattern 204 is used to form an etched shield for patterning the first insulating material layer 202. In some embodiments, a backing layer 206 is pre-formed on the first insulating material layer 202 before forming the core pattern 204.
[0053] exist Figure 2B In the steps shown, a conformal cover is formed. Figure 2AThe structure shown includes a shell layer 208. Specifically, a first lateral extension 208a of the shell layer 208 covers the top surface of the core pattern 204, while a longitudinal extension 208b of the shell layer 208 covers the sidewalls of the core pattern 204. Additionally, a second lateral extension 208c of the shell layer 208 extends laterally between the core patterns 204.
[0054] exist Figure 2C In the steps shown, an isotropic etching process is performed to remove the first lateral extension 208a and the second lateral extension 208c of the shell 208, and to remove the core pattern 204. As a result, the longitudinal extension 208b of the shell 208 that originally existed on both sides of each core pattern 204 is left, which is also called the shield 210. In this way, each core pattern 204 is converted into two shields 210, and the pattern pitch is halved.
[0055] exist Figure 2D In the steps shown, the portion of the first insulating material layer 202 not shielded by the shield 210 is removed by an etching process, and then the shield 210 is removed. As a result, the remaining portion of the first insulating material layer 202 forms a reference. Figure 1B The insulation structure 106 is described.
[0056] exist Figure 2E In the steps shown, a second insulating material layer 212 is formed comprehensively. The second insulating material layer 212 fills the space surrounding the insulating structure 106 and can be formed to a height exceeding the top of the insulating structure 106. Furthermore, the material of the second insulating material layer 212 is selected to have a sufficient etching selectivity relative to the insulating structure 106. As an example, if the material of the insulating structure 106 (i.e., the material of the first insulating material layer 202) is silicon oxide, the material of the second insulating layer 212 can be silicon nitride.
[0057] exist Figure 2F In the steps shown, the second insulating material layer 212 is planarized until the insulating structure 106 is exposed. Subsequently, the insulating structure 106 is removed, forming an opening T in the second insulating material layer 212. In subsequent steps, a capacitive contact structure (not shown) is formed in the opening T.
[0058] As described above, the core pattern 204 defines a shield 210 with double the quantity and half the pitch, and the shield 210 defines the outline of the insulating structure 106. Furthermore, by removing the insulating structure 106, an opening T is defined in the second insulating material layer 212, which determines the position of the capacitor contact structure. Therefore, the pattern of the capacitor contact structure is defined by the insulating structure 106, and the pattern of the insulating structure 106 is influenced by the core pattern 204.
[0059] As a result of continuous miniaturization, the spacing between the insulating structure 106 and the character line WL becomes very short (e.g., ...). Figure 1B (As shown). In certain cases, the insulation structure 106 may even overlap with the character line WL. This could cause the capacitor contact structure to be improperly spaced from the character line WL, potentially leading to leakage current or increased parasitic capacitance between the two.
[0060] To verify the above issues, in addition to forming in the chip region of the semiconductor substrate Figure 1B In addition to the structure shown, a test structure is formed within the dicing region of the semiconductor substrate. The test structure within the dicing region is the same as the array structure within the chip region, except that the test structure includes fewer repeating units and differs in the design of the insulating structure. By observing the relative positional relationship between the insulating structure 106 and the character line WL in the test structure, the relative positional relationship between the insulating structure 106 and the character line WL within the chip region can be accurately determined.
[0061] like Figure 3A As shown, the semiconductor chip 300 includes chip regions 302 arranged in an array and dicing channels 304 extending between the chip regions 302. Figure 1B The array structure shown is disposed in chip region 302, while the test structure 306 is disposed in dicing region 304. The test structure 306 is similar to the array structure in chip region 302, and also includes components such as active region 102, character line WL, bit line contact structure 104, bit line BL, and insulating structure 106. However, compared to the array structure in chip region 302, the test structure 306 includes fewer repeating units, and differs in the pitch of the insulating structure 106.
[0062] Specifically, the insulating structure 106 in the chip region 302 has a pitch P1, while the insulating structure 106 in the test structure 306 of the dicing region 304 has a pitch P2 greater than the pitch P1. In some embodiments, the pitch P2 is approximately twice the pitch P1. In these embodiments, the insulating structure 106 in the chip region 302 is alternately arranged with character lines WL, while the insulating structures 106 in the test structure 306 of the dicing region 304 are spaced apart between the character lines WL. More specifically, in the test structure 306 of the dicing region 304, an insulating structure 106 is placed every two character lines WL in the direction D2. This results in two character lines WL being placed between adjacent insulating structures 106 within the test structure 306. In contrast, an insulating structure 106 is placed every other character line WL within the chip region 302, resulting in only a single character line WL between adjacent insulating structures 106.
[0063] Since the insulating structures 106 are spaced apart between the character lines WL within the test structure 306 of the cut channel area 304, even when the spacing between the insulating structure 106 and the adjacent character line WL is quite short or even when they partially overlap, at least a portion of the outline of the character line WL can still be observed. In this way, it is still possible to verify whether an appropriate distance is maintained between the insulating structures 106 and the adjacent character lines WL by observing the outlines of each insulating structure 106 and the partial outlines of the adjacent character lines WL. For example, when the opposite sides of the insulating structure 106a are quite close to the near edges N1 and N2 of the character lines WL1 and WL2, it is difficult to observe the spacing between the opposite sides of the insulating structure 106a and the near edges N1 and N2 of the character lines WL1 and WL2. Even so, the relative positional relationship between the insulating structure 106a and the character lines WL1 and WL2 can still be identified by the relationship between the opposite sides of the insulating structure 106a and the far edges F1 and F2 of the character lines WL1 and WL2, since no insulating structure 106 is provided at the far edges F1 and F2 of the character lines WL1 and WL2. Therefore, the relative positional relationship between the insulating structure 106 and the character lines WL within the chip area 302 can be accurately identified by observing the insulating structure 106 and the character lines WL within the test structure 306.
[0064] Using self-aligned dual patterning technology (see reference) Figures 2A to 2F In the embodiment where the insulation structure 106 is defined as described, this can be achieved by having the core pattern 204 in the chip region 302 and the core pattern 204 in the test structure 306 of the dicing region 304 have different widths and pitches. Figure 3A The design is shown. Specifically, in these embodiments, the width W204 of the core pattern 204 within the test structure 306 is approximately twice the width W204 of the core pattern 204 within the chip region 302, and the pitch P204 of the core pattern 204 within the test structure 306 is approximately twice the pitch P204 of the core pattern 204 within the chip region 302.
[0065] In the embodiment where self-aligned dual patterning is used to define both the character line WL and the insulating structure 106, the center line of the core pattern 204 within the test structure 306 that defines the insulating structure 106 is substantially aligned with the center line of the core pattern (not shown) that defines the character line WL. In contrast, the center line of the core pattern 204 within the chip region 302 that defines the insulating structure 106 is offset relative to the center line of the core pattern (not shown) that defines the character line WL.
[0066] Please refer to Figure 3BWhen the pitch of the character line WL fluctuates, the pitch size of the character line WL alternates. As a result, the character lines WL on both sides of each insulating structure 106 may move toward the insulating structure 106 between them, partially overlapping the insulating structure 106 between them. Even so, each character line WL has at least one other side that does not overlap with any insulating structure 106. This means that the relative positional relationship between the insulating structure 106 and the character line WL in the chip area 302 can be verified by observing the relationship between the outline of each insulating structure 106 within the test structure 306 and the outline of the unshielded side of the adjacent character line WL. Due to the increased pitch of the insulating structure 106 within the test structure 306, even if severe character line WL pitch fluctuations occur, the character line WL can be prevented from being completely obscured, and pattern verification can be performed using the exposed portion of the character line WL.
[0067] In the embodiments described above, a self-aligned dual patterning technique is used to define the capacitive contact structure. In other embodiments, a self-aligned reverse patterning technique is used to define the capacitive contact structure.
[0068] The self-aligned reverse patterning process is similar to the self-aligned double patterning process in the first half, and also includes a reference. Figure 2A and Figure 2B The steps described above. After forming shell 208, as... Figure 4A As shown, the second lateral extension 208c of the shell 208 is removed, while the first lateral extension 208a and the longitudinal extension 208b are retained, and a dielectric layer 500 is formed to fully cover the resulting structure. In some embodiments, the first lateral extension 208a of the shell 208 may also be removed before forming the dielectric layer 500, leaving only the longitudinal extension 208b of the shell 208. To allow for selective removal of the retained portions of the shell 208 in subsequent steps, the material of the shell 208 should have sufficient etching selectivity relative to the materials of the dielectric layer 500 and the core pattern 204.
[0069] exist Figure 4B At the stage shown, the top of the dielectric layer 500 is first removed to expose the remaining portion of the shell layer 208. Then, the remaining portion of the shell layer 208 is selectively removed, leaving only the core pattern 204 and the remaining portion of the dielectric layer 500. Next, an etching operation is performed using the core pattern 204 and the remaining portion of the dielectric layer 500 as a shield. As a result, the portion of the first insulating material layer 202 (and the substrate 206) that is not shielded by the above-mentioned shield is removed, and an opening T is formed in the first insulating material layer 202.
[0070] exist Figure 4CAt the stage shown, a second insulating material layer 502 is formed on the current structure. Specifically, the second insulating material layer 502 fills the opening T in the first insulating material layer 202 and extends further on the top surface of the first insulating material layer 202. To allow for selective removal of the first insulating material layer 202 in subsequent steps, the material of the second insulating material layer 502 has sufficient etching selectivity relative to the material of the first insulating material layer 202.
[0071] exist Figure 4D At the stage shown, the top of the second insulating layer 502 can be removed until the first insulating layer 202 is exposed. As a result, the portion of the second insulating layer 502 that fills the opening T in the first insulating layer 202 is left. Next, the first insulating layer 202 can be selectively removed, leaving the remaining portion of the second insulating layer 502, which is also referred to as the insulating structure 504.
[0072] Subsequently, capacitive contact structures (not shown) are formed between the insulating structures 504. As can be seen from the above method, the longitudinal extension 208b of the shell layer 208 is defined by the core pattern 204, which further defines the opening T in the first insulating material layer 202. The opening T determines the position of the insulating structures 504, and the gap between the insulating structures 504 determines the position of the capacitive contact structures.
[0073] Figure 5 The embodiments are similar to Figure 3A The embodiments, only in Figure 5 In the illustrated embodiment, the position of the capacitor contact structure is defined by the gaps between the insulating structures 504. For example... Figure 5 As shown, in chip region 302, insulating structures 504 overlap character lines WL and are arranged periodically at a pitch P1. On the other hand, in test structure 606 of dicing track 304, insulating structures 504 are located between adjacent character lines WL and are arranged periodically at a pitch P2 greater than the pitch P1. In some embodiments, the pitch P2 is approximately twice the pitch P1. In these embodiments, the insulating structures 504 in test structure 606 are spaced apart between character lines WL. Furthermore, in test structure 606, an insulating structure 504 is provided on one side of each character line WL, while no insulating structure 504 is provided on the other side, so at least one side is not obscured by any insulating structure 504.
[0074] Using self-aligned reverse patterning technology (see reference) Figures 4A to 4D In the embodiment where the insulating structure 504 is defined as described, this can be achieved by having the core pattern 204 in the chip region 302 and the core pattern 204 in the test structure 606 of the dicing region 304 have different widths and pitches. Figure 5The design is shown. Specifically, in these embodiments, the width W204 of the core pattern 204 within the test structure 606 is approximately twice the width W204 of the core pattern 204 within the chip region 302, and the pitch P204 of the core pattern 204 within the test structure 306 is approximately twice the pitch P204 of the core pattern 204 within the chip region 302.
[0075] In the embodiment where self-aligned dual patterning is used to define both the character line WL and the insulating structure 504, the center line of the core pattern 204 within the test structure 606 used to define the insulating structure 504 is substantially aligned with the center line of the core pattern (not shown) used to define the character line WL. Conversely, the center line of the core pattern 204 within the chip region 302 used to define the insulating structure 504 is also substantially aligned with the center line of the core pattern (not shown) used to define the character line WL.
[0076] In summary, this disclosure provides a memory integrated circuit and a method for manufacturing the same. The memory integrated circuit includes a memory array formed in a chip region of a semiconductor chip, and a test structure formed in a dicing region of the semiconductor chip. The test structure is similar to the memory array in the chip region and is used to verify the pattern configuration of the memory array in the chip region. Both the memory array in the chip region and the test structure in the dicing region include multiple character lines and multiple insulating structures defining capacitor contact structures. The character lines and insulating structures extend in the same direction. Within the chip region, the character lines and insulating structures are arranged alternately. On the other hand, within the test structure in the dicing region, insulating structures are spaced apart between the character lines. This ensures that at least one side of each character line in the test structure is free of any insulating structure. Even if the insulating structures are quite close to or partially overlap the character lines, at least one side of each character line will not be obscured by any insulating structure. In this way, the relative positional relationship between the insulating structures and the character lines within the test structure can still be observed, and the relative positional relationship between the character lines and the insulating structures within the chip region can be determined. Accordingly, the relative positional relationship between the character lines and the capacitor contact structures within the chip region can be accurately verified. Alternatively, within the test structure of the cut track area, the insulation structure overlaps the character lines at intervals. This ensures that the character lines on both sides of the insulation structure are not obscured, allowing for identification of the relative positional relationship between the character lines and the insulation structure.
[0077] As described above, the photolithographic verification mechanism provided in this disclosure embodiment can also be applied to the manufacture of other memory integrated circuits or any integrated circuit with periodic patterns. Specifically, the array structure within the chip region can be replaced with a functional pattern array different from the DRAM array, and a test structure is correspondingly formed within the dicing channel according to the method described herein. As an example, the functional pattern array and the test structure each include multiple first patterns resembling character lines and multiple second patterns resembling the aforementioned insulating structure. The second patterns are configured to define the position of a third pattern resembling a capacitor contact structure. Furthermore, the second patterns in the functional pattern array are arranged with a first pitch, and the second patterns in the test structure are arranged with a second pitch greater than the first pitch. In some embodiments, a second pattern is placed every two first patterns in each test structure. In some embodiments, the first and second patterns are alternately arranged in each functional pattern array. In some embodiments, at least one side of each first pattern in each test structure is not adjacent to or overlaps with any second pattern. In some embodiments, the first patterns in each functional pattern array overlap with a second pattern.
Claims
1. A memory integrated circuit, comprising: Multiple memory arrays located in multiple chip regions of a semiconductor chip; as well as Multiple test structures located in the dicing zone of the semiconductor chip. The plurality of memory arrays and the plurality of test structures each include a plurality of character lines extending in the same direction and a plurality of insulating structures. In each memory array, the plurality of insulating structures are configured to define a plurality of capacitive contact structures. The plurality of insulating structures in each memory array are arranged with a first pitch, and the plurality of insulating structures in each test structure are arranged with a second pitch greater than the first pitch.
2. The memory integrated circuit according to claim 1, wherein one of the plurality of insulating structures is placed every other one of the plurality of character lines in each test structure.
3. The memory integrated circuit according to claim 1, wherein the plurality of character lines and the plurality of insulating structures are arranged alternately in each memory array.
4. The memory integrated circuit of claim 2, wherein in each test structure, at least one side of each character line is not adjacent to any of the plurality of insulating structures.
5. The memory integrated circuit according to claim 2, wherein in each memory array, the plurality of character lines overlap one of the plurality of insulating structures.
6. The memory integrated circuit of claim 1, wherein the second pitch is approximately twice the first pitch.
7. The memory integrated circuit of claim 1, wherein the positions of the plurality of insulating structures in each memory array define the positions of the plurality of capacitor contact structures.
8. The memory integrated circuit of claim 1, wherein the gaps between the plurality of insulating structures in each memory array define the positions of the plurality of capacitor contact structures.
9. A memory integrated circuit, comprising: Multiple functional pattern arrays located in multiple chip regions of a semiconductor chip; as well as Multiple test structures located in the dicing zone of the semiconductor chip. The plurality of functional pattern arrays and the plurality of test structures each include a plurality of first patterns and a plurality of second patterns extending in the same direction. The plurality of second patterns in each functional pattern array are configured to define the positions of a plurality of third patterns. The plurality of second patterns in each functional pattern array are arranged with a first pitch, and the plurality of second patterns in each test structure are arranged with a second pitch greater than the first pitch.
10. The memory integrated circuit of claim 9, wherein in each test structure, one of the plurality of second patterns is placed every other one of the plurality of first patterns.
11. The memory integrated circuit of claim 9, wherein the plurality of first patterns and the plurality of second patterns are alternately arranged in each functional pattern array.
12. The memory integrated circuit of claim 10, wherein in each test structure, at least one side of each first pattern is not adjacent to any of the plurality of second patterns.
13. The memory integrated circuit of claim 10, wherein in each functional pattern array, the plurality of first patterns overlap one of the plurality of second patterns.
14. A method for manufacturing a memory integrated circuit, comprising: Multiple memory arrays are formed in multiple chip regions of a semiconductor chip; as well as Multiple test structures are formed in the dicing zone of the semiconductor chip. The plurality of memory arrays and the plurality of test structures each include a plurality of character lines extending in the same direction and a plurality of insulating structures. In each memory array, the plurality of insulating structures are configured to define a plurality of capacitive contact structures. The plurality of insulating structures in each memory array are arranged with a first pitch, and the plurality of insulating structures in each test structure are arranged with a second pitch greater than the first pitch.
15. The method of manufacturing a memory integrated circuit according to claim 14, wherein forming the plurality of insulating structures in each of the memory arrays or test structures comprises: A first insulating material layer is formed on the substrate structure; Multiple core patterns are formed on the first insulating material layer; A shell is formed that conformally covers the plurality of core patterns and the first insulating material layer; Remove the lateral extension of the shell while retaining the longitudinal extension of the shell covering the sidewalls of the plurality of core patterns; Remove the aforementioned multiple core patterns; The first insulating material layer is etched using the longitudinally extended portion of the shell as a shield, thereby patterning the first insulating material layer into the plurality of insulating structures; as well as Remove the longitudinally extended portion of the shell.
16. The method for manufacturing a memory integrated circuit according to claim 15, wherein the width of each core pattern in each test structure is approximately twice the width of each core pattern in each memory array, and the pitch of the plurality of core patterns in each test structure is approximately twice the pitch of the plurality of core patterns in each memory array.
17. The method of manufacturing a memory integrated circuit according to claim 14, wherein forming the plurality of insulating structures in each memory array or each test structure comprises: An insulating material layer is formed on the substrate structure; Multiple core patterns are formed on the insulating material layer; A shell is formed that conformally covers the multiple core patterns; A dielectric layer is formed that fully covers the shell layer and the insulating material layer; Remove the shell layer; The insulating material layer is etched using the multiple core patterns and the dielectric layer as shielding to form multiple openings in the insulating material layer; as well as The plurality of insulating structures are filled into the plurality of openings.
18. The method for manufacturing a memory integrated circuit according to claim 17, wherein the width of each core pattern in each test structure is approximately twice the width of each core pattern in each memory array, and the pitch of the plurality of core patterns in each test structure is approximately twice the pitch of the plurality of core patterns in each memory array.