Semiconductor memory device

Abstract

A semiconductor memory device is provided, which includes memory cells arranged three-dimensionally. The semiconductor memory device includes: a plurality of cell regions including a plurality of conductive patterns and arranged two-dimensionally along first and second directions intersecting each other, each cell region including conductive patterns of the plurality of conductive patterns extending in a third direction; and a plurality of pad patterns connected to the plurality of conductive patterns, respectively, wherein, in a top view intersecting the third direction, for each cell region, a first cell pitch in the first direction is larger than a second cell pitch in the second direction, wherein, in the top view, each pad pattern has a quadrangular shape including a first side and a second side intersecting each other, wherein, in the top view, for each pad pattern, a length of the first side and a length of the second side are both larger than the second cell pitch, and wherein, in the top view, for each pad pattern, an angle between the first side and the first direction is an acute angle.

Description

Technical Field

[0001] This disclosure relates to semiconductor memory devices. More specifically, this disclosure relates to a semiconductor memory device comprising memory cells arranged in three dimensions. Background Technology

[0002] With the increasing demand for semiconductor memory devices capable of storing high-capacity data in electronic systems, solutions for increasing the data storage capacity of semiconductor memory devices are being researched. One such solution involves semiconductor memory devices comprising three-dimensionally arranged memory cells instead of two-dimensionally arranged memory cells. Summary of the Invention

[0003] The technical objective of this disclosure is to provide a semiconductor memory device with improved process margins.

[0004] The technical objectives of this disclosure are not limited to those mentioned above, and other technical objectives not mentioned can be clearly understood by those skilled in the art from the following description.

[0005] According to one aspect of this disclosure, a semiconductor memory device is provided, the semiconductor memory device comprising: a plurality of cell regions, the plurality of cell regions including a plurality of conductive patterns and arranged two-dimensionally along a first direction and a second direction intersecting each other, each cell region including a conductive pattern of the plurality of conductive patterns extending upward on a third direction intersecting the first direction and the second direction; and a plurality of pad patterns correspondingly connected to the plurality of conductive patterns, wherein, in a top view intersecting the third direction, for each cell region of the plurality of cell regions, a first cell pitch in the first direction is larger than a second cell pitch in the second direction, wherein, in the top view, each of the plurality of pad patterns is a quadrilateral shape including a first side and a second side intersecting each other, wherein, in the top view, the length of the first side and the length of the second side are both larger than the second cell pitch, and wherein, in the top view, for each of the plurality of pad patterns, the angle between the first side of the pad pattern and the first direction is an acute angle.

[0006] According to one aspect of this disclosure, a semiconductor memory device is provided, the semiconductor memory device comprising: a plurality of cell regions arranged two-dimensionally along a first direction and a second direction intersecting each other; a plurality of strip patterns located on the plurality of cell regions, each of the plurality of strip patterns extending in the first direction; and a plurality of pad patterns located on and correspondingly connected to the plurality of strip patterns; wherein each of the plurality of cell regions comprises: a plurality of unit memory cells arranged upward in a third direction intersecting the first direction and the second direction; and a conductive pattern extending upward in the third direction and connected to the plurality of unit memory cells, wherein each of the plurality of strip patterns connects n conductive patterns arranged along the first direction to each other, where n is a natural number of 2 or greater, wherein each of the plurality of pad patterns is square in shape in a top view intersecting the third direction, and wherein for each of the plurality of pad patterns, the angle between one side of the pad pattern and the first direction is an acute angle.

[0007] According to one aspect of this disclosure, a semiconductor memory device is provided, the semiconductor memory device comprising: a first substrate, the first substrate including a first surface and a second surface opposite to each other; a plurality of cell regions located on the first surface, the plurality of cell regions including a plurality of conductive patterns and arranged two-dimensionally along a first direction and a second direction parallel to and intersecting each other with the first surface, and each cell region including a conductive pattern extending upward from a third conductive pattern intersecting the first direction and the second direction; a plurality of pad patterns located on the plurality of cell regions and correspondingly connected to the plurality of conductive patterns; a second substrate, the second substrate including a third surface facing the first surface and a fourth surface opposite to the third surface; and a peripheral circuit element layer, the peripheral circuit element layer, the second substrate including a first surface and a second surface opposite to the first surface; and a third surface facing the first surface and a fourth surface opposite to the third surface; and a peripheral circuit element layer, the second substrate including a first surface and a second surface opposite to the first surface and a third surface opposite to the first surface and a third surface opposite to the first surface and a third surface opposite to the first surface and a third surface opposite to the first surface and a fourth ... fourth surface opposite to the first surface and a third surface opposite to A surrounding circuit element layer is disposed on the third surface, wherein each of the plurality of cell regions includes a plurality of unit storage cells arranged in the third direction, wherein each of the plurality of unit storage cells includes: a semiconductor pattern extending in the first direction and connected to the conductive pattern of the cell region; a data storage structure connected to the semiconductor pattern; and a gate electrode extending in the second direction and intersecting the semiconductor pattern between the conductive pattern and the data storage structure in the cell region, wherein each of the plurality of pad patterns is square in a top view intersecting the third direction, and wherein for each of the plurality of pad patterns, the angle between one side of the pad pattern and the first direction is an acute angle.

[0008] Specific details of other embodiments are included in the detailed description and the accompanying drawings. Attached Figure Description

[0009] The above and other aspects and features of this disclosure will become clearer from the detailed description of embodiments thereof with reference to the accompanying drawings, in which: Figure 1 This is an example block diagram illustrating a semiconductor memory device according to some embodiments.

[0010] Figure 2 This is a schematic perspective view illustrating a semiconductor memory device according to some embodiments.

[0011] Figure 3 This is a schematic top view illustrating a semiconductor memory device according to some embodiments.

[0012] Figure 4 It is shown Figure 3 A 3D view of each unit area.

[0013] Figure 5 This is an example top view illustrating a pad pattern of a semiconductor memory device according to some embodiments.

[0014] Figure 6 This is an example perspective view illustrating a pad pattern of a semiconductor memory device according to some embodiments.

[0015] Figure 7 This is an example top view illustrating a pad pattern of a semiconductor memory device according to some embodiments.

[0016] Figure 8 This is an example perspective view illustrating a pad pattern of a semiconductor memory device according to some embodiments. Detailed Implementation

[0017] The present disclosure will now be described more fully below with reference to the accompanying drawings, in which various embodiments are illustrated. However, the invention may be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. It should also be emphasized that the present disclosure provides details of alternative examples, but this enumeration of alternatives is not exhaustive. Furthermore, any consistency in details among the various examples should not be construed as requiring such details. Items described herein in the singular may be provided in the plural, as can be seen, for example, in the drawings. Therefore, unless the context otherwise indicates, the description of a single item provided in the plural should be understood to apply to the remaining multiple items. Reference should be made to the language of the claims when determining the claims of the invention.

[0018] Throughout this specification, when a component is described as “comprising” a particular element or group of elements, it should be understood that, unless the context otherwise indicates, the component may be formed solely by that element or group of elements, or that the element or group of elements may be combined with additional elements to form the component. On the other hand, the term “composed of” indicates that a component is formed solely by the listed (one or more) elements.

[0019] It will be understood that when an element is referred to as being "connected" or "attached" to another element or "on" another element, it can be directly connected or attached to another element or on another element, or there may be intermediate elements present. In contrast, when an element is referred to as being "directly connected" or "directly attached" to another element, or as being "in contact" with another element or "in contact" with another element (or using any form of the word "in contact"), there are no intermediate elements at the point of contact.

[0020] As used herein, items described as "electrically connected" are configured such that electrical signals can be conducted from one item to another. Therefore, passive conductive components (e.g., wires, pads, internal wires, etc.) physically connected to passive electrically insulating components (e.g., prepreg layers of printed circuit boards, electrically insulating adhesives connecting two devices, electrically insulating underfills or molding layers, etc.) are not electrically connected to those components. Furthermore, items "directly electrically connected" to each other are electrically connected via one or more passive elements such as, for example, wires, pads, internal wires, through-paths, etc. Therefore, directly electrically connected components do not include components electrically connected via active elements (such as transistors or diodes). Directly electrically connected components can be directly physically connected and directly electrically connected.

[0021] Terms such as “identical,” “equal,” “plane,” “coplanar,” “parallel,” and “perpendicular” as used herein cover similarity or near-identity, including variations that may occur due to conventional manufacturing processes. The term “substantially” may be used herein to emphasize this meaning unless the context or other statement indicates otherwise.

[0022] Ordinal numbers such as "first," "second," and "third" can be simply used as labels to distinguish certain elements, steps, etc., from one another. Terms not described using "first," "second," etc., in the specification may still be referred to as "first" or "second" in the claims. Furthermore, a term referenced with a specific ordinal number (e.g., "first" in a particular claim) may be referenced elsewhere without an ordinal number or with a different ordinal number (e.g., "second" in the specification or another claim).

[0023] In the following text, reference will be made to Figures 1 to 8 A semiconductor memory device according to an example embodiment is described.

[0024] Figure 1 This is an example block diagram used to illustrate a semiconductor memory device according to some embodiments.

[0025] refer to Figure 1 According to some embodiments, a semiconductor memory device includes a memory cell array 10, a row decoder 20, a sense amplifier 30, a column decoder 40, and control logic 50.

[0026] Storage cell array 10 may include multiple storage cells arranged in three dimensions (e.g., Figure 2 (MC). The memory cell array 10 can be connected to the row decoder 20 via multiple word lines WL. In addition, the memory cell array 10 can be connected to the sense amplifier 30 via multiple bit lines BL.

[0027] Row decoder 20 can decode an address input from an external source to select one of a plurality of word lines WL connected to memory cell array 10. The address decoded by row decoder 20 can be provided to row driver (not shown). Row driver can provide a predetermined voltage to each of the selected word line WL and the unselected word line WL in response to control of control circuitry.

[0028] The sense amplifier 30 can sense, amplify, and output the voltage change of a selected bit line BL among multiple bit lines BL based on the address decoded by the column decoder 40. For example, the sense amplifier 30 can sense, amplify, and output the difference between the voltage of the selected bit line BL and the voltage of the reference bit line.

[0029] The column decoder 40 can provide a data transfer path between the sense amplifier 30 and an external device (e.g., a memory controller). The column decoder 40 can decode addresses input from an external source and select one of multiple word lines WL based on the decoded address.

[0030] Control logic 50 can generate control signals for controlling write and / or read operations on each memory cell of memory cell array 10.

[0031] Figure 2 This is a schematic perspective view illustrating a semiconductor memory device according to some embodiments.

[0032] refer to Figure 1 and Figure 2 According to some embodiments, a semiconductor memory device includes a memory cell structure (CELL) and a peripheral circuit structure (PERI).

[0033] The storage cell structure CELL may include a first substrate 100 and a plurality of storage cells MC located on the first substrate 100.

[0034] The first substrate 100 may be made of bulk silicon or silicon-on-insulator (SOI). The first substrate 100 may be a silicon substrate, or may include materials other than silicon, such as silicon germanium, gallium arsenide, silicon germanium-on-insulator (SGOI), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or aluminum antimonide. Alternatively, the first substrate 100 may include a base substrate and an epitaxial layer formed on the base substrate, or may include a ceramic substrate, a quartz substrate, a display glass substrate, etc.

[0035] The first substrate 100 may include a first surface 100a and a second surface 100b opposite to each other. In the following description, the first surface 100a may also be referred to as the front side or front surface of the first substrate 100, and the second surface 100b may also be referred to as the back side or back surface or rear surface of the first substrate 100.

[0036] Multiple memory cells MC can be formed on a first surface 100a of a first substrate 100. The multiple memory cells MC can be arranged in three dimensions. For example, multiple cell strings STR arranged in two dimensions along a first direction X and a second direction Y, parallel to and intersecting each other with the upper surface (e.g., the first surface 100a) of the first substrate 100. Each cell string STR may include multiple memory cells MC arranged along a third direction Z, intersecting the upper surface (e.g., the first surface 100a) of the first substrate 100.

[0037] Each memory cell MC can be connected to intersecting word lines WL and bit lines BL and is positioned between the intersecting word lines WL and bit lines BL. For example, each word line WL can extend in a second direction Y, and memory cells MC arranged in the second direction Y can be collectively connected to each word line WL. For example, each bit line BL can extend in a third direction Z, and memory cells MC arranged in the third direction Z can be collectively connected to each bit line BL.

[0038] Each storage unit (MC) may include a selection element (SW) and a data storage element (DS) connected in series with each other.

[0039] A selector element SW can be connected to the bit line BL and the data storage element DS, and is disposed between the bit line BL and the data storage element DS. The selector element SW can be configured to selectively control the charge flow to be supplied to the data storage element DS. For example, the selector element SW can include at least one of a diode, a PNP bipolar transistor, an NPN bipolar transistor, an NMOS field-effect transistor, a PMOS field-effect transistor, or a combination thereof. In some embodiments, the selector element SW can be a field-effect transistor (FET). For example, the gate of the selector element SW can be connected to the word line WL, and the source and drain of the selector element SW can be connected to the bit line BL and the data storage element DS, respectively.

[0040] The data storage element DS can be controlled by word lines WL and bit lines BL to store data in each memory cell MC. For example, the data storage element DS may include a capacitor and / or a variable resistor. In some embodiments, each memory cell MC may be a unit memory cell of dynamic random access memory (DRAM). For example, the data storage element DS may be a capacitor.

[0041] The peripheral circuit structure PERI may include a second substrate 200 and a peripheral circuit element layer 250 located on the second substrate 200.

[0042] The second substrate 200 may include, for example, a semiconductor substrate, such as a silicon substrate, a germanium substrate, or a silicon-germanium substrate. Alternatively, the second substrate 200 may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0043] The second substrate 200 may include a third surface 200a and a fourth surface 200b opposite to each other. In the following description, the third surface 200a may also be referred to as the front side or front surface of the second substrate 200, and the fourth surface 200b may also be referred to as the back side or back surface or rear surface of the second substrate 200.

[0044] The peripheral circuit element layer 250 may be formed on the third surface 200a of the second substrate 200. The peripheral circuit element layer 250 may constitute peripheral circuitry for controlling the operation of the semiconductor memory device. For example, the peripheral circuit element layer 250 may include a row decoder (e.g., Figure 1 20), readout amplifier (e.g., Figure 1 30), column decoder (e.g., Figure 1 40) and / or control logic (e.g., Figure 1 (50).

[0045] The peripheral circuit element layer 250 may include, for example, transistors. However, this disclosure is not limited thereto. For example, the peripheral circuit element layer 250 may include various passive elements such as capacitors, resistors, and inductors, as well as various active elements such as transistors.

[0046] In some embodiments, the storage cell structure (CELL) and the peripheral circuit structure (PERI) can be stacked along a third direction (Z).

[0047] According to some embodiments, semiconductor memory devices may have a chip-to-chip (C2C) structure. A C2C structure means that a lower chip, including a memory cell structure (CELL), is fabricated on a first wafer, and an upper chip, including a peripheral circuit structure (PERI), is fabricated on a second wafer different from the first wafer, and then the lower and upper chips are connected to each other in a bonding manner.

[0048] For example, the bonding method can refer to a scheme in which a first bonding metal 195, which is formed as the uppermost metal layer of the lower chip, and a second bonding metal 295, which is formed as the uppermost metal layer of the upper chip, are connected to each other. For example, when each of the first bonding metal 195 and the second bonding metal 295 is made of copper (Cu), the bonding scheme can be a Cu-Cu bonding scheme. However, this is merely an example, and the first bonding metal 195 and the second bonding metal 295 can be made of various other metals such as aluminum (Al) or tungsten (W), respectively.

[0049] With the first bonding metal 195 and the second bonding metal 295 bonded together, the memory cell structure CELL and the peripheral circuit structure PERI can be electrically connected to each other.

[0050] Figure 3 This is a schematic top view used to illustrate a semiconductor memory device according to some embodiments. Figure 4 It is used to show Figure 3 A 3D view of each unit area.

[0051] refer to Figures 1 to 3 According to some embodiments, a semiconductor memory device includes multiple cell regions CA and multiple pad patterns 190.

[0052] Multiple unit regions CA can be arranged in two dimensions along a first direction X and a second direction Y that intersect (e.g., are orthogonal). For example, multiple unit regions CA can be arranged in a lattice form along the first direction X and the second direction Y.

[0053] Multiple unit regions CA may include multiple conductive patterns 120. Each of the multiple conductive patterns 120 may extend in an elongated manner in a third direction Z that intersects (e.g., is orthogonal) the first direction X and the second direction Y. For example, as Figure 3 As shown, each cell region CA may include a conductive pattern 120 extending in the Z direction. In a semiconductor memory device according to some embodiments, each conductive pattern 120 may be provided as Figure 1 and Figure 2 The bit line BL.

[0054] Multiple pad patterns 190 can be formed on multiple cell regions CA. The multiple pad patterns 190 can be spaced apart from each other. Each pad pattern 190 can be electrically connected to at least one conductive pattern 120. For example, as... Figure 3 As shown, multiple pad patterns 190 corresponding to multiple conductive patterns 120 can be formed. In some embodiments, the number of conductive patterns 120 and the number of pad patterns 190 can have a 1:1 correspondence. In some embodiments, the number of conductive patterns 120 and the number of pad patterns 190 can have an n:1 correspondence (where n is a natural number of 2 or greater).

[0055] In some embodiments, each pad pattern 190 can be provided as Figure 2 The first bonding metal 195. However, this disclosure is not limited thereto.

[0056] Each unit region CA can have a first unit pitch in the first direction X. CAx First unit pitch CAxIt can be defined, for example, as a periodic arrangement of cell regions CA so that they are spaced apart from each other along a first direction X.

[0057] Each unit region CA can have a second unit pitch in the second direction Y. CAy Second unit pitch CAy It can be defined, for example, as a periodic arrangement of cell regions CA so that they are spaced apart from each other along the second direction Y.

[0058] The first unit pitch of each unit region CA CAx It can be greater than the second element pitch of each element region CA. CAy For example, the first unit pitch CAx It can be the second unit pitch. CAy Two times or more, five times or more, or ten times or more. First unit pitch CAx It can be the second unit pitch. CAy 100 times or less, 50 times or less, or 20 times or less. However, this disclosure is not limited thereto.

[0059] In a top view intersecting a third direction Z (e.g., in the XY plane), each pad pattern 190 may include a first side S1 and a second side S2 that intersect each other. In some embodiments, each pad pattern 190 may be quadrilateral in shape. In this regard, the quadrilateral shape includes a quadrilateral shape with rounded corners. For example, each pad pattern 190 may be rectangular in shape including a first side S1 and a second side S2 that are orthogonal to each other.

[0060] Each of the length Wa of the first side S1 and the length Wb of the second side S2 can be greater than the second unit pitch. CAy In some embodiments, each of the length Wa of the first side S1 and the length Wb of the second side S2 may be less than the first unit pitch. CAx In some embodiments, each pad pattern 190 may be square. For example, the length Wa of the first side S1 and the length Wb of the second side S2 may be equal to each other.

[0061] In a top view intersecting a third direction Z (e.g., in the XY plane), each pad pattern 190 may be shaped by a predetermined rotation angle θ relative to either the first direction X or the second direction Y. For example, the first side S1 of each pad pattern 190 may be defined as an acute angle of rotation θ relative to the first direction X. Alternatively, for example, the second side S2 of each pad pattern 190 may be defined as an acute angle of rotation θ relative to the second direction Y. This will be discussed later in the context of... Figures 5 to 8 The description provides a more detailed account of the rotation angle θ.

[0062] In some embodiments, each of the length Wa of the first side S1 and the length Wb of the second side S2 can be smaller than the pad pitch (e.g., Figure 5 of P 1 or Figure 7 of P 2) The pad pitch is achieved by periodically arranging multiple pad patterns 190° apart from each other. This will be explained later in the context of use. Figures 5 to 8 The description provides a more detailed description of the pad pitch.

[0063] refer to Figures 1 to 4 In a semiconductor memory device according to some embodiments, each cell region CA includes a plurality of unit memory cells UC arranged in a third direction Z.

[0064] The conductive pattern 120 of each cell region CA can extend in the third direction Z, and multiple unit memory cells UC can be jointly connected to the conductive pattern 120 of each cell region CA. Each unit memory cell UC may include a semiconductor pattern 110, a gate electrode 130, a gate dielectric layer 135, and a data storage structure 140.

[0065] Semiconductor pattern 110 may extend in a first direction X. Semiconductor pattern 110 may connect conductive pattern 120 and data storage structure 140 to each other. For example, conductive pattern 120 may contact a first portion of semiconductor pattern 110, and data storage structure 140 may contact a second portion of semiconductor pattern 110. In a semiconductor memory device according to some embodiments, the first portion and the second portion of semiconductor pattern 110 may be provided as... Figure 2 Select the source / drain regions of the component SW.

[0066] Although the semiconductor pattern 110 is shown as a rectangular column extending in the first direction X, this is merely an example. Unlike the example shown, the semiconductor pattern 110 may be cylindrical or another polygonal column shape.

[0067] Semiconductor pattern 110 may include semiconductor materials, such as monocrystalline silicon, polycrystalline silicon, organic semiconductor materials, or carbon nanostructures. However, this disclosure is not limited thereto. For example, semiconductor pattern 110 may include a monocrystalline silicon pattern.

[0068] The gate electrode 130 may extend in the second direction Y. The gate electrode 130 may intersect with the semiconductor pattern 110 while being disposed between the conductive pattern 120 and the data storage structure 140. For example, the semiconductor pattern 110 may include a third portion located between a first portion and a second portion. The gate electrode 130 may extend in the second direction Y to intersect with the third portion of the semiconductor pattern 110.

[0069] The gate electrode 130 may include: a conductive material, such as a metal like tungsten (W), molybdenum (Mo), ruthenium (Ru), cobalt (Co), nickel (Ni), etc.; and / or a semiconductor material like silicon. However, this disclosure is not limited thereto. In semiconductor memory devices according to some embodiments, the gate electrode 130 may be provided as… Figure 2 The gate of the selected element SW.

[0070] In some embodiments, the gate electrode 130 may have a gate structure that surrounds the outer surface of the semiconductor pattern 110. For example, the semiconductor pattern 110 may extend in a first direction X so as to extend through the gate electrode 130.

[0071] A gate dielectric layer 135 may be situated between the semiconductor pattern 110 and the gate electrode 130. The gate electrode 130 may be spaced apart from the semiconductor pattern 110 via the gate dielectric layer 135. For example, the gate dielectric layer 135 may surround a third portion of the semiconductor pattern 110.

[0072] The gate dielectric layer 135 may include, but is not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a high-k material with a dielectric constant higher than that of silicon oxide. High-k materials may include, for example, at least one of aluminum oxide, hafnium oxide, lanthanum oxide, tantalum oxide, titanium oxide, lanthanum hafnium oxide, lanthanum aluminum oxide, dysprosium scandium oxide, and combinations thereof.

[0073] The data storage structure 140 may be connected to a second portion of the semiconductor pattern 110. In a semiconductor memory device according to some embodiments, the data storage structure 140 may be provided as follows: Figure 2 The data storage element DS. The data storage structure 140 can be controlled by a gate electrode 130 provided as a word line WL and a conductive pattern 120 provided as a bit line BL to store data in each unit memory cell UC.

[0074] In some embodiments, the data storage structure 140 may include a capacitor. For example, the data storage structure 140 may include a first electrode 142, a capacitor dielectric layer 144, and a second electrode 146. The first electrode 142 may extend in a first direction X. Although the first electrode 142 is shown as a rectangular cylinder extending in the first direction X, this is merely an example. Unlike the example shown, the first electrode 142 may be cylindrical or may be another polygonal cylindrical shape. The second electrode 146 may face the first electrode 142. For example, the second electrode 146 may surround the outer surface of the first electrode 142. The capacitor dielectric layer 144 may be located between the first electrode 142 and the second electrode 146. For example, the capacitor dielectric layer 144 may extend conformally along the contour of the surface of the first electrode 142. The first electrode 142 and the second electrode 146 may be spaced apart from each other via the capacitor dielectric layer 144.

[0075] Each of the first electrode 142 and the second electrode 146 may include a conductive material, such as doped polycrystalline silicon, a metal, or a metal nitride. However, this disclosure is not limited thereto. The capacitor dielectric layer 144 may include, for example, but not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, and high-k dielectric materials. The data storage structure 140 may use the potential difference generated between the first electrode 142 and the second electrode 146 to store charge in the capacitor dielectric layer 144.

[0076] In some embodiments, each cell region CA may include a first cell string STR1 and a second cell string STR2 that share a conductive pattern 120. For example, in each cell region CA, a conductive pattern 120 may be connected to the first cell string STR1 and the second cell string STR2 in a first direction X and disposed between the first cell string STR1 and the second cell string STR2. Each of the first cell string STR1 and the second cell string STR2 may include a plurality of unit storage cells UC arranged in a third direction Z.

[0077] Figure 5 This is an example top view used to illustrate the pad pattern of a semiconductor memory device according to some embodiments. Figure 6 This is an example perspective view illustrating a pad pattern for a semiconductor memory device according to some embodiments. For ease of description, the previous references can be briefly described. Figures 1 to 4 The described features may be omitted.

[0078] refer to Figure 5 and Figure 6 According to some embodiments, a semiconductor memory device may include a first cell region CA1 to a sixth cell region CA6 and a first pad pattern 190a to a sixth pad pattern 190f.

[0079] The first unit region CA1 to the third unit region CA3 can be arranged sequentially along the second direction Y. The fourth unit region CA4 to the sixth unit region CA6 can be arranged sequentially along the second direction Y. The first unit region CA1 and the fourth unit region CA4 can be arranged along the first direction X, the second unit region CA2 and the fifth unit region CA5 can be arranged along the first direction X, and the third unit region CA3 and the sixth unit region CA6 can be arranged along the first direction X.

[0080] The first unit region CA1 to the sixth unit region CA6 may each include a first conductive pattern 120a to a sixth conductive pattern 120f. The first unit region CA1 to the sixth unit region CA6 may respectively correspond to... Figure 3 and Figure 4 The cell region CA. For example, each of the first cell region CA1 to the sixth cell region CA6 may include the above reference. Figure 4 The description refers to multiple unit storage units (UCs).

[0081] The first pad pattern 190a to the sixth pad pattern 190f can be formed on the first cell region CA1 to the sixth cell region CA6. For example, the first pad pattern 190a to the sixth pad pattern 190f can overlap with the first cell region CA1 to the sixth cell region CA6 in the third direction Z.

[0082] The first pad patterns 190a to the sixth pad patterns 190f may be spaced apart from each other. For example, multiple pad regions P190 corresponding to the first pad patterns 190a to the sixth pad patterns 190f may be defined on the first unit region CA1 to the sixth unit region CA6. The multiple pad regions P190 may have a 1:1 correspondence with the first pad patterns 190a to the sixth pad patterns 190f. The first pad patterns 190a to the sixth pad patterns 190f may be respectively disposed in the multiple pad regions P190 in a corresponding manner. In a top view intersecting a third direction Z (e.g., in the XY plane), each pad region P190 may have a size larger than that of its corresponding counterpart among the first pad patterns 190a to the sixth pad patterns 190f and a shape similar to that of its corresponding counterpart among the first pad patterns 190a to the sixth pad patterns 190f. For example, when each of the first pad patterns 190a to the sixth pad pattern 190f is a square with each side having a first length W1, each of the pad regions P190 can have a first pad pitch with each side having a first length W1. P A square shape.

[0083] In a top view intersecting a third direction Z (e.g., in the XY plane), each of the first pad patterns 190a to the sixth pad patterns 190f can be rotated relative to the first direction X or the second direction Y by a predetermined first rotation angle. θ The shape of 1. Because each of the first pad patterns 190a to the sixth pad pattern 190f is rotated by a first rotation angle. θ The shape is 1, so each corresponding pad area P190 can also be rotated by the first rotation angle. θ The shape of 1. For example, when each of the first pad patterns 190a to the sixth pad patterns 190f and the pad region P190 is square, one side of the square can be defined as an acute angle relative to the second direction Y by a first rotation angle. θ 1.

[0084] First pad pitch P 1 can be defined as the interval between the first pad patterns 190a to the sixth pad patterns 190f, which are arranged periodically to be spaced apart from each other. For example, the first pad pitch. P 1 can be defined as a first pad pattern 190a to a sixth pad pattern 190f arranged periodically to define a first rotation angle relative to a first direction X or a second direction Y. θ The intervals that are spaced apart from each other in the direction of 1. For example... Figure 5 As shown, adjacent pad regions in the plurality of pad regions P190 can share the boundary surface between them. That is, each pad region P190 can limit the enlarged range of a corresponding one of the first pad patterns 190a to the sixth pad pattern 190f.

[0085] In some embodiments, the first pad pitch of each pad region P190 P 1 can be expressed based on Equation 1 as described below.

[0086] [Equation 1]

[0087] In equation 1, CAx The first element pitch in the first direction X represents the first element pitch of each of the first element regions CA1 to the sixth element regions CA6. CAx ,and CAy The second unit pitch in the second direction Y represents the second unit pitch of each of the first unit regions CA1 to the sixth unit regions CA6. CAy That is, in a top view intersecting a third direction along the Z-axis (e.g., in the XY plane), the area size of each square-shaped pad region P190 (i.e., P 1 2) can be equal to the area of ​​each cell region CA (i.e., CAx CAy ).

[0088] Additionally, the first rotation angle of each pad area P190 θ 1 can be expressed based on Equation 2 as described below.

[0089] [Equation 2]

[0090] In Equation 2, the first rotation angle θ 1 has a unit of degree (°). Additionally, in equation 2, CAy The second unit pitch in the second direction Y represents the second unit pitch of each of the first unit regions CA1 to the sixth unit regions CA6. CAy ,and P 1 indicates the first pad pitch of each pad region P190. P 1.

[0091] In some embodiments, the first conductive patterns 120a to the sixth conductive patterns 120f and the first pad patterns 190a to the sixth pad patterns 190f may have a 1:1 correspondence with each other and may be connected to each other. For example, as Figure 6 As shown, the first connection patterns 170a to the third connection patterns 170c, spaced apart from each other, can be connected to the first conductive patterns 120a to the third conductive patterns 120c and the first pad patterns 190a to the third pad patterns 190c, and are disposed between the first conductive patterns 120a to the third conductive patterns 120c and the first pad patterns 190a to the third pad patterns 190c. Additionally, a first pass pattern 160 extending in the third direction Z can be formed to connect the first conductive patterns 120a to the third conductive patterns 120c to the first connection patterns 170a to the third connection patterns 170c, respectively. Furthermore, a second pass pattern 180 extending in the third direction Z can be formed to connect the first connection patterns 170a to the third connection patterns 170c to the first pad patterns 190a to the third pad patterns 190c, respectively. The first conductive pattern 120a can be electrically connected to the first pad pattern 190a through the first connection pattern 170a, the second conductive pattern 120b can be electrically connected to the second pad pattern 190b through the second connection pattern 170b, and the third conductive pattern 120c can be electrically connected to the third pad pattern 190c through the third connection pattern 170c. The size, shape, and arrangement of each of the first to third connection patterns 170a are merely examples and are not limited to those shown.

[0092] In some embodiments, the first pad patterns 190a to the sixth pad patterns 190f can be arranged in rows along the first direction X. For example, as Figure 5 As shown, the straight line connecting the centers of the first pad patterns 190a to the sixth pad patterns 190f can extend in the first direction X. In some embodiments, each of the first pad patterns 190a to the sixth pad patterns 190f can overlap with a plurality of cell regions arranged along the second direction Y. For example, each of the first pad patterns 190a to the third pad patterns 190c can overlap with the first cell regions CA1 to the third cell regions CA3 in the third direction Z. The number of cell regions overlapping with each of the first pad patterns 190a to the sixth pad patterns 190f is merely an example and can be based on the first pad pitch. P 1 and the first rotation angle θ 1. And change.

[0093] In some embodiments, pairs of conductive patterns 120a to 120f that are adjacent to each other in the first direction X may be jointly connected to a single sense amplifier region SA. For example, a first pad pattern 190a connected to the first conductive pattern 120a and a fourth pad pattern 190d connected to the fourth conductive pattern 120d may be jointly connected to a single sense amplifier region SA.

[0094] The unit readout amplifier region SA can be configured as described above. Figure 1 The described sense amplifier 30. For example, a first conductive pattern 120a may be provided as a bit line BL for a first cell region CA1, and a fourth conductive pattern 120d may be provided as a reference bit line / BL for the first cell region CA1. A unit sense amplifier region SA may be included above the reference. Figure 2 In the described peripheral circuit structure PERI, in some embodiments, the unit sense amplifier region SA may overlap with its corresponding paired unit regions (e.g., first unit region CA1 and fourth unit region CA4) in the third direction Z. For example, the first circuit pitch SAx of the unit sense amplifier region SA in the first direction X may be the first unit pitch. CAx Twice. Additionally, for example, the second circuit pitch SAy of the unit readout amplifier region SA in the second direction Y can be equal to the second unit pitch. CAy .

[0095] Figure 7 This is an example top view used to illustrate the pad pattern of a semiconductor memory device according to some embodiments. Figure 8 This is an example perspective view illustrating a pad pattern for a semiconductor memory device according to some embodiments. For ease of description, a brief description will be provided in conjunction with the above references. Figures 1 to 6 The description may contain repeated content or omit its description.

[0096] refer to Figure 7 and Figure 8 According to some embodiments, a semiconductor memory device may include a first cell region CA11 to a sixteenth cell region CA82, a first strip pattern 150a to an eighth strip pattern 150h, and a first pad pattern 190a to an eighth pad pattern 190h.

[0097] Unit regions CA11, CA21, CA31, and CA41 from the first to the fourth can be arranged sequentially along the second direction Y. Unit regions CA12, CA22, CA32, and CA42 from the fifth to the eighth can be arranged sequentially along the second direction Y. Unit regions CA51, CA61, CA71, and CA81 from the ninth to the twelfth can be arranged sequentially along the second direction Y. Unit regions CA52, CA62, CA72, and CA82 from the thirteenth to the sixteenth can be arranged sequentially along the second direction Y. Unit regions CA11 (first), CA12 (fifth), CA51 (ninth), and CA52 (thirteenth) can be arranged sequentially along the first direction X. Unit regions CA21 (second), CA22 (sixth), CA61 (tenth), and CA62 (fourteenth) can be arranged sequentially along the first direction X. Unit regions CA31 (third), CA32 (seventh), CA71 (eleventh), and CA72 (fifteenth) can be arranged sequentially along the first direction X. The fourth unit region CA41, the eighth unit region CA42, the twelfth unit region CA81, and the sixteenth unit region CA82 can be arranged sequentially along the first direction X.

[0098] Each of the first unit region CA11 to the sixteenth unit region CA82 may include a corresponding conductive pattern 120. Each of the first unit region CA11 to the sixteenth unit region CA82 may correspond to... Figure 3 and Figure 4 The cell region CA. For example, each of the first cell region CA11 to the sixteenth cell region CA82 may include the above reference. Figure 4 The description refers to multiple unit storage units (UCs).

[0099] The first strip patterns 150a to the eighth strip patterns 150h can be formed on corresponding groups of the first unit regions CA11 to the sixteenth unit regions CA82 (e.g., adjacent pairs of unit regions CA in the first direction X). Each of the first strip patterns 150a to the eighth strip patterns 150h can extend elongatedly in the first direction X (e.g., it can extend longitudinally in the first direction X). In some embodiments, each of the first strip patterns 150a to the eighth strip patterns 150h can be connected together with n conductive patterns 120 (where n is a natural number of 2 or greater) arranged along the first direction X. Therefore, the number of conductive patterns 120 and the number of strip patterns 150a to 150h can have an n:1 correspondence with each other. Figure 7 and Figure 8 The number of conductive patterns 120 and the number of strip patterns 150a to 150h are shown to have a 2:1 correspondence. For example, the first strip pattern 150a may extend in the first direction X to connect the conductive patterns 120 of the first unit region CA11 and the conductive patterns 120 of the fifth unit region CA12 to each other.

[0100] For example, the fifth strip pattern 150e can extend in the first direction X to connect the conductive patterns 120 of the ninth unit region CA51 and the conductive patterns 120 of the thirteenth unit region CA52 to each other. The first pad patterns 190a to the eighth pad patterns 190h can be formed on the first strip patterns 150a to the eighth strip patterns 150h. The first strip patterns 150a to the eighth strip patterns 150h can be located in the third direction Z between the first unit regions CA11 to the sixteenth unit region CA82 and the first pad patterns 190a to the eighth pad patterns 190h.

[0101] The first pad patterns 190a to the eighth pad patterns 190h may be spaced apart from each other. For example, a plurality of pad regions P190 corresponding to the first pad patterns 190a to the eighth pad patterns 190h may be defined on the first unit region CA11 to the sixteenth unit region CA82. The plurality of pad regions P190 may have a 1:1 correspondence with the first pad patterns 190a to the eighth pad patterns 190h. The first pad patterns 190a to the eighth pad patterns 190h may be respectively disposed in the corresponding pad regions P190. In a top view intersecting a third direction Z (e.g., in the XY plane), each pad region P190 may have an area larger than that of its corresponding counterpart among the first pad patterns 190a to the eighth pad patterns 190h and a shape similar to that of its corresponding counterpart among the first pad patterns 190a to the eighth pad patterns 190h. For example, when each of the first pad patterns 190a to the eighth pad pattern 190h is a square with each side having a second length W2, each pad region P190 can have a second pad pitch with each side having a length greater than the second length W2. P A square shape of 2.

[0102] In a top view intersecting a third direction Z (e.g., in the XY plane), each of the first pad patterns 190a to the eighth pad patterns 190h can be rotated relative to the first direction X or the second direction Y by a predetermined second rotation angle. θ The shape of 2. Because each of the first pad patterns 190a to the eighth pad patterns 190h is rotated by a second rotation angle. θ The shape is 2, so each corresponding pad region P190 can also be a shape rotated by a second rotation angle θ2. For example, when each of the first pad pattern 190a to the eighth pad pattern 190h and the pad region P190 is a square, one side of the square can be defined as an acute angle relative to the second direction Y by the second rotation angle θ2. θ 2.

[0103] Second pad pitch P 2 can be defined as the interval between the first pad patterns 190a to the eighth pad patterns 190h, arranged periodically to be spaced apart from each other. For example, the second pad pitch. P 2 can be defined as a first pad pattern 190a to an eighth pad pattern 190h arranged periodically to define a second rotation angle relative to a first direction X or a second direction Y. θ The intervals that are spaced apart from each other in the direction of 2. For example... Figure 7As shown, adjacent pad regions in the plurality of pad regions P190 can share the boundary surface between them. That is, each pad region P190 can limit the range of a corresponding one of the first pad patterns 190a to the eighth pad pattern 190h that is enlarged.

[0104] In some embodiments, the second pad pitch of each pad region P190 P 2 can be expressed based on Equation 3 as described below.

[0105] [Equation 3]

[0106] In equation 3, n (in n (A natural number equal to or greater than 2) represents the number of conductive patterns 120 shared by each of the first pattern 150a to the eighth pattern 150h. CAx The first element pitch in the first direction X represents the first element pitch of each of the first element regions CA11 to the sixteenth element regions CA82. CAx ,and CAy The second unit pitch in the second direction Y represents the second unit pitch of each of the first unit regions CA11 to the sixteenth unit regions CA82. CAy That is, in a top view intersecting a third direction along the Z-axis (e.g., in the XY plane), the area size of each square-shaped pad region P190 (i.e., P 2 2 ) can be equal to the sum of the area sizes of the unit regions shared by each of the first-zone patterns 150a to the eighth-zone patterns 150h (i.e., n CAx CAy ).

[0107] Additionally, the second rotation angle of each pad area P190 θ 2 can be expressed based on Equation 4 as described below.

[0108] [Equation 4]

[0109] In Equation 4, the second rotation angle θ 2 has a unit of degree (°). Additionally, in equation 4, n (in n (A natural number greater than or equal to 2) represents the number of conductive patterns 120 shared by each of the first strip pattern 150a to the eighth strip pattern 150h. CAyThe second unit pitch in the second direction Y represents the second unit pitch of each of the first unit regions CA11 to the sixteenth unit regions CA82. CAy ,and P 2 indicates the second pad pitch of each pad area P190. P 2.

[0110] In some embodiments, the first strip patterns 150a to the eighth strip patterns 150h and the first pad patterns 190a to the eighth pad patterns 190h can be connected to each other in a 1:1 correspondence. For example, as Figure 8 As shown, the first connection patterns 170a to the fourth connection patterns 170d, spaced apart from each other, can be connected to the first strip patterns 150a to the fourth strip patterns 150d and the first pad patterns 190a to the fourth pad patterns 190d, and are disposed between the first strip patterns 150a to the fourth strip patterns 150d and the first pad patterns 190a to the fourth pad patterns 190d. Additionally, a first pass pattern 160 can be formed extending in the third direction Z to connect the first strip patterns 150a to the fourth strip patterns 150d to the first connection patterns 170a to the fourth connection patterns 170d respectively. Furthermore, a second pass pattern 180 can be formed extending in the third direction Z to connect the first connection patterns 170a to the fourth connection patterns 170d to the first pad patterns 190a to the fourth pad patterns 190d respectively. The first conductive pattern 120a can be electrically connected to the first pad pattern 190a via the first connection pattern 170a, the second conductive pattern 120b can be electrically connected to the second pad pattern 190b via the second connection pattern 170b, the third conductive pattern 120c can be electrically connected to the third pad pattern 190c via the third connection pattern 170c, and the fourth conductive pattern 120d can be electrically connected to the fourth pad pattern 190d via the fourth connection pattern 170d. The size, shape, and arrangement of each of the first connection patterns 170a to the fourth connection patterns 170d are merely examples and are not limited to those shown.

[0111] In some embodiments, the first pad patterns 190a to the eighth pad patterns 190h can be arranged row by row along the first direction X. For example, as Figure 7As shown, the straight line connecting the centers of the first pad patterns 190a to the eighth pad patterns 190h can extend in the first direction X. In some embodiments, each of the first pad patterns 190a to the eighth pad patterns 190h can overlap with a plurality of cell regions arranged along the second direction Y. For example, each of the first pad patterns 190a and the second pad patterns 190b can overlap with the first to fourth cell regions CA11, CA21, CA31 and CA41 in the third direction Z. The number of cell regions overlapping with each of the first pad patterns 190a to the eighth pad patterns 190h is merely an example and can be adjusted according to the second pad pitch. P 2 and second rotation angle θ 2. And change.

[0112] In some embodiments, pairs of strip patterns 150a to 150h that are adjacent to each other in the first direction X may be jointly connected to a unit sense amplifier region SA. For example, a first pad pattern 190a connected to the first strip pattern 150a and a fifth pad pattern 190e connected to the fifth strip pattern 150e may be jointly connected to a unit sense amplifier region SA.

[0113] The unit readout amplifier region SA can be configured as described above. Figure 1 The described sense amplifier 30. For example, a first strip pattern 150a can be provided as a bit line BL for the first cell region CA11 and the fifth cell region CA12, and a fifth strip pattern 150e can be provided as a reference bit line / BL for the first cell region CA11 and the fifth cell region CA12. A unit sense amplifier region SA can be included above for use. Figure 2 In the described peripheral circuit structure PERI, in some embodiments, the unit sense amplifier region SA may overlap with n pairs of corresponding unit regions (e.g., first unit region CA11, fifth unit region CA12, ninth unit region CA51, and thirteenth unit region CA52) in the third direction Z (where n is the number of conductive patterns 120 shared by each of the first strip patterns 150a to the eighth strip patterns 150h). For example, the first circuit pitch SAx of the unit sense amplifier region SA in the first direction X may be the first unit pitch. CAx 2n times (where n is the number of conductive patterns 120 shared by each of the first strip patterns 150a to the eighth strip patterns 150h). Additionally, for example, the second circuit pitch SAy of the unit readout amplifier region SA in the second direction Y can be equal to the second unit pitch. CAy .

[0114] Although embodiments of the present disclosure have been described with reference to the accompanying drawings, the present disclosure is not limited to the above embodiments, but can be implemented in various different forms. Those skilled in the art will understand that the present disclosure can be practiced in other specific forms without altering the technical spirit or essential characteristics of the present disclosure. Therefore, it should be understood that the embodiments described above are not limiting in all respects, but rather illustrative.

Claims

1. A semiconductor memory device, the semiconductor memory device comprising: Multiple unit regions, each unit region comprising multiple conductive patterns and arranged in two dimensions along a first direction and a second direction intersecting each other, wherein each unit region comprises a conductive pattern extending upward from a third of the multiple conductive patterns intersecting the first direction and the second direction; as well as Multiple pad patterns, which are correspondingly connected to multiple conductive patterns. In the top view intersecting the third direction, for the plurality of unit regions, the first unit pitch in the first direction is larger than the second unit pitch in the second direction. In the top view, each of the plurality of pad patterns is a quadrilateral shape comprising a first side and a second side that intersect each other. In the top view, for each of the plurality of pad patterns, the length of the first side and the length of the second side are both greater than the second unit pitch, and In the top view, for each of the plurality of pad patterns, the angle between the first side of the pad pattern and the first direction is an acute angle.

2. The semiconductor memory device according to claim 1, wherein, In each of the plurality of pad patterns, the length of the first side and the length of the second side are both greater than the pad pitch represented by Equation 1 below. P 1 small: [Equation 1] In equation 1, CAx It is the pitch of the first unit, and CAy It is the pitch of the second unit.

3. The semiconductor memory device according to claim 2, wherein, For each of the plurality of pad patterns, the acute angle is represented by the following Equation 2: [Equation 2] In equation 2, θ 1 is the acute angle, CAy It is the second unit pitch, and P 1 is the pad pitch.

4. The semiconductor memory device according to claim 1, wherein, Each of the plurality of pad patterns is square in shape in the top view intersecting the third direction.

5. The semiconductor memory device according to claim 1, wherein, The pitch of the first unit is five times or more than the pitch of the second unit.

6. The semiconductor memory device according to claim 1, wherein, Each of the plurality of cell regions includes a plurality of unit storage units arranged upwards from the third party. Each of the plurality of unit storage units includes: A semiconductor pattern that extends in the first direction and is connected to the conductive pattern; Data storage structure, the data storage structure being connected to the semiconductor pattern; and A gate electrode that extends in the second direction and intersects the semiconductor pattern between the conductive pattern and the data storage structure.

7. The semiconductor memory device according to claim 6, wherein, In each of the plurality of unit memory cells, the semiconductor pattern extends in the first direction to extend through the gate electrode.

8. The semiconductor memory device according to claim 6, wherein, In each of the plurality of unit storage cells, the data storage structure includes a first electrode connected to the semiconductor pattern, a second electrode facing the first electrode, and a capacitor dielectric layer located between the first electrode and the second electrode.

9. The semiconductor memory device according to claim 1, wherein the semiconductor memory device further comprises a peripheral circuit structure overlapping the plurality of cell regions in the third direction.

10. The semiconductor memory device according to claim 9, wherein, The peripheral circuit structure includes a readout amplifier electrically connected to the plurality of pad patterns.

11. A semiconductor memory device, the semiconductor memory device comprising: Multiple unit regions are arranged in two dimensions along a first direction and a second direction that intersect each other; Multiple strip patterns are located on the multiple unit regions, and each of the multiple strip patterns extends in the first direction; as well as Multiple pad patterns, the multiple pad patterns being located on the multiple strip patterns and correspondingly connected to the multiple strip patterns, Each of the plurality of unit regions includes: a plurality of unit storage cells arranged along a third direction intersecting the first direction and the second direction; and a conductive pattern extending upward along the third direction and connected to the plurality of unit storage cells. Each of the plurality of strip patterns consists of n conductive patterns arranged along the first direction connected to each other, where n is a natural number of 2 or greater. Each of the plurality of pad patterns is square in shape in a top view intersecting the third direction, and Wherein, for each of the plurality of pad patterns, the angle between one edge of the pad pattern and the first direction is an acute angle.

12. The semiconductor memory device of claim 11, wherein, In the top view intersecting the third direction, for each of the plurality of pad patterns, the length of each side of the pad pattern is greater than the pad pitch as expressed by the following Equation 3. P 2 small: [Equation 3] In equation 3, CAx It is the first unit pitch of the plurality of unit regions in the first direction, and CAy It is the second unit pitch of the plurality of unit regions in the second direction.

13. The semiconductor memory device according to claim 12, wherein, For each of the plurality of pad patterns, the acute angle is represented by the following Equation 4: [Equation 4] In equation 4, θ 2 is the acute angle, CAy It is the second unit pitch, and P 2 is the pad pitch.

14. The semiconductor memory device according to claim 11, wherein, Each of the plurality of unit storage units includes: A semiconductor pattern that extends in the first direction and is connected to the conductive pattern; Data storage structure, the data storage structure being connected to the semiconductor pattern; and A gate electrode that extends in the second direction and intersects the semiconductor pattern between the conductive pattern and the data storage structure.

15. The semiconductor memory device of claim 11, further comprising a peripheral circuit structure overlapping the plurality of cell regions in the third direction.

16. A semiconductor memory device, the semiconductor memory device comprising: A first substrate, the first substrate including a first surface and a second surface opposite to each other; Multiple unit regions are located on the first surface. The multiple unit regions include multiple conductive patterns and are arranged in two dimensions along a first direction and a second direction that are parallel to the first surface and intersect each other. Each unit region includes a conductive pattern that extends upward from a third conductive pattern that intersects the first direction and the second direction. Multiple pad patterns, the multiple pad patterns being located on the multiple unit regions and correspondingly connected to the multiple conductive patterns; The second substrate includes a third surface facing the first surface and a fourth surface opposite to the third surface; as well as A peripheral circuit element layer is disposed on the third surface. Each of the plurality of unit regions includes a plurality of unit storage units arranged upwards from the third party. Each of the plurality of unit storage cells includes: a semiconductor pattern extending in the first direction and connected to the conductive pattern of the cell region; a data storage structure connected to the semiconductor pattern; and a gate electrode extending in the second direction and intersecting the semiconductor pattern between the conductive pattern and the data storage structure in the cell region. Each of the plurality of pad patterns is square in shape in a top view intersecting the third direction, and Wherein, for each of the multiple pad patterns, the angle between one edge of the pad pattern and the first direction is an acute angle.

17. The semiconductor memory device according to claim 16, wherein, The plurality of unit regions include a first unit region and a second unit region arranged in the first direction. The first unit region includes a first conductive pattern that extends upward from the third party and is connected to the plurality of unit storage cells of the first unit region. The second unit region includes a second conductive pattern that extends upward from the third party and is connected to the plurality of unit storage cells of the second unit region. The plurality of pad patterns include a first pad pattern electrically connected to the first conductive pattern and a second pad pattern electrically connected to the second conductive pattern, and The peripheral circuit element layer includes a unit sense amplifier region, which overlaps with the first unit region and the second unit region in the third direction and is electrically connected to the first pad pattern and the second pad pattern.

18. The semiconductor memory device according to claim 16, wherein, The plurality of unit regions include a first unit region, a second unit region, a third unit region, and a fourth unit region arranged sequentially in the first direction. The first unit region, the second unit region, the third unit region, and the fourth unit region each include a first conductive pattern, a second conductive pattern, a third conductive pattern, and a fourth conductive pattern, respectively. Each of the first to fourth conductive patterns extends upwards from the third unit region and is connected to the plurality of unit storage cells in the corresponding unit region. The semiconductor memory device further includes: A first strip pattern is located between the plurality of cell regions and the plurality of pad patterns, the first strip pattern extends in the first direction and connects the first conductive pattern to the second conductive pattern; and A second strip pattern is located between the plurality of cell regions and the plurality of pad patterns, the second strip pattern extending in the first direction and connecting the third conductive pattern to the fourth conductive pattern. The plurality of pad patterns include a first pad pattern electrically connected to the first pattern and a second pad pattern electrically connected to the second pattern. The peripheral circuit element layer includes a unit sense amplifier region, which overlaps with the first unit region to the fourth unit region in the third direction and is electrically connected to the first pad pattern and the second pad pattern.

19. The semiconductor memory device according to claim 16, wherein, The plurality of unit regions include a first unit region and a second unit region arranged in the second direction. The first unit region includes a first conductive pattern that extends upward from the third party and is connected to the plurality of unit storage cells of the first unit region. The second unit region includes a second conductive pattern that extends upward from the third party and is connected to the plurality of unit storage cells of the second unit region. The plurality of pad patterns include a first pad pattern electrically connected to the first conductive pattern and a second pad pattern electrically connected to the second conductive pattern, and The first pad pattern and the second pad pattern are arranged in the first direction.

20. The semiconductor memory device according to claim 19, wherein, Each of the first pad pattern and the second pad pattern overlaps with the first cell region and the second cell region in the third direction.

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