Semiconductor device and method of manufacturing the same

Abstract

The application discloses a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a substrate, a contact pad array and a capacitor. The contact pad array is located on the substrate and comprises a plurality of first contact pads and a contact pad protection ring surrounding the first contact pads. The contact pad protection ring surrounds the periphery of the first contact pads along two mutually perpendicular directions. The contact pad protection ring comprises a plurality of first auxiliary contact pads and a plurality of second auxiliary contact pads. Thus, the edge pattern of the contact pad array is optimized by the arrangement of the contact pad protection ring, and the structural reliability of the semiconductor device is improved.

Description

Technical Field

[0001] This invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device comprising a contact pad array and a method for manufacturing the same. Background Technology

[0002] With the trend towards miniaturization in various electronic products, the design of dynamic random access memory (DRAM) cells must also meet the requirements of high integration and high density. For a DRAM cell with a recessed gate structure, because it can achieve a longer carrier channel length within the same semiconductor substrate, reducing leakage current in the capacitor structure, it has gradually replaced DRAM cells with only planar gate structures under the current mainstream development trend. Generally, a DRAM cell with a recessed gate structure includes a transistor component and a charge storage component to receive voltage signals from the bit line and word line. However, due to limitations in process technology, existing DRAM cells with recessed gate structures still have many shortcomings and require further improvement to effectively enhance the performance and reliability of related memory components. Summary of the Invention

[0003] One objective of this invention is to provide a semiconductor device and a method for manufacturing the same. By setting a contact pad protection ring around the contact pad array, the edge pattern of the contact pad array is optimized, and structural defects that may arise in the semiconductor device due to the continuous increase in memory cell density are improved, thereby enhancing the component reliability and achieving excellent operational performance.

[0004] To achieve the above objectives, one embodiment of the present invention provides a semiconductor device including a substrate, a contact pad array, and a capacitor. The substrate includes an insulating structure and a plurality of active regions. The contact pad array is located on the substrate and includes a plurality of first contact pads and a contact pad protection ring. The first contact pads are arranged along mutually non-perpendicular first and second directions, and are arranged in a plurality of oblique rows along the first direction. The contact pad protection ring surrounds the contact pad array along mutually perpendicular third and fourth directions, wherein neither the third nor the fourth direction is perpendicular to the first or second direction. The contact pad protection ring includes a plurality of first auxiliary contact pads arranged in the third direction and a plurality of second auxiliary contact pads arranged in the fourth direction. Each first auxiliary contact pad has a first side parallel to the third direction, wherein the first sides of each first auxiliary contact pad are collinear with each other. The plurality of second auxiliary contact pads arranged in the fourth direction each have a first side parallel to the fourth direction, wherein the first sides of each second auxiliary contact pad are collinear with each other. The capacitor is located on the contact pad array.

[0005] To achieve the above objectives, one embodiment of the present invention provides another semiconductor device, including a substrate, a plurality of first contact pads, a plurality of first auxiliary contact pads, a plurality of second auxiliary contact pads, peripheral circuitry, and a capacitor. The substrate includes a cell region, a peripheral region, and a boundary region located between the cell region and the peripheral region. The cell region includes a plurality of active regions, and the peripheral region includes a plurality of logic active regions. The first contact pads are located in the cell region and are arranged along mutually non-perpendicular first and second directions. Two adjacent first contact pads in the first or second direction are aligned with each other along the first and second directions. The first and second auxiliary contact pads are located in the boundary region and are arranged along mutually perpendicular third and fourth directions. Each first and second auxiliary contact pad has a major axis extending along the first direction and a minor axis extending along the third or fourth direction. The minor axes of two adjacent first auxiliary contact pads in the third direction or two adjacent second auxiliary contact pads in the fourth direction are aligned with each other along the third or fourth direction. The peripheral circuitry is located on the logic active region. The capacitor is located on the first contact pads.

[0006] To achieve the above objectives, one embodiment of the present invention provides another semiconductor device, including a contact pad array and an insulating structure. The contact pad array includes a plurality of first contact pads and contact pad guard rings. The first contact pads are arranged and spaced apart from each other along a first direction and a second direction that are not perpendicular to each other. The contact pad guard rings surround the contact pad array along a third direction and a fourth direction that are perpendicular to each other, wherein neither the third direction nor the fourth direction is perpendicular to the first direction or the second direction. The insulating structure surrounds each of the first contact pads and the contact pad guard rings.

[0007] The insulating structure includes a first insulating structure, a second insulating structure, and a third insulating structure. The first insulating structure extends continuously along a first direction and is located between any two adjacent first contact pads in the second direction and within the contact pad protection ring, simultaneously contacting both the contact pad protection ring and the first contact pads. The second insulating structure extends continuously along the second direction, is shorter than the first insulating structure in the third direction, is located between any two adjacent first contact pads in the first direction, and contacts the first contact pads. The third insulating structure is located between the first contact pads and the contact pad protection ring. The third insulating structure includes a first portion in the third direction and a second portion in the fourth direction, the first portion and the second portion of the third insulating structure being continuously disposed, wherein the first insulating structure spans the second portion of the third insulating structure, and the second insulating structure contacts the first portion of the third insulating structure.

[0008] To achieve the above objectives, one embodiment of the present invention provides another semiconductor device, including a plurality of first contact pads, a plurality of first insulating structures, a plurality of second insulating structures, and a contact pad protection ring. The first contact pads are arranged along mutually non-perpendicular first and second directions. The first insulating structures extend continuously in the first direction and are disposed between any two adjacent first contact pads in the second direction. The second insulating structures extend continuously in the second direction and are disposed between any two adjacent first contact pads in the first direction. The contact pad protection ring surrounds the contact pad array along mutually perpendicular third and fourth directions, wherein neither the third nor the fourth direction is perpendicular to the first or second direction. Each of the first insulating structures further extends into the contact pad protection ring, dividing the contact pad protection ring into a plurality of independent auxiliary contact pads.

[0009] To achieve the above objectives, one embodiment of the present invention provides a method for fabricating a semiconductor device, comprising the following steps: A target layer is provided, including a first region and a second region surrounding the first region. A plurality of first annular patterns are formed on the first region of the target layer. A plurality of second annular patterns are formed on the second region of the target layer. A third annular pattern is formed on the first region of the target layer, partially covering the first annular patterns. A fourth annular pattern is formed on the target layer, the fourth annular pattern spanning the first region and the second region, and covering the ends of each of the first and second annular patterns. A pattern transfer process is performed to remove portions of the target layer covered by the first, second, third, and fourth annular patterns, thereby forming a target pattern on the target layer. Attached Figure Description

[0010] The accompanying drawings are provided to give a more in-depth understanding of this embodiment and are incorporated herein by reference as a whole. These drawings and descriptions are used to illustrate the principles of some embodiments. It should be noted that all drawings are schematic diagrams for illustrative and drafting purposes, and relative dimensions and scales have been adjusted. The same symbols represent corresponding or similar features in different embodiments.

[0011] Figures 1 to 3 This is a schematic diagram of a semiconductor device according to a first embodiment of the present invention, wherein:

[0012] Figure 1 This is a top view schematic diagram of a semiconductor device;

[0013] Figure 2 for Figure 1 A schematic diagram of a cross-section taken along section line A-A'; and

[0014] Figure 3 This is a partial top view of a semiconductor device;

[0015] Figures 4 to 7 This is a top view schematic diagram of some stages in the method for fabricating a semiconductor device according to the first embodiment of the present invention, wherein:

[0016] Figure 4 This is a top view of a semiconductor device after the formation of a mask layer and sub-ring pattern.

[0017] Figure 5 This is a top view of a semiconductor device after the formation of the mask layer and the first annular pattern.

[0018] Figure 6 This is a top view schematic diagram of a semiconductor device after the formation of the mask layer, the second annular pattern, and the third annular pattern; and

[0019] Figure 7 This is a top view of the semiconductor device after the formation of the mask layer and the fourth annular pattern.

[0020] Figure 8 This is a top view schematic diagram of a semiconductor device according to a second embodiment of the present invention.

[0021] The reference numerals in the attached figures are explained as follows:

[0022] 10, 30 - Semiconductor devices;

[0023] 102 - Shallow ditch isolation;

[0024] 104 - Active region, logically active region;

[0025] 110, 310 - Contact pad array;

[0026] 112 - First contact pad;

[0027] 112s - Side;

[0028] 120 - Contact pad protection ring;

[0029] 120c - Corner Area;

[0030] 122 - First auxiliary contact pad;

[0031] 122s - First side;

[0032] 122t - Second side;

[0033] 124 - Second auxiliary contact pad;

[0034] 124s - Second side;

[0035] 124t - First side;

[0036] 126 - Third auxiliary contact pad;

[0037] 126s - First side;

[0038] 126t - Second side;

[0039] 128 - Fourth auxiliary contact pad;

[0040] 128s - First side;

[0041] 128t - Second side;

[0042] 130 - Conductor structure;

[0043] 132 - First conductor;

[0044] 132s - First side;

[0045] 134 - Second conductor;

[0046] 134s - First side;

[0047] 136 - Third conductor;

[0048] 136s, 136t - side;

[0049] 140 - Insulation structure;

[0050] 142 - First insulation structure;

[0051] 144 - Second insulation structure;

[0052] 146 - Third insulation structure;

[0053] 146a - Part 1;

[0054] 146b - Part Two;

[0055] 148 - Fourth insulation structure;

[0056] 148a - Part 1;

[0057] 148b - Part Two;

[0058] 150-bit line;

[0059] 150c-bit line plug;

[0060] 152-Plug;

[0061] 154-position line gap wall;

[0062] 156 - Insulation layer;

[0063] 160-gate;

[0064] 164 - Gate gap wall;

[0065] 180-capacitor;

[0066] 182 - Bottom electrode;

[0067] 184 - Capacitor dielectric layer;

[0068] 186-Top electrode layer;

[0069] 200 - Target Layer;

[0070] 202 - Block 1;

[0071] 204 - Second Block;

[0072] 210, 212, 214, 216 - Mask layers;

[0073] 314 - Second contact pad;

[0074] BR - Boundary Area;

[0075] C1, C2, Cn - diagonal arrangement;

[0076] CR - Cell region;

[0077] D1 - First direction;

[0078] D2 - Second Block;

[0079] D3-Third direction;

[0080] D4 - Fourth Direction;

[0081] L1, L2 - Extension length;

[0082] OP1 - First circular pattern;

[0083] OP2 - Second ring pattern;

[0084] OP3 - Third ring pattern;

[0085] OP4 - Fourth ring pattern;

[0086] PR - peripheral area;

[0087] RP1 - First sub-ring pattern;

[0088] RP2 - Second sub-ring pattern;

[0089] W1, W2 - Width;

[0090] θ - right angle. Detailed Implementation

[0091] To enable those skilled in the art to further understand the present invention, preferred embodiments are described below in conjunction with the accompanying drawings to explain in detail the composition and desired effects of the invention. It should be understood that the features described below can be substituted, rearranged, or mixed to achieve other embodiments without departing from the spirit of the invention.

[0092] Please refer to the following: Figures 1 to 3 The diagram shown is a schematic representation of a semiconductor device according to a first embodiment of the present invention. Figure 1 The schematic top view of the semiconductor device 10 in the first embodiment of the present invention is provided to clearly show the layout of specific components such as the contact pad array 110. Figure 1 The components located above and below the contact pad array 110 are not shown in the figure. Figure 2 and Figure 3 They are respectively Figure 1 A cross-sectional view and a partially enlarged schematic diagram of the midtangent. (See attached image.) Figure 1 and Figure 2 As shown, the semiconductor device 10 includes at least a substrate 100, a contact pad array 110, and a capacitor 180. The substrate 100 may include, for example, a silicon substrate, a silicon-containing substrate, an epitaxial silicon substrate, a silicon-on-insulator substrate, or other suitable materials, but is not limited thereto. At least one shallow trench isolation (STI) 102 is provided within the substrate 100, and multiple active areas (AA) 104 are defined on the substrate 100. Furthermore, the substrate 100 includes a region with relatively high component density, such as a cell region CR, another region with relatively low component density, such as a peripheral region PR, and a boundary region BR located between the cell region CR and the peripheral region PR. These regions may be arranged adjacently or spaced apart. Preferably, the peripheral region PR is disposed around the outside of the cell region CR, for example, while the boundary region BR can be further disposed between the peripheral region PR and the cell region CR, and disposed around the outside of the cell region CR, such as... Figure 1 As shown, but not limited to. Those skilled in the art will readily understand that although the boundary region BR and the outer region PR are... Figure 1 The overall shape is square, but its specific implementation is not limited to this. In other embodiments, it can also present a racetrack-shaped, circular, or rectangular frame structure, etc., depending on the actual component requirements.

[0093] A contact pad array 110 is disposed on a substrate 100 and is generally located within the cell region CR. The contact pad array 110 includes, in detail, a plurality of first contact pads 112 and a contact pad protective ring 120 surrounding the first contact pads 112. The first contact pads 112 are arranged in a specific array, for example, along a first direction D1 and a second direction D2 that are not perpendicular to each other. Figure 1The array shown is such that the spacing between any two adjacent first contact pads 112 is the same in the first direction D1 or the second direction D2. Each first contact pad 112 has a side 112s parallel to the first direction D1, and they are arranged in a plurality of oblique rows C1, C2…Cn in the first direction D1. A contact pad protection ring 120 is also disposed on the substrate 100, located within the boundary region BR, and surrounds the first contact pads 112 along mutually perpendicular third directions D3 and fourth directions D4. In one embodiment, neither the third direction D3 nor the fourth direction D4 is perpendicular to the first direction D1 or the second direction D2, but this is not a limitation. A capacitor 180 is located on the contact pad array 110. It should be noted that the contact pad protection ring 120 includes a plurality of first auxiliary contact pads 122 arranged in the third direction D3 and a plurality of second auxiliary contact pads 124 arranged in the fourth direction D4. Each first auxiliary contact pad 122 has a first side 122s parallel to the third direction D3, and the first side 122s of the first auxiliary contact pads 122 are collinear with each other. Each second auxiliary contact pad 124 has a first side 124s parallel to the fourth direction D4, and the first side 124s of the second auxiliary contact pads 124 are also collinear with each other. Thus, by additionally providing a contact pad protection ring 120 surrounding the first contact pads 112 within the boundary region BR, the edge pattern of the contact pad array 110 is optimized, so that the first contact pads 112 arranged at the edge of the array can all have a complete outline, thereby improving the structural defects that may arise during the fabrication of the semiconductor device 10, enhancing its component reliability, and achieving excellent operational performance.

[0094] For details, please refer to the following: Figure 2The cross-sectional schematic diagram shows that the cell region CR of the semiconductor device 10 also includes a plurality of bit lines (BLs) 150 and a plurality of plugs 152 alternately disposed on the substrate 100, which are isolated from each other by bit line spacers 154. Below the bit lines 150, there are bit line plugs 150c that partially extend into the substrate 100. The first contact pads 112 of the contact pad array 110 are partially disposed above each plug 152 and partially disposed above each bit line 150, thereby enabling electrical contact with the capacitors 180 above the contact pad array 110. The plugs 152 partially extend into the substrate 100 to directly contact the substrate 100 and receive information therein. In one embodiment, the capacitor 180 further includes a plurality of bottom electrodes 182 (e.g., low-resistivity metal materials such as aluminum, titanium, copper, tungsten, or their nitrides, preferably titanium nitride) disposed in the vertical direction Y, a support layer disposed between the bottom electrodes 182, and a capacitor dielectric layer 184 (e.g., silicon oxide, silicon nitride, or a high dielectric material with a dielectric constant greater than 4, etc.) and a top electrode layer 186 (e.g., low-resistivity metal materials such as aluminum, titanium, copper, tungsten, or their nitrides, preferably titanium nitride) sequentially disposed on the bottom electrodes 182. On the other hand, the first auxiliary contact pad 122 and the second auxiliary contact pad 124 of the contact pad protection ring 120 are disposed on the insulating layer 156, serving as dummy boundary contact pads to maintain the structural integrity of the first contact pad 112 within the unit region CR. Those skilled in the art will readily understand that... Figure 2 Although only the second auxiliary contact pad 124 is shown in the diagram, the first auxiliary contact pad 122 should also be provided on the insulating layer 156 in another tangential direction.

[0095] For example Figure 1As shown, the spacing between any two adjacent first auxiliary contact pads 122 or second auxiliary contact pads 124 in the third direction D3 or the fourth direction D4 is equal to each other and exactly equal to the spacing between the first contact pads 112. The lengths of the second sides 122t and 124t of the first auxiliary contact pads 122 or second auxiliary contact pads 124 in the first direction D1 are greater than the lengths of the first sides 122s and 124s of the first auxiliary contact pads 122 or second auxiliary contact pads 124 in the third direction D3 or the fourth direction D4. In other words, the second sides 122t and 124t of the first auxiliary contact pads 122 or second auxiliary contact pads 124 are their major axes, while the first sides 122s and 124s are their minor axes. Furthermore, the minor axes of any two adjacent first auxiliary contact pads 122 or second auxiliary contact pads 124 are aligned with each other. It should be noted that the distance from the minor axis of each first auxiliary contact pad 122 or each second auxiliary contact pad 124 to a first contact pad 112 adjacent to it in the fourth direction D4 or the third direction D3 is equal to each other and is greater than the interval distance between any two adjacent first contact pads 112 or greater than the interval distance between any two adjacent first auxiliary contact pads 122 or second auxiliary contact pads 124.

[0096] Furthermore, the contact pad protection ring 120 also includes at least one third auxiliary contact pad 126 and at least one fourth auxiliary contact pad 128 located in the corner area 120c. These auxiliary contact pads, for example, simultaneously have a first side 126s / 128s parallel to the third direction D3 and a second side 126t / 128t parallel to the fourth direction D4, and also have a right angle θ sandwiched between the first side 126s / 128s and the second side 126t / 128t. Those skilled in the art will readily understand that the third auxiliary contact pad 126 and / or the fourth auxiliary contact pad 128 are, for example, disposed at the junction of the first auxiliary contact pad 122 and the second auxiliary contact pad 124, and their specific number varies depending on the arrangement of the first auxiliary contact pad 122 and the second auxiliary contact pad 124. For example, in this embodiment, the first auxiliary contact pad 122 and the second auxiliary contact pad 124 are arranged in a rectangular frame structure or a square frame structure along the third direction D3 and the fourth direction D4, respectively. The third auxiliary contact pad 126 and the fourth auxiliary contact pad 128 are respectively disposed at the apex corners of the rectangular frame structure or the square frame structure, and present a corresponding polygonal shape (including but not limited to triangles, trapezoids, or pentagons). In addition, each first auxiliary contact pad 122 and each second auxiliary contact pad 124 also has a second side 122t and 124t parallel to the first direction D1, so that the first auxiliary contact pad 122 or the second auxiliary contact pad 124 can be arranged together with a corresponding first contact pad 112 in the same oblique row C1, C2...Cn, so that the second side 122t and 124t of the aforementioned first auxiliary contact pad 122 or the second auxiliary contact pad 124 can be collinear with the side 112s of the corresponding first contact pad 112 arranged in the same oblique row C1, C2...Cn, such as Figure 1 As shown.

[0097] The semiconductor device 10 also includes a conductive structure 130 disposed around the contact pad protection ring 120, and an insulating structure 140 disposed around the first contact pad 112, the contact pad protection ring 120, and the conductive structure 130. Specifically, the conductive structure 130 is disposed on the substrate 100, entirely within the peripheral region PR, and surrounds the contact pad protection ring 120 along the third direction D3 and the fourth direction D4, presenting a square frame structure. The conductive structure 130 further includes a plurality of first conductive lines 132 arranged in the third direction D3, a plurality of second conductive lines 134 arranged in the fourth direction D4, and a third conductive line 136 arranged at the junction of the first conductive lines 132 and the second conductive lines 134. Each of the first conductors 132 has a first side 132s parallel to the third direction D3, and the first sides 132s of the first conductors 132 are collinear with each other and parallel to the first side 122s of the first auxiliary contact pad 122. Each of the second conductors 134 has a first side 134s parallel to the fourth direction D4, and the first sides 134s of the second conductors 134 are also collinear with each other and parallel to the first side 124s of the second auxiliary contact pad 124. Figure 1 As shown. The third conductor 136 has a side 136s parallel to the third direction D3 and a side 136t parallel to the fourth direction D4, and is located at the top corner of the square structure of the conductor structure 130, but is not limited thereto.

[0098] On the other hand, in such Figure 2 In the cross-sectional schematic shown, the first conductor 132 or the second conductor 134 of the conductor structure 130 is, for example, disposed on the logic active region 104 within the peripheral region PR, to serve as peripheral circuitry and electrically connect to components located within the peripheral region PR. Similarly, those skilled in the art should readily understand that... Figure 2Although only the second conductor 134 is shown in the diagram, the first conductor 132 should also be disposed on the active region 104 in another tangential direction, but this is not a limitation. Specifically, the first conductor 132 of the conductor structure 130 is located on the gate 160, for example, where the gate 160 is disposed on the active region 104 within the peripheral region PR, and gate gap walls 164 are also provided on its two sidewalls. In one embodiment, the bit line 150 located in the cell region CR and the gate 160 located in the peripheral region PR respectively include, for example, a semiconductor layer (not shown, including, for example, semiconductor materials such as doped polycrystalline silicon and doped amorphous silicon), a barrier layer (not shown, including, for example, conductive barrier materials such as titanium and / or titanium nitride, tantalum and / or tantalum oxide), a metal layer (not shown, including, for example, low-resistance metal materials such as tungsten, aluminum or copper), and a capping layer (not shown, including, for example, insulating materials such as silicon oxide, silicon nitride, silicon carbonitride or silicon oxynitride), but this is not a limitation. Furthermore, the bit line gap wall 154 located on the sidewall of bit line 150 and the gate gap wall 164 located on the sidewall of gate 160 may each comprise a single-layer or composite-layer gap wall layer, such as containing insulating materials such as silicon oxide, silicon nitride, silicon carbonitride, or silicon oxynitride, but are not limited thereto. In another embodiment, the first contact pad 112 located in the cell region CR, the first auxiliary contact pad 122 and the second auxiliary contact pad 124 located in the boundary region BR, and the first conductor 132 and the second conductor 134 located in the peripheral region PR may each comprise, for example, sequentially stacked barrier layers (not shown, such as including titanium and / or titanium nitride, tantalum and / or tantalum oxide, etc., conductive barrier materials) and metal layers (not shown, such as including copper, aluminum, tungsten, or other suitable low resistivity conductive materials), but are not limited thereto.

[0099] For example Figure 1 As shown, the insulating structure 140 is also disposed on the substrate 100, and respectively surrounds each of the first contact pads 112 of the contact pad array 110, each of the first auxiliary contact pads 122, each of the second auxiliary contact pads 124 and the third auxiliary contact pads 126 of the contact pad protection ring 120, and each of the first conductors 132, and each of the second conductors 134 and the third conductors 136 of the conductor structure 130. Please refer to the following: Figure 3 As shown, the insulation structure 140 may further include, in detail, a plurality of first insulation structures 142 extending continuously along the first direction D1, a plurality of second insulation structures 144 extending continuously along the second direction D2 and intersecting with the first insulation structures 142, a third insulation structure 146 located between the peripheral first contact pad 112 and the contact pad protection ring 120, and a fourth insulation structure 148 located between the conductor structure 130 and the contact pad protection ring 120.

[0100] In detail, the first insulating structure 142 is disposed between any two adjacent first contact pads 112 in the second direction D2, while the second insulating structure 144 is disposed between any two adjacent first contact pads 112 in the first direction D1. Both the first insulating structure 142 and the second insulating structure 144 are integrally located within the area surrounded by the contact pad protection ring 120. The first insulating structure 142 simultaneously contacts both the contact pad protection ring 120 and the first contact pads 112, while the second insulating structure 144 contacts the first contact pads 112. It should be noted that the maximum extension length of the first insulating structure 142 in the first direction D1 is greater than the maximum extension length of the second insulating structure 144 in the second direction D2, allowing each first insulating structure 142 to partially extend into the contact pad protection ring 120, thus dividing it into a first auxiliary contact pad 122, a second auxiliary contact pad 124, and a third auxiliary contact pad 126, as shown below. Figure 3 As shown. The third insulating structure 146 and the fourth insulating structure 148 are respectively included in the first portion 146a, 148a in the third direction and the second portion 146b, 148b in the fourth direction. The first portion 146a and the second portion 146b of the third insulating structure 146 are continuously arranged, and the first insulating structure 142 also spans across the first portion 146a and the second portion 146b of the third insulating structure 146. Similarly, the first portion 148a and the second portion 148b of the fourth insulating structure 148 are also continuously arranged, as shown. Figure 3 As shown. The width W2 of the first portion 148a or the second portion 148b of the fourth insulating structure 148 is greater than the width W1 of the first portion 146a or the second portion 146b of the third insulating structure 146.

[0101] In this configuration, the capacitor 180 located in the cell region CR can be electrically connected to the transistor assembly (not shown) in the substrate 100 via the contact pad array 110 and plug 152 arranged sequentially below, and together with the transistor assembly, forms the smallest unit of the memory array, receiving voltage information from the bit line 150 and word line (not shown). Thus, the semiconductor device 10 can function as a dynamic random access memory (DRAM) to perform the required functions and operations. The gate 160 and the wire structure 130 located in the peripheral region PR are both located on the logic active region 104 of the peripheral region PR, and together form the peripheral circuitry. The contact pad protection ring 120 located in the boundary region BR can be formed synchronously with the first contact pad 112 in the cell region CR, and together they form the contact pad array 110. This balances the component density difference between the cell region CR and the peripheral region PR, and improves the structural defects that are easily generated on the first contact pads 112 around the contact pad array 110 due to the continuous increase in the density of the first contact pads 112 in the cell region CR. This allows the semiconductor device 10 to have a more stable and reliable structure and achieve relatively optimized device performance. In addition, since the insulating structure 140 of this embodiment includes a first insulating structure 142, a second insulating structure 144, a third insulating structure 146 and a fourth insulating structure 148 extending in different directions, different insulation effects can be achieved around the first contact pads 112 and / or the contact pad protection ring 120 of the contact pad array 110, thereby improving the operational performance of the semiconductor device 10.

[0102] To enable those skilled in the art to easily understand the semiconductor device 10 of the present invention, the manufacturing method of the semiconductor device 10 of the present invention will be further described below.

[0103] Please refer to the following: Figures 4 to 7 The diagram shown is a top view illustrating a portion of the manufacturing process of the semiconductor device 10 according to the first embodiment of the present invention. First, please refer to the foregoing... Figure 2 As shown, a substrate 100 is first provided, and at least one shallow trench isolation 102 is formed within the substrate 100 to define an active region 104. Then, as shown in the diagram, the active region 104 is sequentially formed on the substrate 100. Figure 2 The shown components, including bit line plug 150c, bit line 150, plug 152, bit line spacer 154, and insulating layer 156, are located within the cell region CR; and, during the formation of bit line 150 and bit line spacer 154, components such as... are simultaneously formed on the substrate 100. Figure 2 The gate 160 and gate gap wall 164, as shown, are located within the peripheral region PR. Next, as... Figure 4As shown, a target layer 200 and a mask structure (not shown) are sequentially formed above bit line 150, plug 152, and insulating layer 156. The target layer 200 includes, for example, sequentially stacked barrier layers (not shown, such as titanium and / or titanium nitride, tantalum and / or tantalum oxide, etc., conductive barrier materials) and metal layers (not shown, such as copper, aluminum, tungsten, or other suitable low-resistivity conductive materials). A first block 202 located within the cell region CR and a second block 204 located within the peripheral region PR are pre-formed on it using a patterning process. The second block 204 extends continuously along a third direction D3 and a fourth direction D4, and surrounds the first block 202.

[0104] In detail, the mask structure includes, for example, a composite structure having at least an organic underlayer (not shown), a silicon hard mask bottom anti-reflective coating (not shown), a hard mask layer, and a mask layer 210 located on the top layer of the mask structure, stacked sequentially on the target layer 200. Then, by performing a first patterning process, such as a first self-aligned reverse patterning (SARP) fabrication process, a plurality of first sub-annular patterns RP1 are additionally formed above the mask layer 210, located on the first block 202 of the target layer 200. Each of the first sub-annular patterns RP1 extends parallel to each other in a first direction D1 and is rectangular in shape, such as... Figure 4 As shown. It should be noted that the extension length of each first sub-annular pattern RP1 in the first direction D1 is not exactly the same. For example, it has the largest extension length L1 in the first direction D1, but it is not limited to this.

[0105] like Figure 5 As shown, a mask layer 212 is formed over the first sub-annular pattern RP1 and the mask layer 210, covering the entire structure. Then, by performing a second patterning process, such as a second self-aligned reverse patterning process, a plurality of second sub-annular patterns RP2 are additionally formed above the mask layer 212, also located on the first block 202 of the target layer 200, and intersect with the first sub-annular pattern RP1 formed below. Each of the second sub-annular patterns RP2 extends parallel to each other in the second direction D2, and also presents a rectangular frame shape. It should be noted that the extension lengths of each second sub-annular pattern RP2 in the second direction D2 are not entirely the same, with the largest extension length L2 in the second direction D2, which is preferably less than the extension length L1 of the first sub-annular pattern RP1 in the first direction D1. Thus, the first sub-annular pattern RP1 and the second sub-annular pattern RP2 can together form the first annular pattern OP1, and the extension range of each second sub-annular pattern RP2 in the third direction D3 will not exceed the extension range of the first sub-annular pattern RP1 formed below in the third direction D3, as shown. Figure 5 As shown.

[0106] like Figure 6 As shown, a mask layer 214 is formed over the first annular pattern OP1. Then, by performing a third patterning process, such as a third self-aligned reverse patterning process, multiple second annular patterns OP2 and third annular patterns OP3 are additionally formed above the mask layer 214. The third annular pattern OP3 extends continuously along the third direction D3 and the fourth direction D4, presenting a rectangular shape, and is formed on the first block 202 of the target layer 200, partially covering the first annular pattern OP1 and partially overlapping with each of the first sub-annular patterns RP1 and each of the second sub-annular patterns RP2. Each of the second annular patterns OP2 presents a rectangular shape and sequentially surrounds the third annular pattern OP3 along the third direction D3 and the fourth direction D4, forming on the second block 204 of the target layer 200.

[0107] Next, as Figure 7 As shown, a mask layer 216 is formed over the second annular pattern OP2 and the third annular pattern OP3. Then, by performing a fourth patterning process, such as a fourth self-aligned reverse patterning process, a fourth annular pattern OP4 is additionally formed above the mask layer 216. The fourth annular pattern OP4 extends continuously along the third direction D3 and the fourth direction D4, presenting a square shape, and surrounds the periphery of the third annular pattern OP3, so that it is generally located between the third annular pattern OP3 and the second annular pattern OP2. That is, the fourth annular pattern OP4 is formed, for example, between the cell region CR and the peripheral region PR, and is located on the periphery of the first block 202 of the target layer 200, partially covering the ends of each of the first sub-annular patterns RP1 and each of the second annular patterns OP2 in the first annular pattern OP1. Those skilled in the art will readily understand that the aforementioned ends refer to the edges of each pattern, such as... Figure 7 As shown, the end of the first sub-annular pattern RP1 or the second annular pattern OP2 should be the side adjacent to the fourth annular pattern OP4, but is not limited thereto.

[0108] Then, a pattern transfer process is performed on the fourth annular pattern OP4 formed on the mask layer 216, the second annular pattern OP2 and the third annular pattern OP3 formed on the mask layer 214, and the first annular pattern OP1 partially formed on the mask layer 212 and partially formed on the mask layer 210. The mask layer 216 below the fourth annular pattern OP4, the mask layer 214 below the second annular pattern OP2 and the third annular pattern OP3, the mask layer 210 below the second sub-annular pattern RP2, and the mask layer 210 below the first sub-annular pattern RP1 are etched in sequence. In this way, the portions of the target layer 200 covered by the first annular pattern OP1, the second annular pattern OP2, the third annular pattern OP3 and the fourth annular pattern OP4 can be removed at the same time. Finally, multiple target patterns (not shown) are formed on the target layer 200.

[0109] Please refer to the above. Figure 1 As shown, the target pattern includes a first contact pad 112 formed by simultaneously transferring the first annular pattern OP1 and the third annular pattern OP3 to a first block 202 of the target layer 200, and a conductor structure 130 formed by transferring the second annular pattern OP2 to a second block 204 of the target layer 200. The first contact pad 112 is partially formed above each plug 152 and partially formed above each bit line 150, for electrical connection to each plug 152. The conductor structure 130 includes, in detail, a first conductor 132, a second conductor 134, and a third conductor 136 located within the peripheral region PR. The target pattern also includes a contact pad protection ring 120 formed between the cell region CR and the peripheral region PR by simultaneously transferring the first annular pattern OP1, the second annular pattern OP2, the third annular pattern OP3, and the fourth annular pattern OP4 to the target layer 200. This ring includes, in detail, a first auxiliary contact pad 122, a third auxiliary contact pad 126, and a second auxiliary contact pad 124 arranged sequentially to jointly form the contact pad protection ring 120. Thus, the location where the contact pad protection ring 120 is formed is the boundary region BR, and the first contact pad 112 formed in the cell region CR and the contact pad protection ring 120 formed in the boundary region BR can jointly form the contact pad array 110 of the semiconductor device 10.

[0110] Subsequently, deposition and etch-back processes are performed to form insulating structures 140 on the substrate 100, each surrounding a first auxiliary contact pad 122, a third auxiliary contact pad 126, and a second auxiliary contact pad 124, and each of a first conductor 132, a second conductor 134, and a third conductor 136 of the conductor structure 130. Then, a capacitor 180 is formed on the first contact pad 112 within the cell region CR, such that the capacitor 180 can be electrically connected to the substrate 100 through the first contact pad 112 and the plug 152 to receive information therein. On the other hand, the contact pad protection ring 120 forms a dummy boundary contact pad, which is disposed around the first contact pad 112 during its fabrication to maintain the structural integrity of the first contact pad 112 within the cell region CR.

[0111] This operation completes the fabrication of the semiconductor device 10 in the first embodiment of the present invention. According to the fabrication method of this embodiment, a first annular pattern OP1, a second annular pattern OP2, a third annular pattern OP3, and a fourth annular pattern OP4 are sequentially formed by performing multiple self-aligned reverse patterning processes. Then, an etching process is performed on the first annular pattern OP1, the second annular pattern OP2, the third annular pattern OP3, and the fourth annular pattern OP4, simultaneously removing the corresponding portions of the first annular pattern OP1, the second annular pattern OP2, the third annular pattern OP3, and the fourth annular pattern OP4 on the target layer 200. Simultaneously, a first contact pad 112 is formed in the cell region CR, a conductive structure 130 is formed in the peripheral region PR, and a contact pad protection ring 120 is formed in the boundary region BR. In other words, by simultaneously performing the patterning process of the first contact pad 112 and the contact pad protection ring 120, the overall fabrication process of the semiconductor device 10 can be simplified. Furthermore, the first contact pad 112 is continuously surrounded and protected by the contact pad protection ring 120 during the fabrication process, which helps maintain the structural integrity of the first contact pad 112 surrounding the contact pad array 110. Accordingly, the device 10 of this embodiment can effectively improve the structural defects that easily arise on the first contact pad 112 surrounding the contact pad array 110 due to the continuously increasing density of the first contact pad 112 within the cell region CR, thereby enabling the fabricated semiconductor device 10 to have a more stable and reliable structure and achieve relatively optimized device performance.

[0112] Those skilled in the art will readily understand that, to meet actual product requirements, the semiconductor device 10 and its fabrication method of this invention may have other forms and are not limited to those described above. Further descriptions will follow regarding other embodiments or variations of the semiconductor device of this invention. For simplicity, the following description focuses on the differences between the embodiments, without repeating the similarities. Furthermore, identical components in the embodiments of this invention are designated with the same reference numerals to facilitate comparison between embodiments. For example... Figure 8 As shown, the structure and fabrication method of the semiconductor device 30 in this embodiment are largely the same as those of the semiconductor device 10 in the previous embodiment, and the similarities will not be repeated here. The main difference between the semiconductor device 30 in this embodiment and the previous embodiment is that it also includes a plurality of second contact pads 314 arranged around all the first contact pads 112.

[0113] For details, please refer to the foregoing embodiments. Figures 5 to 7 As shown, by adjusting the extension length of the second sub-annular pattern RP2 in the second direction D2, and / or the overlapping areas of each second sub-annular pattern RP2 and each first sub-annular pattern RP1, a second contact pad 314 is additionally formed between the first contact pad 112 and the contact pad protection ring 120 after simultaneously removing portions of the target layer 200 covered by the first annular pattern OP1, the second annular pattern OP2, the third annular pattern OP3, and the fourth annular pattern OP4. Furthermore, the first contact pad 112 and the second contact pad 314 formed in the cell region CR, and the contact pad protection ring 120 formed in the boundary region BR, can jointly form the contact pad array 310 of the semiconductor device 30. It should be noted that the second contact pads 314 are arranged, for example, along the third direction D3 and the fourth direction D4 around all the first contact pads 112, and each second contact pad 314 can be arranged together with the first contact pads 112 and the first auxiliary contact pads 122 / second auxiliary contact pads 124 arranged in the corresponding oblique rows C1, C2...Cn in the same oblique rows C1, C2...Cn, such as... Figure 8 As shown. In addition, the area of ​​each second contact pad 314 is smaller than the area of ​​each first contact pad 112, for example, about one-half to one-quarter of the area of ​​each first contact pad 112, but not limited thereto.

[0114] In this configuration, the contact pad protection ring 120 disposed in the boundary region BR and the second contact pad 314 additionally disposed in the cell region CR can be simultaneously disposed around the first contact pad 112, further maintaining and protecting the edge pattern of the contact pad array 310, improving the structural integrity of the first contact pad 112 disposed around the array, so that the first contact pads 112 arranged at the edge of the array can all have a complete outline, thereby improving the structural defects that may arise in the fabrication of the semiconductor device 30, enhancing its component reliability and achieving excellent operational performance.

[0115] In general, semiconductor devices and their fabrication methods involve performing a self-aligned reverse patterning process to sequentially form multiple interlocking and partially stacked annular patterns. Then, an etching process is performed on these annular patterns to remove portions of the target layer corresponding to the annular patterns, simultaneously forming different target patterns in the cell region, peripheral region, and boundary region. Thus, simultaneously...

[0116] When performing the patterning process of contact pads and contact pad protection rings, contact pad protection rings can be used to surround the contact pads to protect and maintain the structural integrity of the contact pads. This effectively improves the problem of structural defects that are easily generated on the contact pads around the array due to the continuous increase in the density of contact pads in the cell area. This allows the manufactured semiconductor devices to have more optimized structure and component reliability and achieve excellent operating performance and efficiency.

[0117] The foregoing has outlined the features of several embodiments to enable those skilled in the art to fully understand various aspects of the invention. Those skilled in the art should recognize that the invention provides a basis for designing or modifying other processes and structures to achieve substantially the same functionality and / or substantially the same results as the embodiments described above. Furthermore, such equivalent configurations do not depart from the spirit and scope of the invention, and various changes, substitutions, and modifications can be made without departing from that spirit and scope.

Claims

1. A semiconductor device, characterized in that... include: The substrate includes multiple shallow trench isolations and multiple active regions; A contact pad array, located on the substrate, includes: Multiple first contact pads are arranged along a first direction and a second direction that are not perpendicular to each other, and are arranged in multiple oblique rows in the first direction; A contact pad protection ring surrounds the first contact pad along two mutually perpendicular third and fourth directions, wherein neither the third nor the fourth direction is perpendicular to the first or second direction. The contact pad protection ring includes: A plurality of first auxiliary contact pads are arranged in the third direction, each first auxiliary contact pad having a first side parallel to the third direction, wherein the first sides of the respective first auxiliary contact pads are collinear with each other; and A plurality of second auxiliary contact pads are arranged in the fourth direction, each second auxiliary contact pad having a first side parallel to the fourth direction, wherein the first sides of the respective second auxiliary contact pads are collinear with each other; and The capacitor is located on the contact pad array.

2. A semiconductor device, characterized in that... include: The substrate includes a cell region, a peripheral region, and a boundary region located between the cell region and the peripheral region. The cell region includes a plurality of active regions, and the peripheral region includes a plurality of logical active regions. A plurality of first contact pads are located in the unit area, the first contact pads are arranged along a first direction and a second direction that are not perpendicular to each other, and two first contact pads adjacent in the first direction or the second direction are aligned with each other. A plurality of first auxiliary contact pads and a plurality of second auxiliary contact pads are located in the boundary region and arranged along mutually perpendicular third and fourth directions. Each first auxiliary contact pad and each second auxiliary contact pad has a major axis extending along the first direction and a minor axis extending along the third or fourth direction. The minor axes of two adjacent first auxiliary contact pads in the third direction or two adjacent second auxiliary contact pads in the fourth direction are aligned with each other along the third or fourth direction. Peripheral circuitry is located on the logic active region; as well as The capacitor is located on the first contact pad.

3. The semiconductor device according to claim 1 or 2, characterized in that, Each of the first auxiliary contact pads has a second side parallel to the first direction, wherein the second side of one of the first auxiliary contact pads is collinear with the side of one of the first contact pads parallel to the first direction, and each of the second auxiliary contact pads has a second side parallel to the first direction, wherein the second side of one of the second auxiliary contact pads is collinear with the side of another of the first contact pads parallel to the first direction.

4. The semiconductor device according to claim 1 or 2, characterized in that... Also includes: At least one third auxiliary contact pad is located between a first auxiliary contact pad and a second auxiliary contact pad, and has a first side parallel to the third direction, a second side parallel to the fourth direction, and a right angle sandwiched between them.

5. The semiconductor device according to claim 1 or 2, characterized in that, Also includes: A conductive wire structure surrounds the first auxiliary contact pad and the second auxiliary contact pad along the third and fourth directions, wherein the conductive wire structure includes: A plurality of first conductors are arranged in the third direction, each first conductor having a first side parallel to the third direction, wherein the first sides of each first conductor are collinear with each other; and A plurality of second conductors are arranged in the fourth direction, each second conductor having a first side parallel to the fourth direction, wherein the first sides of each second conductor are collinear with each other.

6. The semiconductor device according to claim 5, characterized in that... Also includes: An insulating structure is disposed on the substrate, surrounding each of the first contact pads, each of the first auxiliary contact pads, each of the second auxiliary contact pads, each of the first conductors, and each of the second conductors.

7. The semiconductor device according to claim 1, characterized in that, At least one of the first auxiliary contact pads or at least one of the second auxiliary contact pads is arranged in the same diagonal row as one of the first contact pads.

8. The semiconductor device according to claim 1 or 2, characterized in that, Also includes: Multiple second contact pads are arranged around all the first contact pads along the third and fourth directions, and the area of ​​each second contact pad is smaller than the area of ​​each first contact pad.

9. The semiconductor device according to claim 2, characterized in that, At least two first contact pads adjacent to one first auxiliary contact pad and one second auxiliary contact pad are aligned with each other in the fourth direction.

10. The semiconductor device according to claim 2, characterized in that, The distance between the short axis of one of the first auxiliary contact pads and one of the second auxiliary contact pads and an adjacent first contact pad in the third direction is equal to the distance between the short axis of another first auxiliary contact pad and one of the second auxiliary contact pads and an adjacent first contact pad in the third direction.

11. The semiconductor device according to claim 10, characterized in that, The spacing between any two adjacent first contact pads in the first direction or the second direction is equal to the spacing between any two adjacent auxiliary contact pads in the third direction or the fourth direction, and the spacing between the first contact pads is less than the spacing between the first auxiliary contact pad or the second auxiliary contact pad.

12. A semiconductor device, characterized in that... include: Contact pad array, including: Multiple first contact pads are arranged and spaced apart from each other along a first direction and a second direction that are not perpendicular to each other; and A contact pad protection ring surrounds the first contact pad along two mutually perpendicular third and fourth directions, wherein neither the third nor the fourth direction is perpendicular to the first or second direction; and An insulating structure surrounding each of the first contact pads and the contact pad protection ring, the insulating structure comprising: A first insulating structure extends continuously along a first direction and is located between any two adjacent first contact pads and within the contact pad protection ring in the second direction, and simultaneously contacts the contact pad protection ring and the first contact pad. The second insulating structure extends continuously along the second direction, is shorter than the first insulating structure in the third direction, and is located between any two adjacent first contact pads and contacts the first contact pads in the first direction. A third insulating structure is located between the first contact pad and the contact pad protection ring. The third insulating structure includes a first portion in the third direction and a second portion in the fourth direction. The first portion and the second portion of the third insulating structure are continuously disposed, wherein the first insulating structure spans the second portion of the third insulating structure, and the second insulating structure contacts the first portion of the third insulating structure.

13. A semiconductor device, characterized in that... include: Multiple first contact pads are arranged along first and second directions that are not perpendicular to each other; Multiple first insulating structures extend continuously in the first direction and are disposed between any two adjacent first contact pads in the second direction; Multiple second insulating structures extend continuously in the second direction and are disposed between any two adjacent first contact pads in the first direction; as well as A contact pad protection ring surrounds the first contact pad along a third and a fourth direction that are perpendicular to each other, wherein neither the third nor the fourth direction is perpendicular to the first and second directions. Each of the first insulating structures also extends into the contact pad protection ring, dividing the contact pad protection ring into a plurality of auxiliary contact pads.

14. The semiconductor device according to claim 12 or 13, characterized in that, Also includes: A conductor structure surrounds the contact pad protection ring along the third and fourth directions, wherein the insulation structure further includes a fourth insulation structure located between the conductor structure and the contact pad protection ring, the fourth insulation structure comprising a first portion in the third direction and a second portion in the fourth direction, the first and second portions of the fourth insulation structure being continuously disposed.

15. The semiconductor device according to claim 14, characterized in that, The conductor structure also includes: A plurality of first conductors are arranged in the third direction, each first conductor having a first side parallel to the third direction, wherein the first sides of each first conductor are collinear with each other; A plurality of second conductors arranged in the fourth direction, each second conductor having a first side parallel to the fourth direction, wherein the first sides of each second conductor are collinear with each other; and A capacitor is disposed on the first contact pad.

16. The semiconductor device according to claim 15, characterized in that... The contact pad protection ring also includes: A plurality of first auxiliary contact pads are arranged in the third direction, each first auxiliary contact pad having a first side parallel to the third direction, wherein the first sides of each first auxiliary contact pad are collinear with each other and parallel to the first side of each first conductor; and A plurality of second auxiliary contact pads are arranged in the fourth direction, each second auxiliary contact pad having a first side parallel to the fourth direction, wherein the first side of each second auxiliary contact pad is collinear with each other and parallel to the first side of each second conductor.

17. The semiconductor device according to claim 16, characterized in that, The contact pad protection ring further includes at least one third auxiliary contact pad, which has a first side parallel to the third direction and a second side parallel to the fourth direction.

18. The semiconductor device according to claim 16, characterized in that, Each of the first auxiliary contact pads also has a second side parallel to the first direction, and each of the second auxiliary contact pads also has a second side parallel to the first direction, wherein the second side of one of the first auxiliary contact pads is collinear with the side of one of the first contact pads parallel to the first direction, and the second side of one of the second auxiliary contact pads is collinear with the side of another of the first contact pads parallel to the first direction.

19. A method for fabricating a semiconductor device, characterized in that... include: A target layer is provided, comprising a first block and a second block surrounding the first block; Multiple first annular patterns are formed on the first block of the target layer; Multiple second annular patterns are formed on the second block of the target layer; A third annular pattern is formed on the first region of the target layer, partially covering the first annular pattern; A fourth annular pattern is formed on the target layer, the fourth annular pattern spanning the first block and the second block, and covering the ends of each of the first annular pattern and the second annular pattern; A pattern transfer process is performed to remove portions of the target layer covered by the first annular pattern, the second annular pattern, the third annular pattern, and the fourth annular pattern, thereby forming a target pattern on the target layer.

20. The method for fabricating a semiconductor device according to claim 19, characterized in that, The first annular pattern includes a first sub-annular pattern and a second sub-annular pattern. The first sub-annular pattern extends in a first direction, and the second sub-annular pattern extends in a second direction. The extension length of each second sub-annular pattern in the second direction is less than the extension length of each first sub-annular pattern in the first direction.

21. The method for fabricating a semiconductor device according to claim 20, characterized in that, The target pattern includes: Contact pad array, including: Multiple first contact pads are arranged along the first direction and the second direction; and A plurality of second contact pads are arranged around all the first contact pads along a third and a fourth direction, wherein the area of ​​each second contact pad is smaller than the area of ​​each first contact pad; and Contact pad protection ring.

22. The method for fabricating a semiconductor device according to claim 21, characterized in that, The target pattern includes: A plurality of first wires arranged in the direction of the third party; and A plurality of second conductors are arranged in the fourth direction, the first conductor and the second conductors sequentially surrounding the contact pad array.

23. The method for fabricating a semiconductor device according to claim 21, characterized in that, Also includes: A capacitor is formed on the contact pad array.

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