An integrated circuit structure and a method of fabricating the same

Abstract

The application provides an integrated circuit structure and a manufacturing method thereof. The integrated circuit structure comprises a substrate layer, a first drift region, a second drift region, a transistor well region, a high-voltage gate oxide layer, a low-voltage gate oxide layer, a gate, a first source-drain region and a second source-drain region. The substrate layer is divided into a high-voltage CMOS region, a low-voltage CMOS region and a transistor region. The first drift region and the second drift region are located in the substrate layer of the transistor region, and a channel region is defined between the first drift region and the second drift region. The transistor well region is located in the substrate layer of the channel region. The low-voltage gate oxide layer is located on the substrate layer of the channel region, and the high-voltage gate oxide layer is located on the first drift region and the second drift region. The thickness of the low-voltage gate oxide layer is less than the thickness of the high-voltage gate oxide layer. The integrated circuit structure of the application is a new transistor prepared by mixed use of a high-voltage device and a low-voltage device. The integrated circuit structure can resist high voltage and selectively realize a depletion mode characteristic or an enhancement mode characteristic. Moreover, the manufacturing process of the integrated circuit structure reduces manufacturing cost because no additional mask is needed.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology and relates to an integrated circuit structure and its fabrication method. Background Technology

[0002] In the fields of power electronics and signal processing, metal-oxide-semiconductor field-effect transistors (MOSFETs) are classified into two main categories based on their ability to control the conductive channel through the gate voltage: enhancement-mode and depletion-mode. Enhancement-mode MOSFETs form a conductive channel only after a voltage is applied to the gate; when the gate voltage is zero, the conductive channel is in the off state. Depletion-mode MOSFETs, on the other hand, have an initial conductive channel, which is already conducting when the gate bias voltage is zero.

[0003] Enhancement-mode MOSFETs and depletion-mode MOSFETs require different fabrication methods due to their structural differences, and each possesses distinct advantages. Enhancement-mode MOSFETs automatically turn off when the gate voltage is zero, achieving extremely low quiescent power consumption and higher system safety, while also simplifying the drive circuit, thus becoming the mainstream in digital integrated circuits and power switching. Depletion-mode MOSFETs naturally turn on at zero gate voltage, significantly simplifying high-voltage startup circuits and serving as series protection devices for rapid overvoltage turn-off, making them irreplaceable in applications such as power supply startup, constant current drives, and solid-state relays. Furthermore, when circuits require handling high voltages and the MOSFET must withstand power supply voltage or system-generated spikes without breakdown in the off-state, high-voltage MOSFETs are required.

[0004] In current integrated circuit chip manufacturing, an additional photomask is typically required to fabricate depletion-type transistors, which increases manufacturing costs. Furthermore, existing technologies necessitate the use of different process methods to fabricate depletion-type and enhancement-type transistors separately. Currently, there is a lack of a high-voltage-resistant transistor structure on the market that can selectively achieve depletion-type characteristics or ultra-low threshold voltage enhancement-type characteristics on the same basic structure through simple process adjustments to meet the needs of different circuit applications. Therefore, there is an urgent need for a high-voltage-resistant transistor that offers high flexibility and low fabrication costs. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide an integrated circuit structure and its fabrication method, which solves the problems of high manufacturing cost and low fabrication flexibility of high voltage-resistant transistors in the prior art.

[0006] To achieve the above and other related objectives, in one aspect, the present invention provides an integrated circuit structure, comprising:

[0007] The substrate layer is of the first conductivity type and is divided into a high-voltage CMOS region, a low-voltage CMOS region and a transistor region according to a preset rule.

[0008] The first drift region and the second drift region are located in the substrate layer of the transistor region and are spaced apart. Both the first drift region and the second drift region are of the second conductivity type. The region between the first drift region and the second drift region defines the channel region of the transistor.

[0009] A transistor well region, located in the substrate layer of the channel region, wherein the transistor well region is of a first conductivity type;

[0010] A high-voltage gate oxide layer and a low-voltage gate oxide layer, wherein the low-voltage gate oxide layer is located on the substrate layer of the low-voltage CMOS region and the channel region, and the high-voltage gate oxide layer is located on the high-voltage CMOS region and the first drift region and the second drift region, and the thickness of the low-voltage gate oxide layer is less than the thickness of the high-voltage gate oxide layer;

[0011] The gate, the low-voltage gate oxide layer covering the channel region, and extending to both sides onto the high-voltage gate oxide layer of the first drift region and the second drift region;

[0012] A first source / drain region and a second source / drain region, wherein the first source / drain region is located in the first drift region and the second source / drain region is located in the second drift region, and both the first source / drain region and the second source / drain region are of the second conductivity type.

[0013] Optionally, the integrated circuit structure includes a low-voltage enhancement-mode transistor well region and a high-voltage depletion-mode transistor well region. The main portion of the low-voltage enhancement-mode transistor well region is located in the substrate layer of the low-voltage CMOS region, and the main portion of the high-voltage depletion-mode transistor well region is located in the substrate layer of the high-voltage CMOS region. A portion of the low-voltage enhancement-mode transistor well region serves as the transistor well region, or a portion of the high-voltage depletion-mode transistor well region serves as the transistor well region.

[0014] Optionally, the thickness of the high-voltage gate oxide layer ranges from 30 nm to 90 nm, and the thickness of the low-voltage gate oxide layer ranges from 3 nm to 4 nm.

[0015] Optionally, the first source / drain region and the gate are spaced apart by a predetermined distance in the horizontal direction. The high-voltage gate oxide layer located on the first drift region overlaps with the gate portion at one end near the channel region and overlaps with the first source / drain region at the other end away from the channel region. The second source / drain region and the gate are spaced apart by a predetermined distance in the horizontal direction. The high-voltage gate oxide layer located on the second drift region overlaps with the gate portion at one end near the channel region and overlaps with the second source / drain region at the other end away from the channel region.

[0016] Optionally, in the direction from the first source / drain region to the second source / drain region, the length of the portion of the high-voltage gate oxide layer on the first drift region that is covered by the gate is M1, the length of the portion of the high-voltage gate oxide layer on the second drift region that is covered by the gate is M2, the length of the portion of the high-voltage gate oxide layer on the first drift region that does not cover the first source / drain region is N1, and the length of the region of the high-voltage gate oxide layer on the second drift region that does not cover the second source / drain region is N2, wherein M1:N1=1 / 3~1 / 2, M2:N2=1 / 3~1 / 2.

[0017] This invention also provides a method for fabricating an integrated circuit structure, comprising the following steps:

[0018] A substrate layer is provided, the substrate layer being of a first conductivity type, and the substrate layer being divided into a high voltage CMOS region, a low voltage CMOS region, and a transistor region according to a preset rule;

[0019] A high-voltage gate oxide layer is formed, the high-voltage gate oxide layer being located on the substrate layer between the high-voltage CMOS region and the transistor region;

[0020] A first drift region and a second drift region are formed at intervals in the substrate layer of the transistor region. Both the first drift region and the second drift region are of the second conductivity type. The region between the first drift region and the second drift region defines the channel region of the transistor.

[0021] The high-voltage gate oxide layer located on the channel region is removed, and a transistor well region is formed in the substrate layer of the channel region, wherein the transistor well region is of a first conductivity type;

[0022] A low-voltage gate oxide layer is formed, which is located on the substrate layer between the low-voltage CMOS region and the channel region, and the thickness of the low-voltage gate oxide layer is less than the thickness of the high-voltage gate oxide layer.

[0023] A gate is formed, the gate covering the low-voltage gate oxide layer of the channel region and extending to both sides onto the high-voltage gate oxide layer of the first drift region and the second drift region;

[0024] A first source / drain region and a second source / drain region are formed. The first source / drain region is located in the first drift region, and the second source / drain region is located in the second drift region. Both the first source / drain region and the second source / drain region are of the second conductivity type.

[0025] Optionally, before the step of forming a transistor well region in the substrate layer of the channel region, a step of forming a sacrificial oxide layer on the substrate layer of the channel region is further included; after the step of forming a transistor well region in the substrate layer of the channel region, a step of removing the sacrificial oxide layer is further included.

[0026] Optionally, forming the transistor well region includes the following steps: providing a high-voltage depletion-type transistor well region photomask, performing ion implantation based on the high-voltage depletion-type transistor well region photomask to form a high-voltage depletion-type transistor well region in the substrate layer of the high-voltage CMOS region and the transistor region, wherein the portion of the high-voltage depletion-type transistor well region located in the transistor region serves as the transistor well region; or, providing a low-voltage enhancement-type transistor well region photomask, performing ion implantation based on the low-voltage enhancement-type transistor well region photomask to form a low-voltage enhancement-type transistor well region in the substrate layer of the low-voltage CMOS region and the transistor region, wherein the portion of the low-voltage enhancement-type transistor well region located in the transistor region serves as the transistor well region.

[0027] Optionally, the ion implantation energy range used to form the low-voltage enhancement-mode transistor well region is 20keV~250keV, and the ion implantation dose range used to form the low-voltage enhancement-mode transistor well region is 1×10⁻⁶. 13 cm -2 ~3×10 13 cm -2 The ion implantation energy range used to form the high-voltage depletion transistor well region is 20keV to 500keV, and the ion implantation dose range used to form the high-voltage depletion transistor well region is 1×10⁻⁶. 12 cm -2 ~2×10 13 cm -2 .

[0028] Optionally, forming the first source / drain region and the second source / drain region includes the following steps:

[0029] Source / drain injection windows are formed in the high-voltage gate oxide layer of the transistor region;

[0030] Ion implantation is performed to form a first source / drain region in a first drift region below the source / drain implantation window, and a second source / drain region is formed in a second drift region below the source / drain implantation window. The first source / drain region and the gate are spaced apart by a predetermined distance in the horizontal direction, and the second source / drain region and the gate are spaced apart by a predetermined distance in the horizontal direction.

[0031] Optionally, the thickness of the high-voltage gate oxide layer ranges from 30 nm to 90 nm, and the thickness of the low-voltage gate oxide layer ranges from 3 nm to 4 nm.

[0032] As described above, the integrated circuit structure of the present invention includes a substrate layer, a first drift region, a second drift region, a transistor well region, a high-voltage gate oxide layer, a low-voltage gate oxide layer, a gate, a first source / drain region, and a second source / drain region. The substrate layer is divided into a high-voltage CMOS region, a low-voltage CMOS region, and a transistor region according to a predetermined rule. The first drift region and the second drift region are located in the substrate layer of the transistor region and are spaced apart. The region between the first drift region and the second drift region defines a transistor channel region. The transistor well region is located in the substrate layer of the channel region. The low-voltage gate oxide layer is located on the substrate layer of the low-voltage CMOS region and the channel region. The high-voltage gate oxide layer is located on the high-voltage CMOS region and the first and second drift regions, and the thickness of the low-voltage gate oxide layer is less than the thickness of the high-voltage gate oxide layer. The gate covers the low-voltage gate oxide layer of the channel region and extends to both sides onto the high-voltage gate oxide layers of the first and second drift regions. The first source / drain region is located in the first drift region, and the second source / drain region is located in the second drift region. The integrated circuit structure of this invention is a novel transistor fabricated using a photomask that combines high-voltage and low-voltage devices. By establishing a drift region and applying a thick gate oxide layer on the drift region, the overall structure can withstand high voltages. By adjusting the doping concentration of the transistor well region and applying a thin gate oxide layer on the well region, the overall structure can selectively achieve depletion-mode or ultra-low threshold voltage enhancement-mode characteristics, thus flexibly adapting to the needs of different circuit applications while reducing process complexity and manufacturing costs. Furthermore, no additional photomask is required when forming the depletion-mode transistor, further reducing fabrication costs. Attached Figure Description

[0033] Figure 1 The diagram shown is a structural schematic of the integrated circuit structure of the present invention.

[0034] Figure 2 The diagram shows a flowchart illustrating the method for fabricating the integrated circuit structure of the present invention.

[0035] Figure 3 The diagram shown is a schematic of the structure obtained after forming a high-voltage gate oxide layer in the method for fabricating the integrated circuit structure of the present invention.

[0036] Figure 4The diagram shown is a schematic of the structure obtained after forming a first drift region and a second drift region spaced apart, in the method for manufacturing the integrated circuit structure of the present invention.

[0037] Figure 5 The diagram shown is a schematic of the structure obtained after removing the high-voltage gate oxide layer located in the channel region in the method for fabricating the integrated circuit structure of the present invention.

[0038] Figure 6 The diagram shown is a schematic of the structure obtained after forming a transistor well region in the substrate layer of the channel region in the method for fabricating the integrated circuit structure of the present invention.

[0039] Figure 7 The diagram shown is a schematic of the structure obtained after forming a low-voltage gate oxide layer in the method for fabricating the integrated circuit structure of the present invention.

[0040] Figure 8 The diagram shown is a schematic of the structure obtained after the gate is formed in the method for fabricating the integrated circuit structure of the present invention.

[0041] Figure 9 The diagram shows a flowchart of the method for forming the first source / drain region and the second source / drain region according to the present invention.

[0042] Figure 10 The diagram shown is a schematic of the structure obtained after forming the source / drain injection window in the method for fabricating the integrated circuit structure of the present invention.

[0043] Explanation of reference numerals in the attached figures

[0044] 1 substrate 2 transistor well region 31 First Drift Zone 32 Second Drift Zone 41 First source leak area 42 Second source leak area 5 High-voltage gate oxide layer 6 Low-voltage gate oxide layer 7 gate 8 Source / drain injection window Detailed Implementation

[0045] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0046] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components.

[0047] Features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0048] In the detailed description of embodiments of the present invention, for ease of explanation, the schematic diagrams illustrating the device structure may be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0049] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0050] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0051] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0052] Please see Figure 1The diagram shows a schematic of the integrated circuit structure of the present invention, including a substrate layer 1, a transistor well region 2, a first drift region 31, a second drift region 32, a first source / drain region 41, a second source / drain region 42, a high-voltage gate oxide layer 5, a low-voltage gate oxide layer 6, and a gate 7. The substrate layer 1 is of a first conductivity type and is divided into a high-voltage CMOS region, a low-voltage CMOS region, and a transistor region according to a preset rule. The first drift region 31 and the second drift region 32 are located in the substrate layer 1 of the transistor region and are spaced apart. Both the first drift region 31 and the second drift region 32 are of a second conductivity type. The region between the first drift region 31 and the second drift region 32 defines a transistor channel region. The transistor well region 2 is located in the channel region. In the substrate layer 1, the transistor well region 2 is of the first conductivity type; the low-voltage gate oxide layer 6 is located on the substrate layer 1 of the low-voltage CMOS region and the channel region, the high-voltage gate oxide layer 5 is located on the high-voltage CMOS region and the first drift region 31 and the second drift region 32, and the thickness of the low-voltage gate oxide layer 6 is less than the thickness of the high-voltage gate oxide layer 5; the gate 7 covers the low-voltage gate oxide layer 6 of the channel region and extends to both sides onto the high-voltage gate oxide layer 6 of the first drift region 31 and the second drift region 32; the first source / drain region 41 is located in the first drift region 31, the second source / drain region 42 is located in the second drift region 32, and both the first source / drain region 41 and the second source / drain region 42 are of the second conductivity type.

[0053] In this invention, the large-area drift region in the substrate layer 1 located on both sides of the channel region and the thick gate oxide thereon form a high-voltage resistant region, enabling the overall structure to withstand high voltage; the transistor well region 2 in the substrate layer 1 located in the channel region and the thin gate oxide thereon enable the overall structure to achieve a conduction state under extremely low gate voltage or even zero gate voltage.

[0054] As an example, the first conductivity type is N-type or P-type, the second conductivity type is N-type or P-type, and the second conductivity type has the opposite conductivity type to the first conductivity type.

[0055] As an example, the substrate layer 1 is divided into a high-voltage CMOS region, a low-voltage CMOS region, and a transistor region according to a preset rule. Figure 1Only the transistor region is shown. The transistor region may exist independently of the high-voltage CMOS region and the low-voltage CMOS region, or it may be located within the high-voltage CMOS region. The concepts of high voltage and low voltage in the high-voltage CMOS region and the low-voltage CMOS region are relative; the same voltage may be classified as high voltage in some cases and low voltage in others. For example, in one embodiment, the operating voltage of the low-voltage device is 1V~12V, and the operating voltage of the high-voltage device is 12V~700V or even higher.

[0056] As an example, the integrated circuit structure includes a low-voltage enhancement-mode transistor well region and a high-voltage depletion-mode transistor well region. The main body of the low-voltage enhancement-mode transistor well region is located in the substrate layer of the low-voltage CMOS region, and the main body of the high-voltage depletion-mode transistor well region is located in the substrate layer of the high-voltage CMOS region. Compared with the low-voltage enhancement-mode transistor well region, the high-voltage depletion-mode transistor well region has a lower ion doping concentration and a deeper ion implantation depth. Transistor well region 2 is a part of the low-voltage enhancement-mode transistor well region, in which case the transistor in the integrated circuit structure is an enhancement-mode transistor with a threshold voltage close to 0; or, transistor well region 2 is a part of the high-voltage depletion-mode transistor well region, in which case the transistor in the integrated circuit structure is a depletion-mode transistor.

[0057] In some embodiments, the transistor well region 2 is a portion of the low-voltage enhancement-mode transistor well region. The implanted ions in the transistor well region 2 are boron ions, the ion implantation energy for forming the transistor well region 2 is 20 keV to 250 keV, and the ion implantation dose for forming the transistor well region 2 is 1 × 10⁻⁶. 13 cm -2 ~3×10 13 cm -2 The implantation depth of the transistor well region 2 is 950nm~1050nm from the upper surface of the substrate layer 1 downwards.

[0058] In some embodiments, the transistor well region 2 is a portion of the high-voltage depletion-type transistor well region. The implanted ions in the transistor well region 2 are boron ions, the ion implantation energy for forming the transistor well region 2 is 20 keV to 500 keV, and the ion implantation dose for forming the transistor well region 2 is 1 × 10⁻⁶. 12 cm -2 ~2×10 13 cm -2 The implantation depth of the transistor well region 2 is 650nm~750nm from the upper surface of the substrate layer 1 downwards.

[0059] In some embodiments, the thickness of the high-voltage gate oxide layer 5 ranges from 30nm to 90nm, such as 40nm, 50nm, 60nm, 70nm, 80nm, etc.; the thickness of the low-voltage gate oxide layer 6 ranges from 3nm to 4nm, such as 3.3nm, 3.6nm, 3.9nm, etc.

[0060] As an example, such as Figure 1 As shown, the first source / drain region 41 and the gate 7 are spaced apart by a predetermined distance in the horizontal direction. The high-voltage gate oxide layer 5 located on the first drift region 31 overlaps with the gate 7 at one end near the channel region and overlaps with the first source / drain region 41 at the other end away from the channel region. The second source / drain region 42 and the gate 7 are spaced apart by a predetermined distance in the horizontal direction. The high-voltage gate oxide layer 5 located on the second drift region 32 overlaps with the gate 7 at one end near the channel region and overlaps with the second source / drain region 42 at the other end away from the channel region.

[0061] In some embodiments, such as Figure 1 As shown, in the direction from the first source / drain region 41 to the second source / drain region 42, the length of the portion of the high-voltage gate oxide layer 5 on the first drift region 31 covered by the gate 7 is M1, the length of the portion of the high-voltage gate oxide layer 5 on the second drift region 32 covered by the gate 7 is M2, the length of the portion of the high-voltage gate oxide layer 5 on the first drift region 31 not covering the first source / drain region 41 is N1, and the length of the region of the high-voltage gate oxide layer 5 on the second drift region 32 not covering the second source / drain region 42 is N2, where M1:N1=1 / 3~1 / 2, M2:N2=1 / 3~1 / 2.

[0062] In some embodiments, the length of the first source / drain region 41 (or the second source / drain region 42) covered by the high-voltage gate oxide layer 5 is 0.2 μm to 1 μm, for example, 0.5 μm, 0.8 μm, etc.

[0063] In this invention, the high-voltage gate oxide layer 5, which is of high thickness and protrudes horizontally beyond the gate 7, helps to further improve the voltage resistance of the overall structure.

[0064] In this invention, the first source / drain region 41, the second source / drain region 42, the first drift region 31, and the second drift region 32 are all of the second conductivity type. The ion doping concentration of the first source / drain region 41 is greater than that of the first drift region 31, and the ion doping concentration of the second source / drain region 42 is greater than that of the second drift region 32. The first source / drain region 41 and the second source / drain region 42, covered by the high-voltage gate oxide layer 5, are affected by the thick gate oxide layer, resulting in a lower ion doping concentration than the first source / drain region 41 and the second source / drain region 42 not covered by the high-voltage gate oxide layer 5. This creates a gradually changing concentration gradient region where the ion doping concentration is between that of the source / drain region and the drift region. Direct contact between the source / drain region and the drift region can cause base region broadening during high-power operation, affecting device reliability. The gradually changing concentration gradient region can effectively reduce the impact of base region broadening on device lifetime. Furthermore, the presence of source / drain regions covered by the high-voltage gate oxide layer 5 reduces the photolithography difficulty before ion implantation to form the first source / drain region 41 and the second source / drain region 42, thus helping to control process stability.

[0065] In some embodiments, the substrate layer 1 is made of silicon, the high-voltage gate oxide layer 5 and the low-voltage gate oxide layer 6 are both made of silicon dioxide generated by thermal oxidation on the silicon substrate, and the gate 7 is made of polycrystalline silicon.

[0066] In some embodiments, the first conductivity type is P-type, the second conductivity type is N-type, and the transistor well region 2 is a portion of the low-voltage enhancement-mode transistor well region. The thickness of the high-voltage gate oxide layer 5 ranges from 30 nm to 90 nm, the thickness of the low-voltage gate oxide layer 6 ranges from 3 nm to 4 nm, the implanted ion type of the transistor well region 2 is boron ions, the ion implantation energy for forming the transistor well region 2 is 20 keV to 250 keV, and the ion implantation dose for forming the transistor well region 2 is 1 × 10⁻⁶. 13 cm -2 ~3×10 13 cm -2 The corresponding threshold voltage range is 0.16V to 0.3V. In this integrated circuit structure, the transistor is an enhancement-mode transistor with a threshold voltage close to 0, requiring a very small voltage to be applied to the gate 7 to achieve channel conduction.

[0067] In some embodiments, the first conductivity type is P-type, the second conductivity type is N-type, and the transistor well region 2 is a high-voltage depletion-type transistor well region. The thickness of the high-voltage gate oxide layer 5 ranges from 30 nm to 90 nm, the thickness of the low-voltage gate oxide layer 6 ranges from 3 nm to 4 nm, the implanted ion type for the high-voltage depletion-type transistor well region is boron ions, the ion implantation energy for forming the transistor well region 2 is 20 keV to 500 keV, and the ion implantation dose for forming the transistor well region 2 is 1 × 10⁻⁶. 12 cm -2 ~2×10 13 cm -2 The corresponding threshold voltage range is -0.16V to -0.02V. In this integrated circuit structure, the transistor is a depletion-type transistor, meaning the channel can be turned on even without applying voltage to the gate 7.

[0068] Through software simulation, when the first conductivity type is P-type and the second conductivity type is N-type, the thickness of the high-voltage gate oxide layer 5 is 90 nm, and the thickness of the low-voltage gate oxide layer 6 is 3.3 nm. Under otherwise identical conditions, adjusting the transistor well region 2 can change the threshold voltage. In one embodiment, the transistor well region 2 is a low-voltage P-well, the implanted ion type is boron ions, the ion implantation energy to form the low-voltage P-well is 20 keV~250 keV, and the ion implantation dose to form the low-voltage P-well is 1 × 10⁻⁶. 13 cm -2 The resulting structure has a threshold voltage of 0.23V, a saturation current of approximately 700μA / μm, and a drain breakdown voltage of approximately 28V. In another embodiment, the transistor well region 2 is a high-voltage P-well, the implanted ion type is boron ions, the ion implantation energy to form the high-voltage P-well is 20keV~500keV, and the ion implantation dose to form the high-voltage P-well is 1×10⁻⁶. 12 cm -2 The obtained structure has a threshold voltage of -0.09V, a saturation current of approximately 800μA / μm, and a drain breakdown voltage of approximately 28V.

[0069] This invention also provides a method for fabricating an integrated circuit structure to prepare the aforementioned integrated circuit structure. Please refer to [link / reference]. Figure 2 The diagram shows a flow chart of a method for fabricating an integrated circuit structure according to the present invention, which includes at least the following steps:

[0070] S201: Provide a substrate layer, the substrate layer being of a first conductivity type, the substrate layer being divided into a high voltage CMOS region, a low voltage CMOS region and a transistor region according to a preset rule;

[0071] S202: Forming a high-voltage gate oxide layer, wherein the high-voltage gate oxide layer is located on the substrate layer between the high-voltage CMOS region and the transistor region;

[0072] S203: A first drift region and a second drift region are formed at intervals in the substrate layer of the transistor region, wherein the first drift region and the second drift region are both of the second conductivity type, and the region between the first drift region and the second drift region defines the channel region of the transistor;

[0073] S204: Remove the high-voltage gate oxide layer located on the channel region and form a transistor well region in the substrate layer of the channel region, wherein the transistor well region is of a first conductivity type;

[0074] S205: Form a low-voltage gate oxide layer, wherein the low-voltage gate oxide layer is located on the substrate layer between the low-voltage CMOS region and the channel region, and the thickness of the low-voltage gate oxide layer is less than the thickness of the high-voltage gate oxide layer;

[0075] S206: Form a gate, the gate covering the low-voltage gate oxide layer of the channel region and extending to both sides onto the high-voltage gate oxide layer of the first drift region and the second drift region;

[0076] S207: A first source / drain region and a second source / drain region are formed, wherein the first source / drain region is located in the first drift region and the second source / drain region is located in the second drift region, and both the first source / drain region and the second source / drain region are of the second conductivity type.

[0077] The following section, using a structural diagram, details the specific implementation methods of each of the above steps.

[0078] First, step S201 is performed: the substrate layer 1 is provided.

[0079] As an example, the substrate layer 1 is divided into a high-voltage CMOS region, a low-voltage CMOS region, and a transistor region according to a preset rule. The transistor region may be independent of the high-voltage CMOS region and the low-voltage CMOS region, or it may be located within the high-voltage CMOS region. The terms "high voltage" and "low voltage" in the high-voltage CMOS region and the low-voltage CMOS region are relative concepts; the same voltage may be classified as high voltage in some cases and low voltage in others. For example, in one embodiment, the operating voltage of the low-voltage device is 1V~12V, and the operating voltage of the high-voltage device is 12V~700V or even higher.

[0080] Optionally, the substrate layer 1 is a silicon substrate. The substrate layer has a first conductivity type, which is either N-type or P-type.

[0081] Please refer to the following: Figure 3 Step S202: Form a high-voltage gate oxide layer 5, wherein the high-voltage gate oxide layer 5 is located on the substrate layer 1 of the high-voltage CMOS region and the transistor region.

[0082] As an example, based on high-voltage integrated circuit technology, a high-thickness high-voltage gate oxide layer 5 is formed by thermal oxidation on the substrate layer 1 located between the high-voltage CMOS region and the transistor region. Wherein, as... Figure 3 The substrate layer 1 in the structure shown only shows the transistor region.

[0083] Please refer to the following: Figure 4 Step S203: Form a first drift region 31 and a second drift region 32 spaced apart in the substrate layer 1 of the transistor region. The first drift region 31 and the second drift region 32 are both of the second conductivity type. The region between the first drift region 31 and the second drift region 32 defines the channel region of the transistor.

[0084] As an example, in such Figure 3 Based on the structure shown, a drift region mask layer is obtained by photolithography on the high-voltage gate oxide layer 5 using a drift region photomask suitable for high-voltage devices. This mask layer exposes the patterns required for forming the first drift region 31 and the second drift region 32. Ion implantation is then performed on the substrate layer 1 through the drift region mask layer to obtain the first drift region 31 and the second drift region 32 spaced apart in the substrate layer 1 of the transistor region. Subsequently, the drift region mask layer is removed to obtain the structure shown. Figure 4 The structure shown is such that the region between the first drift region 31 and the second drift region 32 defines the channel region of the transistor. The first drift region 31 and the second drift region 32 can improve the breakdown voltage performance of the device, and the doping concentration and size of the first drift region 31 and the second drift region 32 can be adjusted according to specific requirements.

[0085] Both the first drift region 31 and the second drift region 32 are of a second conductivity type. The second conductivity type is either N-type or P-type, and it has the opposite conductivity type to the first conductivity type. When the first ion type is P-type, the second ion type is N-type; when the first ion type is N-type, the second ion type is P-type.

[0086] Please refer to the following: Figure 5 and Figure 6 Step S204: Remove the high-voltage gate oxide layer 5 located on the channel region and form a transistor well region 2 in the substrate layer 1 of the channel region, wherein the transistor well region 2 is of the first conductivity type.

[0087] As an example, in such Figure 4 Based on the structure shown, a low-voltage enhancement-mode transistor well region photomask suitable for low-voltage devices or a high-voltage depletion-mode transistor well region photomask suitable for high-voltage devices is selected according to requirements. The high-voltage gate oxide layer 5 is photolithographically etched to obtain a transistor well region mask layer that exposes the pattern required to form the transistor well region 2. The high-voltage gate oxide layer 5 is then etched through the transistor well region mask layer to remove the high-voltage gate oxide layer 5 located in the channel region, resulting in the structure shown. Figure 5 The structure shown. Next, in the following... Figure 5 Based on the structure shown, a thin silicon dioxide layer is formed on the substrate layer 1 in the channel region by thermal oxidation as a sacrificial oxide layer. Ion implantation is then performed on the substrate layer 1 in the channel region through the transistor well mask layer to obtain the transistor well region 2 formed in the substrate layer 1 in the channel region. Subsequently, the sacrificial oxide layer and the transistor well mask layer are removed to obtain the structure shown. Figure 6 The structure is shown. The sacrificial oxide layer is used to protect the upper surface of the substrate layer 1 during ion implantation and to reduce the channel effect of ion implantation in forming the transistor well region 2.

[0088] The transistor well region obtained in this step forms the channel region of the transistor. A low-voltage enhancement-mode transistor (LVMT) well region with a high ion doping concentration can be formed using a low-voltage enhancement-mode transistor (LVMT) well region photomask; the portion of the LVMT well region located within the transistor region is designated as the transistor well region. Conversely, a high-voltage depletion-mode transistor (VDT) well region with a low ion doping concentration can be formed using a high-voltage depletion-mode transistor (VDT) well region photomask; the portion of the VDT depletion-mode transistor (VDT) well region located within the transistor region is designated as the transistor well region. Compared to the LVMT well region, the VDT depletion-mode transistor (VDT) well region has a lower ion doping concentration, resulting in a lower threshold voltage for the structure based on the VDT depletion-mode transistor (VDT) well region compared to the structure based on the LVMT well region.

[0089] In some embodiments, the transistor well region 2 is a portion of a low-voltage enhancement transistor well region formed based on the low-voltage enhancement transistor well region photomask. The implanted ions in the transistor well region 2 are boron ions, the ion implantation energy for forming the transistor well region 2 is 20keV~250keV, and the ion implantation dose for forming the transistor well region 2 is 1×10⁻⁶. 13 cm -2 ~3×10 13 cm -2 The implantation depth of the transistor well region 2 is 950nm~1050nm from the upper surface of the substrate layer 1 downwards.

[0090] In some embodiments, the transistor well region 2 is a portion of a high-voltage depletion transistor well region formed based on the high-voltage depletion transistor well region photomask. The implanted ions in the transistor well region 2 are boron ions, the ion implantation energy for forming the transistor well region 2 is 20keV~500keV, and the ion implantation dose for forming the transistor well region 2 is 1×10⁻⁶. 12 cm -2 ~2×10 13 cm -2 The implantation depth of the transistor well region 2 is 650nm~750nm from the upper surface of the substrate layer 1 downwards.

[0091] In some embodiments, the thickness of the sacrificial oxide layer ranges from 9 nm to 13 nm, such as 10 nm, 11 nm, 12 nm, etc.

[0092] Please refer to the following: Figure 7 Step S205: Form a low-voltage gate oxide layer 6, wherein the low-voltage gate oxide layer 6 is located on the substrate layer 1 of the low-voltage CMOS region and the channel region, and the thickness of the low-voltage gate oxide layer 6 is less than the thickness of the high-voltage gate oxide layer 5.

[0093] As an example, in Figure 6 Based on the structure shown, a low-voltage gate oxide mask layer is obtained by photolithography using a low-voltage gate oxide mask suitable for low-voltage devices, which exposes the pattern required to form the low-voltage gate oxide layer 6. The upper surface of the substrate layer 1 located in the low-voltage CMOS region and the channel region is thermally oxidized through the low-voltage gate oxide mask layer to form a very thin silicon dioxide layer as the low-voltage gate oxide layer 6.

[0094] Both the low-voltage gate oxide layer 6 and the high-voltage gate oxide layer 5 are located on the substrate layer 1. The low-voltage gate oxide layer 6 is located on the channel region, and the high-voltage gate oxide layer 5 is located on the first drift region 31 and the second drift region 32 on both sides of the channel region. The thickness of the low-voltage gate oxide layer 6 is much smaller than the thickness of the high-voltage gate oxide layers 5 on both sides. This design can further reduce the threshold voltage of the final structure. By strictly controlling the oxygen flow rate, heating time, and heating temperature during the thermal oxidation process, the thickness of silicon dioxide can be precisely controlled to obtain the required thickness of the low-voltage gate oxide layer 6.

[0095] In some embodiments, the thickness of the low-pressure gate oxide layer 6 ranges from 3 nm to 4 nm, such as 3.3 nm, 3.6 nm, 3.9 nm, etc.

[0096] Please refer to the following: Figure 8Step S206 is executed: a gate 7 is formed, the gate 7 covers the low-voltage gate oxide layer 6 of the channel region and extends to both sides onto the high-voltage gate oxide layer 5 of the first drift region 31 and the second drift region 32.

[0097] As an example, in Figure 7 Based on the structure shown, polysilicon is deposited on the low-voltage gate oxide layer 6 and the high-voltage gate oxide layer 5 to form a gate material layer. The gate material layer is then subjected to photolithography and etching to remove the gate material layer located in a portion of the high-voltage gate oxide layer 5, forming a structure as shown. Figure 8 The gate 7 shown.

[0098] In the actual fabrication process, after multiple cleaning and etching steps, the high-voltage gate oxide layer 5 will be gradually etched away to a certain thickness. After the gate 7 is formed, the remaining thickness of the high-voltage gate oxide layer 5 will remain unchanged under the protection of the gate 7.

[0099] In some embodiments, such as Figure 8 The thickness of the high-voltage gate oxide layer 5 in the structure shown ranges from 30nm to 90nm, for example, 50nm, 70nm, 80nm, etc.

[0100] Execution step S207: Form a first source / drain region 41 and a second source / drain region 42. The first source / drain region 41 is located in the first drift region 31, and the second source / drain region 42 is located in the second drift region 32. Both the first source / drain region 41 and the second source / drain region 42 are of the second conductivity type.

[0101] This invention provides a method for forming the first source / drain region 41 and the second source / drain region 42. Please refer to [link / reference needed]. Figure 9 The diagram shows a flow chart of the method for forming the first source / drain region 41 and the second source / drain region 42 according to the present invention, which includes at least the following steps:

[0102] S901: Form source / drain injection windows in the high-voltage gate oxide layer of the transistor region;

[0103] S902: Perform ion implantation to form the first source / drain region in the first drift region below the source / drain implantation window, and form the second source / drain region in the second drift region below the source / drain implantation window, wherein the first source / drain region and the gate are spaced apart by a preset distance in the horizontal direction, and the second source / drain region and the gate are spaced apart by a preset distance in the horizontal direction.

[0104] The following section, using a structural diagram, details the specific implementation methods of each of the above steps.

[0105] Please see Figure 10Step S901: Form source / drain injection window 8 in the high-voltage gate oxide layer 5 in the transistor region.

[0106] As an example, in such Figure 8 Based on the structure shown, a high-voltage gate oxide layer 5 is photolithographically lithographically formed using a high-voltage source / drain photomask suitable for high-voltage devices to expose the patterns required for forming at least a portion of the first source / drain region 41 and at least a portion of the second source / drain region 42. The high-voltage gate oxide layer 5 not covered by the high-voltage source / drain photomask is then removed by an etching process to obtain the structure shown. Figure 10 The source / drain injection window 8 in the structure shown.

[0107] Please refer back to this next section. Figure 1 Step S902: Ion implantation is performed to form the first source / drain region 41 in the first drift region 31 below the source / drain implantation window 8, and the second source / drain region 42 in the second drift region 32 below the source / drain implantation window. The first source / drain region 41 and the gate 7 are spaced apart by a preset distance in the horizontal direction, and the second source / drain region 42 and the gate 7 are spaced apart by a preset distance in the horizontal direction.

[0108] As an example, in such Figure 10 Based on the structure shown, ion implantation is performed on the first drift region 31 and the second drift region 32 located below the source / drain implantation window 8 through the high-voltage source / drain mask layer, resulting in the first source / drain region 41 located in the first drift region 31 and the second source / drain region 42 located in the second drift region 32. Both the first source / drain region 41 and the second source / drain region 42 are of the second conductivity type, and the ion doping concentration of the first source / drain region 41 is greater than that of the first drift region 31, and the ion doping concentration of the second source / drain region 42 is greater than that of the second drift region 32.

[0109] As an example, the first source / drain region 41 and the gate 7 are spaced apart by a predetermined distance in the horizontal direction. The high-voltage gate oxide layer 5 located on the first drift region 31 overlaps with the gate 7 at one end near the channel region and overlaps with the first source / drain region 41 at the other end away from the channel region. The second source / drain region 42 and the gate 7 are spaced apart by a predetermined distance in the horizontal direction. The high-voltage gate oxide layer 5 located on the second drift region 32 overlaps with the gate 7 at one end near the channel region and overlaps with the second source / drain region 42 at the other end away from the channel region.

[0110] In some embodiments, such as Figure 1As shown, in the direction from the first source / drain region 41 to the second source / drain region 42, the length of the portion of the high-voltage gate oxide layer 5 on the first drift region 31 covered by the gate 7 is M1, the length of the portion of the high-voltage gate oxide layer 5 on the second drift region 32 covered by the gate 7 is M2, the length of the portion of the high-voltage gate oxide layer 5 on the first drift region 31 not covering the first source / drain region 41 is N1, and the length of the region of the high-voltage gate oxide layer 5 on the second drift region 32 not covering the second source / drain region 42 is N2, where M1:N1=1 / 3~1 / 2, M2:N2=1 / 3~1 / 2.

[0111] In some embodiments, the length of the first source / drain region 41 (or the second source / drain region 42) covered by the high-voltage gate oxide layer 5 is 0.2 μm to 1 μm, for example, 0.5 μm, 0.8 μm, etc.

[0112] Traditional device manufacturing processes require additional photomasks to form conductive channels corresponding to different voltages when manufacturing field-effect transistors with different operating voltages on the same product platform. However, this invention optimizes the device structure based on existing photomasks in the existing process flow, enabling the use of existing photomasks to achieve different operating voltages without additional manufacturing costs.

[0113] This invention, based on high-voltage integrated circuit technology, provides an integrated circuit structure that withstands high voltage and can selectively achieve depletion-mode characteristics or ultra-low threshold voltage enhancement-mode characteristics, thus expanding the device types of high-voltage integrated circuits. In the fabrication process of the integrated circuit structure, existing photomasks suitable for low-voltage devices (such as low-voltage well region photomasks and low-voltage gate oxide photomasks) and photomasks suitable for high-voltage devices (such as high-voltage drift region photomasks, high-voltage well region photomasks, high-voltage gate oxide photomasks, and high-voltage source-drain photomasks) are used in combination as needed, without the need for additional photomasks. Ultimately, a novel device structure with lower operating voltage and excellent withstand voltage capability is obtained without additional manufacturing costs.

[0114] The integrated circuit structure of this invention is fabricated using a high-voltage integrated circuit process platform, making it compatible with most high-voltage integrated circuit processes. Furthermore, this invention yields depletion-type transistors with various threshold voltages without requiring additional photomasks, reducing manufacturing costs and having significant implications for process platform development and device design. By adjusting the photomask combination, NMOS or PMOS transistors can be obtained using the fabrication method of this invention, and the resulting integrated circuit structure can meet most electrical performance requirements.

[0115] In summary, the integrated circuit structure of the present invention includes a substrate layer, a first drift region, a second drift region, a transistor well region, a high-voltage gate oxide layer, a low-voltage gate oxide layer, a gate, a first source / drain region, and a second source / drain region. The substrate layer is divided into a high-voltage CMOS region, a low-voltage CMOS region, and a transistor region according to a predetermined rule. The first drift region and the second drift region are located in the substrate layer of the transistor region and are spaced apart. The region between the first drift region and the second drift region defines the channel region of the transistor. The transistor well region is located in the substrate layer of the channel region. The low-voltage gate oxide layer is located on the substrate layer of the low-voltage CMOS region and the channel region. The high-voltage gate oxide layer is located on the high-voltage CMOS region and the first and second drift regions, and the thickness of the low-voltage gate oxide layer is less than the thickness of the high-voltage gate oxide layer. The gate covers the low-voltage gate oxide layer of the channel region and extends to both sides onto the high-voltage gate oxide layers of the first and second drift regions. The first source / drain region is located in the first drift region, and the second source / drain region is located in the second drift region. The integrated circuit structure of this invention is a novel transistor fabricated using a photomask that combines high-voltage and low-voltage devices. By establishing a drift region and applying a thick gate oxide layer on the drift region, the overall structure can withstand high voltages. By adjusting the doping concentration of the transistor well region and applying a thin gate oxide layer on the well region, the overall structure can selectively achieve depletion-mode or ultra-low threshold voltage enhancement-mode characteristics, thus flexibly adapting to the needs of different circuit applications while reducing process complexity and manufacturing costs. Furthermore, no additional photomask is required when forming the depletion-mode transistor, further reducing fabrication costs.

[0116] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. An integrated circuit structure, characterized in that, include: The substrate layer is of the first conductivity type and is divided into a high-voltage CMOS region, a low-voltage CMOS region and a transistor region according to a preset rule. The first drift region and the second drift region are located in the substrate layer of the transistor region and are spaced apart. Both the first drift region and the second drift region are of the second conductivity type. The region between the first drift region and the second drift region defines the channel region of the transistor. A transistor well region, located in the substrate layer of the channel region, wherein the transistor well region is of a first conductivity type; A high-voltage gate oxide layer and a low-voltage gate oxide layer, wherein the low-voltage gate oxide layer is located on the substrate layer of the low-voltage CMOS region and the channel region, and the high-voltage gate oxide layer is located on the high-voltage CMOS region and the first drift region and the second drift region, and the thickness of the low-voltage gate oxide layer is less than the thickness of the high-voltage gate oxide layer; The gate, the low-voltage gate oxide layer covering the channel region, and extending to both sides onto the high-voltage gate oxide layer of the first drift region and the second drift region; A first source / drain region and a second source / drain region, wherein the first source / drain region is located in the first drift region and the second source / drain region is located in the second drift region, and both the first source / drain region and the second source / drain region are of the second conductivity type.

2. The integrated circuit structure according to claim 1, characterized in that: The integrated circuit structure includes a low-voltage enhancement-mode transistor well region and a high-voltage depletion-mode transistor well region. The main body of the low-voltage enhancement-mode transistor well region is located in the substrate layer of the low-voltage CMOS region, and the main body of the high-voltage depletion-mode transistor well region is located in the substrate layer of the high-voltage CMOS region. A portion of the low-voltage enhancement-mode transistor well region serves as the transistor well region, or a portion of the high-voltage depletion-mode transistor well region serves as the transistor well region.

3. The integrated circuit structure according to claim 1, characterized in that: The thickness of the high-voltage gate oxide layer ranges from 30nm to 90nm, and the thickness of the low-voltage gate oxide layer ranges from 3nm to 4nm.

4. The integrated circuit structure according to claim 1, characterized in that: The first source / drain region is horizontally spaced from the gate by a predetermined distance. The high-voltage gate oxide layer on the first drift region overlaps with the gate at one end near the channel region and with the first source / drain region at the other end away from the channel region. The second source / drain region is horizontally spaced from the gate by a predetermined distance. The high-voltage gate oxide layer on the second drift region overlaps with the gate at one end near the channel region and with the second source / drain region at the other end away from the channel region.

5. The integrated circuit structure according to claim 4, characterized in that: In the direction from the first source / drain region to the second source / drain region, the length of the portion of the high-voltage gate oxide layer on the first drift region that is covered by the gate is M1, the length of the portion of the high-voltage gate oxide layer on the second drift region that is covered by the gate is M2, the length of the portion of the high-voltage gate oxide layer on the first drift region that is not covered by the first source / drain region is N1, and the length of the region of the high-voltage gate oxide layer on the second drift region that is not covered by the second source / drain region is N2, wherein M1:N1=1 / 3~1 / 2, M2:N2=1 / 3~1 / 2.

6. A method for fabricating an integrated circuit structure, characterized in that, Includes the following steps: A substrate layer is provided, the substrate layer being of a first conductivity type, and the substrate layer being divided into a high voltage CMOS region, a low voltage CMOS region, and a transistor region according to a preset rule; A high-voltage gate oxide layer is formed, the high-voltage gate oxide layer being located on the substrate layer between the high-voltage CMOS region and the transistor region; A first drift region and a second drift region are formed at intervals in the substrate layer of the transistor region. Both the first drift region and the second drift region are of the second conductivity type. The region between the first drift region and the second drift region defines the channel region of the transistor. The high-voltage gate oxide layer located on the channel region is removed, and a transistor well region is formed in the substrate layer of the channel region, wherein the transistor well region is of a first conductivity type; A low-voltage gate oxide layer is formed, which is located on the substrate layer between the low-voltage CMOS region and the channel region, and the thickness of the low-voltage gate oxide layer is less than the thickness of the high-voltage gate oxide layer. A gate is formed, the gate covering the low-voltage gate oxide layer of the channel region and extending to both sides onto the high-voltage gate oxide layer of the first drift region and the second drift region; A first source / drain region and a second source / drain region are formed. The first source / drain region is located in the first drift region, and the second source / drain region is located in the second drift region. Both the first source / drain region and the second source / drain region are of the second conductivity type.

7. The method for fabricating an integrated circuit structure according to claim 6, characterized in that: The step of forming a transistor well region in the substrate layer of the channel region includes a step of forming a sacrificial oxide layer on the substrate layer of the channel region before the step of forming a transistor well region in the substrate layer of the channel region; and the step of removing the sacrificial oxide layer includes a step of removing the sacrificial oxide layer after the step of forming a transistor well region in the substrate layer of the channel region.

8. The method for fabricating an integrated circuit structure according to claim 6, characterized in that, Forming the transistor well region includes the following steps: providing a high-voltage depletion-type transistor well region photomask, performing ion implantation based on the high-voltage depletion-type transistor well region photomask to form a high-voltage depletion-type transistor well region in the substrate layer of the high-voltage CMOS region and the transistor region, wherein the portion of the high-voltage depletion-type transistor well region located in the transistor region serves as the transistor well region; or, providing a low-voltage enhancement-type transistor well region photomask, performing ion implantation based on the low-voltage enhancement-type transistor well region photomask to form a low-voltage enhancement-type transistor well region in the substrate layer of the low-voltage CMOS region and the transistor region, wherein the portion of the low-voltage enhancement-type transistor well region located in the transistor region serves as the transistor well region.

9. The method for fabricating an integrated circuit structure according to claim 8, characterized in that: The ion implantation energy range used to form the low-voltage enhancement-mode transistor well region is 20keV to 250keV, and the ion implantation dose range used to form the low-voltage enhancement-mode transistor well region is 1×10⁻⁶. 13 cm -2 ~3×10 13 cm -2 The ion implantation energy range used to form the high-voltage depletion transistor well region is 20keV to 500keV, and the ion implantation dose range used to form the high-voltage depletion transistor well region is 1×10⁻⁶. 12 cm -2 ~2×10 13 cm -2 .

10. The method for fabricating an integrated circuit structure according to claim 6, characterized in that, The formation of the first source / drain region and the second source / drain region includes the following steps: Source / drain injection windows are formed in the high-voltage gate oxide layer of the transistor region; Ion implantation is performed to form a first source / drain region in a first drift region below the source / drain implantation window, and a second source / drain region is formed in a second drift region below the source / drain implantation window. The first source / drain region and the gate are spaced apart by a predetermined distance in the horizontal direction, and the second source / drain region and the gate are spaced apart by a predetermined distance in the horizontal direction.

11. The method for fabricating an integrated circuit structure according to claim 6, characterized in that: The thickness of the high-voltage gate oxide layer ranges from 30nm to 90nm, and the thickness of the low-voltage gate oxide layer ranges from 3nm to 4nm.

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