A memory device and a manufacturing process thereof

Abstract

The application relates to the technical field of semiconductor storage, and discloses a memory device and a preparation process thereof. The structure comprises a bottom metal layer, a bottom insulating medium and a connecting via; a columnar device structure is arranged above the structure and comprises, from bottom to top, a bottom electrode, a first charge trap layer, a switching layer, a second charge trap layer, a top electrode and a second metal interlayer insulating layer; a sidewall of the columnar device is conformally covered with a sidewall protection layer; a device interstitial filling layer, a first interlayer insulating layer and a top interconnection structure are arranged peripherally. The application buffers electric field impact through the double-layer charge trap layer, prolongs the device erasing and writing life, blocks oxygen and moisture penetration through the sidewall protection layer, improves the reliability, the structure characteristics smoothes transient impact during electric field switching, reduces the ion accumulation amount in each resistance state switching process, thereby relieving the structural fatigue of the switching layer and inhibiting irreversible breakdown of the device.

Description

Technical Field

[0001] This application relates to the field of semiconductor memory technology, specifically to a memory device and its fabrication process. Background Technology

[0002] With the rapid development of semiconductor technology, storage-class memory (SCM) has shown great application potential in data-intensive workloads and real-time response fields because it combines the high-speed byte-addressable access characteristics of dynamic random access memory (DRAM) with the power-off data persistence of traditional NAND flash memory. Resistive random access memory (RSM) devices, as one of the important technical paths for realizing SCM, have attracted widespread attention from the industry due to their advantages such as simple structure, fast operation speed and low power consumption.

[0003] Despite the numerous advantages of existing resistive switching memory (RSM) devices, significant reliability and process integration bottlenecks remain in practical mass production and long-term applications. During repeated high-to-low resistance switching operations, the switching layer often lacks effective electric field modulation and charge buffering mechanisms. Transient shocks from externally applied bias voltages can easily cause excessive unidirectional ion accumulation, accompanied by localized thermomechanical stress. This physical loss can lead to structural fatigue or even irreversible electrical breakdown of the switching layer material, severely limiting the device's erase / write cycle life. Simultaneously, under complex back-end semiconductor online (BEOL) processes and actual high-temperature, high-intensity electric field operating conditions, the lack of robust physical isolation and chemical passivation structures on the device sidewalls allows oxygen molecules and free moisture from the external environment to easily penetrate inwards. This erosion triggers interface oxidation degradation, leading to deterioration of key materials such as chalcogens, resulting in abnormally high defect level densities and parasitic leakage currents on the sidewalls, making it difficult to maintain long-term consistency of the stored state.

[0004] Furthermore, the existing devices have insufficient design in their underlying insulating architecture to prevent material diffusion. Under continuous thermal cycling and electric field stress, active ions in the underlying metal tend to migrate upwards, leading to the accumulation of defects and increased leakage current within the bottom insulating dielectric layer, ultimately causing insulation failure at the bottom of the memory. Regarding process compatibility, the existing device patterned structures have limited compatibility with conventional back-end mass production equipment, easily resulting in defects such as excessive mask wear, metal sidewall damage, etching residue, or filling voids during plasma etching and interlayer dielectric filling. These process issues not only increase manufacturing costs but also limit the improvement of array storage density and mass production yield, making it difficult to fully meet the stringent requirements of high density, low cost, and high reliability for memory-class memory. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this application provides a memory device and its fabrication process, which solves the problem that existing resistive switching memory devices are prone to limited erase / write cycle life and reduced long-term reliability due to electric field impact, environmental corrosion and electromigration of the underlying metal under repeated erase / write and complex operating conditions.

[0006] To achieve the above objectives, this application provides the following technical solution:

[0007] In a first aspect, this application provides a storage device, comprising: Underlying metal layer; The bottom electrode and the intermetallic insulating layer are located on top of the bottom metal layer, and the thickness of the bottom electrode and the intermetallic insulating layer is limited to 150 to 2000 Å. A through-hole connecting the bottom electrode and the metal layer, penetrating the intermetallic insulating layer and connecting to the bottom metal layer; A columnar device structure is located at the top of the insulating layer between the bottom electrode and the metal layer and the via connecting the bottom electrode and the metal layer. The columnar device structure includes, from bottom to top, a bottom electrode, a charge trap layer one, a switch layer, a charge trap layer two, a top electrode, and an insulating layer two between metal layers located on the top surface of the top electrode. The thickness of the switch layer is limited to 10 to 500 Å. A conformal protective layer is applied to the sidewalls of the columnar device structure and to the top of the exposed bottom electrode and the intermetallic insulating layer. The thickness of the sidewall protective layer is limited to 10–500 Å. Inter-device filling layer that fills the gaps between adjacent columnar device structures and is located outside the sidewall protective layer; The first metal interlayer insulating layer is located on top of the inter-device filling layer and part of the second metal interlayer insulating layer, and the thickness of the first metal interlayer insulating layer is limited to 100 to 50000 Å. Interconnect vias penetrating intermetallic insulating layer one and intermetallic insulating layer two, and a top metal layer located above the interconnect vias and connected to the exposed top electrode.

[0008] By adopting the above technical solution, and by symmetrically setting charge trap layer one and charge trap layer two at the upper and lower ends of the switching layer, and conformally covering the sidewall protective layer on the device sidewall, the device's erase / write cycle life is extended, and storage reliability under high-temperature conditions is improved. The specific microscopic mechanism is as follows: Step 1: Electric Field Modulation and Charge Buffering. The charge trap layers above and below the switching layer contain specific defect energy levels. When an external bias voltage is applied, injected carriers are captured by these defect energy levels. This carrier capture process establishes a microscopic built-in electric field at the heterojunction. This built-in electric field interacts with the external bias electric field based on electrostatic feedback, regulating the effective electric field strength reaching the main body of the switching layer. This mechanism smooths transient shocks during electric field switching, reduces ion accumulation during each resistive state switch, alleviates structural fatigue in the main body of the switching layer, suppresses irreversible breakdown, and increases the number of erase / write cycles for the memory device.

[0009] Step 2: Physical Isolation and Chemical Passivation. A high-density thin film is conformally wrapped around the sidewalls of the columnar device structure, cutting off the diffusion path of O2 and free water vapor from the external environment into the device. During subsequent processing, this prevents oxidation reactions between O atoms in the environment and chalcogen elements in the switching and charge trap layers, avoiding abnormal increases in defect energy level density and interface leakage caused by oxidation, and maintaining long-term consistency in high and low resistance values.

[0010] Preferably, the insulating layer between the bottom electrode and the metal is composed of one or more of SiO2, N-doped SiC, and plasma-enhanced SiO2; the via connecting the bottom electrode and the metal layer includes an adhesion barrier layer and a main conductive layer, the longitudinal depth of the via connecting the bottom electrode and the metal layer is limited to 150-2000 Å, and the material is selected from one or more of Ti, Hf, Ta, Ru, Ir, Pt, Zr, Al, W, Pd, Co metal materials, TiN, TaN, AlN, WN metal nitride materials with a thickness of 150-2000 Å, or TiON, TaON, AlON metal nitride materials.

[0011] By adopting the above technical solutions, the bottom electrode made of composite materials, the intermetallic insulating layer, and the through-holes made of specific metal compounds optimize the adhesion interface between film layers. Dense materials such as N-doped SiC utilize their internal lattice networks to block the upward electromigration channels of active ions in the underlying metal, suppressing the accumulation of defects and leakage current rise in the bottom insulating dielectric layer caused by high temperature and electric field stress, thereby improving the intrinsic breakdown voltage of the memory bottom architecture.

[0012] Preferably, the thickness of both charge trap layer one and charge trap layer two is 10–200 Å, and the materials are each independently selected from one or more of the following: GeTe, GeSb, SbTe, SnSbSe, SnSeIn, SiSnSe, InTe, SnTe, SbInTe, GeSe, GeAsTe, SiGeAsTe, SiGeAsSe, GeSbTe, GeSeSb, SnSe, GeAsSe, GeAsSb, NbOx, VOx, TiOx, GaOx, ZrOx, HfOx, HfTaO, HfZrO, HfSiO, and HfAlO, or multi-component compounds formed by combining multiple materials; the material of the switching layer is selected from GeTe, GeSb, SbTe, SnSbSe, SnSeIn, and Si... The materials are one or more of SnSe, InTe, SnTe, SbInTe, GeSe, GeAsTe, SiGeAsTe, SiGeAsSe, GeSbTe, GeSeSb, SnSe, GeAsSe, GeAsSb, NbOx, VOx, TiOx, GaOx, ZrOx, HfOx, HfTaO, HfZrO, HfSiO, and HfAlO, forming a multi-component compound, and the thickness of the switching layer is greater than the thickness of charge trap layer one or charge trap layer two; the materials of the bottom electrode and the top electrode are selected from one or more of Ti, Hf, Ta, Ru, Ir, Pt, Zr, Al, W, Pd, Co, WN, TiN, TaN, AlN, TiON, TaON, and AlON.

[0013] By employing the above technical solution, the thickness of the switching layer is limited to be greater than that of a single charge trap layer, ensuring that the externally applied bias voltage establishes a reasonable voltage division state in the series electrical network composed of the charge trap layer and the switching layer. This thickness parameter setting ensures that most of the effective electric field is concentrated in the core switching layer region, guaranteeing that the device reaches the critical electric field strength for triggering a resistive phase transition within a low-voltage range compatible with the logic control circuit. This avoids the attenuation of the effective electric field due to excessive trap layer thickness, prevents overshoot current caused by the need to forcibly increase the external operating voltage, and reduces the system power consumption of the device during a single write operation.

[0014] Preferably, the sidewall protective layer is made of one or more of HfO2, Ta2O5, SiO2, TiO2, ZrO2, Al2O3, SiN, and TEOS-based SiO2; the inter-device filling layer has a thickness of 10–10000 Å and is made of one or more of TEOS-based SiO2 or organic SiO2 glass; the inter-metal insulating layer has a thickness of 100–5000 Å and is made of one or more of SiON, SiN, and plasma-enhanced SiO2.

[0015] By adopting the above technical solution, the high dielectric constant and high density sidewall protective layer provides anti-oxidation barrier function, while constraining the electric field line distribution at the edge of the device sidewall, reducing the parasitic leakage effect between adjacent high-density array units. The second metal interlayer insulating layer is made of a material with a slow etching rate in plasma, providing a consumable physical mask for device patterning, protecting the underlying metal electrodes from plasma bombardment damage, and maintaining the verticality of the sidewall morphology.

[0016] Secondly, this application provides a fabrication process for a memory device, which adopts the following technical solution: A fabrication process for a memory device includes the following steps: depositing a bottom electrode and an intermetallic insulating layer on a bottom metal layer using a plasma-enhanced chemical vapor deposition process; Through-holes are etched into the bottom electrode and the metal interlayer using photolithography and anisotropic plasma etching processes. After depositing a material layer, the surface is planarized by grinding to form the through-holes connecting the bottom electrode and the metal layer. On the top of the planarized bottom electrode and the metal interlayer and the through-holes connecting the bottom electrode and the metal layer, the bottom electrode, charge trap layer one, switch layer, charge trap layer two, top electrode, and metal interlayer insulating layer two as a hard mask layer are deposited sequentially. Using the second intermetallic insulating layer as a mask, the bottom electrode is etched downwards and through to expose the upper surface of the bottom electrode and the intermetallic insulating layer, forming a complete columnar device structure after molding; a sidewall protective layer is deposited to wrap around the sidewall of the columnar device structure. Deposit the inter-device filler layer, perform a global etch rollback process to remove the inter-device filler layer and part of the metal layer insulation layer II at the top of the columnar device structure, expose the upper surface of the top electrode, and at the same time remove the inter-device filler layer and metal layer insulation layer II in the non-device structure area. The deposition of the interlayer insulating layer completes the basic isolation and global planarization between the metal layers. The surface planarization and impurity removal are completed through chemical mechanical polishing and cleaning processes, and a top metal layer connected to the top electrode is prepared.

[0017] By employing the above technical solution, a memory architecture with bidirectional charge trapping buffer and oxidation resistance is constructed from the bottom up using continuous thin-film deposition and high-selectivity etching processes. Deep trench etching is performed using the interlayer insulating layer as a pattern transfer hard mask, relying on the chemical volatilization of halogen gases to remove excess material and ensure the verticality of the core columnar structure's cross-section. Sidewall protective layers and filling dielectrics are deposited to fill device gaps and planarize the surface, providing a physical substrate for the height-free interconnection of the top-layer metal conductors.

[0018] Preferably, when depositing the bottom electrode and the metal interlayer insulating layer, the thickness combination of each sublayer is adjusted according to the region. The bottom electrode and the metal interlayer insulating layer includes a lower sublayer and an upper sublayer. The lower sublayer, which is the contact area with the bottom metal layer, is made of N-doped SiC, and the upper sublayer, which is the contact area with the bottom electrode, is made of plasma-enhanced SiO2. The total deposition thickness is controlled between 150 and 2000 Å.

[0019] By adopting the above technical solution, the composite deposition process combines the physical advantages of different materials. The lower N-doped SiC network cuts off the vertical diffusion channels of the bottom metal ions during thermal cycling, eliminating the risk of hard breakdown of the bottom dielectric; the upper plasma-enhanced SiO2 optimizes the interfacial adhesion between the SiO2 and the upper electrode material, forming an electrical base that balances physical barrier and interfacial stability.

[0020] Preferably, when depositing the connection between the bottom electrode and the metal layer via, if the material is metal, chemical vapor deposition or physical vapor deposition is used, with a deposition depth of 150–2000 Å; if the material is metal nitride or metal oxide nitride, reactive physical vapor deposition is used, with a deposition depth of 150–2000 Å.

[0021] By adopting the above technical solution, and matching the corresponding vapor deposition mode according to the intrinsic film-forming reaction characteristics of the metal material, void-free filling of the high aspect ratio through-holes is achieved, the work function of the upper and lower film layers is matched, and a low-impedance interlayer conductive contact interface is constructed.

[0022] Preferably, the deposition process for forming the columnar device structure specifically includes: depositing a bottom electrode with a thickness of 10–1500 Å using a physical vapor deposition process; and depositing a charge trap layer with a thickness of 10–200 Å using an atomic layer deposition, physical vapor deposition, or plasma-enhanced chemical vapor deposition process. A switch layer with a thickness of 10–500 Å is deposited using atomic layer deposition, physical vapor deposition, or plasma-enhanced chemical vapor deposition (PECVD); a charge trap layer with a thickness of 10–200 Å is deposited using atomic layer deposition, physical vapor deposition, or PECVD; a top electrode with a thickness of 10–5000 Å is deposited using physical vapor deposition; and a metal interlayer insulating layer with a thickness of 100–5000 Å is deposited using PECVD.

[0023] By adopting the above technical solution, a multilayer resistive switching stack containing a switching layer and a trapping layer is continuously grown in situ in a vacuum environment, avoiding the adsorption of impurities at the interface during the transport stage, and precisely controlling the thickness and elemental composition of each functional layer at the molecular scale.

[0024] Preferably, during the etching process to form the columnar device structure, the second interlayer insulating layer acts as a hard mask layer and serves as a polishing stop layer in the subsequent chemical mechanical polishing process. By adopting the above technical solution, the consumable hard mask layer absorbs the kinetic energy impact of high-energy ions in the reaction chamber, maintaining the lattice integrity of the underlying electrode surface. During the polishing stage, the hardness difference provides a physical and mechanical stop surface, preventing over-polishing from exposing the electrode and causing a short circuit.

[0025] Preferably, when depositing the interlayer insulating layer, a plasma-enhanced chemical vapor deposition process is used, and the deposited material is a thin film of organic SiO2 glass, with the deposition thickness controlled between 100 and 50,000 Å. By adopting the above technical solution, the porous organic dielectric thin film reduces the interlayer dielectric constant, reduces the parasitic crosstalk capacitance between the top layer signal traces and the bottom structure, and meets the high-frequency integration requirements of logic chips.

[0026] This application provides a storage device and its fabrication process. It has the following advantages: 1. This application effectively extends the erase / write cycle life of the memory device by symmetrically setting charge trap layer one and charge trap layer two at the upper and lower ends of the core switching layer. When an external bias voltage is applied, the defect energy levels inside the charge trap layer can capture charge carriers and establish a built-in electric field at the interface, regulating the effective electric field strength reaching the switching layer. This structural feature smooths the transient impact during electric field switching, reduces the amount of ion accumulation during each resistive state switching process, thereby alleviating structural fatigue of the switching layer and suppressing irreversible breakdown of the device.

[0027] 2. This application conformally covers the sidewalls of the columnar device structure with a sidewall protective layer, improving the long-term reliability of the device under complex operating conditions. A high-density sidewall protective layer directly wraps around the sidewalls of the core device, physically cutting off the diffusion path of O2 and moisture from the external environment into the device. This feature blocks the interfacial oxidation reaction that occurs in the switching layer and charge trap layer materials during processing and operation, avoiding defect level increases and interfacial leakage caused by oxidation and maintaining the consistency of the storage state.

[0028] 3. This application boasts excellent process compatibility, providing reliable technical support for high-density storage-class memory (SCM) applications. The film materials and corresponding deposition, etching, and polishing process parameters specified in this application are compatible with existing semiconductor back-end mass production equipment, requiring no additional production line modifications. By employing a metal interlayer insulating layer as a hard mask and a matching via deposition process, the defect rates of film damage, etching residue, and void filling are effectively reduced, improving mass production yield. Simultaneously, the sidewall protective layer constrains the electric field distribution at the device edges, suppressing parasitic leakage between adjacent cells. Combined with the device's advantages of high-speed access and persistent data even when power is off, this effectively increases the array's storage density and reduces unit cost, meeting the application requirements of SCM in high-speed data processing and real-time response fields. Attached Figure Description

[0029] Figure 1 This is a schematic diagram of the storage structure provided in an embodiment of this application; Figure 2 This is a schematic diagram of a single-layer storage provided in an embodiment of this application; Figure 3 A schematic diagram of multi-layer stacked storage provided in an embodiment of this application; Figure 4 A comparison chart of the basic electrical characteristics and erase / write cycle life test results of Example 1 and Comparative Example 1 provided for the embodiments of this application; Figure 5 A comparison chart of Example 1 and Comparative Example 4 in terms of operating voltage window and write power consumption, provided for the purposes of this application. Figure 6 The data retention test results of Example 1 and Comparative Example 2 provided for embodiments of this application are shown in the figure at a high temperature of 125°C. Figure 7 Comparison chart of the insulation performance test of the bottom insulating medium of Example 4 and Comparative Example 3 provided for the embodiments of this application; Figure 8 A comparative chart showing the test results of key physicochemical parameters of the preparation process provided in the embodiments of this application.

[0030] The components are: 1. Bottom metal layer; 2. Insulating layer between bottom electrode and metal layer; 3. Via connecting bottom electrode and metal layer; 4. Bottom electrode; 5. Charge trap layer one; 6. Switch layer; 7. Charge trap layer two; 8. Top electrode; 9. Insulating layer between metal layers one; 10. Sidewall protection layer; 11. Inter-device fill layer; 12. Insulating layer between metal layers two; 13. Top metal layer; 14. Word line; 15. Bit line. Detailed Implementation

[0031] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0032] See attached document Figure 1 The storage device is constructed on the bottom metal layer 1 and connected to the top metal layer 13. It includes a base film layer that provides insulation, a columnar device structure that realizes electrical storage function, and an outer isolation filling structure.

[0033] As a preferred embodiment, the structure located on top of the bottom metal layer 1 is a bottom electrode and an intermetallic insulating layer 2. To overcome the performance limitations of a single insulating material, the bottom electrode and the intermetallic insulating layer 2 adopt a composite film structure, and the material is specifically selected from one or more of SiO2, nitrogen-doped silicon carbide (NDC), and plasma-enhanced silicon oxide (PEOX).

[0034] The specific material distribution is adjusted according to the region inside the composite film. The insulating layer 2 between the bottom electrode and the metal includes a lower sub-layer and an upper sub-layer. The lower sub-layer, which is in contact with the bottom metal layer 1, adopts NDC. The dense carbon-nitrogen lattice network of this material blocks the diffusion of Cu elements in the bottom metal layer 1 to the surrounding area. The upper sublayer, which is in contact with the upper main electrode, uses PEOX to optimize the interfacial adhesion between the two layers. In this embodiment, the overall thickness of the bottom electrode and the intermetallic insulating layer 2 is controlled between 150 and 2000 Å. This thickness range is determined because: if it is less than 150 Å, sufficient dielectric breakdown margin cannot be provided (insulation failure), while if it is more than 2000 Å, it will increase the difficulty of high aspect ratio processing for subsequent via etching.

[0035] Based on the aforementioned insulating substrate structure, a via 3 connecting the bottom electrode and the metal layer is provided inside the insulating layer 2 between the bottom electrode and the metal layer. This via structure extends through the insulating layer vertically, with its lower end connected to the bottom metal layer 1. It is fabricated using photolithography and anisotropic plasma etching processes. The via is made of conductive material, adhering to both the barrier layer and the main conductive layer. Its vertical depth is limited to 150–2000 Å. The material is specifically selected from metals such as Ti, Hf, Ta, Ru, Ir, Pt, Zr, Al, W, Pd, and Co; metal nitrides such as TiN, TaN, AlN, and WN; or metal oxides such as TiON, TaON, and AlON. The introduction of the aforementioned metal system and nitrogen-containing groups effectively matches the work function of the upper and lower layers, thereby forming a low-impedance contact interface with adjacent structures, down to below 5 Ω.

[0036] The core part located directly above the bottom electrode, the metal interlayer insulation layer 2, and the through hole is a columnar device structure. This columnar device structure consists of, from bottom to top, a bottom electrode 4, a lower charge trap layer 5, a switching layer 6, an upper charge trap layer 7, a top electrode 8, and a metal interlayer insulation layer 12 located on the top surface of the top electrode 8.

[0037] The bottom electrode and the top electrode serve as charge transport channels at both ends of the device, and their materials are selected from the range of metals, metal nitrides, or metal oxynitrides covered by the aforementioned via.

[0038] For the core storage mechanism of this device, a multilayer structure sandwiched between two electrode layers constitutes the resistive switching body of the device. The thickness of the switching layer located in the core region is limited to the range of 10–500 Å, and its material is selected from one of GeTe, GeSb, SbTe, SnSbSe, SnSeIn, SiSnSe, InTe, SnTe, SbInTe, GeSe, GeAsTe, SiGeAsTe, SiGeAsSe, GeSbTe, GeSeSb, SnSe, GeAsSe, GeAsSb, NbOx, VOx, TiOx, GaOx, ZrOx, HfOx, HfTaO, HfZrO, HfSiO, HfAlO, or a multi-component compound formed therefrom.

[0039] When a bias voltage is applied externally, a reversible phase transition between crystalline and amorphous states occurs within the switching layer material, or conductive filaments connect and break under ion migration drive, achieving switching between high-resistivity and low-resistivity states, thereby recording and storing data. The thickness of this layer is set to 10–500 Å to ensure that the turn-on voltage is within a low-voltage range (below 3V) controllable by the logic control circuit, while avoiding excessive leakage current.

[0040] The charge trap layers, located on the upper and lower sides of the switching layer, have independently limited thicknesses ranging from 10 to 200 Å. These two layers also utilize various chalcogenide mixtures found in the aforementioned switching layers, each independently selected from one of these materials or a multi-component compound formed therefrom. It should be noted that, to ensure a proper distribution of the internal electric field and the appropriate charge buffering mechanism, the thickness of switching layer 6 is greater than that of charge trap layer 5 or charge trap layer 7.

[0041] To ensure the structural integrity of the aforementioned stacked layers during semiconductor back-end processes, a metal interlayer insulating layer 2 (MIL2) is arranged on the top surface of the columnar device structure, i.e., the top electrode. This MIL2 has a thickness of 100–5000 Å and is made of SiON, Si3N4, or PEOX. This layer acts as a hard mask during the patterning stage of the device and protects the main structure during the downward etching process that penetrates the bottom electrode 4, exposing the upper surface of the bottom electrode and the MIL2. Furthermore, this layer also acts as a stop layer in subsequent chemical mechanical polishing (CMP) processes. Its specific mechanism is to utilize its relatively slow etching rate to protect the bottom electrode from direct plasma bombardment, maintaining a nearly vertical cross-sectional morphology on the sidewalls of the columnar structure. For the specific operational specifications of the hard mask in semiconductor etching, those skilled in the art can use conventional anisotropic plasma etching equipment.

[0042] Considering the contamination issues during wafer-level processing, a sidewall protection layer 10 is formed by conformally covering the entire sidewall of the columnar device structure. This layer has a thickness of 10–500 Å and is made of one or more materials selected from HfO2, Ta2O5, SiO2, TiO2, ZrO2, Al2O3, Si3N4, and silicon oxide deposited based on tetraethylsilane. This conformal layer establishes a physical barrier between the device body and the external environment, preventing the diffusion of oxygen atoms from the surrounding medium into the device interior.

[0043] An inter-device filler layer 11 fills the gaps between adjacent columnar device structures and is located outside the sidewall protective layer. This layer, with a thickness of 10–10000 Å, fills the high aspect ratio gaps between adjacent columnar devices. Its material is selected from tetraethylsilane-based silicon oxide or OSG. Above this, a top structure above the inter-device filler layer 11 and the second inter-metal insulating layer 12 is an inter-metal insulating layer 9. This topmost inter-metal insulating layer has a thickness between 100 and 50000 Å and is made of OSG, providing global planarization and interlayer isolation. This material has a low dielectric constant to achieve electrical isolation between the top layer traces and the underlying structure, reducing signal crosstalk caused by parasitic capacitance. The top metal layer 13 includes interconnect vias that penetrate the inter-metal insulating layer 9 and extend to the top electrode 8. These interconnect vias further penetrate the second inter-metal insulating layer 12 as required by the process to form an electrical connection with the top electrode 8.

[0044] See attached document Figure 2 By arranging multiple independent memory devices in an array, and setting the bottom metal layer 1 as a bit line and the top metal layer as a word line perpendicular to the bit line, each cylindrical memory device is precisely located at the intersection of a word line and a bit line in space, thereby forming a high-density two-dimensional addressable memory array.

[0045] See attached document Figure 3 Based on a single-layer cross-point array architecture, the aforementioned complete device assembly, including connecting vias, columnar electrode structures, and interlayer isolation media, is systematically and repeatedly stacked along a direction perpendicular to the substrate. This stacking arrangement utilizes vertical space to expand the number of physical layers, thereby increasing the number of bits of storage capacity per unit area of ​​the chip.

[0046] As a preferred embodiment of this application, in order to further illustrate the microscopic physical processes and collaborative working principles of the above-mentioned device structure, the resistive switching mechanism and the collaborative protection mechanism of the peripheral special film layer of the memory device will be described in detail in conjunction with specific electrical operations and semiconductor manufacturing environment.

[0047] See attached document Figure 3 When an electrical signal is applied to the top metal layer 13 and the bottom metal layer 1, the electric field penetrates the columnar device structure, causing a state transition within the core switching layer 6. The switching layer is made of a specific mixture of chalcogenides. This state transition manifests as a structural phase transition between a high-resistivity state in the amorphous state and a low-resistivity state in the polycrystalline state, or as the connection and disconnection of microscopic conductive channels driven by ion migration. For the conventional electrical signal triggering, read / write circuit settings, and timing control involved in resistive or phase-change memory, those skilled in the art can implement them using conventional pulse generators and detection circuits.

[0048] To clearly illustrate the dynamic storage process of the device, a typical resistive switching operation is broken down into the following steps: S101, the external driving circuit applies a positive voltage pulse to both ends of the device through the top electrode 8 and the bottom electrode 4. Under the combined effect of electric field driving and local Joule heating, the atomic arrangement inside the switching layer 6 is restructured, or metal ions undergo directional migration, and the overall resistance of the device decreases accordingly, completing the switch from a high-resistance state to a low-resistance state.

[0049] S102, during the aforementioned rapid charge transport process, the charge trapping layers (charge trapping layer 5 and charge trapping layer 7) located above and below the switching layer respectively play a buffering role. Because specific defect energy levels are pre-set within the chalcogenide hybrid material of charge trapping layer 5 and charge trapping layer 7, when an external bias voltage causes band bending within the device, some injected electrons or holes are directly captured by these defect energy levels. This capture effect establishes a microscopic built-in electric field in a localized region of the device interface. Based on the electrostatic feedback mechanism, this built-in electric field interacts with the applied bias electric field, smoothing and modulating the transient impact of the electric field on the switching layer body, reducing the probability of irreversible breakdown caused by excessive ion accumulation.

[0050] S103, a reverse voltage pulse or a wide pulse of a specific amplitude is applied to the device, driving the switching layer in the low-resistivity state to return to the initial high-resistivity state. During this electric field reversal process, the charges previously trapped by the trap layer are released again, accelerating the ion retraction or the amorphization transition of the crystal lattice. Based on the buffering and auxiliary release mechanism of the charge trap layer, the structural fatigue of the switching layer during repeated high-low resistance state switching is effectively alleviated, improving the device's erase / write cycle life from a macroscopic electrical perspective.

[0051] In addition to the dynamic working mechanism mentioned above, facing the complex back-end process environment of semiconductor manufacturing, the structural stability and long-term yield of the device depend on the joint protection of specific protective films on the outside.

[0052] The conformally conformal sidewall protection layer 10 covering the device sidewalls functions primarily through physical barrier and chemical passivation. The sidewall protection layer 10 is made of high-density metal oxides, metal nitrides, or TEOS materials, all of which possess low oxygen atom and water vapor diffusion coefficients. During subsequent oxide dielectric deposition and chemical mechanical polishing processes, the sidewall protection layer 10 blocks the penetration and diffusion paths of oxygen molecules and free water vapor from the external environment to the columnar device sidewalls. This mechanism limits unintended oxidation and deterioration of the switching and trapping layer materials at the sidewall edges, maintaining the constant physical volume and consistent electrical parameters of the core resistive switching region of the device.

[0053] To address the physical damage risks during plasma processing, the second interlayer insulating layer 12, located at the top edge of the columnar device, provides a lower-level etching buffer function during the patterning stage of the device. Specifically, the SiON, Si3N4, or PEOX materials used in this layer exhibit significantly lower physical and chemical etching rates under fluorine-based or chlorine-based plasma etching environments compared to the underlying metal electrode materials. By using the second interlayer insulating layer 12 as a hard mask layer in the process, the high-energy plasma bombardment energy within the reaction chamber is largely absorbed and consumed by the second interlayer insulating layer 12. This prevents the formation of etching pits and lattice damage on the surface of the top electrode 8, while ensuring that the sidewalls of the columnar device structure maintain a near-vertical physical morphology after etching, avoiding a tapered failure structure that is narrow at the top and wide at the bottom.

[0054] Furthermore, the bottom electrode located at the bottom of the device and the NDC sublayer in the intermetallic insulating layer 2 form a dense underlying physical barrier using the carbon-nitrogen lattice network within the material. Since active metal ions such as Cu in the bottom metal layer 1 are prone to upward electromigration during subsequent thermal cycling, the NDC sublayer effectively blocks the vertical upward diffusion channels of Cu ions, preventing a large influx of Cu ions into the upper bottom electrode and switching layer region, thus avoiding leakage current and hard breakdown short circuits at the bottom of the device.

[0055] Preparation Examples 1-2: Preparation Example 1: This preparation example provides a method for preparing a Ge-Sb-Te-Se composite target for depositing a switching layer and a charge trapping layer, comprising the following steps: S101, Raw Material Powder Preparation and Mixing. Accurately weigh Ge powder, Sb powder, Te powder, and Se powder with a purity of 99.99% or higher according to the set molar percentages. Place the above raw material powders in a ball mill jar filled with inert gas Ar, add cemented carbide grinding balls, and perform mechanical alloying ball milling. Set the ball milling speed to 300–500 rpm and the grinding time to 10–24 hours. The basis for setting these grinding parameters is to achieve atomic-level uniform mixing of multi-element powders through high-energy mechanical collision, while controlling the powder particle size to below 10 μm to prevent component segregation or local enrichment during subsequent molding processes.

[0056] S102, warm-press solid-state sintering. Thoroughly mixed alloy powder is loaded into a graphite mold and placed in a vacuum hot press furnace for sintering. The vacuum level is controlled below 1.0 × 10⁻⁶. -3The powder is heated to 250–350°C at a constant heating rate, and a unidirectional axial pressure of 50–80 MPa is applied, holding the temperature and pressure for 2–4 hours. The sintering temperature is strictly limited to the low-to-medium temperature range of 250–350°C. The core physical basis for this is that the melting point of Se in the composition is only 221°C. If conventional high-temperature sintering is used in a vacuum environment, the free Se and Te will undergo violent volatilization, resulting in severe selenium and tellurium deficiency in the finished target material. By increasing the axial forming pressure to above 50 MPa, densification can be achieved at low temperatures, before reaching the eutectic points of each element, through the plastic rheology and interfacial diffusion of the powder particles, ensuring that the final composition strictly conforms to the preset stoichiometric ratio.

[0057] S103, Cooling and Machining. The mold is slowly cooled to room temperature in the furnace under vacuum before demolding, yielding a dense, disc-shaped target blank. The blank is then surface-cut and polished using a precision CNC machine tool to remove the carbon-rich reactive layer and microcracks, reducing the target surface roughness to below 0.5 μm. Finally, the target is processed into a finished sputtering target of standard dimensions suitable for physical vapor deposition equipment.

[0058] Preparation Example 2: This preparation example provides a method for preparing a precursor mixture for depositing an organosilica glass film (OSG), comprising the following steps: S201, the silicon-based framework source and the pore-forming agent are mixed in a specific volume ratio. In an oxygen-free and anhydrous environment (nitrogen glove box), tetramethylcyclotetrasiloxane (as the silicon-oxygen framework source) and cyclooctane (as the pore-forming agent) are mixed at a specific volume ratio. As a preferred embodiment of this application, the volume fraction of the pore-forming agent in the mixture is strictly controlled to be between 20% and 40%. This range is determined because when the pore-forming agent ratio is below 20%, the porosity formed after subsequent film formation and UV curing to remove the pore-forming agent is insufficient, failing to effectively reduce the dielectric constant of the dielectric to below 3.0; while when the pore-forming agent ratio is above 40%, through-hole macropores will form inside the deposited dielectric film, severely weakening the mechanical support strength between the inter-device filling layer and the insulating layer between the metal layers, leading to film collapse and peeling during subsequent chemical mechanical polishing processes.

[0059] S202, Ultrasonic Dispersion and Submicron Filtration. The above mixture is placed in an ultrasonic oscillation device with a temperature control module and subjected to isothermal ultrasonic treatment at 20–25°C for 30–60 minutes. The ultrasonic cavitation effect breaks down molecular clusters within the liquid, ensuring that the two components of different densities form a highly homogeneous solution. The uniformly dispersed mixture is then filtered under positive pressure through a 0.02 μm PTFE nanofiltration membrane. This filtration step aims to precisely remove potential metal particles and polymer impurities from the solution, ensuring that the precursor meets high-purity electronic-grade standards and avoiding the introduction of fatal particle defects on the deposition surface of the semiconductor wafer.

[0060] S203, inert gas bubbling displacement degassing treatment. The filtered high-purity mixture is introduced into a sealed stainless steel degassing tank, and high-purity helium is used to perform micro-bubbling from the bottom of the tank into the liquid interior through a specially designed microporous diffuser. Bubbling displacement is continued for 30 to 60 minutes. For volatile organosilicon liquids with high saturated vapor pressure, the high-vacuum direct extraction method is strictly prohibited, otherwise it will cause violent boiling of the precursor and loss of components due to volatilization. The helium bubbling displacement method utilizes the low solubility of helium in organic liquids, and according to the law of partial pressure, gradually carries away the trace amounts of air and moisture dissolved in the mixture, ensuring that the gas phase transport flow rate will not fluctuate due to microbubble bursting during the subsequent high-frequency plasma film formation stage.

[0061] Examples 1-7: Example 1: This example provides a method for fabricating a storage device, including the following steps: In this embodiment, based on a wafer substrate containing a bottom metal layer 1, a plasma-enhanced silicon oxide (PEOX) layer with a thickness of 1000 Å is deposited as an insulating layer 2 between the bottom electrode and the metal layer using plasma-enhanced chemical vapor deposition (PECVD). Through-hole morphology is formed by photolithography and anisotropic plasma etching processes penetrating the insulating substrate. To prevent subsequent metal penetration and improve interface adhesion, a 100 Å thick Ti / TiN composite barrier layer is first conformally deposited using physical vapor deposition (PVD). Subsequently, a 700 Å thick W metal layer is filled using PVD to fill the through-holes. Excess metal on the surface is removed using chemical mechanical polishing (CMP) to ensure that the composite metal through-holes (connecting the bottom electrode and the metal layer through-hole 3) with a vertical depth in the range of 150–2000 Å are flush with the surface of the insulating substrate.

[0062] After the flat base is constructed, the wafer is moved into a high-vacuum physical vapor deposition (PVD) system for continuous fabrication of the core memory stack. A 200 Å thick TiN layer is deposited sequentially as the bottom electrode 4, followed by a 50 Å thick InTe layer as the lower charge trap layer 5 using a high-precision co-sputtering process. The physical rationale for this thickness parameter is that the 50 Å film provides sufficient surface defect energy level density to effectively trap carriers while limiting non-tunneling scattering of electrons, avoiding an increase in parasitic series resistance due to excessive film thickness. Next, a 150 Å thick GeSe layer is sputtered as the switching layer 6. This thickness is greater than that of the upper and lower charge trap layers. Combined with the microscopic built-in electric field modulation of the charge trap layers, this allows the device to achieve stable phase-change resistive state switching at a safe bias voltage below 3V. Subsequently, a 50 Å thick InTe layer is deposited as the upper charge trap layer 7 under symmetrical process conditions, followed by a 200 Å thick TiN layer as the top electrode 8. As a preferred masking scheme, a 1000 Å thick Si3N4 layer is deposited on top of this multilayer stack as an interlayer insulating layer, providing a consumable hard mask support for subsequent high-energy plasma bombardment.

[0063] Relying on the photolithographic pattern transfer of the aforementioned Si3N4 hard mask, a reactive ion etching (RIE) machine using a fluorine- and chlorine-based mixed gas is employed to perform continuous vertical etching downwards on the stacked layers. Based on the chemical volatilization effect of halogen radicals on TiN and chalcogenides, the film layers in the non-patterned areas are precisely stripped, exposing the underlying silicon oxide dielectric surface, thereby forming a columnar structure with steep sidewalls. To suppress unintended oxidation of the newly etched active sidewalls in the exposed environment, an 80 Å thick SiO2 layer is deposited as a sidewall protection layer 10 using atomic layer deposition (ALD) under vacuum transfer conditions. Utilizing the self-confined growth characteristics of this process at the molecular scale, the SiO2 film is uniformly and densely conformally wrapped around the entire micro / nano columnar device, effectively blocking the subsequent intrusion paths of water molecules and free oxygen.

[0064] After sidewall passivation, a 3000 Å thick tetraethylsilane-based silicon dioxide layer 11 is deposited using chemical vapor deposition to fill the narrow gaps between adjacent devices. A global etch-back process is then implemented to selectively remove excess dielectric at the top of the columnar structure, exposing the upper surface of the second intermetallic insulating layer 12. Subsequently, in subsequent interconnect processes, contact holes penetrating the second intermetallic insulating layer 12 are etched to achieve electrical connection between the top metal layer 13 and the top electrode 8, while simultaneously removing the inter-device fill layer 11 and part of the second intermetallic insulating layer 12 in non-device structure areas. A 5000 Å thick low-dielectric-constant organic silica glass (OSG) is deposited as the top intermetallic insulating layer 9, completing the basic isolation and global planarization of the intermetallic layers. Finally, chemical mechanical polishing (CMP) and cleaning processes are used to complete surface planarization and impurity removal, laying a physical substrate without height differences for the interconnection of the top metal wires.

[0065] Example 2: This example provides a method for fabricating a storage device, including the following steps: To meet the low-impedance transmission requirements in low-power scenarios, this embodiment directly uses a 200 Å thick nitrogen-doped silicon carbide (NDC) as the bottom electrode and the metal-interface insulating layer 2. The dense carbon-nitrogen cross-linked network of this material completely blocks ion effervescence from the underlying extremely fine Cu interconnects. After the via is formed, a 200 Å thick Ru metal is filled using physical vapor deposition to connect the bottom electrode and the metal layer via 3, and a 50 Å thick Ru layer is deposited in situ as the bottom electrode 4. The conventional noble metal Pt is abandoned in favor of Ru because Ru not only possesses a high work function similar to Pt to stabilize the interface barrier, but its surface can also generate volatile RuO4 gas in the subsequent halogen etching environment, thus solving the process problem of noble metals being unable to be anisotropically etched by plasma.

[0066] Based on the aforementioned highly conductive substrate, SnTe with a thickness of only 20 Å was deposited using a low-power pulsed physical sputtering technique as the lower charge trapping layer 5 and the upper charge trapping layer 7. In this extremely thin state, approaching the physical film-forming limit, SnTe grains spontaneously aggregate at the interface to form a discontinuous island-like distribution. This microstructure is rich in discrete deep-level charge trapping centers. The intercalated switching layer 6 is made of 30 Å thick GeSbTe material, which reduces the transient Joule heating and trigger current required for amorphous reset operations by minimizing the device's physical volume. The top interlayer insulating layer 12 is correspondingly set as a 200 Å thick plasma-enhanced silicon oxide.

[0067] After shaping the ultrathin columnar structure using high-selectivity plasma etching with a mixture of oxygen-containing groups and halogens, an atomic layer deposition process was used to coat it with a 30 Å thick HfO2 layer as a sidewall protective layer 10. Introducing such a high-dielectric-constant material not only provides dense oxygen-barrier passivation performance, but its high polarization characteristics also effectively constrain the electric field distribution and suppress the edge leakage current effect between adjacent, closely spaced devices. The subsequent gap filling and encapsulation process used a specially prepared organic silica glass film with a porosity of 30% as described in the previous preparation example, with a total thickness controlled at 2000 Å. This filled the gaps while reducing the interlayer dielectric constant to below 3.0, thus weakening array parasitic capacitance crosstalk caused by high-frequency read / write signals.

[0068] Example 3: This example provides a method for fabricating a storage device, including the following steps: To address the challenges of operating environments with strong electric and thermal stresses, this embodiment enhances insulation performance starting from the substrate. A 1500 Å thick plasma-enhanced silicon dioxide layer is deposited as the insulating layer 2 between the bottom electrode and the metal layer, significantly increasing the intrinsic breakdown voltage. After photolithography to create large-sized apertures, a 1500 Å thick TiN or other metal nitride material and W composite conductor are filled using reactive physical vapor deposition to connect the bottom electrode and the metal layer via 3, followed by planarization.

[0069] In constructing the high-capacity charge-carrying region, W metal with a thickness of 400 Å is deposited as the top and bottom electrodes. As a preferred method, a GeSe material with a thickness of 150 Å is deposited using physical vapor deposition (PVD) as the top and bottom charge trap layers, providing a broad carrier buffer region that is less prone to saturation under strong electric fields. The switching layer is a 400 Å thick SiGeAsTe quaternary chalcogenide mixture, thicker than the 150 Å top and bottom charge trap layers. This thicker resistive switching host space elongates the physical growth and breakage path of the conductive filaments. While this sacrifices microsecond-level write speeds physically, it enhances the long-term data retention capability of the device in a high-resistivity state at high temperatures by increasing the resistance of the phase transition interface. A matching hard mask layer is deposited as a 2000 Å thick SiON material to withstand subsequent long-term deep-groove plasma bombardment.

[0070] After etching the high aspect ratio device, the risk of mechanical tipping due to the slender columnar structure was addressed by depositing a dense 300 Å thick Ta₂O₅ film as a sidewall protection layer using atomic layer deposition (ALD). This thicker heavy metal oxide layer not only isolates external reactive oxygen atoms but also provides strong lateral structural stiffness support for the slender columnar device at the micromechanical level, preventing slippage and tilting of the internal lattice during subsequent high-temperature reflow processes. Finally, deep trench interlayer filling and thick surface coverage were performed sequentially using 8000 Å thick tetraethylsilane oxide and 10000 Å thick organosilicon glass. The final planarization and packaging of the high-strength architecture was achieved by extending the chemical mechanical polishing (CMP) time.

[0071] Example 4: This example provides a method for fabricating a storage device, including the following steps: To fully leverage the advantages of different insulating materials and prevent diffusion of the underlying metal, this embodiment employs a composite process to fabricate the bottom electrode and the intermetallic insulating layer 2 on the bottom metal layer 1. First, a 500 Å thick nitrogen-doped silicon carbide (NDC) layer is deposited in the lower region in contact with the bottom metal layer 1 using plasma-enhanced chemical vapor deposition. Then, the process gas is switched in situ to deposit a 500 Å thick plasma-enhanced silicon oxide (PEOX) layer in the upper region in contact with the subsequent bottom electrode, thus controlling the total thickness of the composite insulating layer to 1000 Å.

[0072] Through-holes were formed through the composite insulating layer using photolithography and anisotropic plasma etching. During the through-hole filling stage, metal oxide nitride was introduced to optimize the interfacial work function and thermal stability. Specifically, reactive physical vapor deposition was employed, where a titanium target was sputtered in a mixed plasma atmosphere containing argon, nitrogen, and trace amounts of oxygen to deposit a 1000 Å thick TiON (titanium oxide nitride) layer as the connection between the bottom electrode and the metal layer through-hole 3. Planarization was then achieved through chemical mechanical polishing.

[0073] On the planarized substrate, the core storage stack is deposited sequentially: a 150 Å thick TaN layer is deposited as the bottom electrode 4 using physical vapor deposition; a 20 Å thick GeAsSb layer is deposited as the lower charge trap layer 5 using atomic layer deposition; a 120 Å thick SiGeAsSe layer is deposited as the switching layer 6 using physical vapor deposition, which is thicker than the charge trap layer to ensure the physical capacity of the core resistive switching region; a 20 Å thick GeAsSb layer is deposited as the upper charge trap layer 7 under symmetric conditions; finally, a 200 Å thick TaN layer is deposited as the top electrode 8, and a 1500 Å thick SiON layer is deposited on top as the intermetallic insulating layer 12.

[0074] Using the SiON interlayer insulating layer 12 as a hard mask, high-selectivity deep trench etching is performed, penetrating down to expose the surface of the bottom composite insulating layer, forming a complete columnar device structure. To prevent sidewall damage during the fabrication process, an atomic layer deposition process is used to conformally deposit a 40 Å thick Al2O3 layer as a sidewall protection layer 10. The high density of Al2O3 provides an excellent oxidation barrier for the device sidewalls.

[0075] Finally, a 4000 Å thick tetraethylsilane-based silicon dioxide layer 11 was deposited using chemical vapor deposition (CVD) as the inter-device filler layer. After global etch-back, a 6000 Å thick organic silica glass (OSG) layer was deposited as the top metal interlayer insulating layer 9. Excess dielectric material on top was removed and global planarization was achieved using chemical mechanical polishing (CMP), exposing the top electrodes for subsequent via interconnects in the top metal layer 13.

[0076] Example 5: This example provides a method for fabricating a storage device, including the following steps: A bottom electrode and an intermetallic insulating layer 2 with a thickness of 150 Å are deposited on the bottom metal layer 1. After etching the via, Pt metal is deposited using a physical vapor deposition process, and a via 3 with a vertical depth of 150 Å connecting the bottom electrode and the metal layer is formed by grinding.

[0077] On the planarized surface, a core stack is deposited sequentially: a 10 Å thick Zr metal layer is deposited as the bottom electrode 4 using physical vapor deposition; a 10 Å thick SnSe layer is deposited as the lower charge trapping layer 5 using atomic layer deposition; a 15 Å thick GeAsTe layer is deposited as the switching layer 6; a 10 Å thick SnSe layer is deposited as the upper charge trapping layer 7; and a 10 Å thick Ir metal layer is deposited as the top electrode 8. A 100 Å thick SiON layer is then deposited on top as the interlayer insulating layer 12.

[0078] After etching to form a columnar structure, a 10 Å thick TiO2 film is deposited as a sidewall protective layer 10 using atomic layer deposition (ALD). Subsequently, a 10 Å thick organosilica glass (OSG) is used as an inter-device filling layer 11. Finally, a 100 Å thick OSG is deposited as the top metal interlayer insulating layer 9.

[0079] Example 6: This example provides a method for fabricating a columnar storage device with a large film size, including the following steps: After depositing a bottom electrode with a thickness of 2000 Å and an intermetallic insulating layer 2, deep holes are etched and filled with material using a reactive physical vapor deposition process. After planarization, AlON (aluminum nitride) with a longitudinal depth of 2000 Å is formed as a through hole 3 connecting the bottom electrode and the metal layer.

[0080] Subsequently, a core stack was deposited: a 1500 Å thick Ta metal was deposited as the bottom electrode 4; a 200 Å thick GeAsSe was deposited as the lower charge trap layer 5; a 500 Å thick SbInTe was deposited using a co-sputtering process as the switching layer 6; a 200 Å thick GeAsSe was deposited as the upper charge trap layer 7; and a 5000 Å thick TaON (tantalum nitride) was deposited as the top electrode 8. Finally, a 5000 Å thick Si3N4 was deposited on top as the intermetallic insulating layer 12.

[0081] After deep trench etching to form a columnar structure, a 500 Å thick ZrO2 layer is deposited as a sidewall protective layer 10. Subsequently, a 10,000 Å thick inter-device filling layer 11 is formed by filling the gaps with tetraethylsilane-based silicon oxide (TEOS). Finally, a 50,000 Å thick OSG layer is placed as the top metal interlayer insulating layer 9.

[0082] Example 7: This example provides a method for fabricating a storage device. The overall process flow is basically the same as in Example 1, except that some film materials are replaced: In preparing the via 3 connecting the bottom electrode and the metal layer, physical vapor deposition or chemical vapor deposition processes were used to prepare via structures with a single material of Hf, Al, TaN, AlN or TaON.

[0083] In the deposition of resistive switching layer and charge buffer system, physical vapor deposition was used to prepare a lower charge trap layer (charge trap layer 5, thickness 50 Å), a switching layer 6, thickness 120 Å, and an upper charge trap layer (charge trap layer 7, thickness 50 Å) made of GeSeSb.

[0084] In the fabrication of the bottom electrode 4 and the top electrode 8, Al, W and Hf were used as the corresponding electrode materials, respectively.

[0085] In preparing the sidewall protective layer 10, Si3N4 thin films or silicon oxide thin films based on tetraethylsilane deposition were prepared by chemical vapor deposition as the sidewall passivation structure of the device.

[0086] Comparative Examples 1-6: Comparative Example 1: Compared with Example 1, the difference is that the lower charge trap layer 5 and the upper charge trap layer 7 are not set, and the bottom electrode 4 and the top electrode 8 directly clamp the switch layer 6. All other aspects are the same.

[0087] Comparative Example 2: Compared with Example 1, the difference is that no sidewall protective layer 10 is deposited, and the inter-device filling layer 11 directly covers and contacts the exposed outer sidewall of the columnar device structure; otherwise, they are the same.

[0088] Comparative Example 3: Compared with Example 4, the difference is that the bottom electrode and the metal insulating layer 2 do not use a composite film structure of NDC and PEOX, but only a single plasma-enhanced silicon oxide (PEOX) with a thickness of 1000 Å is deposited, while the rest are the same.

[0089] Comparative Example 4: Compared with Example 1, the difference lies in adjusting the thickness ratio of the core stack. The thickness of both the lower charge trap layer 5 and the upper charge trap layer 7 is increased to 150 Å, while the thickness of the switching layer 6 is reduced to 50 Å (i.e., the thickness of the switching layer is less than the thickness of the charge trap layer). All other aspects are the same.

[0090] Comparative Example 5: Compared with Preparation Example 1, the difference is that the temperature of warm-pressed solid-state sintering in step S102 is set to 600°C (above the limited range of 250-350°C), while the rest are the same.

[0091] Comparative Example 6: Compared with Preparation Example 2, the difference is that in step S201, the volume fraction of the porogen (cyclooctane) in the mixture is set to 60%, while the rest are the same.

[0092] Test Examples 1-5: Test Example 1: Experimental description: The prepared wafer is fixed on the probe stage of a semiconductor parameter analyzer (such as an Agilent B1500A). Ohmic contacts are established with the bottom metal layer 1 interconnect pads at the bottom and the top metal layer interconnect pads at the top of the device using tungsten probes.

[0093] Set up a DC sweep frequency test module. Apply a positive DC sweep voltage gradually increasing from 0V to 3V to the device, setting the compliance current upper limit to 1mA. Monitor the current flowing through the device; when a sudden, significant increase in current is detected, record the voltage value at this point as the turn-on voltage. ).

[0094] After the device switches to the low-resistance state, a small voltage with an amplitude in the range of 0.1V to 0.5V is applied to read the initial low-resistance resistance (LRS). Subsequently, a reverse DC scan voltage is applied to reset the device, and the initial high-resistance resistance (HRS) is read.

[0095] Set the pulse generator module to perform an erase / write cycle lifetime test. Alternately apply positive set pulses (pulse width 50ns, amplitude slightly higher than the measured value) to the device. ) and reverse reset pulse (pulse width 100ns, amplitude adjusted according to device characteristics).

[0096] During the pulse application interval, a 0.2V read pulse is inserted to monitor the real-time resistance values ​​of the high and low resistance states. When the high resistance state resistance decreases or the low resistance state resistance increases, causing the on / off ratio (HRS / LRS) to fall below 10, the device is deemed to have failed, the system stops testing, and the accumulated number of erase / write cycles is recorded.

[0097] Experimental data: Table 1. Basic electrical characteristics and erase / write cycle life test results of Examples 1-7 and Comparative Example 1

[0098] in conclusion: According to the data in Table 1, the turn-on voltages of Examples 1-7 range from 1.68V to 2.35V, while the turn-on voltage of Comparative Example 1 is 1.45V. The turn-on voltages of all examples are generally higher than those of Comparative Example 1, and remain within the logic-compatible low-voltage range of 3V. Combined with... Figure 4 As can be seen from the current-voltage characteristic curves in (a), when the same scanning voltage is applied, the leakage current level in the high-resistivity scanning region of the embodiment is lower than that of Comparative Example 1. This phenomenon corresponds to the architectural mechanism of this application: In this embodiment, charge trapping layers are added above and below the switching layer. The defect energy levels unique to the trapping layer material provide a high density of local charge trapping sites. The trapped charge carriers form a microscopic built-in electric field at the heterojunction. This electric field increases the potential barrier height for charge carriers to cross the interface, causing a slight increase in the external bias voltage required to drive the switching layer to undergo a phase transition or to connect ion-conducting channels. It also suppresses the initial background leakage current at the macroscopic level.

[0099] Combined with Table 1 Figure 4 (b) shows the resistance change curve with the number of cycles. In the initial stage of the test, both Comparative Example 1 and Example 1 established a clear resistance distribution window. As the number of pulses accumulated, Comparative Example 1 showed a resistance change exceeding 10 cycles. 5 Subsequently, the high-resistivity state exhibited a sharp downward trend, eventually closing completely with the low-resistivity state curve. Table 1 records its failure point as 2.15 × 10⁻⁶. 5 This manifests as irreversible low-resistivity breakdown. The high and low resistance curves of Example 1 show a breakdown over a period of 10 seconds. 8 Even under secondary stress impact, it maintained a stable, parallel, and separated trend. Table 1 records its actual lifespan as 1.34 × 10⁻⁶. 8 The above data discrepancies directly confirm the buffering effect of the charge trap layer.

[0100] In Comparative Example 1, the lack of a defect level buffering mechanism means that the repeatedly flipping external high-frequency electric field causes unidirectional accumulation of migrating ions within the switching layer, leading to continuous accumulation of lattice defects at the electrode interface. This results in material fatigue and the formation of permanently conductive filaments that cannot be melted. In the embodiment, the trap layer utilizes interface defects to capture and store some transient charges. The resulting built-in electric field, based on electrostatic feedback, modulates and smooths subsequent erase / write pulses. This dynamic adjustment at the electrical level reduces the amount of ion accumulation during each resistance-state switching process, alleviating thermomechanical stress and chemical fatigue in the main structure and physically suppressing short-circuit failure.

[0101] Test Example 2: Experimental description: The wafer under test is placed on the probe stage in the shielded dark chamber. Radio frequency probes are inserted into the test pads on the top and bottom of the device and connected to a pulse waveform generator and a high-speed digital oscilloscope.

[0102] The pulse generator is set to output a voltage pulse sequence with a pulse width of 100ns and a rise / fall time of 5ns. The pulse amplitude increases incrementally in steps of 0.1V starting from 0.5V, and a 0.2V read pulse is inserted after each write pulse to monitor the resistance change of the device.

[0103] When the device resistance value drops by a significant order of magnitude from a high resistance state to a low resistance state, the amplitude of the applied pulse at this time is recorded as the turn-on voltage.

[0104] The transient current waveform at the moment of resistive state reversal is captured synchronously using an oscilloscope current probe. The peak current in the waveform is extracted, and the product of voltage and current is integrated in the time domain over a 100ns pulse width to calculate the power consumption of a single write operation.

[0105] Several independent storage cells are randomly selected from different regions such as the center and edge of the same wafer. The above operation steps are repeated to extract measured data points with a certain degree of discreteness.

[0106] Experimental data: Table 2. Operating voltage and power consumption data of different test units in Example 1 and Comparative Example 4

[0107] in conclusion: According to the data in Table 2, the turn-on voltages of the five test units selected in Example 1 are concentrated between 1.76V and 1.95V, with corresponding single-write power consumption ranging from 8.1pJ to 10.1pJ. In Comparative Example 4, because the thickness of the lower and upper charge trap layers is increased to be greater than the thickness of the switching layer, the turn-on voltage jumps to between 4.88V and 6.12V, and the highest recorded single-write power consumption reaches 128.8pJ. Combined with... Figure 5 The scatter distribution pattern of (a) shows that, compared with the data in Example 4, not only does the overall data shift significantly to the upper right of the coordinate axis, but the parameter dispersion between its internal units also increases accordingly.

[0108] This macroscopic electrical difference verifies the impact of thickness ratio limitations on the device's operating mechanism. The core stack can be equivalently represented along the electric field direction as an electrical network consisting of upper and lower charge trap layers connected in series with an intermediate switching layer. The trap layer material is a wide-bandgap insulating or semiconductor dielectric with deep-level defects. When the physical thickness of the trap layer is greater than that of the switching layer, the applied voltage is divided in this series network, and most of the electric field drops across the excessively thick trap layer. The effective electric field reaching the switching layer region is severely attenuated, failing to reach the critical electric field strength required to drive a phase transition in the host material or form conductive filaments. To forcibly trigger the switching layer, the externally applied overall bias voltage must be increased.

[0109] Figure 5 The transient current curve in (b) further reflects the secondary consequences caused by the high-voltage drive. In Comparative Example 4, the current amplitude spikes to nearly 200 μA instantaneously when the resistance state reverses near 85 ns. The high-intensity external bias voltage injects an overshoot current into the device that exceeds the material's thermal equilibrium limit during the extremely short time that the switching layer suddenly turns on.

[0110] This uncontrolled current surge leads to excessive Joule heat buildup, directly increasing the macroscopic power consumption data calculated in Table 2. In contrast, Example 1, by setting the switching layer thickness to be greater than the charge trap layer thickness, ensures that the effective voltage division of the applied voltage is concentrated in the core switching region. This allows the device to complete resistive switching at a low voltage of less than 2V. Figure 5 (b) shows that the current after the flip is limited to about 50μA, eliminating the destructive current overshoot phenomenon and ensuring that the device has both low operating power consumption and drive circuit compatibility.

[0111] Test Example 3: Experimental description: The wafer samples prepared in Example 1 and Comparative Example 2 were selected and diced into independent test dies using a wafer dicing device.

[0112] Place the die on the probe stage and apply set and reset pulses to the test cells within the selected memory array using a semiconductor parameter analyzer. Program half of the cells in the array to a low-resistance state and the other half to a high-resistance state. Apply a DC bias voltage of 0.2V and record the initial resistance value of each cell at room temperature.

[0113] The test die, after initial programming, is moved into a high-temperature aging test chamber. The chamber temperature is set to 125°C to simulate the chip's heat generation and storage environment under extreme conditions.

[0114] At the set insulation time points of 10, 50, 100, 200, 500, 800 and 1000 hours, the test bare wafers were temporarily removed from the aging chamber and placed in a nitrogen-protected cabinet to cool naturally to room temperature.

[0115] After cooling, the die is placed back on the probe station, a reading voltage of 0.2V is applied, and the real-time resistance value of the array cells is measured and recorded. After the measurement is completed, the die is placed back into the high-temperature aging test chamber for continued heating until the cumulative time reaches 1000 hours.

[0116] Experimental data: Table 3. Evolution of high and low resistance values ​​of Example 1 and Comparative Example 2 under high temperature stress at 125°C

[0117] in conclusion: According to the data in Table 3, after 1000 hours of baking and aging at 125°C, the high-resistivity resistance of Example 1 only slightly shifted from 683.4kΩ to 627.8kΩ, while the low-resistivity resistance changed from 12.5kΩ to 16.5kΩ. The device still maintained a switching readout window of approximately 38 times. In contrast, the resistance state of Comparative Example 2 degraded significantly over time, with the high-resistivity resistance dropping from 512.6kΩ to 88.5kΩ and the low-resistivity resistance gradually increasing from 8.3kΩ to 68.2kΩ. At the 1000-hour mark, the high-resistivity and low-resistivity values ​​of Comparative Example 2 became extremely close, and the device essentially lost its effective data identification capability.

[0118] Combination Figure 6 The resistance evolution trajectory of (a) and Figure 6As shown in the high-resistivity normalized retention curve of (b), the resistance degradation of Comparative Example 2 exhibits a nonlinear accelerated decay trend that intensifies over time. Comparative Example 2 lacks a sidewall protection layer structure, and the columnar stacked sidewalls exposed by etching are in direct contact with the surrounding inter-device filler layer. The filler layer is composed of silicon oxide deposited by chemical vapor deposition, and the material itself has a relatively loose structure and easily absorbs moisture. Driven by high heat at 125°C, oxygen and water molecules in the environment, as well as the active groups remaining inside the interlayer medium, penetrate into the core device region along the loose silicon oxide medium through the thermal diffusion effect.

[0119] Because the chalcogenides in the core stack of the device are sensitive to oxygen, the oxygen atoms diffusing inward react with the chalcogenides at the sidewall interfaces, disrupting the original stoichiometry of the material system. This interfacial oxidation and deterioration erodes the device layer by layer, leading to an abnormally high defect level density in the switching and charge trapping layers. Macroscopically, this manifests as a sharp increase in leakage current and a drop in resistance in the high-resistivity state. Furthermore, localized oxidation products block some effective ion transport paths, deteriorating the conductive channel interface formed in the low-resistivity state and causing a continuous increase in the low-resistivity resistance.

[0120] Example 1: A 40 Å thick Al₂O₃ sidewall protective layer was conformally coated onto the device sidewalls. The Al₂O₃ film grown by atomic layer deposition (ALD) exhibits high density, forming a continuous, non-porous passivation layer. This film layer cuts off the physical path for external oxygen and moisture to diffuse into the internal material, isolating the core operating region of the device from the external insulating medium. Test data and curve trends confirm the effectiveness of this physical barrier. Example 1 can maintain the stability of chalcogenide compounds and the composition of each interface under long-term thermal stress, preventing energy level degradation caused by environmental erosion and ensuring the long-term storage reliability of the device in both high and low resistivity states.

[0121] Test Example 4: Experimental description: The wafers prepared in Example 4 and Comparative Example 3 were selected, cut into independent test dies, placed in the heated test chamber of the probe station, and the ambient temperature was set and stabilized at 105°C to accelerate the thermal motion and electromigration process of metal ions.

[0122] Using a semiconductor parameter analyzer, tungsten probes were used to contact both ends of the interconnect test pattern formed by the bottom metal layer 1 of the device.

[0123] Perform a voltage scan test by applying a DC bias voltage from 0V to continuously increasing voltage between adjacent metal traces, extracting steady-state leakage current data when the electric field strength reaches 3MV / cm, and calculating the initial leakage current density.

[0124] A time-delayed dielectric breakdown (TDDB) test was performed by applying a constant high-intensity electric field stress of 4 MV / cm between adjacent metal interconnect patterns. The system continuously sampled and recorded the change in current flowing through the intermediate insulating dielectric layer (the insulating layer 2 between the bottom electrode and the metal) over time.

[0125] The failure threshold is set to 1μA. When the monitored current crosses this threshold and a hard breakdown jump occurs, the test channel automatically cuts off the stress output. The system records the time elapsed from the application of the electric field to the occurrence of insulation breakdown, which is taken as the failure time (TTF) of the unit.

[0126] For Example 4 and Comparative Example 3, multiple independent test structures were selected in different regions of the wafer to repeat the above process, and discrete electrical parameters were extracted to reflect the statistical distribution.

[0127] Experimental data: Table 4. Test data of leakage current density and breakdown failure time of the bottom insulating medium in Example 4 and Comparative Example 3.

[0128] in conclusion: According to the data in Table 4, under a high temperature of 105℃ and a test electric field of 3MV / cm, the leakage current density of the sample selected in Example 4 was maintained at 10. -10 ~10 -9 A / cm 2 The leakage current density of Comparative Example 3 is in the order of magnitude range, while the leakage current density of Comparative Example 3 is in the range of 10. -7 A / cm 2 The initial insulation performance of the two samples differs by two orders of magnitude. In a constant strong electric field stress test at 4 MV / cm, all four samples of Comparative Example 3 failed within 500s, with the shortest failure time being only 185s; the breakdown failure time of Example 4 was extended to between 16000s and 22000s, thus improving the breakdown life of the device.

[0129] Combination Figure 7 The curve trend in (a) shows that, in Comparative Example 3, the leakage current exhibits a nonlinear increase after the electric field strength exceeds 1.5 MV / cm. This is the external electrical manifestation of the ionization of the underlying metal (such as copper) under the dual stress of heat and electric field. The underlying insulation of Comparative Example 3 consists of only a single plasma-enhanced silicon oxide (PEOX). The silicon oxide film has large micropores and weak atomic network bonds, resulting in poor ability to block the electromigration of metal ions. Driven by a positive bias electric field, free metal ions drift and inject into the silicon oxide medium, forming microscopic leakage conductive paths. As the stress time increases, Figure 7(b) Comparative Example 3 shows that within a few hundred seconds, the leakage path gradually connects the bottom layer and the upper structure, forming a short circuit in the metal filament, which causes the dielectric layer to undergo a hard breakdown jump.

[0130] Example 4 employs a composite insulating substrate combining nitrogen-doped silicon carbide (NDC) and PEOX. The NDC film at the contact surface, with its highly dense amorphous structure of nitrogen atoms doped into a silicon carbide network, effectively blocks the upward diffusion path of underlying metal ions. The chemical electronegativity of nitrogen atoms passivates dangling bonds at the interface, suppressing the ionization tendency of metal atoms. Leakage current and TDDB test data validate the mechanism of this composite architecture. The 500 Å thick NDC lower film, under strong electric field and high temperature conditions, blocks the longitudinal drift of conductive ions, uniformly distributing the electric field throughout the entire composite dielectric layer. This delays the accumulation of defects and the formation of breakdown channels within the insulating layer, ensuring the electrical isolation reliability of the memory's bottom architecture throughout its entire lifespan.

[0131] Test Example 5: Experimental description: Extract the sintered target materials from Preparation Example 1 and Comparative Example 5. Several powder samples were obtained from different depths and surface areas of the target materials through mechanical micro-drilling. After weighing the same mass, they were placed in a microwave digester and completely digested using a mixed solution of nitric acid and hydrofluoric acid.

[0132] The digested solution was brought to a final volume, and the absolute mass concentration of low-melting-point volatile elements (such as selenium and tellurium) in the solution was tested using inductively coupled plasma optical emission spectrometry (ICP-OES). The macroscopic molar percentage was calculated and compared with the set initial stoichiometric ratio to calculate the element content deviation rate.

[0133] The wafer samples with metal interlayer insulating layer (OSG thin film) prepared in Preparation Example 2 and Comparative Example 6 were extracted. The capacitance of the thin film was measured at a frequency of 1 MHz using a mercury probe capacitance-voltage (CV) test system. Combined with the physical thickness of the thin film measured by ellipsometer, the relative permittivity (k value) of each sample was calculated.

[0134] The aforementioned insulating film sample was placed on a nanoindenter testing platform. A Berkovich diamond indenter was used to vertically press into the film surface at a constant strain rate. The initial slope of the load versus displacement unloading curve was recorded, and continuous stiffness data was extracted to calculate the macroscopic indentation hardness of the film.

[0135] The entire batch of wafers was placed on the table of a chemical mechanical polishing (CMP) machine, and a constant pressure of 2.5 psi was applied with a standard polishing slurry to simulate planarization for 30 seconds. After cleaning, the density of defects such as peeling, microcracks, or mechanical collapse on the surface of the dielectric film was counted using a wafer surface defect scanner (based on the principle of laser dark field scattering).

[0136] Experimental data: Table 5. Low-melting-point element ratios of the target materials in Preparation Example 1 and Comparative Example 5, and test data of the dielectric and mechanical properties of the thin films in Preparation Example 2 and Comparative Example 6.

[0137] Note: The symbol " / " indicates "not applicable" or "this test was not performed".

[0138] in conclusion: According to the data in Table 5, the four target samples extracted in Preparation Example 1 showed a maximum absolute deviation rate of only 1.2% in the molar ratio of volatile elements, maintaining a high degree of stoichiometric consistency. In Comparative Example 5, under the same sampling conditions, but with the sintering temperature set at 600℃, the test results showed that the target material exhibited elemental deficiencies ranging from 16.8% to 24.1%. Figure 8 The height difference of the strip in (a) directly reflects the influence of process parameters on the material composition. Conventional high-temperature solid-state reactions often rely on thermal activation to overcome the diffusion barrier. However, in sulfide systems containing low-melting-boiling-point elements such as selenium or tellurium, high temperature causes these elements to escape in vapor form before complete combination, leaving a large number of vacancies in the microstructure and manifesting as compositional imbalance at the macro level.

[0139] The 250–350°C warm-press solid-state molding process used in Preparation Example 1 increases the contact area between powder particles by applying high pressure simultaneously, thereby reducing the atomic diffusion activation energy. This thermomechanical coupling effect allows the powder particles to complete densification and interdiffusion within a temperature range below the elemental volatilization threshold, fundamentally blocking the loss path of volatile components and ensuring the compositional reliability of the core resistive switching stack during subsequent vapor deposition.

[0140] Based on the thin film parameters in Table 5 and Figure 8 (b) shows the bubble distribution morphology. In Comparative Example 6, the proportion of pore-forming agent in the film-forming precursor was increased to 60%. The relative permittivity of the film was indeed reduced to the range of 1.88 to 2.02, but its indentation hardness plummeted to below 0.6 GPa, and more than 160 bubbles / cm were generated in the CMP simulation test. 2 The density of defects was low. In Preparation Example 2, the proportion of the porogen was controlled within the range of 20% to 40%, resulting in a dielectric constant maintained between 2.58 and 2.72, a hardness stable at 1.38 to 1.48 GPa, and a defect density in the single digits after polishing. The purpose of introducing the porogen was to drive away organic components at high temperatures, leaving nanoscale air pores (air dielectric constant approximately equal to 1) in the matrix, thereby reducing the parasitic capacitance of the overall film.

[0141] When the proportion of pore-forming agent is too high, the originally independent closed-pore structures within the matrix interconnect, forming open macropores and a sponge-like structure. This porous network disrupts the continuous silicon-oxygen support framework, directly leading to a precipitous drop in macroscopic mechanical strength. During subsequent chemical mechanical polishing, the shear stress and downward compressive stress applied by the polishing pad exceed the yield limit of the porous film, causing large-area cracking of the pore walls and triggering overall delamination of the dielectric layer. Data from Example 2 demonstrates that the current parameter constraints can form uniformly discrete closed micropores within the material, reducing the dielectric constant to meet the requirements of RF and high-speed logic interconnects while maintaining sufficient silicon-oxygen framework density to withstand mechanical friction loads in semiconductor processes, thus balancing electrical isolation requirements and physical integration yield.

Claims

1. A storage device, characterized in that, include: Underlying metal layer (1); The bottom electrode and the intermetallic insulating layer (2) located on top of the bottom metal layer (1) are limited to a thickness of 150 to 2000 Å. A through-hole (3) is formed that penetrates the bottom electrode and the metal-insulating layer (2) and connects to the bottom metal layer (1). The columnar device structure located at the top of the insulating layer (2) between the bottom electrode and the metal layer and the through hole (3) connecting the bottom electrode and the metal layer, the columnar device structure comprising, from bottom to top: Bottom electrode (4), charge trap layer one (5), switch layer (6), charge trap layer two (7), top electrode (8) and metal interlayer insulating layer two (12) located on the top surface of the top electrode (8); The thickness of the switch layer (6) is limited to 10–500 Å; A conformal sidewall protective layer (10) is provided covering the sidewall of the columnar device structure and the top of the exposed bottom electrode and the metal-to-metal insulating layer (2), the thickness of which is limited to the range of 10 to 500 Å. Inter-device filling layer (11) that fills the gaps between adjacent columnar device structures and is located outside the sidewall protective layer (10). A metal interlayer insulating layer one (9) located on top of the inter-device filling layer (11) and part of the metal interlayer insulating layer two (12), wherein the thickness of the metal interlayer insulating layer one (9) is limited to the range of 100 to 50000 Å; Interconnect vias penetrating the first metal interlayer insulation layer (9) and the second metal interlayer insulation layer (12), and a top metal layer (13) located above the interconnect vias and connected to the exposed top electrode (8).

2. The storage device according to claim 1, characterized in that, The bottom electrode and the metal insulating layer (2) are composed of one or more of SiO2, nitrogen-doped silicon carbide, and plasma-enhanced silicon oxide; The connecting hole (3) between the bottom electrode and the metal layer includes an adhesion barrier layer and a main conductive layer. The longitudinal depth of the connecting hole (3) between the bottom electrode and the metal layer is limited to 150-2000 Å. The material is selected from one or more of the following: Ti, Hf, Ta, Ru, Ir, Pt, Zr, Al, W, Pd, Co metal materials, TiN, TaN, AlN, WN metal nitride materials with a thickness of 150-2000 Å, or TiON, TaON, AlON metal nitride materials.

3. The storage device according to claim 1, characterized in that, The thickness of the charge trap layer one (5) and the charge trap layer two (7) are both 10 to 200 Å. The materials are each independently selected from one or more of the following: GeTe, GeSb, SbTe, SnSbSe, SnSeIn, SiSnSe, InTe, SnTe, SbInTe, GeSe, GeAsTe, SiGeAsTe, SiGeAsSe, GeSbTe, GeSeSb, SnSe, GeAsSe, GeAsSb, NbOx, VOx, TiOx, GaOx, ZrOx, HfOx, HfTaO, HfZrO, HfSiO, HfAlO, or a multi-component compound formed between them. The material of the switching layer (6) is selected from one or more of GeTe, GeSb, SbTe, SnSbSe, SnSeIn, SiSnSe, InTe, SnTe, SbInTe, GeSe, GeAsTe, SiGeAsTe, SiGeAsSe, GeSbTe, GeSeSb, SnSe, GeAsSe, GeAsSb, NbOx, VOx, TiOx, GaOx, ZrOx, HfOx, HfTaO, HfZrO, HfSiO, and HfAlO, or a multi-component compound formed between them, and the thickness of the switching layer (6) is greater than the thickness of the charge trapping layer one (5) or the charge trapping layer two (7); The materials of the bottom electrode (4) and the top electrode (8) are selected from one or more of Ti, Hf, Ta, Ru, Ir, Pt, Zr, Al, W, Pd, Co, WN, TiN, TaN, AlN, TiON, TaON, and AlON.

4. The storage device according to claim 1, characterized in that, The material of the sidewall protective layer (10) is selected from one or more of HfO2, Ta2O5, SiO2, TiO2, ZrO2, Al2O3, Si3N4, and silicon oxide based on tetraethylsilane deposition; The thickness of the inter-device filling layer (11) is 10 to 10,000 Å, and the material is selected from one or more of silicon dioxide or organic silica glass based on tetraethylsilane deposition; The thickness of the second metal interlayer insulating layer (12) is 100 to 5000 Å, and the material is selected from one or more of SiON, Si3N4, and plasma-enhanced silicon oxide.

5. A fabrication process for a storage device, characterized in that, The preparation of a storage device as described in any one of claims 1-4 comprises the following steps: A bottom electrode and an intermetallic insulating layer (2) are deposited on the bottom metal layer (1), and the bottom electrode and the intermetallic insulating layer (2) are prepared by plasma-enhanced chemical vapor deposition. Through-holes are etched on the insulating layer (2) between the bottom electrode and the metal by photolithography and anisotropic plasma etching process. After depositing the material layer, the through-holes (3) connecting the bottom electrode and the metal layer are formed by grinding to flatten the material. On the top of the planarized bottom electrode and the metal interlayer insulating layer (2) and the through hole (3) connecting the bottom electrode and the metal layer, the bottom electrode (4), charge trap layer one (5), switch layer (6), charge trap layer two (7), top electrode (8) and metal interlayer insulating layer two (12) as a hard mask layer are deposited in sequence. Using the intermetallic insulating layer 2 (12) as a mask, the bottom electrode (4) is etched downwards and through it, exposing the upper surface of the bottom electrode and the intermetallic insulating layer (2), and a complete columnar device structure is formed after molding. A sidewall protective layer (10) is deposited and wrapped around the sidewall of the columnar device structure; Deposited inter-device filling layer (11); A global etching rollback process is performed to remove the inter-device filling layer (11) and part of the metal interlayer insulating layer 2 (12) at the top of the columnar device structure, exposing the upper surface of the top electrode (8), while removing the inter-device filling layer (11) and metal interlayer insulating layer 2 (12) in the non-device structure area. The interlayer insulating layer (9) is deposited to complete the basic isolation and global planarization of the interlayer metal. The surface planarization and impurity removal are completed by chemical mechanical polishing and cleaning process, and the top metal layer (13) connected to the top electrode (8) is prepared.

6. The preparation process according to claim 5, characterized in that, When depositing the bottom electrode and the metal-interlayer insulating layer (2), the thickness combination of each sublayer is adjusted according to the region. The bottom electrode and the metal-interlayer insulating layer (2) includes a lower sublayer and an upper sublayer. The lower sublayer, which is the contact area with the bottom metal layer (1), is made of nitrogen-doped silicon carbide, and the upper sublayer, which is the contact area with the bottom electrode (4), is made of plasma-enhanced silicon oxide. The total deposition thickness is controlled between 150 and 2000 Å.

7. The preparation process according to claim 5, characterized in that, When depositing the through-hole (3) connecting the bottom electrode and the metal layer, if the material is metal, chemical vapor deposition or physical vapor deposition process is used, and the vertical deposition depth is 150 to 2000 Å. If the material is a metal nitride or metal oxide, a reactive physical vapor deposition process is used, with a deposition depth of 150–2000 Å.

8. The preparation process according to claim 5, characterized in that, The deposition process for forming the columnar device structure specifically includes: A bottom electrode with a thickness of 10–1500 Å was deposited using physical vapor deposition (4). A charge trap layer with a thickness of 10–200 Å was deposited using atomic layer deposition, physical vapor deposition or plasma-enhanced chemical vapor deposition (5). A switch layer with a thickness of 10–500 Å was deposited using atomic layer deposition, physical vapor deposition or plasma-enhanced chemical vapor deposition (6). A charge trap layer 2 (7) with a thickness of 10–200 Å was deposited using atomic layer deposition, physical vapor deposition or plasma-enhanced chemical vapor deposition. A top electrode with a thickness of 10–5000 Å was deposited using physical vapor deposition (8). A metal interlayer insulating layer with a thickness of 100–5000 Å was deposited using plasma-enhanced chemical vapor deposition (PECVD) process (12).

9. The preparation process according to claim 5, characterized in that, During the etching process to form the columnar device structure, the second metal interlayer insulating layer (12) acts as a hard mask layer and serves as a grinding stop layer in the subsequent chemical mechanical polishing process.

10. The preparation process according to claim 5, characterized in that, When depositing the metal interlayer insulating layer (9), a plasma-enhanced chemical vapor deposition process is used, the deposited material is a thin film of organic silica glass, and the deposition thickness is controlled between 100 and 50,000 Å.

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