A method and system for patterning for semiconductor processes

Abstract

The application provides a patterning method for a semiconductor process, a semiconductor structure formed by the method and a patterning system. The patterning method comprises: sequentially forming a pattern target layer, a transfer layer and a photoresist layer on a bottom layer; performing photoetching on the photoresist layer to form a plurality of glue axes; performing passivation treatment on the glue axes to form a passivation layer; performing directional etching on the passivation layer to remove the top passivation layer and expose the first photoresist material between the sidewall passivation layers; removing the first photoresist material between the sidewall passivation layers; and taking the sidewall passivation layer as a mask, etching the transfer layer and the pattern target layer to transfer the pattern to the pattern target layer to form a target pattern. Therefore, on the basis of realizing the effect of the SADP technology, the process flow is greatly simplified, the cost is saved, and the efficiency is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and more particularly to a patterning method and system for semiconductor processes. Background Technology

[0002] A chip, also known as a microchip or integrated circuit (IC), is a high-tech product that integrates a large number of tiny electronic devices (such as transistors, diodes, resistors, and capacitors) onto a small piece of semiconductor material (usually silicon). Chip development began in the mid-20th century. With advancements in semiconductor technology, chip manufacturing processes have continuously evolved, from early Small Scale Integration (SSI) and Medium Scale Integration (MSI) to today's Large Scale Integration (LSI), Very Large Scale Integration (VLSI), and Ultra Large Scale Integration (ULSI). Chip manufacturing is extremely complex, involving multiple steps including design, mask fabrication, wafer fabrication, photolithography, etching, ion implantation, chemical vapor deposition, physical vapor deposition, and chemical mechanical polishing. Chip performance largely depends on its pattern size; smaller pattern sizes are advantageous for increasing transistor density, reducing power consumption, improving device performance, increasing production efficiency, and reducing production costs. Existing technologies typically utilize Self-Aligned Double Patterning (SADP) to double the feature density by forming spacers on the mandrel sidewalls, removing the mandrel via an additional etching step, and using the spacers to define the final structure. This allows for smaller pattern sizes without relying on higher resolution lithography equipment. However, SADP involves multiple thin-film deposition and etching processes, making the process complex and costly. SADP is a key technology in semiconductor manufacturing, enabling the creation of patterns exceeding the size and cycle limits of photolithography through multiple etching and deposition processes. Summary of the Invention

[0003] The following provides a brief overview of one or more aspects to offer a basic understanding of them. This overview is not an exhaustive summary of all conceived aspects, nor is it intended to identify key or decisive elements of all aspects, nor to define the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form to prepare for the more detailed descriptions that follow.

[0004] To overcome the above-mentioned shortcomings, the present invention aims to provide a patterning method and system for semiconductor processes to replace the existing SADP technology, while simplifying the process, reducing costs and improving efficiency.

[0005] According to one aspect of the present invention, a patterning method for semiconductor processes is provided.

[0006] In one embodiment, the patterning method includes: sequentially forming a pattern target layer, a transfer layer, and a photoresist layer on a substrate; performing photolithography on the photoresist layer to form a plurality of adhesive shafts; performing passivation treatment on the adhesive shafts to form a passivation layer on the surface of the adhesive shafts, wherein the passivation layer on the surface of each adhesive shaft includes a top passivation layer and a sidewall passivation layer; performing directional etching on the passivation layer to remove the top passivation layer and expose a first photoresist material between the sidewall passivation layers; removing the first photoresist material between the sidewall passivation layers to leave a sidewall passivation layer on the surface of the transfer layer; using the sidewall passivation layer as a mask, etching is performed on the transfer layer and the pattern target layer to transfer the pattern of the sidewall passivation layer to the pattern target layer to form a target pattern.

[0007] In one embodiment, the passivation treatment of the adhesive shaft is performed by: performing plasma surface hardening treatment on the adhesive shaft, so that the surface part of the adhesive shaft hardens into a passivation layer.

[0008] Furthermore, the gas used in plasma surface hardening treatment is Ar or CHF3.

[0009] In another embodiment, the passivation process for the adhesive shaft is performed by introducing a passivation gas to deposit a passivation layer on the surface of the adhesive shaft.

[0010] Furthermore, the passivation gas is a carbon-rich gas, and the passivation layer is a CF polymer.

[0011] Furthermore, the C-rich gas is C4F8 or C4F6.

[0012] In one embodiment, before directional etching of the passivation layer, the method further includes: backfilling a second photoresist material between the adhesive shafts, wherein the second photoresist material and the first photoresist material are soluble in at least one solvent; directional etching of the passivation layer further includes removing the second photoresist material extending beyond the sidewall passivation layer, wherein the solvent used in the removal step is a solvent in which both the first and second photoresist materials are soluble; and removing the first photoresist material between the sidewall passivation layers further includes removing the backfilled second photoresist material.

[0013] In one embodiment, the first photoresist material and the second photoresist material are the same; alternatively, in other embodiments, the first photoresist material and the second photoresist material are different.

[0014] In one embodiment, the first photoresist material and the second photoresist material are positive photoresists, and the solvent used in the removal step is a positive developer; in another embodiment, the first photoresist material and the second photoresist material are negative photoresists, and the solvent used in the removal step is a negative developer.

[0015] Furthermore, directional etching can be categorized as planar plasma etching, reactive ion etching, or ion beam etching.

[0016] Furthermore, the etching gas used for directional etching is one or a combination of O2, CO2, N2 or H2.

[0017] Furthermore, the bottom layer is a base layer, front layer, stop layer, or other target layer; and / or the transfer layer is one or a combination of anti-reflection layers, planarization or graphics transfer sacrifice layers, or hard mask layers.

[0018] Furthermore, this patterning method is used to form fin structures, gate structures, or metal interconnect structures for semiconductor devices.

[0019] According to another aspect of the present invention, a semiconductor structure is provided, including a substrate and a pattern located on the substrate, the pattern being formed using the patterning method of any of the foregoing embodiments.

[0020] According to another aspect of the present invention, a patterning system for semiconductor processes is also provided. The patterning system includes a photolithography apparatus and an etching apparatus, which cooperate to implement the above-described patterning method.

[0021] The present invention provides a patterning method for semiconductor processes that can obtain patterns with sizes and periods exceeding the limits of photolithography resolution by performing only one photolithography, passivation and etch-back process. While achieving the same technical effect as SADP technology, it greatly simplifies the process flow of SADP technology, saves costs and improves efficiency. Attached Figure Description

[0022] The above-described features and advantages of the present invention will be better understood after reading the detailed description of the embodiments of this disclosure in conjunction with the following accompanying drawings.

[0023] Figure 1 A schematic side cross-section of the basic semiconductor structure of existing SADP technology is shown.

[0024] Figure 2 A schematic diagram of the main processes of existing SADP technology is shown.

[0025] Figures 3A-3F The diagram shows a side cross-section of the semiconductor structure formed in several processes of the existing SADP technology.

[0026] Figure 4 A schematic flowchart of a patterning method according to a specific embodiment provided by one aspect of the present invention is shown.

[0027] Figures 5A-5F A schematic diagram of a semiconductor structure sequentially formed during a patterning process in a specific embodiment is shown.

[0028] Figure 6 A side cross-sectional schematic diagram of the adhesive shaft and passivation layer in a specific embodiment is shown.

[0029] Figure 7 A schematic flowchart of a patterning method according to another specific embodiment provided by one aspect of the present invention is shown.

[0030] Figure 8A A side cross-sectional view of the semiconductor structure formed after backfilling is shown in a specific embodiment.

[0031] Figure 8B It shows Figure 7 The semiconductor structure formed in step S72 of the corresponding embodiment.

[0032] Figures 9A-9D A schematic diagram of the semiconductor structure is shown in part of the steps in forming the fin structure in a specific embodiment.

[0033] Figure 10A-10D A schematic diagram of the semiconductor structure is shown in part of the steps of forming the gate structure in a specific embodiment.

[0034] Figure 11 A simplified schematic diagram of a patterning system according to another aspect of the present invention.

[0035] For clarity, a brief explanation of the reference numerals in the accompanying drawings is provided below:

[0036] 101. Bottom layer;

[0037] 102 Pattern target layer;

[0038] 103 Sacrificial Layer;

[0039] 104 Transfer Layer;

[0040] 105 Photoresist layer;

[0041] 103b spacer layer;

[0042] 103c Top spacer layer;

[0043] 103d sidewall spacer layer;

[0044] 201 Bottom Floor;

[0045] 202 Pattern target layer;

[0046] 203 Transfer Layer;

[0047] 204 photoresist layer;

[0048] 204a rubber shaft;

[0049] 205 Passivation layer;

[0050] 205a Top passivation layer;

[0051] 205b sidewall passivation layer;

[0052] 206 Second photoresist material;

[0053] 207 Target Pattern;

[0054] 901 bottom layer;

[0055] 902 Mask layer;

[0056] 903a Carbon coating and organic planarization layer;

[0057] 903b contains a Si anti-reflective coating;

[0058] 904 photoresist layer;

[0059] 1001 Bottom layer;

[0060] 1002 Mask layer;

[0061] 1003a Carbon coating and organic planarization layer;

[0062] 1003b contains a Si anti-reflective coating;

[0063] 1004 photoresist layer. Detailed Implementation

[0064] The following description is provided to enable those skilled in the art to implement and use the invention and adapt it to specific application contexts. Various modifications and uses in different applications will be readily apparent to those skilled in the art, and the general principles defined herein are applicable to a wide range of embodiments. Therefore, the invention is not limited to the embodiments given herein, but should be granted the broadest scope consistent with the principles and novel features disclosed herein.

[0065] In the following detailed description, numerous specific details are set forth to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that practice of the invention is not necessarily limited to these specific details. In other words, well-known structures and devices are shown in block diagram form without being depicted in detail to avoid obscuring the invention.

[0066] Readers should note all documents and references submitted concurrently with this specification and open to public inspection, the contents of which are incorporated herein by reference. Unless otherwise expressly stated, all features disclosed in this specification (including any appended claims, abstracts, and drawings) may be replaced by alternative features for the same, equivalent, or similar purposes. Therefore, unless explicitly stated otherwise, each disclosed feature is merely one example of a set of equivalent or similar features.

[0067] Note that, where used, the markings left, right, front, back, top, bottom, front, back, clockwise, and counterclockwise are merely for convenience and do not imply any specific fixed direction. In fact, they are used to reflect the relative position and / or orientation between different parts of an object. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0068] Note that, in practice, "further," "preferably," "even further," and "more preferably" are simply starting points for describing another embodiment based on the foregoing embodiments. The combination of the content following "further," "preferably," "even further," or "more preferably" with the foregoing embodiments constitutes the complete configuration of another embodiment. Any combination of several "further," "preferably," "even further," or "more preferably" settings following the same embodiment can form yet another embodiment.

[0069] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments. It should be noted that the aspects described below with reference to the accompanying drawings and specific embodiments are merely exemplary and should not be construed as limiting the scope of protection of the present invention in any way.

[0070] Figure 1 A schematic diagram of the basic semiconductor structure of existing SADP technology is shown. (Refer to...) Figure 1It can be understood that the initial object of SADP technology generally includes a bottom layer 101 and a patterned target layer 102, a sacrificial layer 103, a transfer layer 104 and a photoresist layer 105 sequentially deposited on the surface of the bottom layer 101.

[0071] Figure 2 A schematic diagram of the main processes of existing SADP technology is shown. Figures 3A-3F This diagram illustrates the semiconductor structures formed in various processes of existing SADP technology. (Combined with...) Figure 2 and Figures 3A-3F It is understood that the main process of SADP technology may include steps S21 to S26.

[0072] Specifically, such as Figure 2 As shown, step S21 involves photolithography on the photoresist layer 105 to form an initial pattern on the photoresist layer 105. (Refer to...) Figure 3A The photoresist layer 105 is etched into an initial pattern corresponding to the mandrel pattern.

[0073] Step S22 involves etching downwards using the initial pattern of the photoresist layer 105 as a mask, and transferring the initial pattern from the photoresist layer 105 to the sacrificial layer 103 via the transfer layer 104, thereby forming multiple cores in the sacrificial layer 103. (Refer to...) Figure 3B The pattern of the photoresist layer 105 is transferred to the sacrificial layer 103 by the transfer layer 104, forming multiple mandrels 103a.

[0074] Step S23 involves depositing a spacer layer 103b on the surfaces of the plurality of mandrels 103a and on the exposed portions of the patterned target layer 102. (Refer to...) Figure 3C The surface of the mandrel 103a is formed as a spacer layer 103b, which can be divided into a top spacer layer 103c and a sidewall spacer layer 103d.

[0075] Step S24 involves removing the top spacer layer 103c by directional etching, leaving the sidewall spacer layer 103d, and exposing the mandrel 103a. (Refer to...) Figure 3D The top spacer layer 103c is etched, leaving the sidewall spacer layer 103d, and the mandrel 103a is exposed.

[0076] Step S25 is: Remove the mandrel 103a, leaving the sidewall spacer layer 103d. (Refer to...) Figure 3E The mandrel 103a is removed, leaving the sidewall spacer layer 103d.

[0077] Step S26 involves etching downwards using the sidewall spacer layer 103d as a mask to form the target pattern on the target pattern layer 102. (Refer to...) Figure 3F The target pattern is formed on the target layer. (Comparison) Figure 3B and Figure 3E Assuming Figure 3B If there are N mandrels 103a, then Figure 3E There may be 2N orders of magnitude of sidewall spacers 103d, thus achieving pattern multiplication.

[0078] It is understandable that, prior to step S21, a pattern target layer 102, a sacrificial layer 103, a transfer layer 104, and a photoresist layer 105 need to be sequentially formed on the surface of the bottom layer 101. It can be observed that the formation of the mandrel requires two etching processes: first, photolithography is performed on the photoresist layer to form the initial pattern; then, the transfer layer and sacrificial layer are etched using the photoresist layer to form the mandrel. The sidewall spacer layer also requires at least one etching process, and the mandrel itself also needs to be removed. The process is complex and costly.

[0079] In the process of realizing this invention, we discovered that, under normal circumstances, photoresist can be dissolved by solvents such as propylene glycol methyl ether acetate, propylene glycol monomethyl ether, or photoresist diluents. However, after photoresist undergoes plasma treatment under certain specific conditions, a "passivation layer" of a certain thickness that is insoluble in solvents can be formed. After removing this "passivation layer," the remaining photoresist can be dissolved normally by solvents. In summary, certain solvents can be selective for photoresist that has undergone specific plasma treatment (passivation) and untreated photoresist. This application applies this characteristic to patterning, that is, after exposure and development, photoresist undergoes specific plasma treatment to form a passivation layer of a certain thickness, directional etching removes the horizontal passivation layer, and then a specific solvent is used to selectively remove the unpassivated photoresist, retaining the passivation layer on the sidewalls as a mask. In this way, fine line patterns can be multiplied in a self-aligned manner, which can serve as an alternative to traditional SADP technology. It eliminates the need for the sacrificial layer required in the SADP process, reduces the number of deposition and etching operations, simplifies the process, and reduces costs.

[0080] According to one aspect of the present invention, a patterning method for semiconductor processes is provided. Figure 4 A schematic flowchart of a patterning method for semiconductor processes is shown in a specific embodiment. Figures 5A-5F This is a side cross-sectional view of the semiconductor structures sequentially formed during the patterning process in this specific embodiment. For example... Figure 4 As shown, the patterning method may include the following steps S41 to S46.

[0081] Reference Figure 5A Step S41 is as follows: a pattern target layer 202, a transfer layer 203 and a photoresist layer 204 are sequentially formed on the bottom layer 201.

[0082] The pattern target layer 202 and the transfer layer 203 can be formed by existing or future deposition techniques, such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, electrochemical deposition, or through-silicon via (TSV) technology, which can achieve the deposition of pattern target layer material and transfer layer material. This invention does not limit the specific formation method of the two.

[0083] The photoresist layer 204 is a layered structure formed by photoresist coating. The photoresist layer 204 can be coated onto the transfer layer 203 using existing or future photoresist coating techniques such as spin coating, static coating, and dynamic spraying. This invention does not limit the specific coating method.

[0084] The transfer layer 203 is a hierarchical structure used to transfer the initial pattern etched on the photoresist layer 204 to the pattern target layer 202. The transfer layer 203 can be an anti-reflection layer, planarization layer, sacrificial layer, or hard mask layer, or a combination thereof, which are common in the art, or other existing or future material layers or combinations thereof that can realize pattern transfer.

[0085] The pattern target layer 202 is a hierarchical structure that forms a target pattern to achieve a specific circuit function. The target pattern can be a pattern of a functional component in an integrated circuit, such as a transistor, circuit, or electrode. The target pattern is usually formed on the pattern target layer 202 through photolithography or etching processes.

[0086] Specifically, the pattern target layer 202 can be a silicon wafer layer structure when forming a fin structure, and a polycrystalline silicon wafer layer structure when forming a gate structure.

[0087] The bottom layer 201 is the foundational layer structure serving as the pattern target layer 202, transfer layer 203, and photoresist layer 204. Depending on its application or the final semiconductor structure, the bottom layer 201 can be one of the commonly used base layers in existing semiconductor structures, and can be made of different materials and / or have different structures. For example, in some embodiments, the bottom layer can be a mechanically supporting layer such as an unetched silicon wafer base layer, a pre-processed front layer, a stop layer that limits the etching depth, or a remaining target layer for final pattern transfer.

[0088] Those skilled in the art will understand that step S41 is used to form an initial semiconductor structure, but in actual applications, the aforementioned formation order and process may be different depending on the application scenario, and may even cover other transitional structural layers, or the functions of multiple layers may be realized by a single actual structural layer.

[0089] Furthermore, the target pattern refers to the pattern that is expected to be drawn or formed in this process, which is usually mainly line graphics. Those skilled in the art can design it themselves according to the specific application scenario.

[0090] Reference Figure 5B Step S42 is: performing photolithography on the photoresist layer 204 to form multiple adhesive shafts 204a.

[0091] Photolithography refers to the process of selectively irradiating the photoresist in a photoresist layer with a light source of a specific wavelength, causing a change in the solubility of the photoresist, and then rinsing the photoresist with a developer to form an initial pattern in the photoresist layer.

[0092] The adhesive shaft 204a is the photoresist material remaining after photolithography of the photoresist layer. The pattern formed by these photoresist materials is the initial pattern. According to the required initial pattern, the corresponding area of ​​the photoresist layer to be irradiated can be selected during the photolithography process.

[0093] The types of light sources used in the photolithography process correspond one-to-one with the types of photoresist coated on the photoresist layer 201 in step S1. For i-line, KrF, ArF, ArFi, EUV and other photoresists, i-line, KrF, ArF, ArFi, EUV and other light sources can be used.

[0094] It should be noted that different types of light sources and photoresists correspond to the requirements of different process technologies, and those skilled in the art can choose according to the process technology being used. For example, i-line photoresist is suitable for light sources with a wavelength of 365 nanometers and is mainly used for photolithography in processes between 350 and 500 nanometers; KrF photoresist is suitable for light sources with a wavelength of 248 nanometers and is used for linewidth processes above 0.13 micrometers; ArF photoresist is suitable for light sources with a wavelength of 193 nanometers and is divided into dry and immersion types. Dry ArF photoresist is mainly used for processes between 130 and 65 nanometers, while immersion ArF photoresist is mainly used for processes between 65 and 14 nanometers; EUV photoresist is suitable for extreme ultraviolet light with a wavelength of approximately 13 nanometers and is used for advanced processes below 10 nanometers.

[0095] Reference Figure 5C Step S43 is to passivate the adhesive shaft 204a to form a passivation layer 205 on the surface of the adhesive shaft 204a.

[0096] The passivation layer 205 is insoluble in photoresist solvent and developer, and the passivation layer 205 on the surface of each photoresist axis 204a includes a top passivation layer 205a and a sidewall passivation layer 205b.

[0097] Passivation methods can include photoresist modification, passivation layer deposition, or other methods that can form a structure on the surface of the photoresist that is insoluble in photoresist solvents and developers.

[0098] Photoresist modification refers to the process of modifying the surface layer of a photoresist shaft by performing plasma surface hardening treatment, thereby transforming the photoresist material into a passivation layer of a certain thickness that is insoluble in both photoresist solvents and developers. The plasma surface hardening treatment can use argon (Ar) and trifluoromethane (CHF3), or other gases that can react with the photoresist to form insoluble materials, as the processing medium to alter the physical properties of the photoresist shaft's surface material, thus creating a passivation layer.

[0099] Those skilled in the art will understand that photoresist modification can directly form a passivation layer using the surface portion of the photoresist shaft without altering the initial pattern of the photoresist layer, and is easy to control, but will result in the loss of some photoresist.

[0100] Passivation layer deposition refers to the process of depositing an additional passivation layer on the surface of a photoresist layer by introducing a passivation gas. By depositing the passivation layer on the surface of the photoresist layer, no portion of the photoresist is sacrificed, thus ensuring the etching effect when the photoresist layer is used as a mask.

[0101] Preferably, the passivation gas can be a carbon-rich gas, and the passivation layer formed by deposition is a fluorocarbon polymer (CF polymer) similar to Teflon.

[0102] Preferably, the C-rich gas can be C4F8 or C4F6 gas.

[0103] Figure 6 The diagram shows a side cross-sectional view of a single adhesive shaft and passivation layer in this embodiment. The sidewall passivation layer 205b refers to the passivation layer formed along the sidewall of the adhesive shaft 204a, and the top passivation layer 205a refers to the passivation layer formed along the top / upper surface of the adhesive shaft 204a.

[0104] Reference Figure 5D Step S44 is to perform directional etching on the passivation layer 205 to remove the top passivation layer 205a and expose the first photoresist material between the sidewall passivation layers 205b.

[0105] It is understood that in different embodiments, the first photoresist material may correspond completely or partially to the adhesive shaft 204a. For example, in the embodiment where passivation is achieved through photoresist modification, the photoresist material on the surface of the adhesive shaft 204a forms a passivation layer, and the remaining portion of the adhesive shaft constitutes the photoresist material between the sidewall passivation layers. In the passivation layer deposition embodiment, an additional passivation layer structure is formed on the surface of the adhesive shaft 204a, so the first photoresist material may be composed of the complete adhesive shaft 204a or only part of it with its top etched. The first photoresist material is the same as the photoresist material used in the photoresist layer 204.

[0106] In some embodiments, directional etching is achieved through planar plasma etching or reactive ion etching processes. Planar plasma etching or reactive ion etching processes, while directionally removing the top passivation layer, also form a polymer film on the sidewall passivation layer, protecting the sidewall passivation layer from etching and enhancing the directionality of the etching.

[0107] Among them, reactive ion etching and planar plasma etching can use one or more of the following gases as etching gases: oxygen (O2), carbon dioxide (CO2), nitrogen (N2), hydrogen (H2), or other gases that can etch the passivation layer without affecting its normal photoresist dissolution properties.

[0108] Optionally, directional etching can also be achieved using ion beam etching. Ion beam etching has good directionality and can achieve anisotropic etching, that is, the etching direction is perpendicular to the wafer surface, ensuring accurate etching of the top passivation layer.

[0109] Those skilled in the art can choose from existing or future etching methods that can achieve directional etching according to their needs.

[0110] Reference Figure 5E Step S45: Remove the first photoresist material between the sidewall passivation layers 205b to leave the sidewall passivation layers 205b on the surface of the transfer layer 203.

[0111] Those skilled in the art can remove the first photoresist material by solvent extraction using photoresist. Since the sidewall passivation layer 205b is insoluble in the photoresist solvent, it remains on the transfer layer 203. The pattern formed by the remaining sidewall passivation layer 205b is the same as the target pattern.

[0112] Clearly, the number of patterns formed by the sidewall passivation layer 205b is twice that formed by the adhesive shaft 204a. It is understood that in some embodiments, the adhesive shaft and the formed sidewall passivation layer may experience wear.

[0113] Reference Figure 5F Step S46 is as follows: using the sidewall passivation layer 205b as a mask, etching is performed on the transfer layer 203 and the pattern target layer 202 to transfer the pattern on the sidewall passivation layer 205b to the pattern target layer 202, so as to form the target pattern 207 on the pattern target layer 202.

[0114] Using the sidewall passivation layer 205b as a mask means that in subsequent etching steps, the sidewall passivation layer 205b protects the area below it from being etched, defines the structure shape after etching, and ensures the accurate transfer of the target pattern.

[0115] The etching method for the transfer layer 203 and the pattern target layer 202 can be any existing or future etching method, such as photolithography, chemical etching, or physical etching.

[0116] To ensure that more of the sidewall passivation layer is retained, a step of backfilling photolithography material can be added between the above passivation and etching steps. Figure 7 A flowchart illustrating the patterning method in another specific embodiment is shown. Figure 7 The illustrated embodiments are relative to Figure 4 The difference in the embodiment shown is that step S71, which involves backfilling a second photoresist material after the passivation layer is formed, is added, and the subsequent etching and removal steps are adapted accordingly.

[0117] Step S71 is to backfill the second photoresist material between the passivation layers 205.

[0118] The second photoresist material used for backfilling can be dissolved in at least one solvent along with the first photoresist material. The second photoresist material and the first photoresist material can be the same type of photoresist material, or they can be different types of photoresist materials that are dissolved in the same solvent.

[0119] Preferably, the second photoresist material backfilled can be backfilled only between the sidewall passivation layers 205b, and not exceeding the top passivation layer 205a; Figure 8A A side cross-sectional view of the semiconductor structure formed after backfilling is shown in a specific embodiment, as follows: Figure 8A As shown, for ease of control, the second photoresist material 206 backfilled can also extend beyond the top passivation layer 205a and fill the space between the sidewall passivation layers 205b.

[0120] Optionally, the first and second photoresist materials can be either positive or negative photoresist. The removal step requires a solvent that can dissolve both the first and second photoresist materials. For example, for a selected positive photoresist, a positive developer can be used to remove the photoresist; for a selected negative photoresist, a negative developer can be used to remove the photoresist.

[0121] Correspondingly, step S44 can be adjusted to step S72: perform directional etching on the passivation layer 205 to remove the top passivation layer 205a and the second photoresist material 206 extending beyond the sidewall passivation layer 205b, and expose the first photoresist material between the sidewall passivation layers 205b. Figure 8B It shows Figure 7 The semiconductor structure formed in step S72 of the corresponding embodiment.

[0122] Correspondingly, step S45 can be adjusted to step S73: removing the first and second photoresist materials between the sidewall passivation layers 205b. It can be understood that the semiconductor structure formed in step S73 is as follows: Figure 5EAs shown, it will not be drawn again.

[0123] Those skilled in the art can choose existing or future directional etching methods to perform etching as needed.

[0124] The patterning method in any of the foregoing embodiments can be used to form fin structures, poly structures, metal interconnect structures, or other semiconductor structures that require pattern multiplication during semiconductor formation.

[0125] To facilitate understanding, the patterning methods for fin structures and grid structures are briefly described below with reference to specific embodiments.

[0126] Figures 9A-9D A schematic diagram of the semiconductor structure is shown in part of the steps in forming the fin structure in a specific embodiment.

[0127] Reference Figure 9A In this embodiment, a silicon substrate is used as the bottom layer 901, and a mask layer 902, a carbon coating and organic planarization layer 903a, a Si-containing anti-reflection coating 903b, and a photoresist layer 904 are deposited on the bottom layer 901. Among them, the mask layer 902 is the pattern target layer, and the carbon coating and organic planarization layer 903a and the Si-containing anti-reflection coating 903b constitute the transfer layer 903.

[0128] The patterning method described in any of the foregoing embodiments is used to sequentially form the pattern as shown in the figure. Figure 9A The sidewall passivation layer 904b is shown. Using the sidewall passivation layer 904b as a mask, the pattern of the sidewall passivation layer 904b is transferred to the mask layer 902 using the transfer layer 903 to form the target pattern 902a of the fin structure. (See reference...) Figure 9B .

[0129] In this embodiment, the bottom layer 901 is a fin structure layer, and then the bottom layer 901 is etched using the target pattern 902a formed on the mask layer 902 as a mask to form a fin structure on the bottom layer 901.

[0130] It is understandable that the fin structure may also include a cutting step, such as... Figure 9C The cutting steps shown involve cutting the mask layer after the target pattern is formed, and then directly etching the bottom layer 901 using the cut mask layer to form the desired pattern. Figure 9D The fin structure 901a is shown. In other embodiments, the bottom layer 901 may be etched first using a mask layer to form a preliminary fin structure, and then the bottom layer 901 may be cut to form the final fin structure 901a.

[0131] Figure 10A-10D A schematic diagram of the semiconductor structure is shown in part of the steps of forming the gate structure in a specific embodiment.

[0132] Reference Figure 10A In this embodiment, a polycrystalline silicon substrate is used as the bottom layer 1001. A mask layer 1002, a carbon coating and organic planarization layer 1003a, a Si-containing anti-reflective coating 1003b, and a photoresist layer 1004 are deposited on the bottom layer 1001. Among them, the mask layer 1002 is the pattern target layer, and the carbon coating and organic planarization layer 1003a and the Si-containing anti-reflective coating 1003b constitute the transfer layer 1003.

[0133] The patterning method described in any of the foregoing embodiments is used to sequentially form the pattern as shown in the figure. Figure 10A The sidewall passivation layer 1004b shown is then used as a mask. The pattern of the sidewall passivation layer 1004b is transferred to the mask layer 1002 using the transfer layer 1003 to form the target pattern 1002a of the gate structure. (See reference...) Figure 10B .

[0134] In this embodiment, the bottom layer 1001 is a gate structure layer, and then the bottom layer 1001 is etched using the target pattern 1002a formed on the mask layer 1002 as a mask to form a gate structure on the bottom layer 1001.

[0135] It is understandable that the gate structure may also include a cutting step, which can be performed on the mask layer 1002a after the target pattern is formed, such as... Figure 10C As shown, a cut mask layer 1002a is formed, and the bottom layer 1001 can be directly etched using the cut mask layer to form a shape as shown. Figure 10D The gate structure 1001a is shown. In other embodiments, the bottom layer 1001 may be etched first using a mask layer to form a preliminary gate structure, and then the bottom layer 1001 may be cut to form the final gate structure 1001a.

[0136] Although the methods described above are illustrated and depicted as a series of actions for the sake of simplicity, it should be understood and appreciated that these methods are not limited by the order of the actions, as some actions may occur in a different order and / or concurrently with other actions from the illustrations and descriptions herein or not illustrated and described herein but which may be understood by those skilled in the art, according to one or more embodiments.

[0137] According to another aspect of the invention, a semiconductor structure is also included, the structure comprising a substrate and a pattern located on the substrate, the pattern being formed using the patterning method mentioned in any of the above embodiments.

[0138] According to another aspect of the invention, a patterning system for semiconductor processes is also included, such as... Figure 11 As shown, the system may include a photolithography device 1 and an etching device 2, which work together to implement the patterning method mentioned in any of the above embodiments.

[0139] The preceding description is provided to enable any person skilled in the art to practice the various aspects described herein. However, it should be understood that the scope of protection of this invention should be determined by the appended claims and should not be limited to the specific structures and components of the embodiments described above. Various changes and modifications can be made to the embodiments by those skilled in the art within the spirit and scope of this invention, and these changes and modifications also fall within the scope of protection of this invention.

Claims

1. A patterning method for semiconductor processes, characterized in that, The patterning method includes: A pattern target layer, a transfer layer, and a photoresist layer are sequentially formed on the bottom layer. The photoresist layer is photolithographically etched to form multiple adhesive axes; The adhesive shaft is passivated to form a passivation layer on the surface of the adhesive shaft. The passivation layer on the surface of each adhesive shaft includes a top passivation layer and a sidewall passivation layer. The passivation layer is directionally etched to remove the top passivation layer and expose the first photoresist material between the sidewall passivation layers; Remove the first photoresist material between the sidewall passivation layers to leave the sidewall passivation layers on the surface of the transfer layer; Using the sidewall passivation layer as a mask, etching is performed on the transfer layer and the pattern target layer to transfer the pattern of the sidewall passivation layer to the pattern target layer to form a target pattern.

2. The patterning method according to claim 1, characterized in that, The passivation treatment of the adhesive shaft is as follows: The adhesive shaft is subjected to plasma surface hardening treatment, which hardens the surface portion of the adhesive shaft into the passivation layer.

3. The patterning method according to claim 2, characterized in that, The gas used in the plasma surface hardening treatment is Ar or CHF3.

4. The patterning method according to claim 1, characterized in that, The passivation treatment of the adhesive shaft is as follows: A passivation gas is introduced to deposit the passivation layer on the surface of the adhesive shaft.

5. The patterning method according to claim 4, characterized in that, The passivation gas is a carbon-rich gas, and the passivation layer is a CF polymer.

6. The patterning method according to claim 5, characterized in that, The C-rich gas is C4F8 or C4F6.

7. The patterning method according to any one of claims 1 to 6, characterized in that, Before performing directional etching on the passivation layer, the following steps are also included: A second photoresist material is backfilled between the adhesive shafts, and the second photoresist material and the first photoresist material are soluble in at least one solvent. The directional etching of the passivation layer further includes removing the second photoresist material extending beyond the sidewall passivation layer, wherein the solvent used in the removal step is a solvent in which both the first and second photoresist materials are soluble; and The removal of the first photoresist material between the sidewall passivation layers also includes the removal of the second photoresist material that has been backfilled.

8. The patterning method according to claim 7, characterized in that, The first photoresist material and the second photoresist material may be the same or different.

9. The patterning method according to claim 7, characterized in that, The first and second photoresist materials are positive photoresists, and the solvent used in the removal step is a positive developer; or The first photoresist material and the second photoresist material are negative photoresists, and the solvent used in the removal step is a negative developer.

10. The patterning method according to claim 1, characterized in that, The directional etching is planar plasma etching, reactive ion etching, or ion beam etching.

11. The patterning method according to claim 1, characterized in that, The etching gas used for the directional etching is one or a combination of O2, CO2, N2 or H2.

12. The patterning method according to claim 1, characterized in that, The bottom layer is a substrate, front layer, stop layer, or other target layer; and / or The transfer layer is one or a combination of more of the following: an anti-reflection layer, a planarization or pattern transfer sacrifice layer, or a hard mask layer.

13. The patterning method according to any one of claims 1 to 6 or 8 to 12, characterized in that, Fin structures, gate structures, or metal interconnect structures used to form semiconductor devices.

14. A semiconductor structure comprising a substrate and a pattern thereon, characterized in that, The pattern is formed using the patterning method described in any one of claims 1 to 13.

15. A patterning system for semiconductor processes, comprising photolithography equipment and etching equipment, characterized in that, The photolithography equipment and etching equipment work together to implement the patterning method as described in any one of claims 1 to 13.

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