Hybrid power converter, lateral device, vertical device, multiple copper clip, replicated device

Abstract

Disclosed embodiments can include systems, devices, processes, and methods for fabricating and packaging power converters on integrated circuits. In some embodiments, power converter devices can be processed and packaged using a hybrid (co-packaged) approach. A power converter includes a first integrated circuit die having a plurality of first switches and a plurality of second switches. The power converter also includes a second integrated circuit die including a controller circuit electrically coupled to control switching of the plurality of first switches and the plurality of second switches. The power converter can include an additional integrated circuit die coupled to the controller circuit. The plurality of first switches and the plurality of second switches can each include a vertical double-diffused metal oxide semiconductor field effect transistor. The plurality of first switches and the plurality of second switches can each include a lateral double-diffused metal oxide semiconductor field effect transistor.

Description

Cross-reference to related applications

[0001] This application is a continuation of U.S. Patent Application No. 18 / 489,574, filed October 18, 2023, entitled “HYBRID POWER CONVERTERS, LATERALDEVICES, VERTICAL DEVICES, MULTIPLECOPPER CLIPS, REPLICA DEVICES,” and claims priority and benefit thereto. It is also a continuation of U.S. Patent Application No. 18 / 489,623, filed October 18, 2023, entitled “HYBRID POWER CONVERTERS, LATERAL DEVICES, VERTICAL DEVICES, MULTIPLECOPPER CLIPS, REPLICA DEVICES,” and claims priority and benefit thereto, the entire U.S. patent applications being incorporated herein by reference. Technical Field

[0002] This disclosure generally relates to power converter device structures, and to semiconductor device processing and packaging for power converters. More specifically, this disclosure relates to power converters including lateral devices, vertical devices, and laterally double-diffused metal-oxide-semiconductor devices packaged using a hybrid (co-packaging) approach. Background Technology

[0003] With advancements in integrated circuit technology and computing power, the demand for integrated power conversion, regulation, and management has grown accordingly. The power management circuitry of most portable and consumer electronic devices relies on power converters, and more typically DC-DC power converters, to perform energy transfer and voltage conversion to desired voltage levels. For example, some devices may require power converters that can provide high power levels (greater than 1000 watts). Other devices may require power converters that can provide low power levels (less than 100 watts). And still others may require power converters that can provide intermediate power levels (between approximately 100 watts and approximately 1000 watts). Summary of the Invention

[0004] Embodiments of this disclosure provide co-packaged power converter devices or apparatuses. One aspect of this disclosure relates to a power converter device. The device may include a first integrated circuit die including a plurality of first switches, a plurality of second switches, a plurality of first capacitors, and a plurality of second capacitors. The device may also include a second integrated circuit die including controller circuitry coupled to the first integrated circuit die, the controller circuitry controlling the switching of the plurality of first switches and the plurality of second switches.

[0005] For example, embodiments of this disclosure may include an integrated circuit package comprising: a first integrated circuit die electrically coupled to a lead frame; wherein the first integrated circuit die includes a plurality of first switches and a plurality of second switches; wherein the plurality of first switches and the plurality of second switches are interconnected with a plurality of first capacitors to form a first switched capacitor circuit, wherein the first switched capacitor circuit is configured to transition between at least two states in response to switching of the plurality of first switches and the plurality of second switches; and a second integrated circuit die; wherein the second integrated circuit die includes a controller circuit electrically coupled to control the switching of the plurality of first switches and the plurality of second switches; and a third integrated circuit die, wherein the third integrated circuit... The integrated circuit die is electrically coupled to a lead frame; wherein the third integrated circuit die includes a plurality of third switches and a plurality of fourth switches; wherein the plurality of third switches and the plurality of fourth switches are interconnected with a plurality of second capacitors to form a second switched capacitor circuit, wherein the second switched capacitor circuit is configured to transition between at least two states in response to the switching of the plurality of third switches and the plurality of fourth switches; and wherein a controller circuit is electrically coupled to control the switching of the plurality of third switches and the plurality of fourth switches; wherein the first integrated circuit die, the second integrated circuit die, and the third integrated circuit die are co-packaged; and wherein at least one of the plurality of first switches and the plurality of second switches has a different rated current than at least one of the plurality of third switches and the plurality of fourth switches.

[0006] Embodiments of this disclosure may include a vertically double-diffused metal-oxide-semiconductor field-effect transistor (DDSMT), the DDSMT including a drift region, a source region, a drain region, and a gate region; wherein the DDSMT is isolated by an isolation trench formed around the DDSMT; wherein the isolation trench is filled with an electrically insulating material; and wherein the isolation trench extends through the bottom of the drain region.

[0007] Embodiments of this disclosure may include a laterally diffused metal-oxide-semiconductor field-effect transistor (LDMT), which includes a drift region, a source region, a drain region, a gate, and a substrate; wherein the LDMT has a through-silicon via (TSV) for forming an electrical connection from the bottom surface of the LDMT to the drain.

[0008] Additional features and advantages of the disclosed embodiments will be set forth in part in the description which follows, and in part will be apparent from the description, or may be learned by practice of the embodiments. The features and advantages of the disclosed embodiments may be realized and obtained by means of the elements and combinations set forth in the claims. Attached Figure Description

[0009] Embodiments and various aspects of this disclosure are illustrated in the following detailed description and accompanying drawings. Note that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation.

[0010] Figure 1 This is a schematic diagram of an exemplary power converter including a switched capacitor circuit and a controller circuit according to an embodiment of the present disclosure.

[0011] Figure 2 This is a schematic diagram of a monolithic power converter method.

[0012] Figure 3 This is a schematic diagram of a discrete power converter method.

[0013] Figure 4 It is a graphical representation of the cost of using a monolithic approach at various power levels, the cost of using a discrete approach at various power levels, and the cost of using a hybrid (co-packaged) approach at various power levels.

[0014] Figure 5 This is a graphical representation of the packaging cost and silicon cost for each of the monolithic, hybrid, and discrete methods at a given power level, according to embodiments of this disclosure.

[0015] Figure 6 This is a schematic plan view of a power converter device using a hybrid (co-packaged) method according to an embodiment of the present disclosure.

[0016] Figure 7 This is a schematic cross-sectional view of a power converter device using a hybrid (co-packaged) method according to an embodiment of the present disclosure.

[0017] Figure 8A Implementations of embodiments according to this disclosure are shown. Figure 15 A schematic diagram of a cross-sectional view of an integrated circuit die containing three isolated vertically diffused metal-oxide-semiconductor (VDMOS) field-effect transistor devices.

[0018] Figure 8B Implementations of embodiments according to this disclosure are shown. Figure 15 A schematic plan view of an integrated circuit die showing three isolated vertically diffused metal-oxide-semiconductor (VDMOS) field-effect transistor devices.

[0019] Figure 9 This is a plan view of an integrated circuit die that implements a replica field-effect transistor according to an embodiment of the present disclosure.

[0020] Figure 10 This is a schematic cross-sectional view of an exemplary lateral double-diffused metal-oxide-semiconductor (LDMOS) field-effect transistor device according to an embodiment of the present disclosure.

[0021] Figure 11 This is a schematic cross-sectional view of an exemplary lateral double-diffused metal-oxide-semiconductor (LDMOS) field-effect transistor device, which is converted into a vertical device by etching a silicon via from the bottom surface of the device to the drain, according to an embodiment of the present disclosure.

[0022] Figure 12A It is a method for manufacturing according to the embodiments of this disclosure. Figure 11 The flowchart describes the processing of lateral double-diffused metal-oxide-semiconductor (LDMOS).

[0023] Figure 12B This is an implementation method based on the content of this disclosure. Figure 11 The laterally diffused metal-oxide semiconductor (LDMOS) described in [the text] is in Figure 12A The diagram shows cross-sectional views of the various steps in the STL manufacturing process as outlined in the text.

[0024] Figure 13A , Figure 13B , Figure 13C and Figure 13D An embodiment of the present disclosure is shown for manufacturing Figure 11 The processing of lateral double-diffused metal-oxide semiconductor (LDMOS) described in the paper.

[0025] Figure 14 This is a schematic cross-sectional view of two isolated lateral double-diffused metal-oxide-semiconductor (LDMOS) field-effect transistor devices according to an embodiment of the present disclosure.

[0026] Figure 15 This is a schematic cross-sectional view of two exemplary vertical double-diffused metal-oxide-semiconductor (VDMOS) field-effect transistor devices according to embodiments of the present disclosure, wherein the drain regions are connected to each other.

[0027] Figure 16 This is a schematic cross-sectional view of an exemplary isolated vertical double-diffused metal-oxide-semiconductor (VDMOS) field-effect transistor device according to an embodiment of the present disclosure.

[0028] Figure 17 This is a schematic cross-sectional view of two isolated vertically diffused metal-oxide-semiconductor (VDMOS) field-effect transistor devices according to embodiments of the present disclosure. Detailed Implementation

[0029] The following disclosure provides numerous different exemplary implementations or examples for achieving various features of the provided subject matter. Simplified examples of specific components and arrangements are described below to illustrate this disclosure. Of course, these are examples and are not intended to be limiting. Additionally, reference numerals and / or letters may be repeated in the various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various implementations and / or configurations discussed.

[0030] The terms used in this specification generally have their ordinary meanings in the art and in the specific context in which each term is used. The use of examples in this specification (including examples of any terms discussed herein) is merely illustrative and in no way limits the scope and meaning of this disclosure or any of the exemplified terms. Similarly, this disclosure is not limited to the various embodiments given in this specification.

[0031] Although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. For example, without departing from the scope of the embodiments, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0032] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “below,” “above,” and “above” are used herein to describe the relationship between one element or feature and another shown in the figures. In addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and therefore the spatial relative descriptors used herein can be interpreted in the same manner.

[0033] In this disclosure, the term “coupled” may also be referred to as “electrically coupled”, and the term “connected” may be referred to as “electrically connected”. “Coupled” and “connected” may also be used to indicate that two or more elements cooperate or interact with each other or maintain electrical continuity between them.

[0034] Semiconductor packaging is widely used to protect integrated circuit (IC) chips and provide an electrical interface to external circuit systems. With increasing demand for smaller device sizes and higher power density, power module packages are being designed to be more compact, with increased circuit density. In power devices, power converters, such as charge pump converters, include switches forming a switching network and one or more capacitors to achieve power conversion and regulate output voltage or current by switching energy storage elements (e.g., capacitors and / or inductors) between different electrical configurations. These devices are processed using one of two main types of power handling.

[0035] The first approach uses a low mask count and creates a power device with split-field-effect transistors. The field-effect transistors can be vertical double-diffused metal-oxide-semiconductor (VDMOS) field-effect transistor devices or lateral double-diffused metal-oxide-semiconductor (LDMOS) field-effect transistor devices as described in this disclosure. This is known as the monolithic approach. In the monolithic approach, the field-effect transistors are not electrically isolated, and the power converter is rated for only a single rated voltage.

[0036] The second processing method uses high-mask-count bipolar / CMOS / DMOS processing and produces isolated field-effect transistors. The field-effect transistors can be vertically diffused metal-oxide-semiconductor (VDMOS) field-effect transistor devices or laterally diffused metal-oxide-semiconductor (LDMOS) field-effect transistor devices as described in this disclosure. This is referred to as the discrete approach. In the discrete approach, the field-effect transistors are isolated, and the power converter can be rated for multiple voltage ratings.

[0037] There are different trade-offs for each of these approaches. For example, in devices implementing the monolithic approach, the field-effect transistors are not isolated and therefore have only a single rated voltage. Meanwhile, the discrete approach may be more expensive because it uses a high mask count.

[0038] Ideally, there would exist a process with a low mask count that allows for the integration of multiple field-effect transistor devices with different power ratings on a single wafer. This could be achieved by using a process that requires a large number of masks and removing unused masks during that process. However, this still results in a process with a greater number of masks than the low mask count process described above.

[0039] Changing the rated voltage of a device, such as a vertical field-effect transistor (VFET), requires altering specific device parameters, presents additional challenges. For example, changing the doping level and thickness of the epitaxial wafer can alter the rated voltage. As another example, changing the implanted doping level can change the device's rated voltage. Due to the difficulty in changing the rated voltage of a given device, integrating VFETs with different rated voltages on a single substrate would be suboptimal. Furthermore, isolating these devices presents another problem, as the isolation well / region needs to be as deep as the substrate thickness.

[0040] Typically, high-efficiency power converters (e.g., charge pumps, multilevel converters, series capacitor buck converters) use power switches with different rated voltages.

[0041] The disclosed embodiments address the need for devices with reduced packaging costs and the ability to use field-effect transistors with different voltage ratings by providing a co-package of a novel lateral double-diffused metal-oxide-semiconductor (LDMOS) field-effect transistor device and a power converter controller as described in this disclosure. This is referred to as a hybrid (co-package) approach. Compared to power converters implementing a discrete approach, the hybrid (co-package) approach enables devices with a smaller footprint and higher efficiency. Another benefit of the hybrid (co-package) approach is that it enables integrated controllers. Using an integrated controller can improve the overall efficiency of the power converter by minimizing parasitics between the power switches and the controller.

[0042] Implementing the laterally diffused metal-oxide-semiconductor (LDMOS) field-effect transistor device described in this disclosure on a single wafer enables the device to have different rated voltages. The rated voltage can be adjusted by regulating the length of the drift region and the length of the channel without causing changes in the mask count. By implementing this method, the overall manufacturing cost can be reduced compared to other methods that enable devices to have different rated voltages.

[0043] The disclosed embodiments provide examples of lateral double-diffused metal-oxide-semiconductor (LDMOS) field-effect transistor device structures and methods for fabricating these structures for use in the hybrid (co-packaged) power converters described in this disclosure.

[0044] Therefore, considering the nature of the two power converter processes, it is difficult to design a power converter process, device, and package system that can have a low mask count semiconductor package while still achieving different voltage ratings and device isolation. Thus, there is a need for power converter processes, devices, and package systems, such as those described above, that achieve low-cost, low-mask semiconductor packages, where individual field-effect transistors are isolated and can have different voltage ratings.

[0045] Various non-limiting embodiments of this disclosure will be described with respect to implementations in a specific context, i.e., power converters packaged using a hybrid (co-package) approach. As used herein, the term "voltage regulator" refers to a component of a power supply unit (PSU) configured to convert an input voltage to a stable output voltage. While most voltage regulators can be used for DC-DC power conversion, some voltage regulators can also be used for AC-DC power conversion or AC-AC power conversion. Linear voltage regulators can be configured to output a lower, stable voltage signal from a higher voltage signal. In some cases, linear voltage regulators can utilize input and output capacitors or active path devices such as bipolar junction transistors (BJTs) or metal-oxide-semiconductor field-effect transistors (MOSFETs) to regulate the voltage. However, with the aid of additional external components such as inductors, capacitors, FETs, or feedback resistors, switching voltage regulators can be configured as buck converters, boost converters, or buck-boost converters.

[0046] Voltage regulators can be used as power converters. The concepts in this disclosure can be applied to voltage regulators or power converters. A power converter that converts a higher input voltage supply to a lower output voltage level can be called a buck converter because it "steps down" the input voltage. A power converter that converts a lower input voltage supply to a higher output voltage level can be called a boost converter because it "boosts up" the input voltage. Additionally, some power converters, commonly referred to as "buck-boost converters," can be configured to convert an input voltage supply to a wide range of output voltages, where the output voltage can be higher or lower than the input voltage. In various embodiments of this disclosure, the power converter can be bidirectional, depending on how the power supply is connected to the converter, whether it is a boost converter or a buck converter. In some embodiments, an AC-DC power converter can be constructed, for example, by rectifying an AC input voltage to a DC voltage and then applying the DC voltage to the DC-DC power converter.

[0047] However, the inventors have recognized that existing processing and packaging solutions for voltage regulators and / or power converters can present different trade-offs. For example, when the switch (field-effect transistor) and controller are implemented on the same integrated circuit die, the switch may not be isolated and may only have one power rating. As another example, when the switch (field-effect transistor) is implemented on a separate integrated circuit die, high mask count processing can be used, and the cost increases significantly as more switches (field-effect transistors) are added. Certain disclosed implementations address these and other challenges.

[0048] Various embodiments of this disclosure address these problems by using a hybrid (co-package) approach to process and package the voltage regulator. In this hybrid (co-package) approach, the switch (field-effect transistor) is implemented on one integrated circuit die, while the controller is implemented on another. Preferably, the switch integrated circuit die is processed using the first process described above, which is a low-mask-count process that produces split-field-effect transistors.

[0049] For medium-power applications (greater than 100 watts and less than 1000 watts), voltage regulators and power converters processed and packaged using a hybrid (co-package) approach also have lower processing and manufacturing costs. For example, for medium-power applications, the packaging cost of the hybrid (co-package) approach is lower than that of the discrete approach, and the total silicon (Si) cost is lower than that of the monolithic approach.

[0050] In some embodiments utilizing a hybrid (co-packaged) approach, the hybrid power converter may have a single field-effect transistor (FET) die and a single controller die. In yet another embodiment, the hybrid power converter may have multiple FET dies and a single controller die.

[0051] Hybrid power converters can be packaged in a variety of ways. For example, different dies can be wire-bonded to a printed circuit board (PCB) or packaged as flip chips on a leadframe. In some implementations, hybrid power converters can be coupled to each other via metal clips.

[0052] In some implementations, the hybrid power converter may have a FET die that implements a replica field-effect transistor. The replica device can be used to sense current in the main field-effect transistor (FET) device and is typically scaled to the main field-effect transistor (FET) device.

[0053] Hybrid power converters can be implemented using many different types of FET devices, including vertically diffused metal-oxide-semiconductor (VDMOS) field-effect transistor devices and laterally diffused metal-oxide-semiconductor (LDMOS) field-effect transistor devices described in this disclosure.

[0054] In various embodiments of this disclosure, devices, processes, systems, and methods for processing and packaging voltage regulators or power converters using a hybrid (co-package) approach may be disclosed. The disclosed hybrid (co-package) approach can provide a low-cost solution for medium-power level applications while providing isolated devices with multiple rated voltages. Hybrid processing and packaging methods for voltage converters or power converters may be desirable in applications including, but not limited to, portable electronic devices such as tablets, mobile phones or handheld computers, and IoT (Internet of Things) devices.

[0055] Now refer to Figure 1 . Figure 1 This is a schematic diagram of an exemplary power converter including an exemplary first switched capacitor circuit 101 in an integrated circuit package 100, according to some embodiments of this disclosure. Figure 1 As shown, the switched capacitor circuit 101 can be implemented on a first integrated circuit die. The first switched capacitor circuit 101 may be a two-phase switched capacitor power converter including a first plurality of switches M1, M2, M3, and M4 and a second plurality of switches M5, M6, M7, and M8, and a plurality of first capacitors C1, C2, and C3, but this disclosure is not limited thereto. In yet another embodiment, the switched capacitor circuit 101 may be single-phase or multi-phase, and may be designed to have more or fewer switches and / or capacitors based on the desired voltage conversion ratio.

[0056] exist Figure 1 In the example shown, the switched capacitor circuit 101 can be configured to receive energy from an input voltage source with a high input voltage and deliver that energy to an output load with a low output voltage. The controller circuit 102 can be implemented on a second integrated circuit die and operates in response to one or more I / O signals (which may be digital communication signals) to control the switched capacitor circuit 101. The controller circuit 102 may include one or more complementary metal-oxide-semiconductor field-effect transistors (MOSFETs).

[0057] The controller circuit 102 can be coupled to the switched capacitor circuit 101 and can be configured to open and close switches M1, M2, M3, M4, M5, M6, M7, and M8 to achieve the desired power conversion. In some embodiments, a 4:1 conversion ratio can be obtained. In some other embodiments, different conversion ratios (e.g., a 2:1 conversion ratio or a 3:1 conversion ratio) can be obtained by using different numbers of capacitors and different numbers of switches.

[0058] During operation, switches M1, M3, M5, and M8 (in...) Figure 1 (marked as group 1) and switches M2, M4, M6 and M7 (in) Figure 1 The switches (labeled as group 2) can be in complementary states. For example, in a first state, in response to a command from controller circuit 102, switches M1, M3, M5, and M8 can be closed, and switches M2, M4, M6, and M7 can be open. In a second switching state following the first switching state, in response to a command from controller circuit 102, switches M2, M4, M6, and M7 can be closed, and switches M1, M3, M5, and M8 can be open. Furthermore, a dead time interval can exist between the first and second states. During the dead time interval, all switches are open, ensuring a clean transition between the two states. It should be understood that this disclosure is not limited to such a ratio or type of switching circuit. In various embodiments, a descending or ascending configuration can be applied to all possible charge pump ratios.

[0059] In some embodiments, the switched capacitor circuit 101 may be a first switched capacitor circuit with a rated power between about 100 watts and about 1000 watts. The integrated circuit package 100 may be implemented using a surface mount package, a flat leadless package, a quad flat leadless package, or any other suitable package implementation.

[0060] In some embodiments, a third integrated circuit die, including a third plurality of switches and a fourth plurality of switches constituting a second switched capacitor circuit, and a plurality of second capacitors, can be coupled to a controller circuit 102. The second switched capacitor circuits can be coupled in parallel. The controller circuit 102 can control the switching of the third plurality of switches and the fourth plurality of switches in the same manner as it controls the switching of the first plurality of switches and the second plurality of switches. In this embodiment, the first plurality of switches, the second plurality of switches, the third plurality of switches, and the fourth plurality of switches can all have the same rated current, or they can all have different rated currents. Similarly, at least one of the first plurality of switches and the second plurality of switches can have a different rated current than at least one of the third plurality of switches and the fourth plurality of switches.

[0061] In other embodiments, a fourth integrated circuit die, including a fifth plurality of switches and a sixth plurality of switches constituting a third switched capacitor circuit, and a plurality of third capacitors, can be coupled to controller circuit 102. The third switched capacitor circuits can be coupled in parallel. Controller circuit 102 can control the switching of the fifth plurality of switches and the sixth plurality of switches in the same manner as it controls the switching of the first plurality of switches and the second plurality of switches. In this embodiment, the first plurality of switches, the second plurality of switches, the third plurality of switches, the fourth plurality of switches, the fifth plurality of switches, and the sixth plurality of switches can all have the same rated current, or they can all have different rated currents. Similarly, at least one of the first plurality of switches and the second plurality of switches can have a different rated current than at least one of the third plurality of switches and the fourth plurality of switches.

[0062] The controller circuit 102 is capable of controlling the switching of switches with rated currents between approximately 10 amps and approximately 40 amps. The controller circuit 102 can also be configured to control the switching of switches with rated currents less than 10 amps and greater than 40 amps, depending on the desired application.

[0063] The first, second, and third integrated circuit dies can be electrically coupled to the lead frame using wiring bonding or flip-chip bonding. The first, second, and third integrated circuit dies can be coupled to the source and drain terminals of a first set of switches, a second set of switches, a third set of switches, a fourth set of switches, a fifth set of switches, and a sixth set of switches using metal clips. The metal clips can be copper clips.

[0064] It should be understood that, depending on the power level of the application and the desired conversion ratio, switched capacitor circuits (such as...) Figure 1 The switched capacitor circuit shown may be a more expensive implementation for power converters. Due to these cost considerations, power converter designers typically rely on two different types of switched capacitor circuit implementations: monolithic circuit implementations and fully discrete circuit implementations. These implementations have specific advantages and disadvantages depending on the power level of the application and are more or less expensive depending on the desired power level.

[0065] For the purposes of this disclosure, a low power level is a power level of 100 watts or less, a medium power level is a power level of 100 watts or more but less than 1000 watts, and a high power level is a power level of 1000 watts or more. These power levels and ranges are intended to be exemplary and not limiting.

[0066] Now refer to Figure 2 , Figure 2 This is a schematic diagram of a monolithic power converter implementation (excluding passive components). For example... Figure 2 As shown, the monolithic power converter is implemented by including both a controller 201 and a switched capacitor circuit on a single die. This switched capacitor circuit is composed of a separate power MOSFET 202. Figure 2 As shown, a monolithic power converter implementation can use bump 203 and be packaged as a flip chip on a leadframe. Monolithic power converter implementations typically use laterally diffused metal-oxide-semiconductor (LDMOS) field-effect transistors (FETs).

[0067] Now refer to Figure 3 , Figure 3 This is a schematic diagram illustrating the implementation of a discrete power converter. For example... Figure 3 As shown, the discrete power converter implementation is an implementation with a separate integrated circuit die for each of power MOSFETs 302 and 303, and a separate integrated circuit die for the controller 301. Figure 3 As shown, each of the individual integrated circuit dies is connected to a printed circuit board (PCB) 304. The fully discrete power converter has an externally packaged vertically diffused metal-oxide-semiconductor (VDMOS) field-effect transistor (FET) and an external controller die.

[0068] Now refer to Figure 4 , Figure 4 This is a graphical representation 400 of the costs 402 of using the monolithic approach 412 at various power levels, the costs 414 of using the discrete approach 414 at various power levels, and the costs 416 of using the hybrid (co-package) approach 416 at various power levels. The relative costs of these implementations depend on the desired power level 404. For example, as... Figure 4 As shown, at the low power level 422, the monolithic method 412 is the cheapest, while at the high power level 426, the monolithic method 412 is the most expensive. As another example, such as... Figure 4 As shown, at low power level 422, the discrete implementation 414 is the most expensive, while at high power level 426, the discrete implementation 414 is the cheapest. Meanwhile, the hybrid (co-packaged) method 416 described below is the cheapest at medium power level 424. The hybrid power converter (also known as a co-packaged power converter) has a laterally diffused metal-oxide-semiconductor (LDMOS) field-effect transistor (FET) die and a controller die packaged together.

[0069] Now refer to Figure 5 , Figure 5This is a graphical representation 500 of the cost 502 (packaging cost and silicon cost for each of the monolithic, hybrid, and discrete methods, respectively) at a given power level according to embodiments of this disclosure. Figure 5 As shown, it illustrates the relative costs of silicon (Si) and package (PACK) for each of the monolithic, hybrid, and discrete implementations at a medium power level. The silicon cost S512 of the monolithic method 510 is more expensive than the silicon cost S532 of the discrete method 530 and the silicon cost S522 of the hybrid method 520. This is partly because creating the device in the monolithic method 510 requires a larger silicon area, as the monolithic implementation implements a laterally diffused metal-oxide-semiconductor (LDMOS) field-effect transistor (FET) die that carries current laterally rather than vertically, thus driving up the silicon cost. However, in the monolithic method 510, the package cost 514 is relatively low compared to the package cost 534 of the discrete method 530 because a single integrated circuit die is packaged.

[0070] like Figure 5 As shown, the discrete approach 530 may be more expensive overall due to the high packaging cost 534. This is because there are multiple field-effect transistor (FET) dies and controller dies, all of which are individually packaged.

[0071] like Figure 5 As shown, in the hybrid (co-packaged) method 520, since the laterally diffused metal-oxide-semiconductor (LDMOS) field-effect transistor (FET) die and the controller die are packaged together, the cost increase caused by using the laterally diffused metal-oxide-semiconductor (LDMOS) field-effect transistor (FET) die can be offset by the reduction in packaging cost 524.

[0072] Now refer to Figure 6 and Figure 7 , Figure 6 and Figure 7 This is a schematic diagram of an exemplary power converter utilizing a hybrid implementation method according to an embodiment of the present disclosure. Figure 6 A schematic plan view of a power converter device using a hybrid (co-packaged) method according to an embodiment of this disclosure is shown. Figure 6 As shown, a hybrid (co-packaged) approach realizes a single lateral double-diffused metal-oxide-semiconductor (LDMOS) field-effect transistor (FET) die comprising multiple lateral double-diffused metal-oxide-semiconductor (LDMOS) field-effect transistor (FET) switches M1 to M8 and a single controller die 14. The hybrid implementation described herein can also utilize the vertical double-diffused metal-oxide-semiconductor (VDMOS) field-effect transistor (FET) die device described in this disclosure.

[0073] In power converters using a hybrid (co-package) approach, the controller die 14 can be packaged using wiring bonding, and the laterally diffused metal-oxide-semiconductor (LDMOS) field-effect transistor (FET) die 12 can be packaged as a flip-chip component attached to a lead frame. The laterally diffused metal-oxide-semiconductor (LDMOS) field-effect transistor (FET) die 12 can also be packaged using metal clips to connect the individual FETs to each other.

[0074] Figure 7 One such implementation is shown (e.g., Quad Flat No-lead (QFN) 152). Figure 7 This is a schematic cross-sectional view of a power converter device using a hybrid (co-packaged) method according to an embodiment of this disclosure. Figure 7 As shown, the controller die 14 can be packaged using wiring bonding, and the laterally diffused metal-oxide-semiconductor (LDMOS) field-effect transistor (FET) die 12 can be packaged as a flip-chip component attached to the lead frame using bumps 154 and molding compound 151. The advantage of the wiring-bonded controller die 14 is that it reduces the overall area of ​​the controller by decreasing the distance between the pins. For example, the distance between pins in the wiring bond connection can be in the range of 10 to 20 micrometers, while the distance between pins in the lead frame 153 can be as high as and greater than 400 micrometers.

[0075] An additional advantage of the hybrid (co-package) approach is its scalability. This is because multiple field-effect transistor (FET) dies can be implemented in a power converter that implements the hybrid (co-package) approach. As an example, a power converter can implement a single lateral double-diffused metal-oxide-semiconductor (LDMOS) FET die 12 with multiple lateral double-diffused metal-oxide-semiconductor (LDMOS) FETs rated at 10 amps. A controller die 14 can be designed to handle FETs with rated currents between 10 amps and 40 amps. In the hybrid (co-package) approach, additional lateral double-diffused metal-oxide-semiconductor (LDMOS) FET dies can be added and connected in parallel to increase the total rated power of the device. Furthermore, implementing lateral double-diffused metal-oxide-semiconductor (LDMOS) FET dies on two separate silicon wafers allows the device to have scalable power levels.

[0076] Now refer to Figure 8A and Figure 8B , Figure 8A Implementations of embodiments according to this disclosure are shown. Figure 15The diagram shows a schematic cross-sectional view of an integrated circuit die 810 containing three isolated vertically diffused metal-oxide-semiconductor (VDMOS) field-effect transistor devices. Figure 8B Implementations of embodiments according to this disclosure are shown. Figure 15 A schematic plan view of an integrated circuit die 810 showing three isolated vertically diffused metal-oxide-semiconductor (VDMOS) field-effect transistor devices. Figure 8A A cross-sectional view of three isolated field-effect transistors M1, M2, and M3 on a single field-effect transistor (FET) die is shown. In the cross-sectional view, the arrows at the top of the isolated FETs M1, M2, and M3 indicate the directions of the clamps 821, 822, and 823 connecting the corresponding source and drain of the isolated FETs M1, M2, and M3, respectively.

[0077] Figure 8B A plan view of an integrated circuit die implementing three isolated field-effect transistors M1, M2, and M3 is shown. Metal clips 821, 822, and 823 are used to couple the source and drain of the isolated field-effect transistors M1, M2, and M3. Metal clips 821, 822, and 823 can be copper clips. Furthermore, Figure 8B A controller die 14 is shown, connected via wiring bonding to the outputs of isolated field-effect transistors M1, M2, and M3. The controller die 14 is also connected via wiring bonding to I / O1, I / O2, and C1K, which are inputs and / or outputs of an IC device. Although in Figure 8A and Figure 8B The diagram illustrates one approach, but the positions of the source and drain of the field-effect transistor depend on the device structure. Therefore, other implementations are possible. Furthermore, in some implementations, the integrated circuit die can be flipped, and the gate can contact a quad flat no-lead package.

[0078] Power converter applications are typically high-voltage and high-current applications, and are usually implemented in IC packages such as surface mount packages, flat leadless packages, and quad flat leadless packages.

[0079] In a typical system, power converter components implemented on a single die can be connected using wire bonding or via a flip-chip approach. Wire bonding is advantageous for some applications because it allows for a higher number of pins per area, as wire bonding connections are typically spaced 10 to 20 micrometers apart, while leadframe / flip-chip connections are typically spaced 400 micrometers apart.

[0080] However, these connection types have some drawbacks. For example, as the number of wiring bond connections increases, the overall package resistance increases significantly. Metal clips offer an alternative to wiring bonds and flip-chip connections.

[0081] Metal clips are advantageous because they reduce overall package resistance compared to wire bonding. Typically, a single metal clip can be used for a connection on a single field-effect transistor (FET) die.

[0082] However, when multiple isolated vertical devices (such as the vertically lateral double-diffused metal-oxide-semiconductor (LDMOS) and isolated vertical double-diffused metal-oxide-semiconductor (VDMOS) devices described in this disclosure) are used on a single FET die, multiple clips are required to connect the drain and source of the field-effect transistor device.

[0083] In some implementations, the metal clip is a copper clip. For example... Figure 8A and Figure 8B As shown, copper clips 821, 822, and 823 can be soldered to the source and drain terminals of isolated field-effect transistor devices M1, M2, and M3. Power converters using the above hybrid (co-package) method can utilize copper clips to connect the source and drain terminals of field-effect transistor devices on a field-effect transistor (FET) die.

[0084] Now refer to Figure 9 , Figure 9 This is a plan view of an integrated circuit die 910 implementing replicated field-effect transistors 911, 914, 915, and 917 according to embodiments of this disclosure. In certain power converter applications implemented on a field-effect transistor (FET) die, it is advantageous to sense the current through the FET. This can be accomplished by implementing a replicated FET. A replicated FET is a copy of a FET type implemented on a FET die. For example, if a FET die is implemented using a vertical LDMOS device described in this disclosure, the replicated FET will be a copy of the vertical LDMOS device to which it is connected.

[0085] Similarly, if an isolated vertically diffused metal-oxide-semiconductor (VDMOS) device described in this disclosure is used to implement a field-effect transistor (FET) die, the replicated FET will be a replica of the isolated vertically diffused metal-oxide-semiconductor (VDMOS) device to which it is connected.

[0086] These replicated field-effect transistors (FETs) are added to the primary field-effect transistor (FET) device.

[0087] like Figure 9As shown, the source and drain of the replica field-effect transistor (FET) (e.g., replica FETs 911, 914, 915, 917) are electrically coupled to the source and drain of the master field-effect transistor (FET) (e.g., the master FET associated with M1, M4, M5, M7). In some embodiments, the replica field-effect transistor (FET) is smaller than the master field-effect transistor (FET) device. In other embodiments, the size of the replica field-effect transistor (FET) is proportional to the size of the master field-effect transistor (FET) device. In some embodiments, the master FET devices (e.g., a first plurality of switches, a second plurality of switches, etc.) may be of different sizes.

[0088] In some implementations, the replica field-effect transistor (FET) can be used to measure the current through the primary FET device. In other implementations, the replica FET can be used to detect faults in the primary FET device.

[0089] In yet another embodiment, multiple replica field-effect transistors (FETs) may exist on a single field-effect transistor (FET) die. Similarly, in some embodiments, multiple replica field-effect transistors (FETs) may exist on different field-effect transistor (FET) dies.

[0090] like Figure 9 As shown, each of the field-effect transistor (FET) switches M1, M4, M5, and M7 has a replica field-effect transistor (FET). As shown, the replica field-effect transistor (FET) is coupled to the source and drain of the master field-effect transistor (FET) device.

[0091] In some implementations, a power converter implementing a hybrid (co-packaged) approach may utilize a single replicated field-effect transistor (FET) on a single field-effect transistor (FET) die, or may utilize multiple replicated field-effect transistors (FETs) on a single field-effect transistor (FET) die. In other implementations, a power converter implementing a hybrid (co-packaged) approach may utilize multiple replicated devices on multiple field-effect transistor (FET) dies.

[0092] A power converter implementing the hybrid (co-packaged) method described above can be implemented using multiple different field-effect transistor (FET) devices with different structures. In this disclosure, for example in... Figures 10 to 17 The document provides detailed examples of the types of field-effect transistor structures that can be used.

[0093] For example, a power converter implementing a hybrid (co-packaged) approach can be implemented using a vertical field-effect transistor (FET) device. In some embodiments, the power converter can be implemented using, for example, the devices described in this disclosure. Figures 15 to 17 The isolated vertically diffused metal-oxide-semiconductor (VDMOS) device is used to implement the hybrid power converter. In other embodiments, the devices described in this disclosure, such as those described herein, can be utilized. Figures 10 to 14 Vertical and horizontal double-diffused metal-oxide-semiconductor (LDMOS) devices are used to realize hybrid power converters.

[0094] Figure 10 This is a schematic cross-sectional view 1001 of an exemplary lateral double-diffused metal-oxide-semiconductor (LDMOS) field-effect transistor device according to an embodiment of the present disclosure. The lateral double-diffused metal-oxide-semiconductor (LDMOS) has a source (S), a drain (D), a gate (G), and a drift region (N). - DRIFT, in which the source (S), gate (G), and drain (D) are all on the top surface of the device. For example... Figure 10 As shown in the exemplary LDMOS field-effect transistor device, the source region can be p+ type, the drain region can be n+ type, and the drift region can be n- type (PMOS device). In other embodiments, the source region can be n+ type, the drain region can be p+ type, and the drift region can be p- type (NMOS device). Laterally diffused metal-oxide-semiconductor (LDMOS) devices typically have lower wiring losses than vertically diffused metal-oxide-semiconductor (VDMOS) devices. Therefore, it would be beneficial to create devices that have the advantages of laterally diffused metal-oxide-semiconductor (LDMOS) devices (i.e., lower wiring losses) and achieve a vertically stacked vertical device structure. By applying single-layer transfer (SLT) to the laterally diffused metal-oxide-semiconductor (LDMOS) device, the laterally diffused metal-oxide-semiconductor (LDMOS) can be made vertical.

[0095] Figure 11 This is a schematic cross-sectional view of an exemplary lateral double-diffused metal-oxide-semiconductor (LDMOS) field-effect transistor device converted into a vertical device by etching a silicon via 1 from the bottom surface of the device to the drain D using single-layer transfer (SLT). As... Figure 11 As shown, the source region can be p+ type, the drain region can be n+ type, and the drift region can be n- type (PMOS device). In some embodiments, the source region can be n+ type, the drain region can be p+ type, and the drift region can be p- type (NMOS device). Etching the silicon via 1 allows connection through the bottom surface of the device to the drain D of the laterally diffused metal-oxide-semiconductor (LDMOS).

[0096] Figure 12A An embodiment of the present disclosure is shown for manufacturing Figure 11 The flowchart 1200A describes the processing of a lateral double-diffused metal-oxide-semiconductor (LDMOS). Figure 12B The embodiments according to this disclosure are shown. Figure 11 The laterally diffused metal-oxide semiconductor (LDMOS) described in [the text] is in Figure 12A The diagram above shows cross-sectional views of the various steps in the STL manufacturing process. (Implementation) Figure 11 One of the several ways to structure a laterally diffused metal-oxide-semiconductor (LDMOS) device as shown may include a single-layer transfer (SLT) fabrication technique, which, for simplicity, only shows the active region. SLT fabrication may include a bonding process to form a device or structure, such as those used in switched-capacitor power converters. It should be understood that steps may be added, removed, reordered, replaced, or modified as needed to form a structure with desired physical and electrical characteristics based on the application and desired product characteristics. The disclosed embodiments illustrate that SLT technology can be used to fabricate power converters. SLT technology can be understood as limited to bonding layers using a “sacrificial” or “dumb” substrate. However, the disclosed embodiments recognize that, for example, in addition to providing overall structural support, SLT technology can also be used to bond substrates comprising one or more passive devices such as capacitors and inductors, rather than simply providing a sacrificial or dumb substrate.

[0097] Reference Figure 12A and Figure 12B The SLT process consists of eight main steps and enables access to the source or drain terminals of a laterally diffused metal-oxide-semiconductor (LDMOS) on the top or bottom surface of the device. Step 1201 involves processing the wafer. At step 1202, a processed wafer (also known as a temporary wafer) is attached to the top surface of the device, and the device is flipped so that the substrate is on top. At step 1203, the substrate is back-ground downwards to be sufficiently close to the drift region. In some embodiments, the substrate is back-ground to a minimum depth of 50 micrometers. In some embodiments, the substrate is back-ground to a depth greater than 50 micrometers. At step 1204, through-silicon vias (TSVs) can be etched through the device to the drain or source region (e.g., an integrated circuit die may include TSVs configured to form electrical connections to drain or source terminals of a plurality of first switches, a plurality of second switches, etc.).

[0098] TSVs can be formed using techniques such as deep reactive ion etching, isotropic radial etching, reactive ion beam etching, ion milling, ion beam-assisted etching, or sputtering etching. The resulting devices offer the advantages of lateral devices (e.g., lower wiring losses) but also realize the advantages associated with vertical device structures (e.g., vertical stacking of multiple devices, vertical stacking of integrated circuit dies, etc.). The resulting devices can be implemented on integrated circuit dies as switches, for example, in switched capacitor circuits.

[0099] In step 1205, after forming the through-silicon via (TSV), the wafer can be diced, and in step 1206, the diced wafer can be mounted onto the lead frame. In step 1207, the processed wafer can be removed, and in step 1208, copper clips can be installed to connect the source and drain.

[0100] Reference Figure 12B As shown above Figure 12A The SLT process may include the following steps. Step 1201 of the SLT process involves processing the wafer. At step 1202, a processed wafer 1222 (also known as a temporary wafer) may be attached to the top surface of the device, and the device may be flipped so that the substrate is on top. The device may include back-end process (BEOL) 1224, BEOL 1226, LDMOS1 front-end process (FEOL) 1234, and LDMOS2 FEOL 1236.

[0101] At step 1203, the substrate can be back-ground downwards to a depth sufficiently close to the drift region. In some embodiments, the substrate is back-ground to a minimum depth of 50 micrometers. In some embodiments, the substrate can be back-ground to a depth greater than 50 micrometers. At step 1204, through-silicon vias (TSVs) 1214 and 1216 can be etched through the device to the drain or source. At step 1205, after forming the TSVs, the wafer can be diced. At step 1206, the diced wafer can be mounted onto the lead frame 1242. At step 1207, the processed wafer 1222 can be removed. At step 1208, copper clips can be installed to connect the source and drain.

[0102] Figures 13A to 13D An embodiment of the present disclosure is shown for manufacturing Figure 11 The processing of lateral double-diffused metal-oxide semiconductor (LDMOS) described in the paper.

[0103] like Figure 13AAs shown, a temporary wafer 1302 can be added to an extended drain metal-oxide-semiconductor (EDMOS) device. The temporary wafer 1302 can be bonded to an insulating layer 1364 (e.g., oxide) on the device surface via an adhesion layer 1362 (e.g., bonding oxide). In another embodiment, the temporary wafer 1302 can be bonded to the device surface using polymer bonding (e.g., benzocyclobutene (BCB)). In some embodiments, the insulating layer 1364 can be planarized to achieve bonding.

[0104] like Figure 13B As shown, the EDMOS device is then flipped. After flipping the EDMOS device, the substrate 1304 can be back-ground downwards to a depth sufficiently close to the drift region. In some embodiments, the substrate 1304 is back-ground to a minimum depth of 50 micrometers. In some embodiments, the substrate 1304 can be back-ground to a depth greater than 50 micrometers. A trench or end connection 1306 can then be etched through the device to the drain or source region 1308 to create a drain connection or source connection. The trench or end connection can be formed by, for example, deep reactive ion etching, isotropic radial etching, reactive ion beam etching, ion milling, ion beam assisted etching, or sputtering etching. A conductive material such as tungsten or copper can then be used to complete the connection to the source or drain region and to perform wiring throughout the device.

[0105] like Figure 13C As shown, the EDMOS device is flipped back to its original state, with the source 1322, gate 1324, and drain 1326 on the top surface of the device. A redistribution layer (RDL) 1310 is then bonded to the top layer. A hybrid bonding process can be used to bond the RDL 1310 to the top surface of the EDMOS device. The RDL 1310 includes a built-in metal layer to enable connections to the drain region 1308. The RDL 1310 can be made of a highly conductive material such as copper or aluminum.

[0106] In some embodiments, layer 1368 may be over RDL 1310 and bonded to substrate 1304 via bonding 1366. In some embodiments, layer 1368 may be a polyimide layer. In some embodiments, polyimide layer 1368 may help isolate RDL 1310 and substrate 1304 and may enable or facilitate bonding. Without polyimide layer 1368, conduction may occur between RDL 1310 and substrate 1304 at undesirable locations. In some embodiments, layer 1368 may be an oxide layer.

[0107] like Figure 13CAs shown, a support wafer 1330 is also added to the EDMOS device. The support wafer 1330 can be made of, for example, silicon or glass, a high heat dissipation material, or some other high insulating material.

[0108] like Figure 13D As shown, temporary wafer 1302 is removed. Temporary wafer 1302 can be removed by using a blade or by detaching it from the substrate. Once temporary wafer 1302 is removed, source connection portion 1342, gate connection portion 1344, and drain connection portion 1346 are formed on the top surface of the wafer, respectively. Figure 13D As shown, the drain connection 1346 passes through RDL 1310.

[0109] In yet another implementation, it may not include Figure 13C and Figure 13D The support wafer 1330 is shown, and the RDL 1310 can be made thicker. In this embodiment, the RDL 1310 can be, for example, thicker than 100 micrometers. This enables a connection through the bottom of the EDMOS device to the drain 1326.

[0110] In this embodiment, the device can be coupled to other EDMOS devices via a single metal layer on the top surface and a thick single metal layer on the bottom surface. This is advantageous, particularly in low-voltage devices, due to the reduced overall wiring resistance. In prior art low-voltage devices, using interleaved connections only on the top surface leads to performance problems because the overall wiring resistance is high due to the interleaved connections. By using thick single metal layers on both the top and bottom surfaces of the EDMOS device, the wiring resistance is reduced, thus improving performance at low voltages. This solution also allows for the use of smaller MOS devices due to the significantly lower overall wiring resistance.

[0111] Figure 14 This is a schematic cross-sectional view of two isolated laterally diffused metal-oxide-semiconductor (LDMOS) field-effect transistor devices 1410 and 1420 according to an embodiment of the present disclosure. Both LDMOS field-effect transistor devices 1410 and 1420 have TSVs 1411 and 1421 etched therein, respectively. Because TSVs 1411 and 1421 separate device 1 1410 and device 2 1420, these devices are considered isolated. In some embodiments, these devices may be stacked vertically on top of each other (e.g., vertical stacking of integrated circuit dies, etc.).

[0112] The drift region N can be adjusted. -The lengths of DRIFT 1418 and 1428, as well as the amount of doping, are used to change the rated voltage of a lateral double-diffused metal-oxide-semiconductor (LDMOS) field-effect transistor device. Therefore, multiple devices with different rated voltages can be mounted on the same die.

[0113] Figure 15 This is a schematic cross-sectional view of two exemplary vertically double-diffused metal-oxide-semiconductor (VDMOS) field-effect transistor devices according to embodiments of the present disclosure, wherein the drain regions 1516 are connected to each other. Figure 15 As shown, a vertically double-diffused metal-oxide-semiconductor (VDMOS) field-effect transistor device may have a source 1512, a drain 1516, a gate 1514, and a drift region 1518, wherein the source region 1512 and the drain region 1516 may be located on opposite sides of the device. The source region may be p+ type, the drain region may be n+ type, and the drift region may be n- type. In some embodiments, the source region may be n+ type, the drain region may be p+ type, and the drift region may be p- type.

[0114] The source region can be on the top surface of the device, and the drain region can be on the bottom surface, such as... Figure 15 As shown. In some embodiments, the drain region can be on the top surface of the device, and the source region can be on the bottom surface.

[0115] When multiple vertically double-diffused metal-oxide-semiconductor (VDMOS) field-effect transistors are implemented on a single die, the drain regions are interconnected, such as... Figure 15 As shown. Therefore, when implementing multiple vertical double-diffused metal-oxide-semiconductor (VDMOS) field-effect transistor devices on a single die, isolation is required to prevent the drain regions from connecting to each other and to enable the devices to have different rated voltages.

[0116] To isolate multiple vertically double-diffused metal-oxide-semiconductor (VDMOS) field-effect transistors on a single die, it is always necessary to form deep trenches around the VDMOS field-effect transistors and fill them with an insulating material.

[0117] Figure 16 This is a schematic cross-sectional view of an exemplary isolated vertical double-diffused metal-oxide-semiconductor (VDMOS) field-effect transistor device according to an embodiment of the present disclosure.

[0118] Figure 16Two vertically double-diffused metal-oxide-semiconductor (VDMOS) field-effect transistor (FET) devices 16M1 and 16M2 are shown. As illustrated, the VDMOS FET devices 16M1 and 16M2 are isolated from each other by a deep trench 1612 filled with an insulating material. The isolation trench 1612 can be formed by dry etching of the wafer. The isolation trench can be formed using, for example, deep reactive ion etching, isotropic radial etching, reactive ion beam etching, ion milling, ion beam-assisted etching, or sputtering etching. In some embodiments, the isolation trench 1612 can be formed by doping the region between the VDMOS FET devices 16M1 and 16M2 (e.g., an integrated circuit die may include an isolation trench configured to electrically isolate a plurality of first switches and a plurality of second switches from each other, etc.).

[0119] The N+ (PMOS) or P+ (NMOS) substrate 1610 (e.g., an integrated circuit die) can be back-ground until the isolation trench 1612 extends through the bottom of the drain. After back-grounding the substrate 1610, the isolation trench 1612 can be filled with an electrical isolation material. The electrical isolation material can be, for example, silicon or silicon dioxide.

[0120] The resulting device enables the realization of multiple vertically double-diffused metal-oxide-semiconductor (VDMOS) field-effect transistors on a single die. Due to the vertical structure, the resulting devices can also be stacked vertically.

[0121] Figure 17 This is a schematic cross-sectional view of isolated vertically diffused metal-oxide-semiconductor (VDMOS) field-effect transistor devices 1710 and 1720 according to embodiments of the present disclosure. Figure 17 As shown, the drain regions 1711 and 1721 of the two devices 1710 and 1720 are isolated from each other (e.g., by insulating material 1730). In some embodiments, the two isolated devices 1710 and 1720 may have the same rated voltage. In some embodiments, the two isolated devices 1710 and 1720 may have different rated voltages.

[0122] In some embodiments, a hybrid power converter utilizing isolated vertically diffused metal-oxide-semiconductor (VDMOS) and vertically laterally diffused metal-oxide-semiconductor (LDMOS) devices can use metal clips to couple the source and drain of the devices. In some embodiments, the metal clips can be copper clips.

[0123] In some implementations, a hybrid power converter utilizing isolated vertically diffused metal-oxide-semiconductor (VDMOS) and vertically and laterally diffused metal-oxide-semiconductor (LDMOS) devices can have corresponding replica devices, as described above.

[0124] In some implementations, the hybrid power converter may utilize a replicating device to sense current. In some implementations, the hybrid power converter may utilize a replicating device to detect faults.

[0125] It should be understood that certain features of this specification described in the context of separate embodiments for clarity may also be provided in combination in a single embodiment. Conversely, various features of this specification described in the context of a single embodiment for brevity may also be provided individually or in any suitable sub-combination or as suitably as in any other embodiment described in this specification. Certain features described in the context of various embodiments are not considered essential features of those embodiments unless the embodiment would be inoperable without these elements.

[0126] The implementation method may be further described using the following terms: 1. An apparatus comprising: Integrated circuit package, the integrated circuit package comprising: A first integrated circuit die, the first integrated circuit die being electrically coupled to a lead frame; The first integrated circuit die includes a plurality of first switches and a plurality of second switches; The plurality of first switches and the plurality of second switches are interconnected with a plurality of first capacitors to form a first switched capacitor circuit, wherein the first switched capacitor circuit is configured to transition between at least two states in response to switching of the plurality of first switches and the plurality of second switches; and Second integrated circuit die; The second integrated circuit die includes a controller circuit electrically coupled to control the switching of the plurality of first switches and the plurality of second switches; and A third integrated circuit die, wherein the third integrated circuit die is electrically coupled to the lead frame; The third integrated circuit die includes multiple third switches and multiple fourth switches; The plurality of third switches and the plurality of fourth switches are interconnected with a plurality of second capacitors to form a second switched capacitor circuit, wherein the second switched capacitor circuit is configured to switch between at least two states in response to the switching of the plurality of third switches and the plurality of fourth switches; and The controller circuit is electrically coupled to control the switching of the plurality of third switches and the plurality of fourth switches; The first integrated circuit die, the second integrated circuit die, and the third integrated circuit die are co-packaged; and Wherein, at least one of the plurality of first switches and the plurality of second switches has a rated current different from that of at least one of the plurality of third switches and the plurality of fourth switches. 2. The apparatus according to Clause 1, wherein the first switched capacitor circuit has a rated power of about 100 watts to about 1000 watts. 3. The apparatus according to Clause 1, wherein the integrated circuit package is a surface mount package. 4. The apparatus according to Clause 3, wherein the integrated circuit package is a flat, leadless package. 5. The apparatus according to Clause 4, wherein the integrated circuit package is a quad flat no-lead package. 6. The apparatus according to Clause 1, wherein the controller circuitry comprises one or more complementary metal-oxide-semiconductor field-effect transistors. 7. The apparatus according to Clause 1, wherein each of the plurality of first switches and the plurality of second switches comprises one or more double-diffused metal-oxide-semiconductor field-effect transistors. 8. The apparatus according to Clause 1, wherein the controller circuit is configured to control the switching of a switch with a rated current between about 10 amperes and about 40 amperes. 9. The apparatus according to Clause 1, wherein the first integrated circuit die includes a first replication switch, wherein at least two terminals of the first replication switch are electrically connected to at least two corresponding terminals of one of the plurality of first switches or the plurality of second switches. 10. The apparatus according to Clause 9, wherein the size of the first copying switch is smaller than the size of the one switch, and the terminals of the first copying switch are electrically connected to the one switch. 11. The apparatus according to Clause 9, wherein the first copy switch is configured to sense current flowing through the one of the switches to which its terminals are electrically connected. 12. The apparatus according to Clause 9, wherein the first copy switch is configured to detect a fault associated with the one switch to which its terminals are electrically connected. 13. The apparatus according to Clause 9, wherein the first integrated circuit die includes a second replication switch, wherein at least two terminals of the second replication switch are electrically connected to at least two corresponding terminals of the plurality of first switches or another switch among the plurality of second switches; Wherein, the one switch and the other switch have different sizes; and The dimensions of the first copy switch and the second copy switch are proportional to the dimensions of the first switch and the other switch, respectively. 14. The apparatus according to Clause 13, wherein the second copy switch is smaller than the other switch, and the terminals of the second copy switch are electrically connected to the other switch. 15. The apparatus according to Clause 13, wherein the second copy switch is configured to sense current flowing through the other switch to which its terminals are electrically connected. 16. The apparatus according to Clause 13, wherein the second copy switch is configured to detect a fault associated with the other switch to which its terminals are electrically connected. 17. The apparatus according to Clause 1, wherein the first integrated circuit die is electrically coupled to the lead frame using wiring bonding. 18. The apparatus according to Clause 1, wherein the second integrated circuit die is electrically coupled to the lead frame using flip-chip bonding. 19. The apparatus according to Clause 1, wherein each of the plurality of first switches and the plurality of second switches comprises one or more laterally double-diffused metal-oxide-semiconductor field-effect transistors. 20. The apparatus according to Clause 19, wherein the first integrated circuit die includes a through-silicon via (TSV) configured to form an electrical connection to the drain or source terminals of the plurality of first switches or the plurality of second switches. 21. The apparatus according to Clause 20, wherein the through-silicon via is fabricated using a single transfer layer process. 22. The apparatus according to Clause 19, further comprising: A fourth integrated circuit die, which is electrically coupled to the lead frame; The fourth integrated circuit die includes multiple fifth switches and multiple sixth switches; The plurality of fifth switches and the plurality of sixth switches are interconnected with a plurality of third capacitors to form a third switched capacitor circuit, wherein the third switched capacitor circuit is configured to switch between at least two states in response to the switching of the plurality of fifth switches and the plurality of sixth switches; and The controller circuit is electrically coupled to control the switching of the plurality of fifth switches and the plurality of sixth switches; and The first integrated circuit die and the fourth integrated circuit die are stacked vertically. 23. The apparatus according to Clause 19, wherein the first integrated circuit die includes a plurality of metal clips coupled between at least two pairs of source terminals and drain terminals of the plurality of first switches or the plurality of second switches. 24. The apparatus according to Clause 23, wherein the metal clip is a copper clip welded to the source terminal and the drain terminal. 25. The apparatus according to Clause 1, wherein each of the plurality of first switches and the plurality of second switches comprises one or more vertically double-diffused metal-oxide-semiconductor field-effect transistors. 26. The apparatus of claim 25, wherein the first integrated circuit die includes a plurality of isolation trenches configured to electrically isolate the plurality of first switches and the plurality of second switches from each other. 27. The apparatus according to Clause 26, wherein the plurality of isolation trenches are formed using deep reactive ion etching. 28. The apparatus according to Clause 26, wherein an insulating layer is deposited in the plurality of isolation trenches. 29. The apparatus according to Clause 26, wherein the substrate of the first integrated circuit die is ground to reduce its thickness compared to the wafer from which the first integrated circuit die is formed. 30. The apparatus according to Clause 25, wherein the first integrated circuit die includes a plurality of metal clips coupled between at least two pairs of source terminals and drain terminals of the plurality of first switches or the plurality of second switches. 31. The apparatus according to Clause 30, wherein the metal clip is a copper clip welded to the source terminal and the drain terminal. 32. The apparatus according to Clause 1, wherein the plurality of first switches and the plurality of second switches are laterally double-diffused metal-oxide-semiconductor devices. 33. An apparatus comprising: A vertically double-diffused metal-oxide-semiconductor field-effect transistor, the vertically double-diffused metal-oxide-semiconductor field-effect transistor comprising a drift region, a source region, a drain region, and a gate; The vertically double-diffused metal-oxide-semiconductor field-effect transistor is isolated by an isolation trench formed around it. The isolation trench is filled with an electrical isolation material; and The isolation trench passes through the bottom of the drain electrode. 34. The apparatus according to Clause 33, wherein the drift region is n-type, the source region is p-type, and the drain is n+ type. 35. The apparatus according to Clause 33, wherein the electrically insulating material filling the isolation trench is silicon. 36. The apparatus according to Clause 33, wherein the electrically insulating material filling the isolation trench is silicon dioxide. 37. The apparatus according to Clause 33, wherein the isolation trench is formed using deep reactive ion etching. 38. The apparatus according to Clause 33, wherein the isolation trench is formed using isotropic radial etching. 39. The apparatus according to Clause 33, wherein the isolation trench is formed using reactive ion beam etching. 40. The apparatus according to Clause 33, wherein the isolation trench is formed using ion milling. 41. The apparatus according to Clause 33, wherein the isolation trench is formed using ion beam-assisted etching. 42. The apparatus according to Clause 33, wherein the isolation trench is formed using sputter etching. 43. The apparatus according to Clause 33, wherein the drain is on the top surface of the vertical double-diffused metal-oxide-semiconductor field-effect transistor and the source is on the bottom surface of the vertical double-diffused metal-oxide-semiconductor field-effect transistor. 44. The apparatus according to clause 33 further includes: Integrated circuit package, the integrated circuit package comprising: A first integrated circuit die, the first integrated circuit die being electrically coupled to a lead frame; The first integrated circuit die includes a plurality of first switches and a plurality of second switches; The plurality of first switches and the plurality of second switches are interconnected with a plurality of first capacitors to form a first switched capacitor circuit, wherein the first switched capacitor circuit transitions between at least two states in response to switching of the plurality of first switches and the plurality of second switches; and Each of the plurality of first switches and the plurality of second switches includes one or more of the vertically double-diffused metal-oxide-semiconductor field-effect transistors, wherein the vertically double-diffused metal-oxide-semiconductor field-effect transistors are electrically isolated from each other through the isolation trench. 45. The apparatus according to Clause 44, wherein the first switched capacitor circuit has a power rating of about 100 watts to about 1000 watts. 46. ​​The apparatus according to Clause 44, wherein the integrated circuit package is a surface mount package. 47. The apparatus according to Clause 46, wherein the integrated circuit package is a flat, leadless package. 48. The apparatus according to Clause 47, wherein the integrated circuit package is a quad flat no-lead package. 49. The apparatus according to Clause 44, wherein the first integrated circuit die includes a first replication switch, wherein at least two terminals of the first replication switch are electrically connected to at least two corresponding terminals of one of the plurality of first switches or the plurality of second switches. 50. The apparatus according to Clause 49, wherein the size of the first copying switch is smaller than the size of the one switch, and the terminals of the first copying switch are electrically connected to the one switch. 51. The apparatus according to Clause 49, wherein the first copy switch senses the current flowing through the one switch, and the terminals of the first copy switch are electrically connected to the one switch. 52. The apparatus according to Clause 49, wherein the first copy switch detects a fault associated with the one switch, and the terminals of the first copy switch are electrically connected to the one switch. 53. The apparatus according to Clause 49, wherein the first integrated circuit die includes a second replication switch, wherein at least two terminals of the second replication switch are electrically connected to at least two corresponding terminals of the plurality of first switches or another switch among the plurality of second switches; Wherein, the one switch and the other switch have different sizes; and The dimensions of the first copy switch and the second copy switch are proportional to the dimensions of the first switch and the other switch, respectively. 54. The apparatus according to Clause 53, wherein the second copy switch is smaller than the other switch, and the terminals of the second copy switch are electrically connected to the other switch. 55. The apparatus according to Clause 53, wherein the second copy switch senses the current flowing through the other switch, and the terminals of the second copy switch are electrically connected to the other switch. 56. The apparatus according to Clause 53, wherein the second copy switch detects a fault associated with the other switch, and the terminals of the second copy switch are electrically connected to the other switch. 57. The apparatus according to Clause 44, wherein the first integrated circuit die is electrically coupled to the lead frame using flip-chip bonding. 58. The apparatus according to clause 33 further includes: A second integrated circuit die, the second integrated circuit die being electrically coupled to the lead frame; The second integrated circuit die includes multiple third switches and multiple fourth switches; The plurality of third switches and the plurality of fourth switches are interconnected with a plurality of second capacitors to form a second switched capacitor circuit, wherein the second switched capacitor circuit transitions between at least two states in response to switching of the plurality of third switches and the plurality of fourth switches; and Each of the plurality of third switches and the plurality of fourth switches includes one or more of the vertically double-diffused metal-oxide-semiconductor field-effect transistors, wherein the vertically double-diffused metal-oxide-semiconductor field-effect transistors are electrically isolated from each other through the isolation trench. 59. The apparatus according to Clause 58, wherein at least one of the plurality of first switches and the plurality of second switches has a rated current different from that of at least one of the plurality of third switches and the plurality of fourth switches. 60. The apparatus according to Clause 44, wherein the first integrated circuit die includes a plurality of metal clips coupled between at least two pairs of source terminals and drain terminals of the plurality of first switches or the plurality of second switches. 61. The apparatus according to Clause 60, wherein the metal clip is a copper clip welded to the source terminal and the drain terminal. 62. An apparatus comprising: A laterally double-diffused metal-oxide-semiconductor field-effect transistor, the laterally double-diffused metal-oxide-semiconductor field-effect transistor comprising a drift region, a source region, a drain region, a gate, and a substrate; The lateral double-diffused metal-oxide-semiconductor field-effect transistor has a through-silicon via for forming an electrical connection from the bottom surface of the lateral double-diffused metal-oxide-semiconductor field-effect transistor to the drain. 63. The apparatus according to Clause 62, wherein the through-silicon via is formed using a single-layer transfer process. 64. The apparatus according to Clause 63, wherein the single-layer transfer process includes back-side grinding and etching of the substrate and etching of the through-silicon via. 65. The apparatus according to Clause 64, wherein the through-silicon via is formed using deep reactive ion etching. 66. The apparatus according to Clause 64, wherein the through-silicon via is formed using isotropic radial etching. 67. The apparatus according to Clause 64, wherein the through-silicon via is formed using reactive ion beam etching. 68. The apparatus according to Clause 64, wherein the through-silicon via is formed using ion milling. 69. The apparatus according to Clause 64, wherein the through-silicon via is formed using ion beam assisted etching. 70. The apparatus according to Clause 64, wherein the through-silicon via is formed using sputter etching. 71. The apparatus according to Clause 64, wherein the substrate is back-side ground and etched to a thickness of 50 micrometers or greater. 72. The apparatus according to Clause 62, wherein the laterally diffused metal-oxide-semiconductor field-effect transistor has a through-silicon via for forming an electrical connection from the bottom surface of the laterally diffused metal-oxide-semiconductor field-effect transistor to the source. 73. The apparatus according to clause 62 further includes: Integrated circuit package, the integrated circuit package comprising: A first integrated circuit die, the first integrated circuit die being electrically coupled to a lead frame; The first integrated circuit die includes a plurality of first switches and a plurality of second switches; The plurality of first switches and the plurality of second switches are interconnected with a plurality of first capacitors to form a first switched capacitor circuit, wherein the first switched capacitor circuit transitions between at least two states in response to switching of the plurality of first switches and the plurality of second switches; and Each of the plurality of first switches and the plurality of second switches includes one or more of the lateral double-diffused metal-oxide-semiconductor field-effect transistors. 74. The apparatus according to Clause 73, wherein the first switched capacitor circuit has a power rating of about 100 watts to about 1000 watts. 75. The apparatus according to Clause 73, wherein the integrated circuit package is a surface mount package. 76. The apparatus according to Clause 75, wherein the integrated circuit package is a flat, leadless package. 77. The apparatus according to Clause 76, wherein the integrated circuit package is a quad flat no-lead package. 78. The apparatus according to Clause 73, wherein the first integrated circuit die includes a first replication switch, wherein at least two terminals of the first replication switch are electrically connected to at least two corresponding terminals of one of the plurality of first switches or the plurality of second switches. 79. The apparatus according to Clause 78, wherein the first copying switch is smaller than the switch to which its terminals are electrically connected. 80. The apparatus according to Clause 78, wherein the first copy switch senses the current flowing through the one switch, and the terminals of the first copy switch are electrically connected to the one switch. 81. The apparatus according to Clause 78, wherein the first copy switch detects a fault associated with the one switch, and the terminals of the first copy switch are electrically connected to the one switch. 82. The apparatus according to Clause 78, wherein the first integrated circuit die includes a second replication switch, wherein at least two terminals of the second replication switch are electrically connected to at least two corresponding terminals of the plurality of first switches or another switch among the plurality of second switches; Wherein, the one switch and the other switch have different sizes; and The dimensions of the first copy switch and the second copy switch are proportional to the dimensions of the first switch and the other switch, respectively. 83. The apparatus according to Clause 82, wherein the second copy switch is smaller than the other switch, and the terminals of the second copy switch are electrically connected to the other switch. 84. The apparatus according to Clause 82, wherein the second copy switch senses the current flowing through the other switch, and the terminals of the second copy switch are electrically connected to the other switch. 85. The apparatus according to Clause 82, wherein the second copy switch detects a fault associated with the other switch, and the terminals of the second copy switch are electrically connected to the other switch. 86. The apparatus according to Clause 73, wherein the first integrated circuit die is electrically coupled to the lead frame using flip-chip bonding. 87. The apparatus according to clause 62 further includes: A second integrated circuit die, the second integrated circuit die being electrically coupled to the lead frame; The second integrated circuit die includes multiple third switches and multiple fourth switches; The plurality of third switches and the plurality of fourth switches are interconnected with a plurality of second capacitors to form a second switched capacitor circuit, wherein the second switched capacitor circuit transitions between at least two states in response to switching of the plurality of third switches and the plurality of fourth switches; and Each of the plurality of third switches and the plurality of fourth switches includes one or more of the lateral double-diffused metal-oxide-semiconductor field-effect transistors. 88. The apparatus according to Clause 87, wherein at least one of the plurality of first switches and the plurality of second switches has a rated current different from at least one of the plurality of third switches and the plurality of fourth switches. 89. The apparatus according to Clause 87, wherein the first integrated circuit die and the second integrated circuit die are stacked perpendicularly to each other. 90. The apparatus according to Clause 73, wherein the first integrated circuit die includes a plurality of metal clips coupled between at least two pairs of source terminals and drain terminals of the plurality of first switches or the plurality of second switches. 91. The apparatus according to Clause 90, wherein the metal clip is a copper clip welded to the source terminal and the drain terminal.

[0127] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or realize the same advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. An apparatus comprising: A vertically double-diffused metal-oxide-semiconductor field-effect transistor, the vertically double-diffused metal-oxide-semiconductor field-effect transistor comprising a drift region, a source region, a drain region, and a gate; The vertically double-diffused metal-oxide-semiconductor field-effect transistor is isolated by an isolation trench formed around it. The isolation trench is filled with an electrical isolation material; and The isolation trench passes through the bottom of the drain electrode.

2. The apparatus according to claim 1, wherein, The drift region is n-type, the source region is p-type, and the drain is n+ type.

3. The apparatus according to claim 1, wherein, The electrical isolation material filling the isolation trench is silicon.

4. The apparatus according to claim 1, wherein, The electrical isolation material filling the isolation trench is silicon dioxide.

5. The apparatus according to claim 1, wherein, The isolation trenches were formed using deep reactive ion etching.

6. The apparatus according to claim 1, wherein, The isolation trenches are formed using isotropic radial etching.

7. The apparatus according to claim 1, wherein, The isolation trenches were formed using reactive ion beam etching.

8. The apparatus according to claim 1, wherein, The isolation trenches were formed using ion milling.

9. The apparatus according to claim 1, wherein, The isolation trenches were formed using ion beam-assisted etching.

10. The apparatus according to claim 1, wherein, The isolation trenches were formed using sputter etching.

11. The apparatus according to claim 1, wherein, The drain is located on the top surface of the vertical double-diffused metal-oxide-semiconductor field-effect transistor, and the source is located on the bottom surface of the vertical double-diffused metal-oxide-semiconductor field-effect transistor.

12. The apparatus according to claim 1, further comprising: Integrated circuit package, the integrated circuit package comprising: A first integrated circuit die, the first integrated circuit die being electrically coupled to a lead frame; The first integrated circuit die includes a plurality of first switches and a plurality of second switches; The plurality of first switches and the plurality of second switches are interconnected with a plurality of first capacitors to form a first switched capacitor circuit, wherein the first switched capacitor circuit transitions between at least two states in response to switching of the plurality of first switches and the plurality of second switches; and Each of the plurality of first switches and the plurality of second switches includes one or more of the vertically double-diffused metal-oxide-semiconductor field-effect transistors, wherein the vertically double-diffused metal-oxide-semiconductor field-effect transistors are electrically isolated from each other through the isolation trench.

13. The apparatus according to claim 12, wherein, The first switched capacitor circuit has a rated power of approximately 100 watts to approximately 1000 watts.

14. The apparatus according to claim 12, wherein, The integrated circuit packaging is a surface mount package.

15. The apparatus according to claim 14, wherein, The integrated circuit is packaged as a flat, leadless package.

16. The apparatus according to claim 15, wherein, The integrated circuit is packaged as a quad flat leadless package.

17. The apparatus according to claim 12, wherein, The first integrated circuit die includes a first replication switch, wherein at least two terminals of the first replication switch are electrically connected to at least two corresponding terminals of one of the plurality of first switches or the plurality of second switches.

18. The apparatus according to claim 17, wherein, The size of the first copy switch is smaller than the size of the first switch, and the terminals of the first copy switch are electrically connected to the first switch.

19. The apparatus according to claim 17, wherein, The first copy switch senses the current flowing through the first switch, and the terminals of the first copy switch are electrically connected to the first switch.

20. The apparatus according to claim 17, wherein, The first copy switch detects a fault associated with the first copy switch, whose terminals are electrically connected to the switch.

21. The apparatus according to claim 18, wherein, The first integrated circuit die includes a second replication switch, wherein at least two terminals of the second replication switch are electrically connected to at least two corresponding terminals of the plurality of first switches or another switch among the plurality of second switches; Wherein, the one switch and the other switch have different sizes; and The dimensions of the first copy switch and the second copy switch are proportional to the dimensions of the first switch and the other switch, respectively.

22. The apparatus according to claim 21, wherein, The second copy switch is smaller than the other switch, and the terminals of the second copy switch are electrically connected to the other switch.

23. The apparatus according to claim 21, wherein, The second copy switch senses the current flowing through the other switch, and the terminals of the second copy switch are electrically connected to the other switch.

24. The apparatus according to claim 21, wherein, The second copy switch detects a fault associated with the other switch, and the terminals of the second copy switch are electrically connected to the other switch.

25. The apparatus according to claim 12, wherein, The first integrated circuit die is electrically coupled to the lead frame using flip-chip bonding.

26. The apparatus according to claim 1, further comprising: A second integrated circuit die, the second integrated circuit die being electrically coupled to the lead frame; The second integrated circuit die includes multiple third switches and multiple fourth switches; The plurality of third switches and the plurality of fourth switches are interconnected with a plurality of second capacitors to form a second switched capacitor circuit, wherein the second switched capacitor circuit transitions between at least two states in response to switching of the plurality of third switches and the plurality of fourth switches; and Each of the plurality of third switches and the plurality of fourth switches includes one or more of the vertically double-diffused metal-oxide-semiconductor field-effect transistors, wherein the vertically double-diffused metal-oxide-semiconductor field-effect transistors are electrically isolated from each other through the isolation trench.

27. The apparatus according to claim 26, wherein, At least one of the plurality of first switches and the plurality of second switches has a different rated current than at least one of the plurality of third switches and the plurality of fourth switches.

28. The apparatus according to claim 12, wherein, The first integrated circuit die includes a plurality of metal clips coupled between at least two pairs of source terminals and drain terminals of the plurality of first switches or the plurality of second switches.

29. The apparatus according to claim 28, wherein, The metal clip is a copper clip welded to the source terminal and the drain terminal.

30. An apparatus comprising: A laterally double-diffused metal-oxide-semiconductor field-effect transistor, the laterally double-diffused metal-oxide-semiconductor field-effect transistor comprising a drift region, a source region, a drain region, a gate, and a substrate; The lateral double-diffused metal-oxide-semiconductor field-effect transistor has a through-silicon via for forming an electrical connection from the bottom surface of the lateral double-diffused metal-oxide-semiconductor field-effect transistor to the drain.

31. The apparatus according to claim 30, wherein, The through-silicon vias are formed using a single-layer transfer process.

32. The apparatus according to claim 31, wherein, The single-layer transfer process includes back-side grinding and etching of the substrate, as well as etching of the through-silicon vias.

33. The apparatus according to claim 32, wherein, The through-silicon vias are formed using deep reactive ion etching.

34. The apparatus according to claim 32, wherein, The through-silicon vias are formed using isotropic radial etching.

35. The apparatus according to claim 32, wherein, The through-silicon vias are formed using reactive ion beam etching.

36. The apparatus according to claim 32, wherein, The through-silicon vias were formed using ion milling.

37. The apparatus according to claim 32, wherein, The through-silicon vias are formed using ion beam-assisted etching.

38. The apparatus according to claim 32, wherein, The through-silicon vias are formed using sputtering etching.

39. The apparatus according to claim 32, wherein, The substrate is back-side ground and etched to a thickness of 50 micrometers or greater.

40. The apparatus according to claim 30, wherein, The lateral double-diffused metal-oxide-semiconductor field-effect transistor has a through-silicon via for forming an electrical connection from the bottom surface of the lateral double-diffused metal-oxide-semiconductor field-effect transistor to the source.

41. The apparatus of claim 30, further comprising: Integrated circuit package, the integrated circuit package comprising: A first integrated circuit die, the first integrated circuit die being electrically coupled to a lead frame; The first integrated circuit die includes a plurality of first switches and a plurality of second switches; The plurality of first switches and the plurality of second switches are interconnected with a plurality of first capacitors to form a first switched capacitor circuit, wherein the first switched capacitor circuit transitions between at least two states in response to switching of the plurality of first switches and the plurality of second switches; and Each of the plurality of first switches and the plurality of second switches includes one or more of the lateral double-diffused metal-oxide-semiconductor field-effect transistors.

42. The apparatus according to claim 41, wherein, The first switched capacitor circuit has a rated power of approximately 100 watts to approximately 1000 watts.

43. The apparatus according to claim 41, wherein, The integrated circuit packaging is a surface mount package.

44. The apparatus according to claim 43, wherein, The integrated circuit is packaged as a flat, leadless package.

45. The apparatus according to claim 44, wherein, The integrated circuit is packaged as a quad flat leadless package.

46. ​​The apparatus according to claim 41, wherein, The first integrated circuit die includes a first replication switch, wherein at least two terminals of the first replication switch are electrically connected to at least two corresponding terminals of one of the plurality of first switches or the plurality of second switches.

47. The apparatus according to claim 46, wherein, The first copy switch is smaller than the first switch, and the terminals of the first copy switch are electrically connected to the first switch.

48. The apparatus according to claim 46, wherein, The first copy switch senses the current flowing through the first switch, and the terminals of the first copy switch are electrically connected to the first switch.

49. The apparatus according to claim 46, wherein, The first copy switch detects a fault associated with the one switch, and the terminals of the first copy switch are electrically connected to the one switch.

50. The apparatus according to claim 46, wherein, The first integrated circuit die includes a second replication switch, wherein at least two terminals of the second replication switch are electrically connected to at least two corresponding terminals of the plurality of first switches or another switch among the plurality of second switches; Wherein, the one switch and the other switch have different sizes; and The dimensions of the first copy switch and the second copy switch are proportional to the dimensions of the first switch and the other switch, respectively.

51. The apparatus according to claim 50, wherein, The second copy switch is smaller than the other switch, and the terminals of the second copy switch are electrically connected to the other switch.

52. The apparatus according to claim 50, wherein, The second copy switch senses the current flowing through the other switch, and the terminals of the second copy switch are electrically connected to the other switch.

53. The apparatus according to claim 50, wherein, The second copy switch detects a fault associated with the other switch, and the terminals of the second copy switch are electrically connected to the other switch.

54. The apparatus according to claim 41, wherein, The first integrated circuit die is electrically coupled to the lead frame using flip-chip bonding.

55. The apparatus of claim 30, further comprising: A second integrated circuit die, the second integrated circuit die being electrically coupled to the lead frame; The second integrated circuit die includes multiple third switches and multiple fourth switches; The plurality of third switches and the plurality of fourth switches are interconnected with a plurality of second capacitors to form a second switched capacitor circuit, wherein the second switched capacitor circuit transitions between at least two states in response to switching of the plurality of third switches and the plurality of fourth switches; and Each of the plurality of third switches and the plurality of fourth switches includes one or more of the lateral double-diffused metal-oxide-semiconductor field-effect transistors.

56. The apparatus according to claim 55, wherein, At least one of the plurality of first switches and the plurality of second switches has a different rated current than at least one of the plurality of third switches and the plurality of fourth switches.

57. The apparatus according to claim 55, wherein, The first integrated circuit die and the second integrated circuit die are stacked vertically on top of each other.

58. The apparatus according to claim 41, wherein, The first integrated circuit die includes a plurality of metal clips coupled between at least two pairs of source terminals and drain terminals of the plurality of first switches or the plurality of second switches.

59. The apparatus according to claim 58, wherein, The metal clip is a copper clip welded to the source terminal and the drain terminal.

60. An apparatus comprising: Integrated circuit package, the integrated circuit package comprising: A first integrated circuit die, the first integrated circuit die being electrically coupled to a lead frame; The first integrated circuit die includes a plurality of first switches and a plurality of second switches; The plurality of first switches and the plurality of second switches are interconnected with a plurality of first capacitors to form a first switched capacitor circuit, wherein the first switched capacitor circuit is configured to transition between at least two states in response to switching of the plurality of first switches and the plurality of second switches; and Second integrated circuit die; The second integrated circuit die includes a controller circuit electrically coupled to control the switching of the plurality of first switches and the plurality of second switches; and A third integrated circuit die, wherein the third integrated circuit die is electrically coupled to the lead frame; The third integrated circuit die includes multiple third switches and multiple fourth switches; The plurality of third switches and the plurality of fourth switches are interconnected with a plurality of second capacitors to form a second switched capacitor circuit, wherein the second switched capacitor circuit is configured to switch between at least two states in response to the switching of the plurality of third switches and the plurality of fourth switches; and The controller circuit is electrically coupled to control the switching of the plurality of third switches and the plurality of fourth switches; The first integrated circuit die, the second integrated circuit die, and the third integrated circuit die are co-packaged; and Wherein, at least one of the plurality of first switches and the plurality of second switches has a rated current different from that of at least one of the plurality of third switches and the plurality of fourth switches.

61. The apparatus according to claim 60, wherein, The first switched capacitor circuit has a rated power of approximately 100 watts to approximately 1000 watts.

62. The apparatus according to claim 60, wherein, The integrated circuit packaging is a surface mount package.

63. The apparatus according to claim 62, wherein, The integrated circuit is packaged as a flat, leadless package.

64. The apparatus according to claim 63, wherein, The integrated circuit is packaged as a quad flat leadless package.

65. The apparatus according to claim 60, wherein, The controller circuit includes one or more complementary metal-oxide-semiconductor field-effect transistors.

66. The apparatus of claim 60, wherein, Each of the plurality of first switches and the plurality of second switches includes one or more double-diffused metal-oxide-semiconductor field-effect transistors.

67. The apparatus of claim 60, wherein, The controller circuit is configured to control the switching of a switch with a rated current between about 10 amps and about 40 amps.

68. The apparatus according to claim 60, wherein, The first integrated circuit die includes a first replication switch, wherein at least two terminals of the first replication switch are electrically connected to at least two corresponding terminals of one of the plurality of first switches or the plurality of second switches.

69. The apparatus according to claim 68, wherein, The size of the first copy switch is smaller than the size of the first switch, and the terminals of the first copy switch are electrically connected to the first switch.

70. The apparatus according to claim 68, wherein, The first copy switch is configured to sense the current flowing through the one switch, and the terminals of the first copy switch are electrically connected to the one switch.

71. The apparatus according to claim 68, wherein, The first copy switch is configured to detect a fault associated with the one switch, and the terminals of the first copy switch are electrically connected to the one switch.

72. The apparatus according to claim 68, wherein, The first integrated circuit die includes a second replication switch, wherein at least two terminals of the second replication switch are electrically connected to at least two corresponding terminals of the plurality of first switches or another switch among the plurality of second switches; Wherein, the one switch and the other switch have different sizes; and The dimensions of the first copy switch and the second copy switch are proportional to the dimensions of the first switch and the other switch, respectively.

73. The apparatus according to claim 72, wherein, The second copy switch is smaller than the other switch, and the terminals of the second copy switch are electrically connected to the other switch.

74. The apparatus according to claim 72, wherein, The second copy switch is configured to sense the current flowing through the other switch, and the terminals of the second copy switch are electrically connected to the other switch.

75. The apparatus according to claim 72, wherein, The second copy switch is configured to detect a fault associated with the other switch, and the terminals of the second copy switch are electrically connected to the other switch.

76. The apparatus of claim 60, wherein, The first integrated circuit die is electrically coupled to the lead frame using wiring bonding.

77. The apparatus of claim 60, wherein, The second integrated circuit die is electrically coupled to the lead frame using flip-chip bonding.

78. The apparatus according to claim 60, wherein, Each of the plurality of first switches and the plurality of second switches includes one or more laterally double-diffused metal-oxide-semiconductor field-effect transistors.

79. The apparatus according to claim 78, wherein, The first integrated circuit die includes a through-silicon via (TSV), which is configured to form an electrical connection to the drain or source terminals of the plurality of first switches or the plurality of second switches.

80. The apparatus according to claim 79, wherein, The through-silicon vias are fabricated using a single transfer layer.

81. The apparatus of claim 78, further comprising: A fourth integrated circuit die, which is electrically coupled to the lead frame; The fourth integrated circuit die includes multiple fifth switches and multiple sixth switches; The plurality of fifth switches and the plurality of sixth switches are interconnected with a plurality of third capacitors to form a third switched capacitor circuit, wherein the third switched capacitor circuit is configured to switch between at least two states in response to the switching of the plurality of fifth switches and the plurality of sixth switches; and The controller circuit is electrically coupled to control the switching of the plurality of fifth switches and the plurality of sixth switches; and The first integrated circuit die and the fourth integrated circuit die are stacked vertically.

82. The apparatus according to claim 78, wherein, The first integrated circuit die includes a plurality of metal clips coupled between at least two pairs of source terminals and drain terminals of the plurality of first switches or the plurality of second switches.

83. The apparatus according to claim 82, wherein, The metal clip is a copper clip welded to the source terminal and the drain terminal.

84. The apparatus according to claim 60, wherein, Each of the plurality of first switches and the plurality of second switches includes one or more vertically double-diffused metal-oxide-semiconductor field-effect transistors.

85. The apparatus according to claim 84, wherein, The first integrated circuit die includes a plurality of isolation trenches configured to electrically isolate the plurality of first switches and the plurality of second switches from each other.

86. The apparatus according to claim 85, wherein, The multiple isolation trenches were formed using deep reactive ion etching.

87. The apparatus according to claim 85, wherein, An insulating layer is deposited in the plurality of isolation trenches.

88. The apparatus according to claim 85, wherein, Compared to the wafer from which the first integrated circuit die is made, the substrate of the first integrated circuit die is ground to reduce its thickness.

89. The apparatus according to claim 84, wherein, The first integrated circuit die includes a plurality of metal clips coupled between at least two pairs of source terminals and drain terminals of the plurality of first switches or the plurality of second switches.

90. The apparatus according to claim 89, wherein, The metal clip is a copper clip welded to the source terminal and the drain terminal.

91. The apparatus according to claim 60, wherein, The plurality of first switches and the plurality of second switches are laterally double-diffused metal-oxide-semiconductor devices.

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