A method, system, device and storage medium for adding automatic register connection optimization

Abstract

The application discloses a kind of newly added register automatic connection optimization method, system, equipment and storage medium, the method includes: identifying the newly added register needing to be inserted in existing layout and wiring design in engineering change instruction;In the tree structure of the existing layout and wiring design, search the candidate connection node set corresponding to the network source point logic equivalence of the newly added register;The physical distance of the newly added register is calculated with each candidate node in the candidate connection node set;The candidate node closest to the physical distance of the newly added register is used as the target connection node, and the corresponding signal end of the newly added register is connected to the target connection node.The application realizes the full-process automation of chip logic ECO newly added register connection, significantly improves ECO processing efficiency, avoids the problem of logic error and low efficiency caused by manual operation.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit automated design technology, and specifically to a method, system, computer device, and readable storage medium for automatic connection optimization of newly added registers in chip logic ECO. Background Technology

[0002] In the later stages of the chip design process, logic ECOs (Engineering Change Orders) are often required due to functional changes or bug fixes. This involves inserting new registers into a design that has already largely completed its placement and routing. The clock and reset terminals of these new registers are connected by default to the source of the global network in the logic netlist. However, at the physical level, the clock and reset signals are already distributed and driven through a tree structure (clock tree / reset tree), with multiple levels of buffering between the signal source and the leaf nodes (existing registers). Currently, register connections in this scenario primarily rely on manual handling by design engineers. Specific methods include: first, manually rebuilding the local tree, i.e., manually inserting buffers to create new branches starting from the new register; and second, manually searching and connecting, i.e., engineers relying on experience to find a suitable existing node (such as the output of a buffer) within the vast existing tree structure for connection.

[0003] In existing technologies, manually reconstructing local trees increases area and power consumption and may interfere with already stable circuit nodes. Manually searching and switching is extremely inefficient and is basically not feasible in large-scale ECO scenarios (involving hundreds or thousands of registers). Furthermore, the selection criteria for "suitable" nodes are vague, making it difficult for engineers to make quantitative trade-offs between timing optimization (such as low connection point delay) and electrical safety (such as sufficient connection point drive margin). Improper selection can easily lead to timing violations in new registers or cause the target node to have drive capability problems due to excessive fan-out, thereby triggering new timing violations.

[0004] Therefore, given the problems of low automation, poor processing efficiency, lack of timing quality, and susceptibility to secondary design issues in existing technologies, a new technical solution is needed. Summary of the Invention

[0005] In view of this, embodiments of the present invention provide a method and system for automatic connection optimization of newly added registers in chip logic ECO, so as to at least solve the problems in the prior art.

[0006] The embodiments of the present invention provide the following technical solutions: This invention provides a method for automatically optimizing the connection of newly added registers in a chip logic ECO, comprising: Identify new registers that need to be inserted into the existing layout and routing design in engineering change instructions; In the tree structure of the existing layout and routing design, a set of candidate connection nodes that are logically equivalent to the network source point corresponding to the newly added register is searched. The set of candidate connection nodes includes at least one candidate node. Logical equivalence means that the candidate node has the same logical function as the network source point corresponding to the newly added register. Calculate the physical location of the newly added register and the physical distance between it and each of the candidate nodes in the candidate connection node set; The candidate node that is physically closest to the newly added register is selected as the target connection node, and the corresponding signal terminal of the newly added register is connected to the target connection node.

[0007] Preferably, in the tree structure of the existing layout and routing design, searching for a set of candidate connection nodes logically equivalent to the network source node corresponding to the newly added register includes: Determine the signal network type of the newly added register, wherein the signal network type is either a clock network or a reset network; When the signal network type is a clock network, the candidate node that is logically equivalent to the clock network source point corresponding to the newly added register is searched in the tree structure, and the candidate nodes located at the deepest or second deepest logical level of the tree structure are gathered to form the candidate connection node set. When the signal network type is a reset network, a candidate node logically equivalent to the reset network source point corresponding to the newly added register is searched in the tree structure, and all the logically equivalent candidate nodes are gathered to form the candidate connection node set.

[0008] Preferably, selecting the candidate node with the closest physical distance to the newly added register as the target connection node, and connecting the corresponding signal terminal of the newly added register to the target connection node includes: When the signal network type is a clock network, the candidate node that is closest in physical distance to the newly added register is selected as the target connection node; if there are multiple candidate nodes that are close in physical distance, the candidate node with the deepest logical level is selected as the target connection node. When the signal network type is a reset network, the candidate node that is closest in physical distance to the newly added register is directly selected as the target connection node.

[0009] Preferably, the method further includes: The total fan-out load of the target connection node connected to the newly added register is evaluated. If the total fan-out load exceeds a preset threshold, a drive capability optimization operation is automatically performed.

[0010] Preferably, the drive capability optimization operation includes increasing the size of the buffer unit driving the target connection node, or copying the driver of the target connection node to share the load.

[0011] This invention also provides an automatic connection optimization system for newly added registers in chip logic ECO, comprising: The register identification module is used to identify new registers that need to be inserted into the existing layout and routing design in engineering change instructions; The candidate node search module is used to search for a set of candidate connection nodes that are logically equivalent to the network source point corresponding to the newly added register in the tree structure of the existing layout and routing design. The set of candidate connection nodes includes at least one candidate node. The logical equivalence means that the candidate node has the same logical function as the network source point corresponding to the newly added register. The physical distance calculation module is used to calculate the physical distance between the physical location of the newly added register and each of the candidate nodes in the candidate connection node set; The target node connection module is used to select the candidate node that is closest to the new register in terms of physical distance as the target connection node, and connect the corresponding signal terminal of the new register to the target connection node.

[0012] Preferably, the candidate node search module includes: A network type determination unit is used to determine the signal network type of the newly added register, wherein the signal network type is a clock network or a reset network; The clock candidate filtering unit is used to search for candidate nodes in the tree structure that are logically equivalent to the clock network source point corresponding to the newly added register when the signal network type is a clock network, and to include the candidate nodes located at the deepest or second deepest logical level of the tree structure to form the candidate connection node set. The reset candidate filtering unit is used to search in the tree structure for candidate nodes that are logically equivalent to the reset network source point corresponding to the newly added register when the signal network type is a reset network, and to include all the logically equivalent candidate nodes to form the candidate connection node set.

[0013] Preferably, the system further includes: The drive capability evaluation and optimization module is used to evaluate the total fan-out load of the target connection node connected to the newly added register. If the total fan-out load exceeds a preset threshold, the drive capability optimization operation is automatically executed.

[0014] This invention also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the automatic connection optimization method for newly added registers as described above.

[0015] This invention also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the automatic connection optimization method for newly added registers as described in any of the preceding embodiments.

[0016] Compared with the prior art, the technical effects that can be achieved by at least one of the above-mentioned technical solutions adopted in the embodiments of the present invention include at least the following: This invention discloses an automatic connection optimization method for new registers in a chip logic ECO. By identifying new registers to be inserted into the existing layout and routing design in engineering change instructions, the method searches within the established tree-like driver structure for candidate connection nodes logically equivalent to the network source point of the new register, ensuring that the candidate nodes and network source points have consistent logical functions. Then, it accurately calculates the physical distance between the physical location of the new register and each candidate node, selects the candidate node with the closest physical distance as the target connection node, and completes the connection of the corresponding signal terminals of the new register. The optimized tree-like driver structure is reused throughout the process to achieve signal transfer. This achieves full automation of the connection process for new registers in the chip logic ECO, significantly improving ECO processing efficiency, avoiding logic errors and inefficiencies caused by manual operation, and shortening the signal transmission path and reducing signal insertion delay through proximity-based physical connections, providing an optimal starting point for subsequent timing convergence. Furthermore, it eliminates the need to rebuild local driver branches for the new register, minimizing design disturbances to the existing stable layout and routing, reducing circuit area and power consumption, and ensuring logical consistency and electrical stability of the circuit connections. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a flowchart of an automatic connection optimization method for newly added registers in a chip logic ECO according to an embodiment of the present invention; Figure 2 The initial circuit used in this embodiment of the invention: The newly added registers (the three rightmost devices) are connected to a candidate original clock source node; Figure 3This is a schematic diagram showing that after executing steps S102-S108 in an embodiment of the present invention, the newly added register is connected to the candidate original clock source node on the right. Figure 4 After performing step S110 in this embodiment of the invention Figure 3 The diagram on the right shows the driver of the candidate original clock source node being copied to meet the load requirements.

[0019] The reference numerals in the drawings of this invention are as follows: 1. Target connection node; 2. Add register. Detailed Implementation

[0020] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0021] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. This application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0022] It should be noted that various aspects of embodiments within the scope of the appended claims are described below. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any particular structure and / or function described herein is merely illustrative. Based on this application, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspects set forth herein can be used to implement the device and / or practice the method. Additionally, this device and / or method can be implemented using structures and / or functionalities other than one or more of the aspects set forth herein.

[0023] It should also be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this application. The drawings only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0024] Additionally, specific details are provided in the following description to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that practice can be carried out without these specific details.

[0025] Based on the shortcomings of existing technologies, this specification proposes a processing solution in its embodiments: such as Figure 1 As shown, the present invention provides an automatic connection optimization method for newly added registers in chip logic ECO. For chip designs with completed placement and routing, the method first identifies the new registers to be inserted in the ECO and distinguishes between clock and reset network types. Based on the network type, it searches for candidate connection nodes that are logically equivalent to the corresponding network source point (for clock networks, it selects nodes near the bottom layer of the tree structure; for reset networks, it selects all equivalent nodes). By calculating the physical distance, it selects the optimal target node to complete the signal connection. Then, it automatically evaluates the fan-out load of the target node and performs driver optimization by increasing the buffer size or copying the driver. The existing tree-like driver structure is reused throughout the process, realizing full automation of ECO register connection, efficiently ensuring timing convergence, and reducing design disturbances and area and power consumption overhead.

[0026] The technical solutions provided by the various embodiments of this application are described below with reference to the accompanying drawings.

[0027] like Figure 1-3 As shown, this embodiment of the invention provides a method for automatic connection optimization of newly added registers in chip logic ECO, including: Step S102: Identify the new registers that need to be inserted into the existing layout and routing design in the engineering change instruction.

[0028] An Engineering Change Order (ECO) is an engineering change instruction in the integrated circuit design process. After the chip has completed back-end design such as logic synthesis and placement and routing and is basically finalized, it is used to make partial logic modifications, cell additions or removals, or signal connection adjustments to the finalized circuit design due to necessary needs such as functional requirement adjustments, design defect repairs, and logic error corrections. In digital chip physical design, logic ECOs do not require restarting the entire placement and routing process; they only target the changed parts and make partial modifications. This is a core technical means for rapid iteration and problem-solving in the later stages of chip design.

[0029] Existing layout and routing design refers to a complete chip physical implementation scheme in the process of digital chip physical design (back-end design) where standard cell placement, clock tree and reset tree synthesis, global and detailed routing have been completed, the physical location of circuit units is fixed, the interconnection paths and driving structures of key signals have been constructed, and the timing, electrical and other design rules have been initially converged. This design has formed a stable layout and netlist data, and only local logic modifications and cell adjustments are required based on engineering change instructions (ECOs), without having to re-execute the entire layout and routing process.

[0030] In this embodiment, the newly added register refers to a timing logic unit that is newly inserted in the finalized physical design after the standard cell layout, clock tree / reset tree synthesis and interconnect routing have been completed, in order to meet the needs of functional iteration updates, design defect repair or logic error correction, etc., when the logic engineering change instructions are executed in the later stage of chip physical design.

[0031] New registers are usually not involved in the early placement and routing process and the construction of clock and reset trees. Therefore, it is necessary to match them with stable signal drive connections according to their signal network type in order to achieve logical coordination with the original circuit and normal timing operation.

[0032] Step S102, by identifying the new register 2 that needs to be inserted into the existing layout and routing design in the engineering change instruction, can accurately locate the target timing unit that needs to be processed in this logic ECO, thereby facilitating subsequent candidate node selection, physical distance calculation and signal terminal connection.

[0033] Step S104: In the tree structure of the existing layout and routing design, search for a set of candidate connection nodes that are logically equivalent to the network source point corresponding to the newly added register 2. The set of candidate connection nodes includes at least one candidate node. Logical equivalence means that the candidate node has the same logical function as the network source point corresponding to the newly added register 2.

[0034] The existing tree structure of the layout and routing design is a distributed signal driving topology formed by clock tree synthesis and reset tree synthesis during the chip physical design stage. Specifically, it includes a clock tree and a reset tree: the clock tree is used to provide low-skew, high-stability synchronous clock drive signals for all registers in the chip, and the reset tree is used to provide synchronous and reliable reset / set drive signals for the registers in the chip.

[0035] The candidate connection node set is obtained by retrieving physical connection nodes within the existing clock tree and reset tree driving structure of the layout and routing design, which have the same logical function as the signal source point of the clock / reset network signal to which the newly added register 2 belongs. Therefore, the candidate connection node set may include multiple candidate nodes.

[0036] Logical equivalence means that the candidate node and the clock network source or reset network source corresponding to the newly added register 2 have the same logical function, signal level attributes and signal transmission intention. The candidate node and the network source only have differences in physical driving level, physical location and driving capability. There is no logical inversion, logical operation, signal modulation or functional change. The two can be equivalently replaced and directly interconnected in circuit logic.

[0037] Step S104 involves filtering out nodes with the same logical function as the network source point corresponding to the newly added register 2 from the existing tree-like drive structure of the layout and routing design, forming a set of candidate connection nodes, so as to accurately lock the available signal connection points and ensure that the candidate nodes and the network source point have the same logical attributes, thereby avoiding logical anomalies after the newly added register 2 is connected.

[0038] Step S106: Calculate the physical location of the newly added register 2 and the physical distance between it and each candidate node in the candidate connection node set.

[0039] The physical distance is the physical distance between the newly added register 2 and each candidate node on the chip layout, which can be calculated using the physical coordinates of each node.

[0040] The physical distance mentioned in this step is the Manhattan distance. The Manhattan distance is a common distance calculation method in the field of integrated circuit physical design. It refers to the sum of the absolute values ​​of the coordinate differences between two points on the horizontal and vertical coordinate axes of the chip layout. This calculation method conforms to the standard cell grid layout and metal interconnect wiring rules of the chip, and can truly reflect the actual physical transmission path length of the signal.

[0041] Step S106 accurately calculates the Manhattan distance to objectively determine the physical proximity of each candidate node to the newly added register 2, ensuring that the connection node with the shortest physical path is selected in the future. This effectively shortens the clock / reset signal transmission distance, reduces insertion delay and timing skew, provides optimal physical support for timing convergence, and improves the automation accuracy and processing efficiency of node selection.

[0042] Step S108: Select the candidate node that is closest to the new register 2 in terms of physical distance as the target connection node 1, and connect the corresponding signal terminal of the new register 2 to the target connection node 1.

[0043] Step S108 uses the calculated physical distance as the preferred criterion to select the node closest to the spatial location of the newly added register 2 from the candidate connection node set as the final target connection node 1, so as to complete the interconnection and docking of the corresponding new signal terminal and other functional new signal terminal of the newly added register 2 with the target connection node 1.

[0044] For example, when the signal network type of the newly added register 2 is a reset network, the reset signal terminal of the newly added register 2 can be directly connected to the corresponding target connection node 1 to achieve automatic optimized connection of the newly added register 2.

[0045] Step S108 ensures that the access node and the signal network source point have consistent logical functions and that there is no deviation in the circuit logic. It achieves the physical optimal configuration of the signal connection path, effectively shortens the actual wiring transmission length of the clock and reset signals, significantly reduces signal transmission delay and timing deviation, and helps the overall chip design to successfully complete timing convergence.

[0046] In some specific implementations, the search for a set of candidate connection nodes logically equivalent to the network source node corresponding to the newly added register 2 in step S104 specifically includes: Step S104a: Determine the signal network type of the newly added register 2. The signal network type is either a clock network or a reset network.

[0047] Among them, the clock network is a global drive tree link that provides a dedicated timing synchronization reference pulse signal, which is responsible for ensuring the synchronous operation of the register clock. The reset network is a global drive tree link that provides a dedicated start / stop and initialization reset control signal, which is responsible for ensuring reliable reset initialization of the register under power-on and abnormal conditions.

[0048] Step S104a clearly defines the type of signal network (clock network or reset network) that the newly added register 2 needs to connect to, thereby achieving accurate differentiation of interconnection links with different functional attributes, thus avoiding the use of different network selection logics when selecting candidate nodes in the future.

[0049] Step S104b: When the signal network type is a clock network, search in the tree structure for candidate nodes that are logically equivalent to the source node of the clock network corresponding to the newly added register 2, and gather the candidate nodes located at the deepest or second deepest logical level of the tree structure to form a candidate connection node set.

[0050] The logical hierarchy of a tree structure (clock tree, reset tree, control signal distribution tree) refers to its hierarchical structure divided according to signal transmission paths and driving relationships. It extends gradually from the top level (signal source) to the bottom level (terminal execution unit / load). The higher the level number (or the later the level position), the farther the node is from the signal source and the closer it is to the terminal user (such as the newly added register 2). Among them, "deepest logical level" refers to the node corresponding to the level in the tree structure that is closest to the terminal load and farthest from the signal source; "second deepest logical level" refers to the node that is adjacent to the deepest level and second only to the deepest level. Both belong to the lower-level nodes in the tree structure that are close to the terminal.

[0051] For example, such as Figure 2-3 As shown, Figure 2 The newly added register (far right) can be understood as being connected to the next deepest candidate node. Figure 3 The newly added register can be understood as being connected to the candidate node at the deepest logical level.

[0052] Step S104b identifies the clock network source corresponding to the newly added register 2, then retrieves nodes that are logically equivalent to this source (i.e., have completely identical signal attributes and functions, with no logical inversion or functional addition / reduction). Subsequently, it filters out nodes located at the deepest or second-deepest level of the clock tree logic hierarchy, and summarizes these qualified nodes to form a set of candidate connection nodes that can be directly used for connection. By selecting nodes at the deepest or second-deepest level of the clock tree logic hierarchy, the transmission path of the clock signal from the source to the newly added register 2 can be shortened to the greatest extent, reducing signal delay, reducing clock signal skew, and aiding timing convergence. Simultaneously, it minimizes modifications to the original clock tree structure, avoiding disruption of the already stable timing system.

[0053] Step S104c: When the signal network type is a reset network, search in the tree structure for candidate nodes that are logically equivalent to the source point of the reset network corresponding to the newly added register 2, and gather all logically equivalent candidate nodes to form a candidate connection node set.

[0054] When the signal that the newly added register 2 needs to intervene in is the reset network, in the existing reset tree structure, all connection nodes that meet the logical equivalence condition with the source point of the reset network corresponding to the newly added register 2 are comprehensively searched. The logical level of the candidate nodes is not screened, eliminated or limited. All nodes with logical equivalence attributes are directly summarized and collected to form the candidate connection node set corresponding to the reset network.

[0055] In step S104c, since the design constraints of the reset signal on transmission delay and timing skew are much lower than those on the clock signal, there is no need to limit the node logic level; then, by fully including all logically equivalent nodes, the range of available connection points for the reset signal is expanded to the maximum extent, providing sufficient selection space for subsequent selection of connection nodes based on physical distance.

[0056] Step S104c can flexibly adapt to the access requirements of newly added register 2 in different areas of the chip layout, and facilitate the quick selection of the nearest node to complete the connection. Under the premise of ensuring the accuracy of the reset signal logic and the stability and reliability of the initialization control function, it shortens the wiring length, saves wiring resources, and does not change the overall architecture of the original reset tree throughout the process, effectively ensuring that the overall operating status of the original circuit is not affected by engineering change operations.

[0057] In some specific embodiments, step S108 specifically includes: Step S108a: When the signal network type is a clock network, select the candidate node that is closest in physical distance to the newly added register 2 as the target connection node 1; if there are multiple candidate nodes that are close in physical distance, select the candidate node with the deepest logical level as the target connection node 1.

[0058] In step S108a, based on the physical location of the newly added register 2 in the layout, the node closest to the newly added register 2 in terms of physical distance (Manhattan distance) is selected as the target connection node 1 from the candidate connection node set formed in step S104b (the deepest or second deepest in the clock tree logic level and logically equivalent to the source node of the clock network). If the search finds that there are multiple candidate nodes with the same physical distance to the newly added register 2, or the distance difference is within the preset threshold range (i.e., the physical distance is similar), then the candidate node located at the deepest in the clock tree logic level is selected as the final target connection node 1, based on the logic level as the secondary screening criterion, thus laying the foundation for the subsequent interconnection of the clock signal end of the newly added register 2.

[0059] Step S108a prioritizes selecting the candidate node with the closest physical distance, minimizing the transmission path of the clock signal from the target node to the newly added register 2. This effectively reduces clock signal insertion delay and timing skew, meeting the core design requirement of clock network timing convergence and avoiding problems such as timing errors and synchronization failures caused by excessively long transmission paths. When multiple candidate nodes with similar physical distances exist, selecting the node with the deepest logical level can further shorten the signal transmission link (the deepest level node is closer to the terminal load, and the actual wiring path from the physical location of the newly added register 2 is shorter). At the same time, it reduces disturbance to the original clock tree driving level, avoiding potential problems such as uneven driving load and signal attenuation caused by selecting higher-level nodes, and ensuring the stability and consistency of clock signal transmission.

[0060] Step S108b: When the signal network type is a reset network, directly select the candidate node that is closest in physical distance to the newly added register 2 as the target connection node 1.

[0061] In step S108b, when the signal required for the new register 2 to be connected is a reset signal (i.e., the signal network type is a reset network), there is no need to set additional complex screening conditions. The core judgment criterion is "closest physical distance". The candidate node that is closest to the new register 2 in terms of physical distance (calculated using Manhattan distance) is selected from the candidate nodes as the target connection node 1, and the line connection between the new register 2 and the target node is completed, ensuring that the connection operation is simple and efficient and meets the usage requirements of the reset network.

[0062] In embodiments of the present invention, such as Figure 1 As shown, the automatic connection optimization method for the newly added register 2 also includes: Step S110: Evaluate the total fan-out load of the target connected node 1 of the newly added register 2. If the total fan-out load exceeds the preset threshold, the drive capability optimization operation will be automatically executed.

[0063] The total fan-out load refers to the total load of all downstream circuits carried at the output of a signal-driven node within the chip's clock tree or reset tree.

[0064] In this embodiment, the preset threshold can be flexibly set according to the chip design.

[0065] In one embodiment, the drive capability optimization operation includes increasing the size of the buffer unit of the target connection node 1, or copying the driver of the target connection node 1 to share the load.

[0066] The core of the drive capability optimization operation is to address the issue of insufficient drive capability caused by the total fan-out load of the target connection node 1 exceeding the rated drive range after the addition of register 2. Two standardized and implementable engineering optimization methods are adopted to compensate for the drive margin of the target connection node 1, ensuring stable signal (clock signal or reset signal) transmission and meeting timing standards, without changing the original signal logic function or the overall topology of the clock tree and reset tree. This adapts to the core requirement of partial ECO modification of the chip. The two specific operation methods are as follows: The first optimization operation is to increase the size of the buffer unit driving the target connection node 1. As the core signal driving device of the target connection node 1, the size of the buffer unit (specifically the aspect ratio of the device in integrated circuit design) directly determines its driving capability. The larger the size, the stronger the output current capability of the device, and the more downstream loads it can drive. By increasing the size of this buffer unit, the driving capability of the target connection node 1 can be directly improved, offsetting the additional fan-out load after the addition of the new register 2, avoiding problems such as increased signal transmission delay, slow signal edge transition, and waveform distortion caused by insufficient driving, and ensuring that the signal can be transmitted stably and quickly to the new register 2. like Figure 4 As shown, the second optimization operation is to copy the driver of target connection node 1 for load sharing. The driver is the core driving device of target connection node 1, responsible for driving all its downstream fan-out loads. By copying one or more drivers with specifications and logic functions exactly the same as the original drivers, the copied drivers work in parallel with the original drivers, evenly distributing the total fan-out load of target connection node 1 to the original drivers and the copied drivers, thus achieving load sharing. This method can effectively reduce the load pressure on a single driver without changing the original driver size, ensuring that the load of each driver is controlled within the rated driving range, guaranteeing sufficient driving capability, and avoiding signal abnormalities caused by overload of a single driver, thus balancing the optimization effect with the stability of the original circuit structure. The two drive capability optimization operations mentioned above can be flexibly selected according to the load excess of the target connection node 1 and the chip layout resource margin. Both can quickly make up for the drive margin without destroying the original layout and routing design or changing the signal logic equivalence, ensuring the stability of the circuit function and timing convergence after the new register 2 is connected, and meeting the compliance requirements of the chip back-end physical design.

[0067] The automatic connection optimization method for the newly added register 2 of the present invention has the following technical effects: 1. Achieved full-process automation, greatly improving ECO efficiency: The algorithm automatically completes the optimal node search, connection and driver repair, completely replacing inefficient and error-prone manual operations. It can efficiently handle large-scale ECO scenarios, reducing processing time from the "day" level to the "minute" level, and significantly accelerating design iteration.

[0068] 2. Optimize timing convergence starting point through intelligent differentiation strategy: For timing-sensitive clock signals, a composite strategy of "logical equivalence + lower-level priority + nearest distance" is adopted to naturally align the clock insertion delay of the newly added register 2 with the existing balanced tree, providing the best starting point for subsequent timing convergence; a simplified strategy is adopted for reset signals, which reflects intelligent differentiation processing and takes into account both optimization effect and execution efficiency.

[0069] 3. Proactive load management and integrity assurance: Automatically checks and optimizes drive capability after connection, which can avoid secondary problems such as signal slope degradation and additional delay caused by increased fan-out, improve the first-time success rate and stability of the circuit after ECO modification, and avoid subsequent lengthy debugging and iteration.

[0070] 4. Maximize resource reuse and minimize design disturbances: By intelligently integrating new registers into the existing, optimized clock / reset tree structure, the area and power overhead of rebuilding a local tree for a small number of cells, as well as the disturbance to the surrounding stable layout and routing, are avoided.

[0071] The following detailed explanation of the automatic connection optimization method for the newly added register 2 in this application, with reference to a specific implementation method, is as follows: This embodiment applies to a chip module that has already completed clock tree synthesis (clock tree depth of 20 levels). Due to chip function upgrade requirements, 500 new registers need to be inserted into this module. Based on the ECO (Engineering Change) connection optimization method described in this invention, the specific implementation process is as follows, fully conforming to the technical flow described in the claims of this invention: First, in step S102 of this invention, the tool automatically reads the chip design database and ECO modification list, accurately identifies the 500 new registers to be inserted, and clarifies the clock network and reset network to which each new register belongs, laying the foundation for subsequent node selection and connection operations and ensuring the accuracy of the operation objects. Secondly, corresponding to steps S104-S106 of this invention, for the clock network of each new register, the tool searches for nodes logically equivalent to the source node of the clock network in the existing clock tree (tree depth 20 levels) of the chip. The filtering range is limited to levels 19 and 20 of the clock tree (i.e., the deepest level of the clock tree), forming a set of candidate nodes corresponding to each new register. Subsequently, the tool automatically calculates the Manhattan distance between each new register and the corresponding candidate node, strictly following the principle of "nearest distance priority, and deeper level priority when the distance is close", selecting a unique clock target node for each new register. Ultimately, the 500 new registers are connected to only about 40 clock nodes, achieving efficient centralized connection. For the reset network, the tool follows the method described in this invention, without additionally limiting the node level, and only selects nodes that are logically equivalent to the source point of the reset network as candidates. Similarly, based on the principle of prioritizing physical distance, it completes the selection of candidate nodes for the reset end of each new register (without considering the level depth, only ensuring logical consistency). Then, corresponding to step S108 of the present invention, the tool automatically performs the connection operation, connecting the clock and reset terminals of each new register to their respective selected target nodes, without any manual intervention, ensuring the standardization and efficiency of the connection operation. Finally, corresponding to step S110 of this invention, the tool automatically initiates a drive capability check and detects that among the dozens of connected target nodes, 18 nodes have fan-out loads exceeding their drivers' rated drive capabilities. To address this issue, the tool automatically performs adjustments according to the drive optimization scheme described in this invention: for 12 of these nodes, their original drivers are replaced with units of the same type but with stronger drive capabilities (i.e., increasing the buffer unit size to improve drive capability); for the remaining 6 nodes with extremely high fan-out load concentration, a driver with specifications and logic functions completely identical to the original driver is copied, and the original load is evenly distributed between the two drivers to achieve load sharing. In this embodiment, the entire ECO connection optimization process is executed fully automatically, with the total time controlled within 5 minutes. Subsequent static timing analysis verified that the average difference between the clock insertion delay of all new registers and the original registers is controlled within 15ps, with no setup time, hold time violations, or maximum fan-out violations. It meets the timing requirements and electrical rules of the chip design in one go, perfectly realizing the fast and stable access of the new registers, and fully demonstrating the efficiency, stability, and practicality of the method of this invention.

[0072] This invention also provides an automatic connection optimization system for a newly added register 2 in chip logic ECO, including a register identification module, a candidate node search module, a physical distance calculation module, and a target node connection module. The register identification module identifies the newly added register 2 that needs to be inserted into the existing layout and routing design in the engineering change instruction; the candidate node search module searches the tree structure of the existing layout and routing design for a set of candidate connection nodes that are logically equivalent to the network source point corresponding to the newly added register 2. The candidate connection node set includes at least one candidate node, and logical equivalence means that the candidate node has the same logical function as the network source point corresponding to the newly added register 2; the physical distance calculation module calculates the physical distance between the physical location of the newly added register 2 and each candidate node in the candidate connection node set; the target node connection module selects the candidate node with the closest physical distance to the newly added register 2 as the target connection node 1 and connects the corresponding signal terminal of the newly added register 2 to the target connection node 1.

[0073] Furthermore, the candidate node search module includes a network type determination unit, a clock candidate filtering unit, and a reset candidate filtering unit. The network type determination unit is used to determine the signal network type of the newly added register 2, which is either a clock network or a reset network. The clock candidate filtering unit is used to search for candidate nodes in the tree structure that are logically equivalent to the source point of the clock network corresponding to the newly added register 2 when the signal network type is a clock network, and to include the candidate nodes located at the deepest or second deepest logical level of the tree structure to form a candidate connection node set. The reset candidate filtering unit is used to search for candidate nodes in the tree structure that are logically equivalent to the source point of the reset network corresponding to the newly added register 2 when the signal network type is a reset network, and to include all logically equivalent candidate nodes to form a candidate connection node set.

[0074] Furthermore, the target node connection module is also configured to select the candidate node with the closest physical distance to the newly added register 2 as the target connection node 1 when the signal network type is a clock network; if there are multiple candidate nodes with similar physical distances, select the candidate node with the deepest logical level as the target connection node 1; when the signal network type is a reset network, directly select the candidate node with the closest physical distance to the newly added register 2 as the target connection node 1.

[0075] In some preferred embodiments, the system further includes a drive capability evaluation and optimization module, which is used to evaluate the total fan-out load of the target connected node 1 connected to the newly added register 2. If the total fan-out load exceeds a preset threshold, the drive capability optimization operation is automatically performed.

[0076] The drive capability optimization operation includes increasing the size of the buffer unit driving the target connection node 1, or copying the driver of the target connection node 1 to share the load.

[0077] In some embodiments, a computer device may be provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the automatic connection optimization method for the newly added register 2 in the above embodiments.

[0078] This specification also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a computer, causes the computer to perform the automatic connection optimization method for the newly added register 2 in any of the above embodiments.

[0079] This specification also provides a computer program product containing instructions that, when executed by a computer, cause the computer to perform the automatic connection optimization method for the newly added register 2 in any of the above embodiments.

[0080] In one embodiment, a computer device is provided, which may be a terminal. The computer device includes a processor, memory, and a communication interface connected via a system bus. The processor of the computer device provides computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The communication interface of the computer device is used for wired or wireless communication with an external terminal; wireless communication can be achieved through Wi-Fi, carrier networks, NFC (Near Field Communication), or other technologies. When the computer program is executed by the processor, it implements the automatic connection optimization method for the newly added register 2.

[0081] It is understood that the specific examples in this document are only intended to help those skilled in the art better understand the embodiments described herein, and are not intended to limit the scope of the invention.

[0082] It is understood that the various implementation methods described in this specification can be implemented individually or in combination, and the implementation methods in this specification are not limited in this respect.

[0083] It is understood that the processor in the embodiments of this specification can be an integrated circuit chip with signal processing capabilities. In implementation, each step of the above method embodiments can be completed by the integrated logic circuits in the processor's hardware or by instructions in software form. The processor can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this specification. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this specification can be directly implemented by a hardware decoding processor, or by a combination of hardware and software modules in the decoding processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory; the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method.

[0084] It is understood that the memory in the embodiments of this specification may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. Non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory may be random access memory (RAM). It should be noted that the memory in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0085] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this specification.

[0086] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the aforementioned method implementations, and will not be repeated here.

[0087] In the several embodiments provided in this specification, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0088] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment, depending on actual needs.

[0089] In addition, the functional units in the various embodiments of this specification can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0090] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of this specification, in essence, or the parts that contribute to the prior art, or parts of the technical solutions, can be embodied in the form of software products. These computer software products are stored in a storage medium and include several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this specification. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0091] In this specification, the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, for the product embodiments described later, since they correspond to the methods, the descriptions are relatively simple, and the relevant parts can be referred to the descriptions in the system embodiments.

[0092] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for automatically linking and optimizing newly added registers, characterized in that, include: Identify new registers that need to be inserted into the existing layout and routing design in engineering change instructions; In the tree structure of the existing layout and routing design, a set of candidate connection nodes that are logically equivalent to the network source point corresponding to the newly added register is searched. The set of candidate connection nodes includes at least one candidate node. Logical equivalence means that the candidate node has the same logical function as the network source point corresponding to the newly added register. Calculate the physical location of the newly added register and the physical distance between it and each of the candidate nodes in the candidate connection node set; The candidate node that is physically closest to the newly added register is selected as the target connection node, and the corresponding signal terminal of the newly added register is connected to the target connection node. The total fan-out load of the target connection node connected to the newly added register is evaluated. If the total fan-out load exceeds a preset threshold, a drive capability optimization operation is automatically performed. The drive capability optimization operation includes increasing the size of the buffer unit driving the target connection node or copying the driver of the target connection node to share the load. In the existing tree structure of the layout and routing design, the search for the set of candidate connection nodes logically equivalent to the network source node corresponding to the newly added register includes: Determine the signal network type of the newly added register, wherein the signal network type is either a clock network or a reset network; When the signal network type is a clock network, the candidate node that is logically equivalent to the clock network source point corresponding to the newly added register is searched in the tree structure, and the candidate nodes located at the deepest or second deepest logical level of the tree structure are gathered to form the candidate connection node set. When the signal network type is a reset network, a candidate node logically equivalent to the reset network source point corresponding to the newly added register is searched in the tree structure, and all the logically equivalent candidate nodes are gathered to form the candidate connection node set.

2. The method according to claim 1, characterized in that, Using the candidate node that is physically closest to the newly added register as the target connection node, and connecting the corresponding signal terminal of the newly added register to the target connection node includes: When the signal network type is a clock network, the candidate node that is closest in physical distance to the newly added register is selected as the target connection node; if there are multiple candidate nodes that are close in physical distance, the candidate node with the deepest logical level is selected as the target connection node. When the signal network type is a reset network, the candidate node that is closest in physical distance to the newly added register is directly selected as the target connection node.

3. A newly added register automatic connection optimization system, characterized in that, include: The register identification module is used to identify new registers that need to be inserted into the existing layout and routing design in engineering change instructions; The candidate node search module is used to search for a set of candidate connection nodes that are logically equivalent to the network source point corresponding to the newly added register in the tree structure of the existing layout and routing design. The set of candidate connection nodes includes at least one candidate node. The logical equivalence means that the candidate node has the same logical function as the network source point corresponding to the newly added register. The physical distance calculation module is used to calculate the physical distance between the physical location of the newly added register and each of the candidate nodes in the candidate connection node set; The target node connection module is used to select the candidate node that is closest to the new register in terms of physical distance as the target connection node, and connect the corresponding signal terminal of the new register to the target connection node; The drive capability evaluation and optimization module is used to evaluate the total fan-out load of the target connection node connected to the newly added register. If the total fan-out load exceeds a preset threshold, the drive capability optimization operation is automatically executed. The candidate node search module includes: A network type determination unit is used to determine the signal network type of the newly added register, wherein the signal network type is a clock network or a reset network; The clock candidate filtering unit is used to search for candidate nodes in the tree structure that are logically equivalent to the clock network source point corresponding to the newly added register when the signal network type is a clock network, and to include the candidate nodes located at the deepest or second deepest logical level of the tree structure to form the candidate connection node set. The reset candidate filtering unit is used to search in the tree structure for candidate nodes that are logically equivalent to the reset network source point corresponding to the newly added register when the signal network type is a reset network, and to include all the logically equivalent candidate nodes to form the candidate connection node set.

4. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the automatic connection optimization method for newly added registers as described in any one of claims 1 to 2.

5. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the automatic connection optimization method for the newly added registers as described in any one of claims 1 to 2.

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