A SOC chip on-chip power management structure and control method

Abstract

The application discloses a SOC chip on-chip power management structure and a control method. The structure and the control method comprise a global control core module, an array distribution power supply module, a bottom layer bias adjustment module and a target area temperature sensor; the global control core module is electrically connected with the array distribution power supply module and the bottom layer bias adjustment module; the global control core module is internally provided with an instruction decoding sniffer and a power consumption state lookup table; the array distribution power supply module is physically inserted between each operation sub-cluster; and the bottom layer bias adjustment module comprises an independent well region isolation structure and is connected with a bottom substrate bias driver. The application can extract a pipeline instruction to pre-sense a power consumption mutation point, establish sufficient charge reserves, relieve transient voltage drop phenomena, satisfy timing requirements under high heat density by using a transistor body bias, and improve power supply and calculation stability.

Description

Technical Field

[0001] This invention relates to an on-chip power management structure and control method for a System-on-Chip (SoC). This application relates to the field of semiconductor integrated circuit design technology, and specifically to an on-chip power management structure and control method applied to autonomous driving SoC chips with high-performance neural network processors. Background Technology

[0002] Autonomous driving vision processing SOC chips typically integrate multiple parallel computing neural processing unit arrays. When handling sudden road condition target recognition tasks, the neural processing unit array needs to switch from a clock-gated idle state to a full tensor operation state within several clock cycles.

[0003] This abrupt state transition can cause transient current surges in the on-chip power supply network. Existing on-chip power management units primarily rely on proportional-integral-derivative feedback control based on digital codes acquired by a voltage monitor. Due to the inherent delay in the feedback loop, a deep voltage drop occurs at local nodes when a transient current occurs. If the drop reaches the data hold limit of the triggers, it can lead to data flip-flops or even system resets. While using global dynamic voltage and frequency regulation to pre-boost the overall chip voltage can mitigate the voltage drop, in advanced processes of 7nm and below, global boosting leads to an exponential increase in leakage current and power consumption, exacerbating local hotspot accumulation and creating thermal dissipation bottlenecks. Currently, it is difficult to effectively address the response lag problem of closed-loop feedback mechanisms in dealing with transient current surges, and it is also difficult to overcome the local thermal runaway defects caused by global boosting. Summary of the Invention

[0004] This application provides an on-chip power management structure and control method for a SOC chip to overcome the problems of lag response in existing closed-loop feedback mechanisms and thermal runaway caused by global boost.

[0005] This application provides an on-chip power management structure for a System-on-a-Chip (SoC), including a global control core module, an array distributed power supply module, a low-level bias adjustment module, and a target area temperature sensor. The global control core module is electrically connected to both the array distributed power supply module and the low-level bias adjustment module. The global control core module contains an instruction decoding sniffer and a power status lookup table. The array distributed power supply module consists of an array of digital low-dropout linear regulators, physically interspersed among the various operational subclusters of a neural processing unit. The low-level bias adjustment module includes an independent well isolation structure covering each operational subcluster and is connected to a substrate bias driver. The target area temperature sensor is located within the corresponding operational subcluster.

[0006] This application also provides a control method based on the above-mentioned on-chip power management structure of SOC chip, including reading the pipeline to parse the opcode, calculating the transient power consumption prediction value according to the power consumption state lookup table and outputting a warning signal when the high computing power continuous execution condition is met; after receiving the warning signal, directly forcibly turning on the corresponding number of power transistors in the digital low dropout linear regulator array according to the digital code corresponding to the transient power consumption prediction value; when the target area temperature sensor detects that the junction temperature exceeds the preset temperature threshold T, cutting off the boost path of the digital low dropout linear regulator array, and applying the target body bias voltage to the independent well isolation structure of the transistor through the substrate bias driver, wherein T is configured to 85°C.

[0007] By extracting pipeline instructions to anticipate power consumption spikes, sufficient charge reserves can be built up before current spikes occur, mitigating transient voltage drops. Furthermore, by utilizing the spatial and temporal physical coordination of transistor body bias and voltage regulator array, timing requirements are met when facing localized high heat density, improving the stability of power supply and computation. Attached Figure Description

[0008] Figure 1 This is a schematic diagram of the overall structure of the on-chip power management structure of the SOC chip provided in the embodiment of the present invention.

[0009] Figure 2 This is a logic block diagram of the on-chip power management structure of the SOC chip provided in the embodiment of the present invention.

[0010] Figure 3 This is a flowchart of the control method provided in an embodiment of the present invention.

[0011] Explanation of reference numerals in the attached figures:

[0012] In the diagram: 101-Global control core module, 102-Array distributed power supply module, 103-Bottom bias adjustment module, 104-Target area temperature sensor, 105-Neural processing unit, 106-Arithmetic sub-cluster, 107-Bottom metal wiring layer, 108-Top metal wiring layer, 110-Reference temperature sensor acquisition circuit, 111-Polysilicon deep trench isolation structure, 112-Isolation island, 201-Instruction decoding sniffer, 202-Power state lookup table, 203-Substrate bias driver, 204-Independent well isolation structure, 205-Deep N-well structure, 206-P-type buried layer structure, 207-Pipeline mounting interface, 208-Power transistor driver register, 209-Power supply contact. Detailed Implementation

[0013] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0014] This embodiment is based on advanced process nodes, particularly for chip processes of 7nm and below. At this microscale, leakage current is sensitive to local junction temperature, and conventional large-area global pull-up of source-drain voltage can easily induce leakage positive feedback, generating uncontrollable hot spots. Therefore, this embodiment provides a hardware scheduling scheme based on instruction prediction and body bias coordination.

[0015] Figure 1 This is a schematic diagram of the overall structure of the on-chip power management structure of the SOC chip provided in an embodiment of the present invention. Figure 1 As shown, this application provides an on-chip power management structure for a System-on-a-Chip (SoC). This structure mainly includes a global control core module 101, an array-distributed power supply module 102, a low-level bias adjustment module 103, and a target area temperature sensor 104. The global control core module 101 is the central decision-making brain of the entire on-chip power network. Its hardware is constructed using a dedicated logic processing unit and is directly electrically connected to the array-distributed power supply module 102 and the low-level bias adjustment module 103, respectively. The neural processing unit 105 constitutes a high-density computing core, internally divided into multiple parallel operation sub-clusters 106 for performing matrix and vector calculations. The target area temperature sensor 104 is embedded and located within the corresponding operation sub-cluster 106 to collect the junction temperature of the local semiconductor material. Through the target area temperature sensor 104, the thermal field distribution can be converted into readable electrical parameters.

[0016] As a foundational closed loop for achieving a complete on-chip operating environment, the system also includes an on-chip reference clock signal generator and a reference temperature sensor acquisition circuit 110. The on-chip reference clock signal generator provides the on-chip reference clock signal and synchronization interface through a global tree network, ensuring that the operation of the global control core module 101 is fully phase-locked with the execution cycle of the neural processing unit 105. The reference temperature sensor acquisition circuit 110 provides the necessary analog-to-digital conversion and calibration bias reference for the target area temperature sensor 104, ensuring accurate reading of the junction temperature even under transient noise interference.

[0017] The array distributed power supply module 102 does not employ a single macrocell design, but rather a segmented structure. Specifically, the array distributed power supply module 102 consists of an array of 32 digital low-dropout linear regulators. This array is physically interspersed in a distributed grid pattern between the bottom metal wiring layer 107 and the top metal wiring layer 108 of the neural processing unit 105. The top metal wiring layer 108 is preferably an M11 / M12 metal wiring layer in an advanced process, forming a power supply grid through on-chip top-level wiring. The bottom metal wiring layer 107 is closer to the active region of the standard cell. The bottom bias adjustment module 103 includes an independent well region isolation structure covering each sub-cluster 106 and forms an isolation island 112 with physical boundaries in the semiconductor substrate. The substrate bias driver establishes an electrical connection with the isolation island 112 through a polysilicon deep trench isolation structure 111, thereby forming an interconnect feedback network on the bottom metal wiring layer 107. By combining grid-like physical interleaving with deep trench isolation, high-frequency transient currents can be spatially sliced ​​and decomposed, significantly reducing the parasitic impedance of individual power supply nodes, thereby reducing dynamic voltage drop under large transient loads.

[0018] Figure 2 This is a logic block diagram of the on-chip power management structure of the SOC chip provided in an embodiment of the present invention. For example... Figure 2 As shown, in Figure 1 Building upon this foundation, the logical connection details of the global control core module 101 and its underlying structure are further revealed. The global control core module 101 internally contains a hardwired instruction decoding sniffer 201 and a power state lookup table 202. The instruction decoding sniffer 201 is equipped with a pipelined mounting interface 207 for bypassing the reading of instruction fetch cycle data from the neural processing unit 105. The power state lookup table 202 is composed of a static random access memory array with a two-dimensional index architecture, containing transient power prediction value entries mapped to different opcodes and toggle rates. This structure does not intrude on the original instruction dispatch logic of the neural processing unit 105, thus enabling the detection of the power consumption characteristics of the task to be executed without performance loss.

[0019] Furthermore, the underlying bias adjustment module 103 includes a substrate bias driver 203 and an independent well isolation structure 204. The independent well isolation structure 204 specifically includes a deep N-well structure 205 and a P-type buried layer structure 206. Each digital low-dropout linear regulator node of the array distributed power supply module 102 is radially metal-bonded to the power supply contacts 209 of at least four operational subclusters 106, shortening the charging and discharging distance from the regulator to the load. The substrate bias driver 203 is internally configured with a positive body bias network and a negative body bias network. The positive body bias network forms an ohmic contact with the deep N-well structure 205, and the negative body bias network is connected to the P-type buried layer structure 206 through metal contact holes in the highly doped region. The establishment of the ohmic contact effectively eliminates the barrier voltage drop when the bias drive signal is injected into the well region, ensuring the linearity of the body bias voltage transmission.

[0020] Figure 3 This is a flowchart of the control method provided in an embodiment of the present invention. Figure 3 As shown, this control method is applied to the aforementioned on-chip power management structure of the SOC chip. This method is executed at the pure hardware level and specifically includes the following steps:

[0021] Step S301: Read the pipeline to parse the opcode. When the high computing power continuous execution condition is met, calculate the transient power consumption prediction value according to the power consumption status lookup table 202 and output the warning signal.

[0022] Specifically, the instruction decoding sniff 201 continuously intercepts the current instruction fetching phase data of the neural processing unit 105 through the pipeline mounting interface 207. The hardware parsing logic inside the sniff extracts the opcode of the instruction to be executed and extracts the flip-flop rate feature corresponding to the operand. Meeting the conditions for high-performance continuous execution specifically includes: within a preset time window, the instruction decoding sniff 201 continuously detects a sequence of multiply-accumulate operation instructions involved in the sudden traffic condition recognition task. In this embodiment, the continuous queuing cycle depth threshold is configured to 16 instructions. Once a high-density multiply-accumulate task satisfying the above 16 consecutive instructions is identified, the system determines that a sudden high power consumption is about to occur.

[0023] After determining the high computing power warning, the global control core module 101 extracts the operand bit width information to form a combined index, which is then input into the power state lookup table 202 with a two-dimensional index architecture. The global control core module 101 calculates the transient power consumption prediction value based on the physical product relationship of the switching rate factor, equivalent switched capacitor, supply voltage, and requested frequency. Specifically, the system performs a multiplication operation on the above four variables. In one embodiment, the above calculation logic is implemented through the following formula:

[0024]

[0025] Among them, P transientRepresents the predicted transient power consumption; α represents the instruction-level toggle factor; C eff V represents the physical parameters of the equivalent switched capacitor of the target sub-cluster 106; dd Indicates the source-drain supply voltage; f req Indicates the target requested clock frequency.

[0026] The value of α differs fundamentally for different instruction types. Based on the mapping in the power state lookup table 202, α is set to 0.85 for high-density matrix multiplication and addition instructions, while it is set to 0.15 for ordinary arithmetic and scalar control instructions. Based on this formula, the system calculates and outputs a digital code representing the power transistor's on-state ratio. To provide a buffer time for the underlying charging and discharging process, the instruction decoding sniffer 201 is configured to intercept the opcode output warning signal in the computation pipeline a preset number of N clock cycles, where N is 15. This 15-clock-cycle advance prediction provides a sufficient buffer window for the subsequent microsecond-level charging and discharging of the silicon well parasitic capacitance.

[0027] Step S302: After receiving the warning signal, the corresponding number of power transistors in the digital low-dropout linear regulator array are forcibly turned on directly according to the digital code corresponding to the transient power consumption prediction value.

[0028] Specifically, during the pre-power-on execution phase, the digital low-dropout linear regulator array employs a non-uniform phase sequence conduction structure, with each digital low-dropout linear regulator containing 256 parallel PMOS power transistors. Conventional closed-loop control requires bit-by-bit approximation. In this scheme, after receiving the digital code, the gate control terminal of the regulator array skips the closed-loop voltage feedback approximation process and directly injects the pre-extracted digital code into the internal power transistor drive register 208. Within a set extremely short timing window, the hardware circuit forces the corresponding number of parallel PMOS power transistors to turn on according to the weight of the digital code. By directly forcing the power transistors to turn on based on the power consumption prediction digital code, the response lag caused by proportional-integral-derivative closed-loop control is overcome, and sufficient charge reserves are established before a current drop occurs.

[0029] In step S303, when the target area temperature sensor 104 detects that the junction temperature exceeds the preset temperature threshold T, the boost path of the digital low dropout linear regulator array is cut off, and the target body bias voltage is applied to the independent well isolation structure 204 of the transistor through the substrate bias driver 203.

[0030] When the neural processing unit 105 operates for an extended period, the temperature collected by the target area temperature sensor 104 continuously increases. When the junction temperature exceeds a preset temperature threshold T (wherein the preset temperature threshold T represents the physical limit of the junction temperature at which the hot carrier effect of the transistor intensifies, and is specifically configured to be 85°C), the hot carrier effect intensifies dramatically. If the voltage V is further increased at this point...dd This can lead to runaway leakage current and power consumption. Based on this physical limitation, the global control core module 101 actively intervenes and cuts off the boost path of the digital low-dropout linear regulator after reaching this threshold. Subsequently, the substrate bias driver 203 intervenes, applying a forward body bias voltage of 0.3V to 0.5V to the P-type buried structure 206 and P-well of the NMOS transistor through its forward body bias network; simultaneously, it applies a voltage relative to the source-drain voltage V to the deep N-well structure 205 of the PMOS transistor through its reverse body bias network. dd A low reverse body bias voltage of 0.3V. By actively applying forward and reverse body bias voltages, the threshold voltage for transistor turn-on can be directly and physically reduced. This allows the switching speed of the transistor to be improved even when the supply voltage cannot be pulled up due to hot carrier thermal walls, thereby meeting the timing tolerance required for high-performance computing.

[0031] It should be noted that the specific parameters regarding the threshold, voltage range, and number of components mentioned above are merely best-example configurations under a specific architecture. Those skilled in the art can scale the feedforward constant N or the bias voltage value proportionally according to the actual chip area and heat dissipation process. As long as the technical objective of coordinated feedforward sniffing and underlying body bias is achieved, it is covered within the scope of protection of this application.

[0032] Based on the aforementioned hardware circuitry and method steps, this application further provides a device system for integrating and embodying the aforementioned management and control logic. This system includes a memory and an external monitoring processor. When the external monitoring processor reads and executes the microcode firmware in the memory, it configures and coordinates the aforementioned instruction decoding sniffer 201, substrate bias driver 203, and voltage regulator array, thereby fully realizing global scheduling steps such as forward prediction and underlying volume bias adjustment.

[0033] In summary, the embodiments of this application achieve nanosecond-level charge storage before current surges by pre-sensing power consumption abrupt changes through instruction extraction, skipping the approximation cycle of traditional voltage feedback. Simultaneously, by pre-detecting and reserving microsecond-level charging and discharging buffers for the body bias, it achieves coordinated response times of different orders of magnitude. Through the physical coordination of transistor body bias and the voltage regulator array, timing compensation is achieved without increasing node thermal density when a local critical thermal threshold is reached. The deep coupling of these two elements in both time and space effectively overcomes the thermal limitations encountered by single dynamic voltage control, achieving excellent power supply stability under high-density computing across all scenarios.

[0034] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. An on-chip power management structure for a System-on-a-Chip (SOC) chip, characterized in that, This includes a global control core module, an array distributed power supply module, a low-level bias adjustment module, and a target area temperature sensor; The global control core module is electrically connected to the array distributed power supply module and the underlying bias adjustment module, respectively. The global control core module is equipped with an instruction decoding sniffer and a power status lookup table. The array distributed power supply module consists of an array of digital low-dropout linear regulators, which are physically interspersed among the various operational subclusters of a neural processing unit. The underlying bias adjustment module includes an independent well region isolation structure covering each of the operational subclusters and is connected to the substrate bias driver; The target area temperature sensor is located within the corresponding computational sub-cluster.

2. The on-chip power management structure of the SOC chip as described in claim 1, characterized in that, The digital low-dropout linear regulator array in the array distributed power supply module is physically interspersed in a distributed grid between a bottom metal wiring layer and a top metal wiring layer of the neural processing unit; the independent well isolation structure in the bottom bias adjustment module forms an isolation island with physical boundaries in a semiconductor substrate, and the substrate bias driver establishes an electrical connection with the isolation island through a polysilicon deep trench isolation structure, and forms an interconnected feedback network in the bottom metal wiring layer.

3. The on-chip power management structure of the SOC chip as described in claim 1, characterized in that, The instruction decoding sniffer in the global control core module is configured with a pipelined mounting interface to bypass the reading of the instruction fetch cycle data of the neural processing unit; the power state lookup table is composed of a static random access memory array with a two-dimensional index architecture, containing transient power prediction value entries mapped to different opcodes and flip rates.

4. The on-chip power management structure of the SOC chip as described in claim 3, characterized in that, The instruction decoding sniffer is configured to intercept the opcode in the computation pipeline for a preset number of N clock cycles, and extract the operand bit width information to form a combined index and input it into the power state lookup table, wherein the value of N is 15; the power state lookup table outputs a digital code representing the power transistor on-state ratio to the gate control terminal of the digital low dropout linear regulator array based on the combined index.

5. A control method for an on-chip power management structure of a SOC chip, applied to the on-chip power management structure of an SOC chip as described in claim 1, characterized in that, This includes reading the pipeline to parse the opcode; when the high computing power continuous execution condition is met, calculating the transient power consumption prediction value according to the power consumption state lookup table and outputting a warning signal; upon receiving the warning signal, directly forcibly turning on the corresponding number of power transistors in the digital low dropout linear regulator array according to the digital code corresponding to the transient power consumption prediction value; when the target area temperature sensor detects that the junction temperature exceeds the preset temperature threshold T, cutting off the boost path of the digital low dropout linear regulator array, and applying a target body bias voltage to the independent well isolation structure of the transistor through the substrate bias driver, wherein T is configured to be 85°C.

6. The control method for the on-chip power management structure of an SOC chip as described in claim 5, characterized in that, The read pipeline is configured to intercept the current instruction fetch stage data of the neural processing unit by parsing opcodes and extract the flip rate features corresponding to the operands; the condition for satisfying high computing power continuous execution includes continuously detecting the multiply-accumulate operation instruction sequence involved in the sudden road condition recognition task within a preset time window.

7. The control method for the on-chip power management structure of an SOC chip as described in claim 6, characterized in that, The configuration of directly forcibly turning on a corresponding number of power transistors in the digital low-dropout linear regulator array based on the digital code corresponding to the transient power consumption prediction value is to skip the closed-loop voltage feedback approximation process. The pre-extracted digital code is directly injected into the power transistor drive register, and the start-up operation of the specified array node is completed within the set timing window.

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