Adaptive pre-emphasis LVDS circuit and method

Abstract

This invention discloses an adaptive pre-emphasis LVDS circuit, including a driving unit and an adaptive logic unit. The driving unit includes a first differential output terminal out_p and a second differential output terminal out_n. The adaptive logic unit includes a comparator, a logic module, and a current bias module connected in sequence. The first differential output terminal out_p is connected to the positive input terminal of the comparator, and the current bias module is connected to the driving unit. This invention also discloses an adjustment method for the adaptive pre-emphasis LVDS circuit. The adaptive pre-emphasis LVDS circuit and method disclosed in this invention solve the problem of high power consumption redundancy of the fixed pre-emphasis current in the prior art when the channel conditions are good or the data transmission rate is low.

Description

Technical Field

[0001] This invention belongs to the field of interface circuit simulation technology, specifically relating to an adaptive pre-emphasis LVDS circuit, and also to a method for adjusting the circuit. Background Technology

[0002] LVDS (Low Voltage Differential Signaling) technology features low voltage swing and differential signal transmission, offering advantages such as high transmission rate, low power consumption, strong common-mode interference immunity, and excellent signal integrity. Its low drive current and low electromagnetic radiation enable stable signal transmission during high-speed data transmission, making it suitable for long-distance and high-speed interconnection scenarios. It is widely used in displays, image sensing, and high-speed interfaces, balancing energy efficiency and reliability. With the continuous development of IoT technology, higher demands are being placed on the data transmission rate of LVDS interface circuits. Under high-speed transmission conditions, high-frequency attenuation and inter-symbol interference (ISI) become increasingly prominent, severely impacting signal quality.

[0003] Pre-emphasis technology is an effective means to improve the data transmission rate of LVDS circuits by injecting additional drive current during signal transitions to compensate for high-frequency losses in the transmission link. However, traditional pre-emphasis technology usually uses a fixed pre-emphasis current, the magnitude of which is determined during the design based on the worst-case channel conditions. When the channel conditions are good or the data transmission rate is low, this will result in a large power redundancy, making it difficult to effectively improve the power utilization efficiency of LVDS circuits while ensuring signal quality. Summary of the Invention

[0004] The first objective of this invention is to provide an adaptive pre-emphasis LVDS circuit that solves the problem of high power consumption redundancy of the fixed pre-emphasis current in the prior art when the channel conditions are good or the data transmission rate is low.

[0005] A second objective of this invention is to provide an adjustment method for an adaptive pre-emphasis LVDS circuit.

[0006] The first technical solution adopted in this invention is an adaptive pre-emphasis LVDS circuit, including a driving unit and an adaptive logic unit; the driving unit includes a first differential output terminal out_p and a second differential output terminal out_n; the adaptive logic unit includes a comparator, a logic module and a current bias module connected in sequence; the first differential output terminal out_p is connected to the positive input terminal of the comparator, and the current bias module is connected to the driving unit.

[0007] The first technical solution of this invention is also characterized by, The adaptive logic unit also includes the output voltage pre_vbp terminal and pre_vbn terminal; the driving unit also includes PMOS transistor M9 and NMOS transistor M6; the pre_vbp terminal is connected to the gate of PMOS transistor M9, and the pre_vbn terminal is connected to the gate of NMOS transistor M6.

[0008] The driving unit also includes PMOS transistors M1, M2, M8, and M10, and NMOS transistors M3, M4, M5, and M7; The source of PMOS transistor M10 is connected to VDD, the gate is connected to the bias voltage vbp, and the drain is connected to the source of M1 and M2; the source of PMOS transistor M9 is connected to VDD, and the drain is connected to the source of PMOS transistor M8; the gate of PMOS transistor M8 is connected to the Pre_ep terminal with pre-emphasis enable signal, and the drain is connected to the source of M1 and M2. The gate of PMOS transistor M1 is connected to the data signal terminal (data_n), and its drain is connected to the drain of NMOS transistor M3; the gate of NMOS transistor M3 is connected to the data signal terminal (data_n), and its source is connected to the drains of M5 and M7; the gate of PMOS transistor M2 is connected to the data signal terminal (data_p), and its drain is connected to the drain of NMOS transistor M4; the gate of NMOS transistor M4 is connected to the data_p terminal, and its source is connected to the drains of M5 and M7. The gate of NMOS transistor M5 is connected to the pre-emphasis enable signal Pre_en, and its source is connected to the drain of NMOS transistor M6. The source of NMOS transistor M6 is connected to GND. The gate of NMOS transistor M7 is connected to the bias voltage vbn, and its source is connected to GND.

[0009] The adaptive logic unit also includes switch S1, switch S2, capacitor C1, and current bias module; The negative input of the comparator is connected to a reference voltage Vref. The input of the logic module Logic is connected to a reference clock REFCLK. The first output of the logic module Logic is connected to the control terminal of the first switch S1. One end of the first switch S1 is connected to VDD, and the other end is connected to capacitor C1. The second output of the logic module Logic is connected to the control terminal of the second switch S2. One end of the second switch S2 is connected to GND, and the other end is connected to capacitor C1. The lower end of capacitor C1 is connected to GND. Capacitor C1 is connected to the input terminal of the current bias module and serves as the control voltage Vref. C end.

[0010] The current bias module includes a resistor R1, an operational amplifier AMP, PMOS transistors M11 and M12, and an NMOS transistor M13; The non-inverting input of the operational amplifier AMP is connected to the control voltage V. CThe inverting input terminal is connected to the output terminal of the operational amplifier, the drain and gate of PMOS transistor M11, the gate of PMOS transistor M12, and one end of resistor R1. The gate of PMOS transistor M11 is connected to the gate of PMOS transistor M12, and the other end of resistor R1 is connected to GND. The source of PMOS transistor M11 is connected to VDD. The source of PMOS transistor M12 is connected to VDD. The connection point between the drain and gate of NMOS transistor M13 is connected to the drain of PMOS transistor M12, and the source of NMOS transistor M13 is connected to GND.

[0011] The node where the inverting input and output terminals of the operational amplifier AMP, the drain and gate of PMOS transistor M11, the gate of PMOS transistor M12, and one end of resistor R1 are connected together is the pre_vbp terminal; the node where the drain of PMOS transistor M12 and the drain and gate of NMOS transistor M13 are connected together is the pre_vbn terminal.

[0012] The second technical solution adopted in this invention is an adjustment method for an adaptive pre-emphasis LVDS circuit. Using the aforementioned adaptive pre-emphasis LVDS circuit, the method includes the following steps: comparing the voltage at the output terminal out_p of the driving unit with the reference voltage Vref using a comparator; and adjusting the control voltage Vref by controlling the conduction state of switch S1 or S2 according to the timing relationship between the comparison result and the reference clock REFCLK. C This allows for adjustment of the pre-weighting current.

[0013] The second technical solution of the present invention is further characterized in that, When the falling edge of the comparator output signal cmp_out precedes the falling edge of the reference clock REFCLK, the logic module controls the second switch S2 to turn on, pulling the control voltage V low. C This reduces the pre-emphasis current, causing the voltage at the first differential output terminal out_p of the drive unit to drop to the reference voltage Vref.

[0014] When the falling edge of the comparator output signal cmp_out lags behind the falling edge of the reference clock REFCLK, the logic module controls the first switch S1 to turn on, pulling up the control voltage V. C Increase the pre-emphasis current to raise the voltage at the first differential output terminal out_p of the drive unit to the reference voltage Vref.

[0015] The beneficial effects of this invention are: The adaptive pre-emphasis LVDS interface circuit and method proposed in this invention monitors the output voltage of the driving unit through a comparator, and the logic module adaptively adjusts the pre-emphasis current according to the timing relationship between the output voltage and the reference clock. This allows the pre-emphasis current to dynamically match the data transmission rate and channel conditions, solving the problem of high power redundancy of traditional fixed pre-emphasis current when the channel conditions are good or the data transmission rate is low, and significantly improving power utilization efficiency. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the adaptive pre-emphasis LVDS circuit of the present invention; Figure 2 This is a schematic diagram of the current bias module of the present invention; Figure 3 This is a schematic diagram of the first operating state of the adaptive pre-emphasis LVDS circuit of the present invention; Figure 4 This is a schematic diagram of the second operating state of the adaptive pre-emphasis LVDS circuit of the present invention. Detailed Implementation

[0017] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0018] This invention provides an adaptive pre-emphasis LVDS circuit, such as Figure 1 As shown, the system includes a driving unit and an adaptive logic unit. The driving unit includes a first differential output terminal out_p and a second differential output terminal out_n. The adaptive logic unit includes a comparator, a logic module, and a current bias module connected in sequence. The first differential output terminal out_p is connected to the positive input terminal of the comparator, and the current bias module is connected to the driving unit. Since out_n and out_p are a pair of differential signals with the same setup time and timing characteristics, monitoring only one end out_p is sufficient to characterize the overall quality of the LVDS differential signal, without the need for additional processing and sampling of out_n. The adaptive logic unit also includes output voltage terminals pre_vbp and pre_vbn. The driving unit also includes a PMOS transistor M9 and an NMOS transistor M6. The pre_vbp terminal is connected to the gate of the PMOS transistor M9, and the pre_vbn terminal is connected to the gate of the NMOS transistor M6.

[0019] The driving unit also includes PMOS transistors M1, M2, M8, and M10, and NMOS transistors M3, M4, M5, and M7. The source of PMOS transistor M10 is connected to VDD, its gate is connected to the bias voltage vbp, and its drain is connected to the sources of M1 and M2. The source of PMOS transistor M9 is connected to VDD, and its drain is connected to the source of PMOS transistor M8. The gate of PMOS transistor M8 is connected to the pre-emphasis enable signal Pre_ep, and its drain is connected to the sources of M1 and M2. The gate of PMOS transistor M1 is connected to the data signal data_n, and its drain is connected to the drain of NMOS transistor M3. The gate of NMOS transistor M3 is connected to the data signal terminal (data_n), and its source is connected to the drain of M5 and M7. The gate of PMOS transistor M2 is connected to the data signal terminal (data_p), and its drain is connected to the drain of NMOS transistor M4. The gate of NMOS transistor M4 is connected to the data_p terminal, and its source is connected to the drain of M5 and M7. The gate of NMOS transistor M5 is connected to the pre-emphasis enable signal terminal (Pre_en), and its source is connected to the drain of NMOS transistor M6. The source of NMOS transistor M6 is connected to GND. The gate of NMOS transistor M7 is connected to the bias voltage (vbn), and its source is connected to GND. `pre_vbp` and `pre_vbn` adjust the pull-up pre-emphasis current and pull-down pre-emphasis current, respectively.

[0020] The adaptive logic unit also includes switches S1 and S2, capacitor C1, and a current bias module. The negative input of the comparator is connected to a reference voltage Vref. The input of the logic module Logic is connected to a reference clock REFCLK. The first output of the logic module Logic is connected to the control terminal of the first switch S1, with one end of switch S1 connected to VDD and the other end connected to capacitor C1. The second output of the logic module Logic is connected to the control terminal of the second switch S2. One end of the second switch S2 is connected to GND and the other end connected to capacitor C1. The lower end of capacitor C1 is connected to GND. Capacitor C1 is connected to the input of the current bias module and serves as the control voltage Vref. C end.

[0021] like Figure 2 As shown, the current biasing module includes a resistor R1, an operational amplifier AMP, PMOS transistors M11 and M12, and an NMOS transistor M13; the non-inverting input of the operational amplifier AMP is connected to the control voltage V. CThe inverting input terminal is connected to the output terminal of the operational amplifier, the drain and gate of PMOS transistor M11, the gate of PMOS transistor M12, and one end of resistor R1. The gate of PMOS transistor M11 is connected to the gate of PMOS transistor M12, and the other end of resistor R1 is connected to GND. The source of PMOS transistor M11 is connected to VDD. The source of PMOS transistor M12 is connected to VDD. The connection point between the drain and gate of NMOS transistor M13 is connected to the drain of PMOS transistor M12, and the source of NMOS transistor M13 is connected to GND. The node where the inverting input terminal, output terminal, drain and gate of PMOS transistor M11, gate of PMOS transistor M12, and one end of resistor R1 are connected is the pre_vbp terminal. The node where the drain of PMOS transistor M12 and the drain and gate of NMOS transistor M13 are connected is the pre_vbn terminal.

[0022] The working principle of the adaptive pre-emphasis LVDS circuit of this invention is as follows: Pre_en is the pre-emphasis enable signal. During data transmission, Pre_en is high, activating the pre-emphasis function. data_p and data_n are a pair of data signals with opposite phases. After a change in the data transmission rate, an adaptive adjustment mechanism is activated, and the system can enter normal operation mode at any time after the adjustment process is complete. During the adjustment of the pre-emphasis current, the data frequency needs to be less than 1 / 4 of the normal data frequency to ensure the adaptive logic unit can function properly. During the adjustment process, a comparator compares the reference voltage Vref and the driver unit output voltage out_p in real time. The Logic module in the adaptive logic unit generates control signals for switches s1 and s2 based on the comparator output cmp_out and the reference clock REFCLK. When the falling edge of cmp precedes the falling edge of the reference clock REFCLK, switch s2 is turned on, pulling down the voltage Vref. C This reduces the pre-emphasis current. When the falling edge of cmp lags behind the falling edge of the reference clock REFCLK, control switch S1 is turned on, pulling up voltage V. C This increases the pre-emphasis current. The high-level pulse width of the reference clock REFCLK is consistent with the normal data transmission rate. According to the LVDS signal transmission protocol, the output voltage out_p of the drive unit should reach the reference voltage Vref at the falling edge of the reference clock REFCLK. Under this operating mechanism, the adaptive pre-emphasis circuit will exhibit two operating states. The reference voltage Vref value is increased by 350mV at the LVDS common-mode level.

[0023] This invention also provides an adjustment method for an adaptive pre-emphasis LVDS circuit. Using the aforementioned adaptive pre-emphasis LVDS circuit, the method includes the following steps: comparing the voltage at the output terminal out_p of the driving unit with the reference voltage Vref using a comparator; and adjusting the control voltage Vref by controlling the conduction state of switch S1 or S2 according to the timing relationship between the comparison result and the reference clock REFCLK. C This allows for adjustment of the pre-weighting current.

[0024] Specifically, when the falling edge of the comparator output signal cmp_out precedes the falling edge of the reference clock REFCLK, the logic module controls the second switch S2 to turn on, pulling the control voltage V low. C The pre-emphasis current is reduced, causing the voltage at the first differential output terminal out_p of the drive unit to drop to the reference voltage Vref. When the falling edge of the comparator output signal cmp_out lags behind the falling edge of the reference clock REFCLK, the logic module controls the first switch S1 to turn on, pulling up the control voltage Vref. C Increase the pre-emphasis current to raise the voltage at the first differential output terminal out_p of the drive unit to the reference voltage Vref.

[0025] Example 1 This embodiment provides an adaptive pre-emphasis LVDS circuit, including a driver unit and an adaptive logic unit. The driver unit includes a first differential output terminal out_p and a second differential output terminal out_n. The adaptive logic unit includes a comparator, a logic module, and a current bias module connected in sequence. The first differential output terminal out_p is connected to the positive input terminal of the comparator, and the current bias module is connected to the driver unit.

[0026] In this embodiment, the comparator compares the voltage of out_p with the reference voltage Vref and outputs the comparison result to the logic module. The logic module, based on the timing relationship between the comparison result and the reference clock REFCLK, controls the current bias module to adjust the pre-emphasis current output to the drive unit. When the out_p voltage changes too quickly, the pre-emphasis current is reduced; when the out_p voltage changes too slowly, the pre-emphasis current is increased. Through this closed-loop adjustment, the output voltage of the drive unit automatically matches the requirements of the reference voltage Vref.

[0027] Example 2 Based on Embodiment 1, the adaptive logic unit further includes an output voltage pre_vbp terminal and a pre_vbn terminal, and the driving unit further includes a PMOS transistor M9 and an NMOS transistor M6. The pre_vbp terminal is connected to the gate of the PMOS transistor M9, and the pre_vbn terminal is connected to the gate of the NMOS transistor M6.

[0028] In this implementation, the current bias module outputs a first pre-emphasis control voltage and a second pre-emphasis control voltage to the drive unit through the pre_vbp and pre_vbn terminals, respectively, based on the control signal from the logic module Logic. The pre_vbp terminal is connected to the gate of PMOS transistor M9 and controls the magnitude of the pull-up pre-emphasis current. When the pre_vbp voltage increases, the conduction capability of PMOS transistor M9 weakens, and the pull-up pre-emphasis current decreases; when the pre_vbp voltage decreases, the pull-up pre-emphasis current increases. The pre_vbn terminal is connected to the gate of NMOS transistor M6 and controls the magnitude of the pull-down pre-emphasis current. When the pre_vbn voltage increases, the conduction capability of NMOS transistor M6 strengthens, and the pull-down pre-emphasis current increases; when the pre_vbn voltage decreases, the pull-down pre-emphasis current decreases. By adjusting the pull-up and pull-down pre-emphasis currents respectively, the switching rate of the output signals of the first differential output terminal out_p and the second differential output terminal out_n of the drive unit is controlled, so that out_p reaches the reference voltage Vref at the falling edge of the reference clock REFCLK.

[0029] Example 3 This embodiment corresponds to the adaptive pre-emphasis LVDS circuit of claims 1 to 3. Based on embodiment 2, the driving unit further includes PMOS transistors M1, M2, M8, and M10, and NMOS transistors M3, M4, M5, and M7. The source of PMOS transistor M10 is connected to VDD, its gate is connected to the bias voltage vbp, and its drain is connected to the sources of M1 and M2. The source of PMOS transistor M9 is connected to VDD, and its drain is connected to the source of PMOS transistor M8. The gate of PMOS transistor M8 is connected to the Pre_ep terminal, and its drain is connected to the sources of M1 and M2. The gate of PMOS transistor M1 is connected to the data_n terminal, and its drain is connected to the drain of NMOS transistor M3. The gate of NMOS transistor M3 is connected to the data_n terminal, and its source is connected to the drains of M5 and M7. The gate of PMOS transistor M2 is connected to the data_p terminal, and its drain is connected to the drain of NMOS transistor M4. The gate of NMOS transistor M4 is connected to the data_p terminal, and its source is connected to the drains of M5 and M7. The gate of NMOS transistor M5 is connected to the Pre_en terminal, and its source is connected to the drain of NMOS transistor M6. The source of NMOS transistor M6 is connected to GND. The gate of NMOS transistor M7 is connected to the bias voltage vbn, and its source is connected to GND.

[0030] In this embodiment, the pre-emphasis function is activated when the Pre_en terminal is high. data_p and data_n are a pair of data signals with opposite phases. PMOS transistor M10 and NMOS transistor M7 provide constant bias current for the drive unit under the control of bias voltages vbp and vbn, respectively. When data_p is high and data_n is low, PMOS transistors M1 and M4 are turned on, and current flows from VDD through M10 and M1 to out_n, while simultaneously flowing from out_p through M4, M5, and M6 to GND, forming a differential voltage between out_p and out_n. When a data signal transition occurs, the Pre_ep terminal controls M8 to turn on, and the pull-up pre-emphasis current provided by PMOS transistor M9 is injected into the sources of M1 and M2 through M8. NMOS transistor M6 adjusts the pull-down pre-emphasis current according to the voltage at the pre_vbn terminal to achieve accelerated compensation for the output signal transition edge.

[0031] Example 4 Based on Embodiment 3, the adaptive logic unit further includes a first switch S1, a second switch S2, and a capacitor C1. The negative input terminal of the comparator is connected to the reference voltage Vref, the input terminal of the logic module Logic is connected to the reference clock REFCLK, the first output terminal of the logic module Logic is connected to the control terminal of the first switch S1, and the second output terminal is connected to the control terminal of the second switch S2. One end of the first switch S1 is connected to VDD, and the other end is connected to the capacitor C1. One end of the second switch S2 is connected to GND, and the other end is connected to the capacitor C1. The lower end of the capacitor C1 is connected to GND, and the capacitor C1 is connected to the input terminal of the current bias module and serves as the control voltage V. C end.

[0032] In this embodiment, the comparator compares the voltage of out_p with the reference voltage Vref in real time and outputs the comparison result to the logic module Logic. The logic module Logic simultaneously receives the reference clock REFCLK and generates a control signal based on the timing relationship between the comparison result and REFCLK. When the voltage of out_p changes too quickly and reaches Vref before the falling edge of REFCLK, the comparator output signal flips before REFCLK, and the logic module Logic controls the second switch S2 to turn on. Capacitor C1 discharges to GND through S2, controlling the voltage Vref. C When the voltage out_p changes too slowly and has not yet reached Vref at the falling edge of REFCLK, the comparator output signal lags behind REFCLK in its flip. The logic module controls the first switch S1 to turn on, and VDD charges capacitor C1 through S1, increasing the control voltage VC. The current bias module then increases the pre-emphasis current accordingly.

[0033] The adaptive closed-loop regulation mechanism, consisting of a comparator, a logic module, a first switch S1, a second switch S2, a capacitor C1, and a current bias module, can automatically adjust the magnitude of the pre-emphasis current according to the timing relationship between the out_p voltage and the reference clock REFCLK. This allows the pre-emphasis current to dynamically match the data transmission rate and channel conditions, solving the problem of high power consumption redundancy in traditional fixed pre-emphasis current when the channel conditions are good or the data transmission rate is low.

[0034] Example 5 Based on Example 4, such as Figure 2 As shown, the current biasing module includes a resistor R1, an operational amplifier AMP, PMOS transistors M11 and M12, and an NMOS transistor M13. The non-inverting input of the operational amplifier AMP is connected to the control voltage VC, and the inverting input is connected to the output of the operational amplifier AMP, the drain and gate of PMOS transistor M11, the gate of PMOS transistor M12, and one end of resistor R1. The gate of PMOS transistor M11 is connected to the gate of PMOS transistor M12. The other end of resistor R1 is connected to GND. The source of PMOS transistor M11 is connected to VDD. The source of PMOS transistor M12 is connected to VDD. The drain and gate of NMOS transistor M13 are connected to the drain of PMOS transistor M12, and the source of NMOS transistor M13 is connected to GND. The node where the inverting input and output of the operational amplifier AMP, the drain and gate of PMOS transistor M11, the gate of PMOS transistor M12, and one end of resistor R1 are connected is the pre_vbp terminal. The node where the drain of PMOS transistor M12 and the drain and gate of NMOS transistor M13 are connected together is the pre_vbn terminal.

[0035] In this embodiment, the control voltage V C After being buffered by the operational amplifier AMP, a reference current is generated in the branch of PMOS transistor M11 and resistor R1. The magnitude of this reference current is V. C Divide by R1. PMOS transistors M12 and M11 form a current mirror, mirroring the reference current and injecting it into NMOS transistor M13. NMOS transistor M13 is connected as a diode, converting the mirrored current into a gate voltage. The voltage at the drain node of PMOS transistor M11 is output as pre_vbp to the gate of PMOS transistor M9 in the drive unit, and the voltage at the drain node of NMOS transistor M13 is output as pre_vbn to the gate of NMOS transistor M6 in the drive unit. When V C As the voltage increases, the reference current increases, pre_vbp decreases, pre_vbn increases, and the pre-emphasis current increases. When V C When the current decreases, the reference current decreases, pre_vbp increases, pre_vbn decreases, and the pre-emphasis current decreases.

[0036] Example 6 This embodiment provides an adjustment method for an adaptive pre-emphasis LVDS circuit. Using the adaptive pre-emphasis LVDS circuit provided in the above embodiment, the method includes the following steps: comparing the voltage at the output terminal out_p of the driving unit with the reference voltage Vref using a comparator; the logic module Logic controls the conduction state of switch S1 or S2 according to the timing relationship between the comparison result and the reference clock REFCLK, thereby adjusting the control voltage Vref. C This allows for adjustment of the pre-weighting current.

[0037] More specifically, a comparator compares the voltage at the first differential output terminal out_p of the drive unit with the reference voltage Vref. The logic module, based on the comparison result and the timing relationship with the reference clock REFCLK, controls the conduction state of either the first switch S1 or the second switch S2, thereby adjusting the control voltage V. C The current bias module is based on V C The pre-emphasis current output to the drive unit is adjusted by varying the current. When the out_p voltage changes too quickly, the pre-emphasis current is decreased; when the out_p voltage changes too slowly, the pre-emphasis current is increased. Through this closed-loop adjustment, the output voltage of the drive unit adaptively matches the requirement of the reference voltage Vref.

[0038] Example 7 Based on Example 7, such as Figure 3 The diagram shows the first operating state of the adaptive pre-emphasis LVDS circuit of this invention. In this operating state, the initial pre-emphasis current is too large, causing the output voltage out_p of the drive unit to be too high, reaching the reference voltage Vref before the predetermined time. At this time, the comparator output signal cmp_out flips before the falling edge of the reference clock REFCLK. The logic module Logic controls the second switch S2 to turn on based on the comparator output signal cmp_out and the reference clock REFCLK, pulling down the control voltage Vref. C This reduces the pre-emphasis current, thereby enabling the drive unit output to reach the reference voltage Vref.

[0039] Example 8 Based on Example 7: Figure 4 The diagram shows the second operating state of the adaptive pre-emphasis LVDS circuit of this invention. In this operating state, the initial pre-emphasis current is too small, resulting in a low voltage at the first differential output terminal out_p of the drive unit, lagging behind the predetermined time to reach the reference voltage Vref. At this time, the comparator output signal cmp_out flips behind the falling edge of the reference clock REFCLK. The logic module Logic controls the first switch S1 to turn on based on the comparator output signal cmp_out and the reference clock REFCLK, pulling up the control voltage Vref. CThe pre-emphasis current is increased, thereby bringing the drive unit output to the reference voltage Vref. Through closed-loop regulation in these two operating states, the pre-emphasis current can adaptively adjust according to the data transmission rate, thus enabling the system to achieve better power efficiency. After the adjustment process is completed, the circuit enters normal operating mode, where the pre-emphasis current matches the current data transmission rate.

Claims

1. An adaptive pre-emphasis LVDS circuit, characterized in that, It includes a driving unit and an adaptive logic unit; the driving unit includes a first differential output terminal out_p and a second differential output terminal out_n; the adaptive logic unit includes a comparator, a logic module Logic and a current bias module connected in sequence; the first differential output terminal out_p is connected to the positive input terminal of the comparator, and the current bias module is connected to the driving unit.

2. The adaptive pre-emphasis LVDS circuit according to claim 1, characterized in that, The adaptive logic unit further includes an output voltage pre_vbp terminal and a pre_vbn terminal; the driving unit further includes a PMOS transistor M9 and an NMOS transistor M6; the pre_vbp terminal is connected to the gate of the PMOS transistor M9, and the pre_vbn terminal is connected to the gate of the NMOS transistor M6.

3. The adaptive pre-emphasis LVDS circuit according to claim 2, characterized in that, The driving unit also includes PMOS transistors M1, M2, M8, and M10, and NMOS transistors M3, M4, M5, and M7; The source of PMOS transistor M10 is connected to VDD, the gate is connected to the bias voltage vbp, and the drain is connected to the sources of M1 and M2; the source of PMOS transistor M9 is connected to VDD, and the drain is connected to the source of PMOS transistor M8. The gate of the PMOS transistor M8 is connected to the Pre-emphasis enable signal Pre_ep, and the drain is connected to the source of M1 and M2. The gate of PMOS transistor M1 is connected to the data signal terminal (data_n), and its drain is connected to the drain of NMOS transistor M3; the gate of NMOS transistor M3 is connected to the data signal terminal (data_n), and its source is connected to the drains of M5 and M7; the gate of PMOS transistor M2 is connected to the data signal terminal (data_p), and its drain is connected to the drain of NMOS transistor M4; the gate of NMOS transistor M4 is connected to the data_p terminal, and its source is connected to the drains of M5 and M7. The gate of NMOS transistor M5 is connected to the Pre_en terminal of the pre-emphasis enable signal, and its source is connected to the drain of NMOS transistor M6; the source of NMOS transistor M6 is connected to GND, and the gate of NMOS transistor M7 is connected to the bias voltage vbn, and its source is connected to GND.

4. The adaptive pre-emphasis LVDS circuit according to claim 3, characterized in that, The adaptive logic unit also includes switch S1, switch S2, capacitor C1, and current bias module; The negative input of the comparator is connected to a reference voltage Vref. The input of the logic module Logic is connected to a reference clock REFCLK. The first output of the logic module Logic is connected to the control terminal of the first switch S1, one end of which is connected to VDD and the other end to capacitor C1. The second output of the logic module Logic is connected to the control terminal of the second switch S2, one end of which is connected to GND and the other end to capacitor C1. The lower end of capacitor C1 is connected to GND. Capacitor C1 is connected to the input terminal of the current bias module and serves as the control voltage Vref. C end.

5. The adaptive pre-emphasis LVDS circuit according to claim 4, characterized in that, The current bias module includes a resistor R1, an operational amplifier AMP, PMOS transistors M11 and M12, and an NMOS transistor M13; The non-inverting input of the operational amplifier AMP is connected to the control voltage V. C The inverting input terminal is connected to the output terminal of the operational amplifier, the drain and gate of PMOS transistor M11, the gate of PMOS transistor M12, and one end of resistor R1. The gate of PMOS transistor M11 is connected to the gate of PMOS transistor M12, and the other end of resistor R1 is connected to GND. The source of PMOS transistor M11 is connected to VDD. The source of PMOS transistor M12 is connected to VDD. The connection point between the drain and gate of NMOS transistor M13 is connected to the drain of PMOS transistor M12, and the source of NMOS transistor M13 is connected to GND.

6. The adaptive pre-emphasis LVDS circuit according to claim 5, characterized in that, The node where the inverting input and output terminals of the operational amplifier AMP, the drain and gate of PMOS transistor M11, the gate of PMOS transistor M12, and one end of resistor R1 are connected together is the pre_vbp terminal; the node where the drain of PMOS transistor M12 and the drain and gate of NMOS transistor M13 are connected together is the pre_vbn terminal.

7. An adjustment method for an adaptive pre-emphasis LVDS circuit, characterized in that, The adaptive pre-emphasis LVDS circuit according to claim 6 includes the following steps: comparing the voltage of the first differential output terminal out_p of the driving unit with the reference voltage Vref through the comparator; the logic module Logic controls the conduction state of switch S1 or S2 according to the timing relationship between the comparison result and the reference clock REFCLK, and adjusts the control voltage V. C This allows for adjustment of the pre-weighting current.

8. The adjustment method for the adaptive pre-emphasis LVDS circuit according to claim 7, characterized in that, When the falling edge of the comparator output signal cmp_out precedes the falling edge of the reference clock REFCLK, the logic module Logic controls the second switch S2 to turn on, pulling the control voltage V low. C This reduces the pre-emphasis current, causing the voltage at the first differential output terminal out_p of the drive unit to drop to the reference voltage Vref.

9. The adjustment method of the adaptive pre-emphasis LVDS circuit according to claim 7, characterized in that, When the falling edge of the comparator output signal cmp_out lags behind the falling edge of the reference clock REFCLK, the logic module Logic controls the first switch S1 to turn on, pulling the control voltage V high. C Increase the pre-emphasis current to raise the voltage at the first differential output terminal out_p of the drive unit to the reference voltage Vref.

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