A constant lock time frequency and phase discriminator

Abstract

The application discloses a constant lock time frequency discriminator, and relates to the technical field of electronic devices. The application introduces a true single-phase clock flip-flop, and simultaneously combines a first pair of output prediction logic circuits in a traditional PFD. At this time, a reset feedback loop is a charging and discharging path of a specific transistor node in the true single-phase clock flip-flop, and an output state of the output prediction logic circuit is combined to form an implicit reset path. The width of a high-level output pulse is determined by the extremely short carrier migration time of the specific transistor node in the flip-flop, so that τ d is compressed to a physical limit. Meanwhile, the flip-flop utilizes the pre-charging state of the specific transistor node to pre-judge the change trend of the output level, so that T setup tends to zero when working at a high frequency. The whole process minimizes τ d and T setup , that is, the lock time determined by τ d and T setup remains fixed and does not drift with frequency, and finally is efficiently applied.

Description

Technical Field

[0001] This invention relates to the field of electronic device technology, and in particular to a frequency and phase detector with a constant lock time. Background Technology

[0002] Phase-locked loops (PLLs) are indispensable key modules in modern electronic systems, widely used in wireless communication, high-speed serial interfaces, clock data recovery, and frequency synthesizers. As the core component of a PLL, the performance of the phase frequency detector (PFD) directly determines the overall performance of the entire loop in terms of lock-in time, phase noise, and spurious suppression. Currently, the most commonly used PFD in industry is the traditional three-state PFD based on two D flip-flops and a feedback AND gate. However, as application requirements evolve towards wider bandwidths, higher frequencies, and faster frequency hopping, two inherent nonlinear timing effects of the traditional PFD architecture—reset delay (τ)—become increasingly problematic. d ) effect and setup time (T) setup The ) effect has become a significant bottleneck restricting further improvement in PLL performance.

[0003] In traditional PFD, the reset delay (τ) of the feedback path d The minimum width of the output pulse is determined by the D flip-flop's setup time (T). setup When the input signal frequency increases, it races against the clock edge. As the PLL's operating frequency changes, the generation of the PFD output signal depends on the timing coordination between the D flip-flop and the reset path, especially near the circuit's highest operating frequency (F). max When τ d and T setup The coupling effect can cause the gain characteristics of the PFD to change nonlinearly. At this time, the lock time of the phase-locked loop is inconsistent at different operating frequencies, that is, the lock time drifts with the frequency, which makes the response delay of the system unpredictable when switching between different channels.

[0004] To address the shortcomings of traditional PFDs, researchers have proposed various schemes such as dual-edge detection / subsampling PFDs, digitally assisted accelerated PFDs, dead-time-free / reset-optimized PFDs, and high-gain sampling PFDs. These schemes attempt to reduce noise by avoiding dead time or improve gain through dual-edge sampling. However, these methods are essentially still "post-hoc corrections" or "local optimizations," all of which retain the competition path of the D flip-flop and its reset network. Under high-speed, wideband switching conditions, the F... max With T setup The frequency-dependent physical properties still exist, and F has not been eliminated synchronously at the physical structure level. max With T setupThese two nonlinear sources mean that the frequency dependence of the lock time remains stubbornly present under high frequency and wide bandwidth switching conditions, making it difficult to apply efficiently to high frequency and wide bandwidth phase-locked loops (PLLs). Summary of the Invention

[0005] This invention provides a frequency and phase detector with a constant lock time, which can solve the problems existing in the prior art.

[0006] This invention provides a frequency and phase detector with constant lock time, including a first input stage, a second input stage, a first output predictive logic circuit, and a pair of true single-phase clock flip-flops; The first input stage and the second input stage are used to receive the reference clock signal and the feedback clock signal, respectively; the input terminal of the first output prediction logic circuit is connected to the output terminal of the first input stage and the second input stage, respectively, and is used to predict and latch the output level change according to the current clock edge state. The clock input and data input of each true single-phase clock flip-flop are respectively connected to the output of the first output predictive logic circuit. The clock input is used to receive the signal processed by the first output predictive logic circuit, and the data input receives a logic high level. Wherein, after the output level change of the first output prediction logic circuit is transmitted to a true single-phase clock flip-flop, the true single-phase clock flip-flop flips to generate a valid output, and then resets the true single-phase clock flip-flop in the charging and discharging path of the predefined transistor inside another true single-phase clock flip-flop to form an implicit reset path. The implicit reset path utilizes the predefined channel charge discharge mechanism of the transistor itself to reset the internal node of the corresponding true single-phase clock flip-flop to the initial waiting state within a preset locking time.

[0007] Preferably, the first output prediction logic circuit is to merge the first pair of output prediction logic circuits OPL inside the traditional frequency and phase detector PFD, and remove the second pair of output prediction logic circuits OPL and the first pair of positive latches PL, in order to reduce the number of transmission gate stages from the input clock edge to the output of the true single-phase clock trigger.

[0008] Preferably, the reset delay τ of the true single-phase clock trigger is... d The reset path speed of a true single-phase clock flip-flop is accelerated by adjusting the width-to-length ratio of a predefined transistor that constitutes the implicit reset path.

[0009] Preferably, the setup time T of the true single-phase clock trigger is... setup This is achieved by adjusting the size of a predefined transistor that forms the implicit reset path, which balances the competition between data setup and the rising edge of the clock.

[0010] Preferably, it further includes a second pseudo-output prediction logic circuit, which is connected after the first output prediction logic circuit, and is used to compensate for residual phase errors introduced by input frequency changes in order to maintain a constant lock-in time across the frequency range.

[0011] Preferably, the implicit reset path does not contain any independent logic gate circuits, and is composed of the output node of the first output prediction logic circuit and the source-drain channels of the predefined transistors inside a pair of true single-phase clock flip-flops; When one true single-phase clock flip-flop toggles and generates a valid output level, this output level is directly applied to the predefined transistor inside another true single-phase clock flip-flop through an implicit reset path, so as to reset the internal node of the true single-phase clock flip-flop to the initial waiting state within a preset locking time.

[0012] Preferably, when the phase difference between the reference clock signal and the feedback clock signal approaches zero, the minimum width of the frequency and phase detector is limited only by the intrinsic discharge time of the transistor predefined inside the true single-phase clock trigger in the implicit reset path.

[0013] Preferably, when the initial phase difference between the reference clock signal and the feedback clock signal is close to ±2π, the setup time T of the true single-phase clock trigger is... setup Approaching zero, used to maintain the linear response of the frequency and phase detector.

[0014] Preferably, the transistors predefined inside the true single-phase clock trigger are all CMOS transistors.

[0015] Preferably, the lock-in time of the frequency and phase detector remains unchanged when the operating frequency of the frequency and phase detector changes from DC to 2.5 GHz.

[0016] This invention provides a frequency and phase detector with a constant locking time, which has the following advantages compared with the prior art: This invention introduces a true single-phase clock flip-flop with output prediction logic as the core sampling unit to replace the standard D flip-flop with a long setup time in traditional PFDs. It also incorporates the first pair of output prediction logic circuits in traditional PFDs. In this case, the explicit reset feedback loop composed of logic gates is no longer set between the output prediction logic circuit and the true single-phase clock flip-flop. Instead, the charging and discharging path of a specific transistor node inside the true single-phase clock flip-flop is reused, and combined with the output state of the output prediction logic circuit, an implicit reset path is formed. When there is a phase difference between the reference clock and the feedback clock, the first arriving clock edge enables the corresponding true single-phase clock flip-flop to generate a high-level output through the output prediction logic circuit. Due to the existence of the implicit reset path, the width of this high-level output pulse no longer depends on the loop delay of the external reset logic, but is determined by the extremely short carrier migration time of the specific transistor node inside the other true single-phase clock flip-flop, thus reducing the reset delay τ. d By compressing to physical limits, and simultaneously enabling a true single-phase clock trigger to pre-judge the output level change trend using the pre-charge state of a specific internal crystal node before the clock rising edge arrives, the time window required for effective data setup is greatly shortened, thus reducing the setup time T during high-frequency operation. setup Approaching zero, the entire process will τ d and T setup Synchronization minimization means that regardless of whether the PLL jumps from a low frequency to a high frequency or from a high frequency to a low frequency, the equivalent damping coefficient and natural frequency experienced by the loop do not change, i.e., from τ d and T setup The determined lock time remains fixed and does not drift with frequency changes, ultimately enabling the designed frequency and phase detector to be used efficiently in high-frequency broadband phase-locked loops (PLLs). Attached Figure Description

[0017] Figure 1 This is a schematic diagram of a conventional PFD structure provided in an embodiment of the present invention; Figure 2 Provided for embodiments of the present invention T setup & τ d A schematic diagram illustrating the effect of the effect on lock-in time and maximum operating frequency; Figure 3 A schematic diagram of an improved PFD architecture with fast triggers provided in an embodiment of the present invention; Figure 4 The diagram shows the overall architecture of the CLT-PFD provided in the embodiment of the present invention; wherein, (a) is the functional architecture of the improved PFD with fast triggers, and (b) is the final architecture of the designed CLT-PFD; Figure 5This is a schematic diagram of the overall architecture of CLT-PFD provided in an embodiment of the present invention; wherein, (a) is the detailed architecture of CLT-PFD, and (b) is the actual circuit of CLT-PFD; Figure 6 A schematic diagram of the CLT-PFD locking detection mechanism in the entire phase-locked loop provided in an embodiment of the present invention; Figure 7 This is a simulation diagram illustrating the lock-time constancy of CLT-PFD under simulation, provided in an embodiment of the present invention. Figure 8 This is a schematic diagram of CLT-PFD frequency hopping simulation provided in an embodiment of the present invention; Figure 9 This is a simulation diagram of the CLT-PFD dead zone characteristics provided in an embodiment of the present invention; Figure 10 A schematic diagram of CLT-PFD phase noise simulation provided for an embodiment of the present invention. Detailed Implementation

[0018] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a thorough understanding of the present invention. However, the present invention can be practiced in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0019] The frequency and phase detector (PFD) is the core module of the phase-locked loop (PLL). It is responsible for detecting the frequency and phase difference between the reference clock and the feedback clock, and outputting control signals to drive the charge pump to adjust the VCO frequency, ultimately achieving phase locking.

[0020] In high-frequency broadband PLL applications (especially frequency synthesizers, clock data recovery, etc.), the following two core technical problems exist: (1) The lock-in time drifts nonlinearly with the operating frequency.

[0021] Traditional PFDs use a classic tri-state structure (two D flip-flops + AND gate reset), and their lock-in time is affected by two key timing parameters: ① Reset delay (τ) d Effect: The propagation delay of the combined path of the AND gate and the flip-flop determines the lower limit (i.e., dead zone) of the PFD output pulse width.

[0022] ② Setup time (T) setup Effect: At high frequencies, the reference signal edge conflicts with the trigger setup time window, causing the PFD response behavior to change with frequency.

[0023] Both of these effects intensify with increasing operating frequency, causing inconsistent locking times of the phase-locked loop at different frequencies, which is particularly prominent in frequency hopping applications.

[0024] (2) Dead zone effect leads to phase noise and nonlinearity.

[0025] Traditional PFDs have an unavoidable dead zone, and the gain approaches zero within a small phase difference range, introducing phase error and phase noise, which reduces the purity of the PLD output spectrum.

[0026] The main solutions to the above two problems at this stage include: (1) Classical PFD.

[0027] Solution: Two reset-type D flip-flops with AND gate feedback is the most widely used PFD structure in the industry.

[0028] defect: ① There is a dead zone. When the phase difference is extremely small, the charge pump cannot respond normally, resulting in phase noise.

[0029] ② The lock-in time varies with the operating frequency and is unstable in wideband / frequency hopping PLLs.

[0030] ③ In F max Nearby due to T setup The effect leads to nonlinear gain and increased phase error.

[0031] (2) Double-Edge Sampling Detector (PFD).

[0032] Solution: Detect phase difference by using the double edges of the reference signal or by subsampling the output frequency division signal, thereby reducing the phase noise floor and shortening the frequency locking time. This solution is mainly aimed at high frequency transition and ultra-low jitter applications.

[0033] defect: ① The subsampling structure is sensitive to the amplitude and waveform quality of the input signal, and its performance is unstable under PVT variations.

[0034] ② The symmetry error introduced by dual-edge detection worsens at high frequencies, affecting the settling time (T). setup The improvement is limited.

[0035] ③ It is impossible to fundamentally eliminate the reset delay (τ). d The problem of lock-in time varying with frequency caused by this means that the lock-in time is still not constant over a wide frequency range.

[0036] (3) Digital Auxiliary Acceleration PFD (TDC Auxiliary Compensation / Dead Zone Automatic Controller DZAC).

[0037] Solution: Introduce a digital module (such as TDC or DZAC) outside the PFD to adaptively calibrate the phase error, thereby speeding up the acquisition and automatically compensating for the dead zone.

[0038] defect: ① Additional digital circuitry (TDC, control logic, etc.) is required, significantly increasing area and power consumption overhead.

[0039] ② Digital calibration introduces additional delays and clock domain transitions, which limits calibration convergence speed at extremely high frequencies.

[0040] ③ Essentially, this is a "post-hoc compensation" strategy and does not eliminate the nonlinear parameter (τ) at the PFD architecture level. d and T setup The improvement in frequency hopping robustness is limited.

[0041] (4) Dead-Zone-Free / Reset-Optimized PFD (for fractional N-type PLLs).

[0042] Solution: To address the specific requirements of fractional N-type PLLs, the reset path of the PFD is specifically optimized to eliminate dead zones or shorten the reset pulse width, thereby improving noise and spurious performance.

[0043] defect: ① The solution is customized for a specific application (fractional N-type PLL) and lacks universality, making it difficult to directly apply to wideband integer N-type or frequency hopping PLLs.

[0044] ② Although the dead zone was eliminated, the setup time (T) was affected. setup The suppression of the effect is insufficient, and the lock-in time still varies with frequency in the high-frequency range.

[0045] ③ Failed to minimize τ synchronously d and T setup The nonlinear parameter (τNon-Linear) is still relatively high overall, which limits the frequency hopping performance.

[0046] (5) High-Gain Sampling Detector (PFD, for IoT low-power PLL).

[0047] Solution: A high-gain sampling structure is adopted to improve the detection sensitivity of PFD to small phase differences, so as to maintain low phase noise under ultra-low power budget, mainly for Internet of Things (IoT) application scenarios.

[0048] defect: ① The linear range of high-gain sampling structures is narrow, and they are prone to saturation at large frequency deviations (such as the initial stage of frequency hopping), thus limiting the capture range.

[0049] ② Power consumption optimization at the expense of the upper limit of operating frequency (F max As a trade-off, it is not suitable for high-speed broadband scenarios.

[0050] ③ Locking time affects the nonlinear parameter (τ) d T setup It is also sensitive and cannot achieve constant lock-in time across frequencies.

[0051] The five solutions mentioned above each have their own focus, improving dead zone, accelerating acquisition speed, or reducing power consumption, but none of them can simultaneously satisfy the following three points: zero dead zone (eliminating τ). d Impact), constant lock-in time (τNon-Linear, frequency independent), wide frequency jump range (up to F) max The fundamental reason is that none of these solutions simultaneously minimize the reset latency τ at the PFD architecture level. d With establishment time T setup These are the two key nonlinear parameters.

[0052] like Figure 1 and Figure 2 As shown, the root cause of the variation in the lock-up time of a traditional PFD with frequency lies in the fact that the generation of the PFD output signal depends on the timing coordination between the D flip-flop and the reset path. At high frequencies, the reset delay τ d Effect and setup time (T) setup The dead-time effect causes nonlinear changes in PFD behavior, leading to an increase in lock-in time. This invention aims to solve the problems of non-constant lock-in time variation with frequency and increased phase noise caused by dead-time effect in traditional PFDs over a wide operating frequency range. Specifically: Traditional PFDs struggle to effectively detect rising edges at high frequencies because the clock edge spacing is too close. The root cause of high-frequency failure in traditional PFDs lies in their constituent units—flip-flops and NAND gates (or NOR gates). When the frequency is high and the phase difference between two clock edges is close to π or 2π, the flip-flops, due to their long setup time, cannot effectively detect this phase difference, leading to period slippage and prolonged lock-in time. The CLT-PFD proposed in this invention incorporates two improvements. The first improvement is the use of fast flip-flops instead of the flip-flops in traditional PFDs. Figure 3 The black dashed box section in the image (representing the time reduction of Tsetup) shortens the Tsetup time; its architecture is as follows: Figure 4 As shown in (a); the second improvement is in Figure 4Based on (a), the first pair of output predictive logic (OPL) circuits were merged, the first pair of positive latches (PL) and the second pair of OPL were removed, and an implicit reset path (IRP) was used instead of a reset network, further simplifying the overall circuit architecture, reducing circuit transmission delay, and ensuring that the functionality remained unchanged. This improved the various problems mentioned above in the high-frequency operation of traditional PFDs. The final architecture of the CLT-PFD is as follows: Figure 4 As shown in (b).

[0053] like Figure 5 (a) is a more detailed architecture diagram of the CLT-PFD, and (b) is the actual circuit. This invention optimizes the dimensions of key components in the actual circuit, further improving the performance of traditional PFDs. setup and τ d This causes high-frequency operational abnormalities. The principle is as follows:

[0054] The traditional PFD lock-in time formula is approximately T. lock ≈ κ1·τ d + κ2·T setup + C (constant term), where κ1 and κ2 are loop correlation coefficients, and C combines the contributions of the filter and VCO; the CLT-PFD practical circuit proposed in this invention simultaneously minimizes τ d and T setup : (1) Reset delay control: By adjusting the width-to-length ratio (W / L) of transistors M5 and M10, the reset path speed of the trigger is accelerated, effectively reducing τ. d .

[0055] (2) Establishing time control: By adjusting the dimensions of transistors M1 and M2, the competition between data establishment and the rising edge of the clock is balanced, so that T setup It approaches zero over a wide frequency range.

[0056] (3) After both are optimized simultaneously, T lock The influence of the frequency-dependent terms (the first two terms) in the time-locking mechanism is significantly reduced, and the lock-in time tends to a constant C, thus achieving a constant lock-in time.

[0057] The CLT-PFD locking detection mechanism proposed in this invention throughout the phase-locked loop is as follows: Figure 6 As shown, it includes two stages: (1) First OPL level: ensures correct locking at both the lowest and highest frequencies, covering the entire operating frequency range.

[0058] (2) Second pseudo-OPL stage: Maintains constant lock time across frequencies by compensating for input frequency changes and residual phase errors.

[0059] In the specific simulation, CLT-PFD was integrated into the PLL, and the results are as follows: like Figure 7 As shown, the PLL lock-in time remains almost unchanged from DC to 2.5 GHz, proving the constant lock-in time of the CLT-PFD proposed in this invention.

[0060] like Figure 8 As shown, in frequency hopping simulation, compared with traditional PFD and only optimizing τ d For PFDs, CTL-PFD can achieve fast locking over a frequency modulation range of up to 1 GHz, and the locking performance is not affected by step size or jump direction.

[0061] like Figure 9 As shown, in the dead-time characteristic simulation, the dead-time width of CLT-PFD is the smallest compared with similar schemes, which directly corresponds to lower phase noise.

[0062] like Figure 10 As shown, in phase noise simulation, CLT-PFD has the lowest phase noise, which is beneficial to the purity of the output spectrum.

[0063] In summary, CLT-PFD has no dead zone, the lowest phase noise, the lowest power consumption, and the best overall FOM value, outperforming all existing comparative solutions.

[0064] The advantages of this invention include: ① Constant lock-in time: The PLL lock-in time remains almost constant across the entire operating frequency range from near DC to 2.5 GHz, completely eliminating the problem of lock-in time drift with frequency; ② Zero or minimal dead time: The FTL-TSPC structure minimizes the PFD dead time, resulting in the smallest dead time compared to similar designs and significantly reducing phase noise; ③ Lowest phase noise: In simulation comparisons, the CLT-PFD exhibits the lowest phase noise, which is beneficial for output spectrum purity; ④ Lowest power consumption: The use of a single-phase clock TSPC structure and an auxiliary charge pump on-demand start strategy results in the lowest overall power consumption; ⑤ Optimal FOM (Figure of Merit): Considering dead time, noise, and power consumption, the FOM value of this invention is superior to all existing comparative schemes; ⑥ Strong frequency hopping robustness: Stable lock-in is possible within a 1 GHz step range, supporting wideband frequency hopping applications (such as wideband frequency synthesizers and wireless communication transceivers); ⑦ Simple and scalable structure: Implemented based on standard CMOS technology, key parameters can be adjusted and optimized for different process nodes.

[0065] This invention uses an implicit reset path to... dCompressed to the physical limit determined by the intrinsic discharge time of the transistor, while simultaneously triggering T through the OPL-TSPC flip-flop. setup Approaching zero across the entire frequency band, the elimination of the coupling effect between the two causes the first two frequency-related terms in the PLL lock-in time formula to be less effective from DC to F. max The value is always zero within the range, and the locking time is determined solely by the loop constant term C.

[0066] This invention internalizes the reset behavior into the natural discharge process of the internal node of the TSPC flip-flop, eliminating random jitter introduced by external reset logic. This invention adopts a true single-phase clock (TSPC) structure, whose dynamic power consumption is naturally lower than that of traditional static complementary logic. Its implicit reset path eliminates short-circuit power consumption and contention power consumption in the traditional PFD reset branch.

[0067] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A constant lock time frequency discriminator characterized by, include: The circuit consists of a first input stage, a second input stage, a first output predictive logic circuit, and a pair of true single-phase clock flip-flops. The first input stage and the second input stage are used to receive the reference clock signal and the feedback clock signal, respectively; the input terminal of the first output prediction logic circuit is connected to the output terminal of the first input stage and the second input stage, respectively, and is used to predict and latch the output level change according to the current clock edge state. The clock input and data input of each true single-phase clock flip-flop are respectively connected to the output of the first output predictive logic circuit. The clock input is used to receive the signal processed by the first output predictive logic circuit, and the data input receives a logic high level. Wherein, after the output level change of the first output prediction logic circuit is transmitted to a true single-phase clock flip-flop, the true single-phase clock flip-flop flips to generate a valid output, and then resets the true single-phase clock flip-flop in the charging and discharging path of the predefined transistor inside another true single-phase clock flip-flop to form an implicit reset path. The implicit reset path utilizes the predefined channel charge discharge mechanism of the transistor itself to reset the internal node of the corresponding true single-phase clock flip-flop to the initial waiting state within a preset locking time.

2. A constant lock time frequency and phase discriminator as claimed in claim 1, wherein, The first output prediction logic circuit is to merge the first pair of output prediction logic circuits OPL inside the traditional frequency and phase detector PFD, and remove the second pair of output prediction logic circuits OPL and the first pair of positive latches PL, in order to reduce the number of transmission gate stages from the input clock edge to the output of the true single-phase clock trigger.

3. The constant lock time frequency and phase detector of claim 1, wherein, The reset delay τ of the true single phase clock flip-flop d The reset path speed of the true single phase clock flip-flop is accelerated by tuning the width-length ratio of the predefined transistors that constitute the implicit reset path.

4. The constant lock time frequency and phase detector of claim 1, wherein, setup time T of the true single phase clock flip-flop setup The balance between data setup and clock rising edge race is regulated by adjusting the size of the predefined transistors that make up the implicit reset path.

5. The constant lock time frequency and phase detector of claim 1, wherein, It also includes a second pseudo-output prediction logic circuit, which is connected after the first output prediction logic circuit and is used to compensate for residual phase errors introduced by input frequency changes in order to maintain a constant lock time across the frequency range.

6. A constant lock time frequency and phase detector as claimed in claim 1, wherein, The implicit reset path does not contain any independent logic gate circuits, and is composed of the output node of the first output prediction logic circuit and the source-drain channels of the predefined transistors inside a pair of true single-phase clock flip-flops. When one true single-phase clock flip-flop toggles and generates a valid output level, this output level is directly applied to the predefined transistor inside another true single-phase clock flip-flop through an implicit reset path, so as to reset the internal node of the true single-phase clock flip-flop to the initial waiting state within a preset locking time.

7. A frequency and phase detector with constant locking time according to claim 1, characterized in that, When the phase difference between the reference clock signal and the feedback clock signal approaches zero, the minimum width of the frequency and phase detector is limited only by the intrinsic discharge time of the transistor predefined inside the true single-phase clock trigger in the implicit reset path.

8. A frequency and phase detector with constant locking time according to claim 1, characterized in that, The setup time T of a true single phase clock flip flop when the initial phase difference between the reference clock signal feedback clock signal is close to ±2π setup Approaching zero for maintaining the linear response of the phase frequency detector.

9. The constant lock time frequency and phase detector of claim 1, wherein, The transistors predefined inside the true single-phase clock trigger are all CMOS transistors.

10. A frequency and phase detector with constant locking time according to claim 1, characterized in that, The lock-in time of the frequency and phase detector remains unchanged as the operating frequency of the frequency and phase detector changes from DC to 2.5 GHz.

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