Dual-state machine high-speed sampling driving system and method suitable for FPGA

Abstract

The application relates to the technical field of state machine high-speed sampling, in particular to a double-state machine high-speed sampling driving system and method suitable for FPGA, which comprises a first state machine used for controlling conversion timing of an analog-digital converter, the first state machine is configured to return to a waiting state for preparing next conversion without waiting for completion of an SPI reading operation after triggering the SPI reading operation; a second state machine runs in parallel with the first state machine and is used for responding to the SPI reading operation triggered by the first state machine; the first state machine and the second state machine run in parallel by setting the first state machine and the second state machine, and the first state machine returns to the waiting state immediately after triggering the SPI reading operation, so that the conversion timing and the reading timing are pipelined in parallel, and the SPI reading time is not counted into a sampling period; meanwhile, the system is realized by using a standard hardware description language, and dependence on manufacturer-specific primitives is eliminated, so that the technical problems of low sampling rate and difficult cross-platform transplantation of a traditional scheme are fundamentally solved.

Description

Technical Field

[0001] This invention relates to the field of high-speed sampling technology for state machines, and in particular to a dual-state machine high-speed sampling driving system and method adapted to FPGA. Background Technology

[0002] The CL1606 is an 8-channel synchronous sampling analog-to-digital data acquisition system with a throughput rate of up to 200kSPS, widely used in power electronics, motor control, and other fields. Traditional CL1606 driver schemes generally employ a single-state machine sequential control method. Its workflow includes: wait cycle, start transition, monitoring the BUSY signal, SPI (Serial Peripheral Interface) data reading, and end state. This serial control architecture has the following drawbacks: (1) Low sampling rate: Since the next conversion can only begin after the SPI reading is completed, the SPI reading time is included in the sampling period. Taking a 25MHz system clock as an example, a single sampling requires waiting for 1000 clock cycles, conversion for 15 clock cycles, and SPI reading for 64 clock cycles, with a total cycle of about 1079 clock cycles. The sampling rate is only 23.2kHz, which is far below the theoretical upper limit of 200kHz for the chip.

[0003] (2) Difficult cross-platform porting: Existing driver solutions usually rely on proprietary primitives (such as Xilinx's BUFG, IDDR, etc.) or IP cores from specific FPGA vendors, and the code is strongly coupled with the specific FPGA platform. When porting between FPGA platforms of different vendors is required, the code must be modified or redesigned, resulting in a long development cycle and high technical risks.

[0004] Therefore, a dual-state machine high-speed sampling drive system and method adapted to FPGA is proposed. Summary of the Invention

[0005] In this section, as well as in the abstract and title of this application, some simplifications or omissions may be made to avoid obscuring the purpose of this section, the abstract, and the title of this application, and such simplifications or omissions shall not be used to limit the scope of the invention.

[0006] To address the shortcomings of existing technologies, one objective of this invention is to provide a dual-state machine high-speed sampling drive system adapted to FPGA.

[0007] To achieve the above objectives, the present invention adopts the following technical solution: a dual-state machine high-speed sampling drive system adapted to FPGA, comprising a first state machine for controlling the conversion timing of the analog-to-digital converter, wherein the first state machine is configured to: after triggering an SPI read operation, return to a waiting state ready for the next conversion without waiting for the SPI read operation to complete; and a second state machine, which runs in parallel with the first state machine, for responding to the SPI read operation triggered by the first state machine and independently controlling the SPI data read timing of the analog-to-digital converter; wherein the first state machine and the second state machine are implemented using a standard hardware description language.

[0008] As a preferred embodiment of the dual-state machine high-speed sampling drive system adapted to FPGA described in this invention, the state transition path of the first state machine includes: an idle waiting state, used to maintain a preset waiting period; a conversion start state, used to generate a CONVST signal to start analog-to-digital (AD) conversion; a conversion completion detection state, used to monitor a BUSY signal to confirm conversion completion; and a trigger state, used to generate a start signal for the SPI read operation.

[0009] As a preferred embodiment of the dual-state machine high-speed sampling drive system adapted to FPGA described in this invention, the first state machine immediately jumps back to the idle waiting state after generating a start signal in the trigger state, and begins the waiting count for the next sampling.

[0010] As a preferred embodiment of the dual-state machine high-speed sampling drive system adapted to FPGA described in this invention, the state transition path of the second state machine includes: an idle detection state, used to monitor the SPI start signal triggered by the first state machine; a multi-channel read state, used to sequentially read multiple channel data of the analog-to-digital converter; and a read end state, used to end the SPI read and set the completion flag.

[0011] As a preferred embodiment of the dual-state machine high-speed sampling drive system adapted to FPGA described in this invention, the multi-channel reading state includes continuously reading 16-bit data from two channels within one state cycle.

[0012] As a preferred embodiment of the dual-state machine high-speed sampling drive system adapted to FPGA described in this invention, the number of clock cycles maintained by the first state machine in the idle waiting state is determined based on the maximum throughput rate of the analog-to-digital converter and the system clock frequency.

[0013] As a preferred embodiment of the dual-state machine high-speed sampling drive system adapted to FPGA described in this invention, wherein: when the second state machine reads channel data, the data sampling point is set in a stable interval within the SPI clock cycle that avoids the data transition edge, and the setting of the sampling point satisfies the timing constraint formula T. sample ≥T co +T delay +T setup T sample T is the time from the data transition edge to the rising edge of the FPGA's internal sampling clock. co T is the data output delay of the analog-to-digital converter. delay For PCB trace delay, T setup The setup time for the FPGA input register is set at the middle of the SPI clock cycle 40ns after the rising edge of SCLK in an application scenario with an SPI clock frequency of 12.5MHz.

[0014] As a preferred embodiment of the dual-state machine high-speed sampling drive system adapted to FPGA described in this invention, the system supports the cascading expansion of multiple analog-to-digital converters (ADCs). Synchronous control of the multiple ADCs is achieved by sharing an SPI clock, a CONVST conversion start signal, and dual data signals DOUTA and DOUTB, and configuring an independent chip select signal CS_N for each ADC. The BUSY signals of the multiple ADCs are connected to the FPGA after logical AND. When any ADC is in a conversion state, the BUSY signal is high. The second state machine of the FPGA sequentially selects the independent CS_N of each ADC to read the channel data of each ADC. The first state machine performs unified analog-to-digital (AD) conversion timing control on the multiple ADCs.

[0015] As a preferred embodiment of the dual-state machine high-speed sampling drive system adapted to FPGA described in this invention, the standard hardware description language is Verilog-2001 standard syntax, and its implementation includes: using standard always blocks to describe sequential logic, and using standard assign statements or always@(*) blocks to describe combinational logic.

[0016] The advantages of the dual-state machine high-speed sampling drive system adapted to FPGA of the present invention are as follows: by setting up a first state machine and a second state machine to run in parallel, and making the first state machine return to the waiting state immediately after triggering the SPI read operation, the pipeline parallelism of the conversion timing and the read timing is realized, and the SPI read time is no longer included in the sampling period; at the same time, it is implemented using a standard hardware description language, which gets rid of the dependence on vendor-specific primitives and fundamentally solves the technical problems of low sampling rate and difficulty in cross-platform porting of traditional solutions.

[0017] To address the shortcomings of existing technologies, another objective of this invention is to provide a dual-state machine high-speed sampling driving method adapted to FPGA.

[0018] To achieve the above objectives, the present invention adopts the following technical solution: a dual-state machine high-speed sampling driving method adapted to FPGA, which adopts the aforementioned dual-state machine high-speed sampling driving system adapted to FPGA, including the following steps: the first state machine executes analog-to-digital (AD) conversion timing control, and immediately returns to the waiting state after triggering the SPI read operation to start waiting for the next conversion; the second state machine responds to the SPI read operation and independently executes SPI data reading, and the SPI data reading of the Nth sample and the analog-to-digital (AD) conversion of the N+1th sample are executed in parallel in time to form a pipeline structure.

[0019] The beneficial effects of the dual-state machine high-speed sampling driving method adapted to FPGA of the present invention are the same as those of the dual-state machine high-speed sampling driving system adapted to FPGA, and will not be repeated here. Attached Figure Description

[0020] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a diagram of the overall system architecture of the present invention.

[0022] Figure 2 This is a timing diagram for a traditional single-state machine (executed serially).

[0023] Figure 3 This is a timing diagram for a two-state machine pipeline (executed in parallel).

[0024] Figure 4 This is the state transition diagram of the present invention. Detailed Implementation

[0025] To make the objectives, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0026] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0027] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it a single or selective embodiment that is mutually exclusive with other embodiments.

[0028] Reference Figure 1 This embodiment provides a dual-state machine high-speed sampling drive system adapted to FPGA, including a first state machine 101 for controlling the conversion timing of an analog-to-digital converter (ADC). The first state machine 101 is configured to return to a waiting state for the next conversion without waiting for the SPI read operation to complete after triggering the SPI read operation. The second state machine 102 runs in parallel with the first state machine 101 and is used to respond to the SPI read operation triggered by the first state machine 101 and independently control the SPI data read timing of the ADC. The first state machine 101 and the second state machine 102 are implemented using a standard hardware description language.

[0029] The first state machine 101 is only responsible for detecting the start and completion of the analog-to-digital converter (ADC). Once the conversion is complete, it immediately triggers the SPI read and returns to the waiting state to start the waiting for the next sampling, without waiting for the SPI read operation to complete. The second state machine 102 is independently responsible for SPI data reading. When it detects the SPI start signal issued by the first state machine 101, it wakes up from the idle detection state and starts to execute the SPI read process of multi-channel data. The two state machines run in parallel under the same clock domain, so that the SPI read of the Nth sampling and the analog-to-digital (AD) conversion of the N+1th sampling form a pipeline overlap in time. It is implemented using a standard hardware description language (such as Verilog-2001) to ensure that the code does not depend on any proprietary primitives of any FPGA vendor, thereby achieving cross-platform portability.

[0030] It solves the problems of low sampling rate (because the SPI read time is no longer included in the sampling period), low resource utilization (the analog-to-digital converter chip can start the next conversion during the SPI read), and difficulty in cross-platform porting caused by the serial execution of traditional single-state machines (implemented in a standard language, freeing it from the dependence on vendor-specific primitives).

[0031] The sampling rate is significantly improved, reaching over 168kHz in actual measurements, which is 572% higher than traditional solutions. The utilization rate of the analog-to-digital converter chip is close to 100%, and it is only idle during the BUSY waiting period. The code can be directly compiled and run on FPGA platforms from different manufacturers such as Xilinx, Intel, Anlu, and Fudan Micro Cloud, realizing "write once, deploy everywhere".

[0032] Table 1: Performance Comparison of Traditional Solution and Invention Solution (System Clock 25MHz)

[0033] As shown in Table 1, the present invention increases the sampling rate from 25kHz in the traditional scheme to 168kHz, an increase of 572%. The actual tested sampling rate is 152.4kHz higher than the theoretical value. This is due to the efficient scheduling of the pipeline and the optimized design of the state machine. At the same time, the analog-to-digital converter chip in the present invention is no longer idle during SPI reading, and the resource utilization rate is increased from 50% to over 95%.

[0034] The theoretical improvement rate is +556.9% (calculation baseline: (152.4-23.2) / 23.2 = 556.9%).

[0035] Among them, the first state machine 101 (transition control state machine)

[0036] Responsible for controlling the conversion timing of CL1606, including the following states:

[0037] Key innovation: In the AD_CSN state, after the first state machine 101 sets spi_start=1'b1, it immediately jumps back to the AD_IDLE state without waiting for the SPI read to complete.

[0038] Second state machine 102 (SPI read state machine)

[0039] Responsible for independently controlling SPI data reading, including the following states:

[0040] The two state machines are synchronized using the following signals: spi_start (output by state machine 101): indicates that the analog-to-digital (AD) conversion is complete and SPI reading can begin.

[0041] spi_start_wr (used internally by the second state machine 102): used to maintain SPI clock enable.

[0042] Shared clock domain: The two state machines operate under the same clock domain (25MHz).

[0043] Compared to traditional methods, the sampling rate is improved, specifically as follows:

[0044] Note: The sampling rate is limited by the CL1606 chip specifications (maximum 200KHz). This solution provides margin for chip cascading and overclocking applications.

[0045] CONVST: Conversion start signal, generated by the first state machine, active low, pulled low for 4 clock cycles to start the analog-to-digital converter (AD) conversion.

[0046] BUSY: Busy signal, output by the analog-to-digital converter. A high level indicates that the converter is in the conversion state, and a low level indicates that the conversion is complete.

[0047] CS_N: Chip select signal, generated by the second state machine, active low, used to select the analog-to-digital converter to be read.

[0048] SCLK: SPI clock signal, generated by the second state machine, provides a clock reference for SPI data transmission, and is fixed at 12.5MHz in this scheme.

[0049] DOUTA and DOUTB dual-channel data signals: SPI data signals, which are sampled data signals transmitted from the analog-to-digital converter to the FPGA, and are output serially.

[0050] Multi-channel read state: The core working state of the second state machine, collectively referring to the four sub-states AD_CH1_5, AD_CH2_6, AD_CH3_7, and AD_CH4_8. Each sub-state reads 16-bit data from two channels.

[0051] Furthermore, the state transition paths of the first state machine 101 include: Idle waiting state (AD_IDLE): The first state machine 101 maintains a preset number of waiting cycles (e.g., 149 clock cycles) in this state to meet the sampling cycle requirements.

[0052] Conversion Start-up State (AD_CVAB): In this state, pull the CONVST signal low and maintain it for several cycles (e.g., 4 clock cycles) to start the analog-to-digital converter conversion.

[0053] Conversion Completion Detection Status (AD_BUSY1 / AD_BUSY2): The BUSY signal goes high after the analog-to-digital converter starts conversion and goes low after conversion is complete. This status detects the rising and falling edges of the BUSY signal to confirm conversion completion.

[0054] Triggering state (AD_CSN): After the conversion is complete, an SPI start signal (spi_start) is generated in this state, and the idle waiting state is returned immediately.

[0055] The state machine has a simple structure, a small number of states (only 5 states), low logic complexity, easy timing convergence, and configurable waiting period. It is convenient to adjust the sampling rate according to different system clocks and analog-to-digital converter models, and solves the problem of how to accurately control the timing of analog-to-digital converter conversion, ensuring that the conversion process meets the timing requirements of CL1606. The clear state division makes the logic of the first state machine 101 clear, easy to implement and debug.

[0056] Furthermore, after generating a start signal in the triggered state, the first state machine 101 immediately jumps back to the idle waiting state and begins the waiting count for the next sampling.

[0057] Limiting the behavior of the first state machine 101 after the trigger state—immediately jumping back to the idle waiting state instead of waiting for the SPI read to complete—is a key step in achieving pipelined parallelism. By completing the state transition within the same clock cycle of generating the spi_start signal, the first state machine 101 can immediately start the waiting count for the next sample, which completely overlaps with the SPI read operation of the second state machine 102.

[0058] It achieves true pipelined operation, with the sampling period determined solely by the waiting period plus the transition time, independent of the SPI read time. This greatly improves the sampling rate and solves the problem in traditional solutions where the state machine must wait for the SPI to complete before continuing, thus eliminating the SPI read time's impact on the sampling period.

[0059] Reference Figure 1 The state transition paths of the second state machine 102 include: Idle detection state (AD_IDLE): In this state, the second state machine 102 monitors the spi_start signal issued by the first state machine 101. When spi_start is detected to be valid, it enters the multi-channel read state.

[0060] Multi-channel read state: Reads data from multiple channels of the analog-to-digital converter sequentially. For the CL1606, there are usually 8 channels, which can be divided into 4 read states (each state reads 2 channels).

[0061] Read complete status (AD_STOP): After all channel data has been read, the chip select signal CS_N is pulled high, the ad_done flag is set, indicating that a complete SPI read is completed, and then the idle detection state is returned to wait for the next trigger.

[0062] The SPI read state machine operates independently and is not affected by the state changes of the first state machine 101, which improves the stability and reliability of the system. The multi-channel read state design simplifies the logic within each state, facilitates timing optimization, solves the problem of how to independently control the SPI read timing, decouples it from the first state machine 101, clarifies the complete SPI read process, and ensures that the data is read correctly.

[0063] Reference Figure 1 The multi-channel read state is configured to continuously read sampled data from multiple channels within a single state cycle. For example, in the CL1606 application, two channels can be read per state cycle. For instance, the AD_CH1_5 state reads data from channels 1 and 5 simultaneously, the AD_CH2_6 state reads data from channels 2 and 6 simultaneously, and so on. This design leverages the CL1606's SPI interface's support for continuous multi-channel data output. By reading multiple channels within a single state, it effectively reduces the number of state machine states, simplifies logic design, and improves read efficiency. It should be noted that the number of channels read per state cycle can be adjusted according to the specific analog-to-digital converter chip's interface protocol and system requirements, and is not limited to two.

[0064] In serial SPI mode, the CL1606 is equipped with two independent data output lines, DOUTA and DOUTB, which output the sampled data of the odd and even channels respectively. Specifically, DOUTA outputs the data of channels 1, 3, 5, and 7 in sequence, and DOUTB outputs the data of channels 2, 4, 6, and 8 in sequence. Therefore, in each 16 SCLK cycle, the second state machine 102 reads the data of two channels (such as channels 1 and 2, channels 3 and 4, etc.) simultaneously through the two data lines DOUTA and DOUTB, obtaining a total of 32 bits of valid data. The scheme is not limited to the specific interface naming of the CL1606; any analog-to-digital converter with at least one serial data output can be used.

[0065] The number of state machine states has been reduced from a possible 8 to 4, making the logic simpler. Two channels are read continuously within each state, and the SPI timing is continuous, reducing the frequent switching of the chip select signal, improving reading efficiency, solving the problem of how to efficiently read multi-channel data, and avoiding the complexity of the state machine due to too many states.

[0066] Reference Figures 1-4 The number of clock cycles maintained by the first state machine 101 in the idle waiting state is a configurable parameter. Its value is determined based on the maximum throughput rate of the analog-to-digital converter and the system clock frequency to ensure that the sampling period does not exceed the theoretical minimum sampling period of the analog-to-digital converter, while also taking into account system stability.

[0067] Taking the CL1606 analog-to-digital converter as an example, its maximum throughput rate is 200kSPS. The corresponding theoretical minimum sampling period is calculated using a 25MHz system clock. The single clock cycle T is obtained by calculating the system clock frequency using the formula. clk =1 / 25×10⁶Hz=40ns, the timing cycle of the CL1606's analog-to-digital (AD) conversion is 15 fixed clock cycles (corresponding to 15×40ns=600ns=0.6μs). This cycle is an inherent property of the chip hardware and is not adjusted with system optimization. The number of clock cycles maintained by the first state machine 101 in the idle waiting state is a configurable parameter, and its value is determined based on the maximum throughput rate of the analog-to-digital converter and the system clock frequency. The core calculation formula is: number of idle waiting cycles ≤ (theoretical minimum sampling period of the analog-to-digital converter / single clock cycle) - number of fixed conversion timing cycles. In practical applications, engineering factors such as PCB trace delay, BUSY signal timing margin, and signal stabilization time need to be taken into account. After multiple sets of experimental optimizations, 149 25MHz clock cycles were determined to be the optimal number of waiting cycles. The corresponding waiting time is 149 × 40 ns = 5960 ns = 5.96 μs. This sampling period slightly exceeds the theoretical minimum but is still close to the chip's throughput limit. The core reasons include: ① The actual conversion time of the chip is similar to the typical value in the datasheet. After the conversion is started, the BUSY signal output by the analog-to-digital converter only maintains a high level for about 90 clock cycles to complete the conversion, releasing its respective margin; ② The first state machine triggers SPI in the AD_CSN state and then triggers back to AD_IDLE in the same clock cycle, making the waiting time start point more compact and effectively shortening the sampling period; ③ The actual operating frequency of the system clock is 25.1 MHz (a slight deviation is within the allowable range of industrial-grade FPGAs). After conversion, the actual waiting time is about 149 / (25.1 × 106) = 5.93 μs, which is closer to the theoretical value.

[0068] In this invention, the single sampling period is uniformly defined as: the total number of clock cycles from the start of the first state machine 101 from the idle waiting state, when the level completes one analog-to-digital (AD) conversion and triggers the SPI read operation, and then jumps back to the idle waiting state. Since the SPI read cycle executed by the second state machine 102 and the next sampling analog-to-digital (AD) conversion process form a cycle in time, the SPI read is not included in the total single sampling period.

[0069] The total number of sampling cycles per session consists of two parts: a configurable "idle wait period" and a fixed "analog-to-digital (AD) conversion" control period. Taking the optimal configuration as an example, the total number of sampling cycles per session is approximately 164 (including 149 idle wait periods and 15 fixed "analog-to-digital (AD) conversion" control periods). Since the "analog-to-digital (AD) conversion" control period is a fixed value implemented by logic, in practical applications, users can refresh and modify the idle wait period of the first state machine 101 to achieve precise adjustment of the overall sampling rate of the system. The calculation rules for the improvement ratio in the two performance comparison tables are unified: theoretical improvement ratio = (theoretical value of this scheme - theoretical value of the traditional scheme) / theoretical value of the traditional scheme × 100%, and measured improvement ratio = (measured value of this scheme - measured value of the traditional scheme) / measured value of the traditional scheme × 100%.

[0070] Table 2: Measured highest sampling rate (25MHz system clock) corresponding to different waiting cycles

[0071] As can be seen from Table 2, there is a clear trade-off between the number of waiting cycles and system performance: when the number of waiting cycles is too small (e.g., 100), the system stability is poor and the sampling rate is also low. As the number of waiting cycles increases, the system stability gradually improves and the sampling rate continues to rise. In the range of 140 to 155, fine-grained testing revealed that the system reaches the optimal balance point when the number of waiting cycles is 149: the sampling rate is the highest (168kHz), and it runs stably without errors for a long time. If the number of waiting cycles is further increased (e.g., 151 to 155), although the system remains stable, the sampling rate begins to decrease. When the number of waiting cycles increases to 180, the sampling rate drops significantly to 139kHz.

[0072] The measured sampling rate of 168kHz corresponds to an actual sampling period of approximately 5.95μs, slightly higher than the theoretical minimum period of 5μs, but close to the upper limit of 200kSPS for the CL1606 chip. The reason why the measured value is slightly higher than the theoretical calculated value (152kHz) is mainly due to: ① The actual conversion time of the chip is better than the typical value in the datasheet, which reduces the clock cycles occupied in the conversion stage; ② In the pipeline scheduling, the first state machine returns to AD_IDLE immediately after triggering SPI in the AD_CSN state, making the starting point of the waiting timer more compact and effectively shortening the sampling period; ③ There is a slight positive deviation in the system clock, with the actual frequency slightly higher than 25MHz, which further shortens the sampling period after conversion.

[0073] When faced with different system clock frequencies or different analog-to-digital converter chip models, those skilled in the art can refer to the above experimental method to determine the optimal value suitable for specific application scenarios by adjusting the number of waiting cycles and observing the changes in system stability and sampling rate. For example, if the system clock is increased to 50MHz, the number of waiting cycles needs to be adjusted accordingly (the waiting time remains unchanged, and the number of cycles is doubled) to ensure that the waiting time matches the conversion time and avoid timing violations or waste of sampling rate.

[0074] By setting the number of clock cycles in the idle waiting state as a configurable parameter, it is possible to optimize for different models of analog-to-digital converters and different frequency system clocks, maximize the utilization of analog-to-digital converter performance, avoid sampling rate waste or timing violations caused by fixed waiting periods, and achieve a measured sampling rate of 168kHz, which is more than 5.72 times higher than the traditional solution. The determined optimization method is simple, reliable and easy to implement on various hardware platforms.

[0075] Furthermore, when reading channel data, the second state machine 102 sets the data sampling point in a stable region far from the data transition edge within the SPI clock cycle to increase timing margin. Specifically, in SPI communication, data typically changes at clock edges (such as falling edges). If the sampling point is too close to this edge, bit errors may occur due to unstable data or transmission delays. By placing the sampling point in the middle of the clock cycle or at a reliable position determined by static timing analysis, the data setup and hold times can be ensured to meet the requirements. For example, in a preferred embodiment of the present invention, when the SPI clock frequency is 12.5MHz, setting the sampling point 40ns after the rising edge of SCLK (i.e., the middle point of the clock cycle) allows for reliable data reading. In practical applications, the optimal sampling point can be calculated through static timing analysis and must satisfy: T sample ≥T co +T delay +T setup , among which, T sample T is the time from the data transition edge to the rising edge of the FPGA's internal sampling clock. co For the data output delay of the analog-to-digital converter, T delay For PCB trace delay, T setup Establishment time for FPGA input registers.

[0076] It increases the timing margin for data setup, reduces the sensitivity to PCB layout and signal quality, enables the system to work stably at higher SPI clock frequencies, avoids occasional data errors caused by improper sampling point settings, improves the robustness of the system, solves the problem of unstable data sampling during SPI reading, and improves the reliability of the system.

[0077] Furthermore, the system supports cascading expansion of multiple analog-to-digital converters (ADCs). Synchronous control of multiple ADCs is achieved through sharing the SPI clock and chip select signal. When more channels are needed, multiple CL1606 chips can be cascaded. The hardware connection method is as follows: All analog-to-digital converter chips share dual data signals: CONVST, SCLK, DOUTA, and DOUTB.

[0078] Each analog-to-digital converter uses an independent chip select signal CS_N, which is controlled by the FPGA.

[0079] The BUSY signal can be connected to the FPGA via a logical AND operation (BUSY is high if any chip is busy), or it can be connected to the FPGA separately and then determined by software.

[0080] In terms of software implementation, the first state machine 101 remains unchanged (because all analog-to-digital converters convert simultaneously, sharing CONVST and BUSY). The second state machine 102 is expanded to sequentially select the CS_N of each analog-to-digital converter and read the data from the 8 channels of each chip. Since the SPI reading time is parallel to the conversion cycle, the sampling rate can still be maintained at the level of a single chip (close to 168kHz) after cascading, instead of the sampling rate decreasing linearly with the number of channels as in traditional schemes.

[0081] It supports channel expansion without sacrificing sampling rate, meeting the application requirements of high-speed synchronous acquisition of multiple channels. The hardware connection is simple, the software modification is minimal, and it is easy to implement, solving the problem of a significant drop in sampling rate caused by cascading multiple chips in traditional solutions.

[0082] Furthermore, the standard hardware description language is the Verilog-2001 standard syntax, and its implementation methods include: using standard always blocks to describe sequential logic, and using standard assign statements or always@(*) blocks to describe combinational logic.

[0083] The Verilog-2001 standard syntax is a hardware description language standard widely supported by all major FPGA synthesis tools. In its implementation: The sequential logic is described using the standard always@(posedge clk or negedge rst_n) block.

[0084] Combinational logic is described using the assign statement or the always@(*) block.

[0085] It does not instantiate any FPGA vendor-specific primitives (such as Xilinx's BUFG, IBUF, IDDR, ODDR, Intel's ALTDDIO, etc.).

[0086] It does not call any vendor-specific IP cores (such as PLL, FIFO, etc., unless a general module is instantiated through a standard language).

[0087] This implementation ensures platform independence of the code, allowing it to be compiled directly in FPGA synthesis tools from different vendors (such as Vivado, Quartus, Pango, GowinIDE, etc.) without requiring code modification.

[0088] It achieves "write once, run anywhere", significantly shortening the product porting cycle between different FPGA platforms, reducing dependence on specific vendor EDA tools, improving the independent controllability of the design, facilitating code reuse and maintenance, and allowing the same code to be used in multiple projects at the same time, solving the problem of code non-portability caused by the reliance on vendor-specific primitives in traditional solutions.

[0089] A dual-state machine high-speed sampling driving method adapted for FPGA is also provided, including the following steps: The first state machine 101 performs analog-to-digital (AD) conversion timing control and immediately returns to the waiting state after triggering the SPI read operation to begin waiting for the next conversion. After returning to the waiting state, the first state machine 101 continuously monitors the read completion flag (spi_done) fed back by the second state machine 102. Only when the flag is valid is it allowed to start waiting and starting the next conversion after the preset waiting period ends. If the preset waiting period has ended but spi_done is not yet valid, the first state machine 101 inserts an extra waiting period in the idle waiting state until spi_done is valid, thereby avoiding conflict with the previous incomplete SPI read.

[0090] The second state machine 102 responds to the SPI read operation and independently performs SPI data reading. Before each new SPI read begins, the second state machine 102 automatically clears the spi_done flag and sets it again after the read is completed.

[0091] The SPI data reading of the Nth sample and the analog-to-digital (AD) conversion of the N+1th sample are executed in parallel in time, forming a pipeline structure.

[0092] The first state machine 101 performs analog-to-digital (AD) conversion timing control, including waiting for a preset period, starting the conversion, detecting the completion of the conversion, and triggering SPI reading. After triggering SPI reading, the first state machine 101 immediately returns to the waiting state: without waiting for the SPI reading to complete, it directly starts the waiting count for the next conversion. The second state machine 102 responds to the SPI start signal and independently performs SPI data reading: reading the data of all channels in sequence. The SPI reading of the Nth sample and the analog-to-digital (AD) conversion of the N+1th sample are executed concurrently in time.

[0093] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A dual-state machine high-speed sampling drive system adapted to FPGA, characterized in that, include: The first state machine (101) is used to control the conversion timing of the analog-to-digital converter. The first state machine (101) is configured to return to the waiting state for the next conversion without waiting for the SPI read operation to be completed after the SPI read operation is triggered. The second state machine (102) runs in parallel with the first state machine (101) and is used to respond to the SPI read operation triggered by the first state machine (101) and independently control the SPI data read timing of the analog-to-digital converter. The first state machine (101) and the second state machine (102) are implemented using a standard hardware description language.

2. The dual-state machine high-speed sampling drive system adapted to FPGA as described in claim 1, characterized in that: The state transition path of the first state machine (101) includes: Idle waiting state, used to maintain a preset waiting period; "Change start state to generate CONVST signal to start analog-to-digital (AD) conversion"; The conversion completion detection status is used to monitor the BUSY signal to confirm that the conversion is complete. Trigger state, used to generate the start signal for the SPI read operation.

3. The dual-state machine high-speed sampling drive system adapted to FPGA as described in claim 2, characterized in that: After the first state machine (101) generates a start signal in the trigger state, it immediately jumps back to the idle waiting state and starts the waiting count for the next sampling.

4. The dual-state machine high-speed sampling drive system adapted to FPGA as described in claim 3, characterized in that: The state transition path of the second state machine (102) includes: The idle detection state is used to monitor the SPI start signal triggered by the first state machine (101); Multi-channel read mode, used to sequentially read data from multiple channels of the analog-to-digital converter; The read completion status is used to end the SPI read and set the completion flag.

5. The dual-state machine high-speed sampling drive system adapted to FPGA as described in claim 4, characterized in that: The multi-channel read state includes continuously reading 16-bit data from two channels within one state cycle.

6. The dual-state machine high-speed sampling drive system adapted to FPGA as described in claim 5, characterized in that: The number of clock cycles that the first state machine (101) maintains in the idle waiting state is determined based on the maximum throughput rate of the analog-to-digital converter and the system clock frequency.

7. The dual-state machine high-speed sampling drive system adapted to FPGA as described in claim 6, characterized in that: When reading channel data, the second state machine (102) sets the data sampling point in a stable interval within the SPI clock cycle that avoids the data transition edge. The setting of the sampling point satisfies the timing constraint formula T. sample ≥T co +T delay +T setup T sample T is the time from the data transition edge to the rising edge of the FPGA's internal sampling clock. co T is the data output delay of the analog-to-digital converter. delay For PCB trace delay, T setup The setup time for the FPGA input register is set at the middle of the SPI clock cycle 40ns after the rising edge of SCLK in an application scenario with an SPI clock frequency of 12.5MHz.

8. The dual-state machine high-speed sampling drive system adapted to FPGA as described in claim 7, characterized in that: The system supports the cascading expansion of multiple analog-to-digital converters (ADCs). Synchronous control of multiple ADCs is achieved by sharing the SPI clock, CONVST conversion start signal, DOUTA and DOUTB dual data signals, and configuring an independent chip select signal CS_N for each ADC. The BUSY signal of multiple analog-to-digital converters is connected to the FPGA after being ANDed with logic. When any analog-to-digital converter is in the conversion state, the BUSY signal is high. The second state machine (102) of the FPGA reads the channel data of each analog-to-digital converter by sequentially selecting the independent CS_N of each analog-to-digital converter. The first state machine (101) performs unified analog-to-digital (AD) conversion timing control on multiple analog-to-digital converters.

9. The dual-state machine high-speed sampling drive system adapted to FPGA as described in any one of claims 1, 2, 4 to 8, characterized in that: The standard hardware description language is Verilog-2001 standard syntax, and its implementation includes: using standard always blocks to describe sequential logic, and using standard assign statements or always@(*) blocks to describe combinational logic.

10. A dual-state machine high-speed sampling driving method adapted to FPGA, implemented using the dual-state machine high-speed sampling driving system adapted to FPGA as described in any one of claims 1 to 9, characterized in that: Includes the following steps: The first state machine (101) performs analog-to-digital (AD) conversion timing control and immediately returns to the waiting state after triggering the SPI read operation to begin waiting for the next conversion; The second state machine (102) responds to the SPI read operation and independently performs SPI data reading; The SPI data reading of the Nth sample and the analog-to-digital (AD) conversion of the N+1th sample are executed in parallel in time, forming a pipeline structure.

Images