A random instruction-based fault injection detection method and related apparatus

Abstract

The application discloses a fault injection detection method based on random instructions and related devices, and relates to the technical field of information security. In the random instruction generation stage, the application applies a preset mathematical constraint code to one or more encoding bits of the random instruction, and injects the instruction carrying the encoding feature into a downstream operation or memory unit; when the downstream unit executes the instruction, it checks whether the actual calculation result conforms to the preset mathematical constraint code in parallel. If the check fails, it is determined that a fault injection attack has occurred. The application applies a preset encoding constraint to the random instruction, so that the random instruction itself carries verifiable fault detection information; the downstream module uses the encoding feature to perform fault injection detection in parallel, so that the random instruction has both side channel defense and fault injection detection functions. The detection logic is deeply integrated with normal instruction flow, has strong concealment, and is difficult to be evaded by attackers.

Description

Technical Field

[0001] This invention relates to the field of processor technology, and in particular to a fault injection detection method and related apparatus based on random instructions. Background Technology

[0002] In information security processors, defending against side-channel attacks and fault injection attacks are two core security requirements. For side-channel attacks, existing technologies typically employ random instruction injection, which involves inserting random instructions into a specific stage of the processor's pipeline to disrupt the processor's physical characteristics, such as power consumption and current flow, thereby increasing the difficulty of side-channel attacks. For example... Figure 1 The diagram shown is a schematic of an existing scheme for random instruction injection.

[0003] However, the aforementioned random instruction injection schemes only defend against side-channel attacks by obfuscating physical characteristics. The inserted random instructions themselves do not possess fault detection capabilities, thus failing to improve the processor's resistance to fault injection attacks. Attackers can still alter instruction execution results or data flow through methods such as voltage glitches and laser irradiation, without the system's detection.

[0004] Therefore, there is a lack of existing technologies that can both defend against side-channel attacks using random instructions and effectively detect fault injection attacks. Summary of the Invention

[0005] The purpose of this invention is to provide a fault injection detection method and related apparatus based on random instructions, so as to solve the problem that existing random instructions cannot improve the fault injection resistance capability.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0007] A fault injection detection method based on random instructions, comprising:

[0008] Generate random instructions, wherein the random instructions are constrained to carry preset coding features;

[0009] The random instructions are injected into the processor's pipeline;

[0010] In the downstream module of the pipeline, a fault injection detection operation is performed using the encoding characteristics of the random instruction. The fault injection detection operation includes checking the correctness of the actual execution result of the random instruction based on the preset encoding characteristics.

[0011] If the inspection results do not meet the expected preset coding characteristics, a fault injection alarm signal will be output.

[0012] Furthermore, the random instruction is a random addition instruction, and the constraint includes applying a preset mathematical constraint encoding to the operands and / or immediate values ​​of the random addition instruction; the fault injection detection operation includes at least one of the following:

[0013] Check whether the operands read from the register file satisfy the preset mathematical constraint encoding;

[0014] Check whether the calculation result of the arithmetic operation unit satisfies the preset mathematical constraint encoding.

[0015] Furthermore, the random instruction is a random conditional branch instruction, and the constraint includes applying a preset mathematical constraint encoding to the operands and / or immediate values ​​of the random conditional branch instruction; the fault injection detection operation includes at least one of the following:

[0016] Check whether the operands read from the register file satisfy the preset mathematical constraint encoding;

[0017] Check whether the comparison result of the arithmetic operation unit satisfies the preset mathematical constraint encoding;

[0018] Check whether the prediction result of the branch prediction unit is consistent with the conditions implied by the preset mathematical constraint encoding.

[0019] Further, the random instruction is a random loading instruction, and the constraints include applying a preset mathematical constraint encoding to the operands and / or immediate values ​​of the random loading instruction, and / or applying preset characteristics to the loaded data; the fault injection detection operation includes at least one of the following:

[0020] Check whether the operands read from the register file and the immediate value encoding satisfy the preset mathematical constraint encoding;

[0021] Check whether the calculation result of the address generation unit satisfies the preset mathematical constraint encoding;

[0022] Check if the address of the loaded storage unit meets the preset range;

[0023] Check whether the read data returned from downstream meets the preset characteristics;

[0024] Check whether the written-back data meets the preset characteristics.

[0025] The present invention also provides a processor configured to perform the methods described above.

[0026] The present invention also provides a chip including the processor according to the above description.

[0027] The present invention also provides an electronic device comprising the chip described above.

[0028] Beneficial effects:

[0029] This invention imposes preset encoding constraints on random instructions, enabling the random instructions to carry verifiable fault detection information. Downstream modules utilize this encoding feature to perform fault injection detection in parallel, thus giving the random instructions both side-channel defense and fault injection detection capabilities. This detection logic is deeply integrated with the normal instruction pipeline, exhibiting strong concealment and making it difficult for attackers to circumvent. Attached Figure Description

[0030] Figure 1 A schematic diagram of a random instruction injection scheme in existing technology;

[0031] Figure 2 This is a schematic diagram of the random instruction injection scheme in this invention;

[0032] Figure 3 This is a schematic diagram of the random addition instruction (add) in this invention;

[0033] Figure 4 This is a schematic diagram of the random conditional branch instruction (beq) in this invention;

[0034] Figure 5 This is a schematic diagram of the random loading instruction (lb) in this invention. Detailed Implementation

[0035] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0036] Example 1

[0037] This embodiment provides a fault injection detection method based on random instructions, such as... Figure 2 As shown, the specific steps include:

[0038] Step 1: Generate random instructions.

[0039] The Random Instruction Generator (RIG) receives random numbers and control signals, and generates random instructions carrying preset mathematical constraint codes under the received preset mathematical constraint code input.

[0040] Step 2: Inject the random instructions into the processor pipeline.

[0041] This random instruction is injected into each stage of the instruction fetch unit (IFU) pipeline (IFU_ip1 to IFU_n) via a selector (MUX), running in parallel with the normal instruction fetch request / return path.

[0042] Step 3: In the downstream module of the pipeline, a fault injection detection operation is performed using the encoding characteristics of the random instruction. The fault injection detection operation includes checking the correctness of the actual execution result of the random instruction based on the preset encoding characteristics. If the check result does not meet the expectation of the preset encoding characteristics, a fault injection alarm signal is output.

[0043] like Figure 2 As shown, the instruction flow passes through the Decoder (DEC), Multiplication Unit (MUL), Branch Prediction Unit (BJP), Arithmetic Logic Unit (ALU), Address Generation Unit (AGU), Load Memory Unit (LSU), and other modules within the Execution Unit (EXU), and is completed through Write-Back Arbitration (WBCK) and Commit (CMT). Random instruction error checks 1 to 16 are set at each of the above instruction fetch stages, decoding, ALU, AGU, LSU, write-back, and commit locations. Figure 2 (See annotations). Different instruction types will activate some of the checkpoints, as described below. It should be noted that the preset mathematical constraint encoding mentioned in this invention can be applied to any encoding bit of a random instruction, including but not limited to operands, immediate values, opcodes, function codes, reserved bits, etc. This application uses operands and / or immediate values ​​as examples for illustration, but this does not constitute a limitation on the scope of protection.

[0044] Based on the above architecture, this embodiment will further illustrate the concept using a random addition instruction as an example. Figure 3 As shown, when generating random instructions, for example, the preset mathematical constraint applied to the random addition instruction (add) is encoded so that the two operand indices are the same. Specifically, the operand index fields rs1idx and rs2idx in the instruction code are set to the same register number.

[0045] After the random addition instruction is injected into the processor pipeline, it enters the downstream arithmetic unit. Multiple error checkpoints, as shown in Table 1, are set at locations such as the decoding and execution stages.

[0046] Table 1 Error Checking for Random Addition Instruction (add)

[0047]

[0048] Random instruction error checks 1-1 to 1-4 verify the consistency of operand indices in the instruction code and the consistency of operand values ​​read from the register file. Random instruction error check 1-5 further verifies whether the actual values ​​of the two operands are equal. Random instruction error check 1-6 checks whether the calculation result satisfies the preset mathematical constraint encoding after the arithmetic unit completes the addition operation. For example, when the constraint is that the two operand indices are the same, the calculation result should be equal to twice the value of operand 1, i.e., R[rs1] + R[rs1].

[0049] It should be noted that the use of identical operand indices here is a specific example of a predefined mathematical constraint encoding. In actual implementations, the predefined mathematical constraint encoding can be any mathematical relationship that can be verified by downstream modules, such as equality relationships between operands, arithmetic relationships, bit constraints, etc., and is not limited to this example.

[0050] If any check fails, a fault injection attack is detected, and the processor may trigger an alarm, interrupt, or enter a safe state. If all checks pass, the random addition instruction writes back the result normally.

[0051] Example 2

[0052] Steps 1 and 2 in this embodiment are the same as in Embodiment 1. The difference is that the random instruction in this embodiment is a random conditional branch instruction (beq). The specific operation of step 3 is as follows.

[0053] Step 3: In the downstream module of the pipeline, a fault injection detection operation is performed using the encoding characteristics of the random instruction.

[0054] like Figure 4 As shown, when generating random instructions, for example, the preset mathematical constraint applied to the random conditional branch instruction (beq) is encoded so that the two operand indices are the same. Specifically, the rs1idx and rs2idx fields in the instruction code are set to the same register number.

[0055] After the random conditional branch instruction (beq) is injected into the processor pipeline, error checkpoints are set in the arithmetic unit and the branch prediction unit as shown in Table 2.

[0056] Table 2 Error Checking for Random Conditional Branch Instructions (beq)

[0057]

[0058] Random instruction error checks 2-1 to 2-5 verify operand index consistency and operand value equality. Since the two operand indices are the same, the read operand values ​​should be equal; therefore, the comparison result of the arithmetic unit should be "equal". Random instruction error check 2-6 also checks whether the comparison result is equal and whether the prediction result of the branch prediction unit meets expectations; that is, a jump should be executed when the random conditional branch instruction condition is met.

[0059] It should be noted that the use of identical operand indices here is a specific example of encoding a predefined mathematical constraint. Other implementations can also employ other mathematical constraints, such as one operand being a multiple of another, or operands and immediate values ​​satisfying a certain relationship, as long as the constraint implicitly implies that the comparison result is the expected value and can be verified downstream.

[0060] If the checks are inconsistent, a fault injection attack is determined to have occurred. Otherwise, the branch instruction will proceed according to the normal flow, either jumping or continuing sequentially.

[0061] Example 3

[0062] Steps 1 and 2 of this embodiment are the same as those of Embodiment 1. The difference is that the random instruction in this embodiment is a random loading instruction (lb). The specific operation of step 3 is as follows.

[0063] Step 3: In the downstream module of the pipeline, a fault injection detection operation is performed using the encoding characteristics of the random instruction.

[0064] like Figure 5 As shown, when generating a random instruction, for example, the preset mathematical constraint applied to the random load instruction (lb) is encoded such that the index of operand 1 is the same as the index of the equivalent operand 2, wherein the index of the equivalent operand 2 is located in the lower 5 bits of the immediate value and the higher 7 bits of the immediate value are 0.

[0065] It should be noted that the decoding logic forces the equivalent operand 2 index value to be read from the register file, and then saves the read equivalent operand 2 value by copying it back, such as... Figure 5 The annotation indicates that "the lower 5 bits of the immediate value are used as an index to the equivalent operand 2 to access the register file and push it to the downstream pipeline." Furthermore, for inserted random load instructions (lb), the higher 22 bits of the actual memory access address are specified through a special register.

[0066] After the random load instruction (lb) is injected into the processor pipeline, error checkpoints are set in stages such as decoding, address generation, memory access, and write-back, as shown in Table 3, which correspond to... Figure 5 Error checks 3-1 to 3-5, 3-12, 3-13, 3-14, and 3-15 are performed.

[0067] Table 3 Error checks for random load instructions (lb)

[0068]

[0069] Specifically, random instruction error checks 3-1 to 3-5 verify the consistency of operand indices in the instruction code, whether the immediate value encoding meets the preset mathematical constraint encoding (e.g., the lower 5 bits of the immediate value equal the index of operand 1 and the higher 7 bits are 0), and whether the values ​​of the two operands read are equal). Random instruction error check 3-12 verifies whether the calculation result of the address generation unit meets the preset mathematical constraint encoding (e.g., the immediate value after sign extension of operand 1 should equal the index value of operand 1 plus the value of operand 2; since the higher 7 bits of the immediate value are 0, this addition is actually equivalent to adding only 0). Random instruction error checks 3-13 to 3-14 verify whether the higher 22 bits of the memory access address are equal to the value in the special register, and check whether the data returned from memory is a preset characteristic value, such as 0x5c. This preset characteristic value requires downstream memory access units to perform special processing on the randomly injected random load instruction (lb), such as forcing a return of 0x5c. Random instruction error check 3-15 checks whether the data written back to the register meets the preset characteristic value.

[0070] It should be noted that the preset mathematical constraint encoding for the load instruction here specifically refers to the operand 1 index being equal to the lower 5 bits of the immediate value and the higher 7 bits of the immediate value being 0, and the preset characteristic value being 0x5c. These are merely examples. In other implementations, different mathematical constraints can be used, such as the higher 7 bits of the immediate value being in a fixed pattern, the operand index and the immediate value satisfying a linear relationship, and different preset data characteristics, as long as they can be verified downstream.

[0071] If any of the above checks fails, a fault injection attack is determined to have occurred. If all checks pass, the random loading instruction completes normally.

[0072] Based on the same inventive concept, the present invention also provides a processor configured to perform the methods described in any of the above embodiments.

[0073] Specifically, the processor includes a random instruction generation unit, a pipeline, and a fault detection unit located in a downstream module of the pipeline, such as... Figure 2 The selector, each level of instruction fetch, and each checkpoint in the execution unit are shown to implement the random instruction generation, instruction injection, and fault checking operations under the preset mathematical constraint encoding in the above embodiments.

[0074] The present invention also provides a chip comprising the processor described above.

[0075] The present invention also provides an electronic device comprising the above-described chip.

[0076] Although embodiments of the present invention have been described in the specification, these embodiments are merely illustrative and should not be construed as limiting the scope of protection of the present invention. Various omissions, substitutions, and modifications made without departing from the spirit of the present invention should be included within the scope of protection of the present invention.

Claims

1. A fault injection detection method based on random instructions, characterized in that, include: Generate random instructions, wherein the random instructions are constrained to carry preset coding features; The random instructions are injected into the processor's pipeline; In the downstream module of the pipeline, a fault injection detection operation is performed using the encoding characteristics of the random instruction; the fault injection detection operation includes checking the correctness of the actual execution result of the random instruction based on the preset encoding characteristics; If the inspection results do not meet the expected preset coding characteristics, a fault injection alarm signal will be output.

2. The fault injection detection method based on random instructions according to claim 1, characterized in that, The random instruction is a random addition instruction, and the constraint includes applying a preset mathematical constraint encoding to the operands and / or immediate values ​​of the random addition instruction; the fault injection detection operation includes at least one of the following: Check whether the operands read from the register file satisfy the preset mathematical constraint encoding; Check whether the calculation result of the arithmetic operation unit satisfies the preset mathematical constraint encoding.

3. The fault injection detection method based on random instructions according to claim 1, characterized in that, The random instruction is a random conditional branch instruction, and the constraint includes applying a preset mathematical constraint encoding to the operands and / or immediate values ​​of the random conditional branch instruction; the fault injection detection operation includes at least one of the following: Check whether the operands read from the register file satisfy the preset mathematical constraint encoding; Check whether the comparison result of the arithmetic operation unit satisfies the preset mathematical constraint encoding; Check whether the prediction result of the branch prediction unit is consistent with the conditions implied by the preset mathematical constraint encoding.

4. The fault injection detection method based on random instructions according to claim 1, characterized in that, The random instruction is a random loading instruction, and the constraints include applying a preset mathematical constraint encoding to the operands and / or immediate values ​​of the random loading instruction, and / or applying preset characteristics to the loaded data; The fault injection detection operation includes at least one of the following: Check whether the operands read from the register file and the immediate value encoding satisfy the preset mathematical constraint encoding; Check whether the calculation result of the address generation unit satisfies the preset mathematical constraint encoding; Check if the address of the loaded storage unit meets the preset range; Check whether the read data returned from downstream meets the preset characteristics; Check whether the written-back data meets the preset characteristics.

5. A processor, characterized in that, The processor is configured to execute the fault injection detection method based on random instructions as described in any one of claims 1 to 4.

6. A chip, characterized in that, Includes the processor according to claim 5.

7. An electronic device, characterized in that, Includes the chip according to claim 6.

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