Driving method of data driving device and data driving device

Abstract

A driving method of a data driving device and the data driving device are disclosed. The driving method includes receiving a data signal and a first clock signal from a timing controller, generating a second clock signal having a phase difference of 180° based on the received first clock signal, and transmitting first data to a data register based on the first clock signal, the first data being data of odd-numbered bits of the data signal, and transmitting second data to the data register based on the second clock signal, the second data being data of even-numbered bits of the data signal.

Description

Technical Field

[0001] This disclosure relates to a driving method for a data driving device and the data driving device itself. Background Technology

[0002] In high-speed data transmission environments, timing synchronization between clock and data signals is a significant technical challenge. Insufficient timing margin between clock and data signals can lead to data loss, signal distortion, or abnormal system operation. Such problems can be particularly pronounced in high-frequency environments.

[0003] In conventional systems, a mixed clock signal (CLK) and an inverted clock signal (CLKB) architecture is used to process data. However, this approach may limit the operating frequency due to insufficient timing margin between CLK and CLKB. In particular, stability may degrade in high-speed data transmission environments. Ensuring stable operation in high-frequency environments may also be impossible. Furthermore, there may be limitations in terms of system design scalability.

[0004] In particular, these limitations have emerged as major technical challenges in modern electronic and communication systems, where data transmission rates are constantly increasing and high-performance data processing is required. Summary of the Invention

[0005] Therefore, this disclosure relates to a driving method and a data driving device that substantially eliminates one or more problems caused by the limitations and disadvantages of the prior art.

[0006] This disclosure can solve the problem of operating frequency limitation due to insufficient timing margin between clock signal (CLK) and inverted clock signal (CLKB) during data processing, as well as the problem of reduced system stability in high-speed data transmission environments.

[0007] This disclosure is not limited to the foregoing aspects, and other aspects of this disclosure not described herein will be more clearly understood by those skilled in the art from the following description.

[0008] In one aspect of this disclosure, a driving method for a data driving device is provided, the driving method comprising the steps of: receiving a data signal and a first clock signal from a timing controller; generating a second clock signal having a phase difference of 180° based on the received first clock signal; and sending first data to a data register based on the first clock signal, the first data being odd-numbered bits of the data signal, and sending second data to the data register based on the second clock signal, the second data being even-numbered bits of the data signal.

[0009] In a driving method according to at least one embodiment of the present disclosure, sending first data to a data register based on a first clock signal may include: generating a third clock signal having a period corresponding to twice the period of the first clock signal; and generating a fifth clock signal delayed from the third clock signal by 1-CLK time, wherein the 1-CLK time may be based on the first clock signal.

[0010] In a driving method according to at least one embodiment of the present disclosure, sending first data to a data register based on a first clock signal may further include: sampling the first data at the rising edges of a third clock signal and a fifth clock signal to generate first parallel data.

[0011] In a driving method according to at least one embodiment of the present disclosure, sending first data to a data register based on a first clock signal may further include: generating a seventh clock signal having a period corresponding to four times the period of the first clock signal, and the seventh clock signal being delayed from the first clock signal by 1-CLK time; and generating a ninth clock signal being delayed from the seventh clock signal by 1-CLK time.

[0012] In a driving method according to at least one embodiment of the present disclosure, sending first data to the data register based on a first clock signal may further include: sampling the first parallel data at the rising edges of the seventh clock signal and the ninth clock signal to generate third parallel data; and sending the third parallel data to the data register.

[0013] In a driving method according to at least one embodiment of the present disclosure, sending the second data to the data register based on the second clock signal may include: generating a fourth clock signal having a period corresponding to twice the period of the second clock signal; and generating a sixth clock signal delayed from the fourth clock signal by 1-CLK time, wherein the 1-CLK time may be based on the first clock signal.

[0014] In a driving method according to at least one embodiment of the present disclosure, sending the second data to the data register based on the second clock signal may further include: sampling the second data at the rising edges of the fourth clock signal and the sixth clock signal to generate second parallel data.

[0015] In a driving method according to at least one embodiment of the present disclosure, sending second data to the data register based on the second clock signal may further include: generating an eighth clock signal having a period corresponding to four times the period of the second clock signal, and the eighth clock signal being delayed from the second clock signal by 1-CLK time; and generating the tenth clock signal being delayed from the eighth clock signal by 1-CLK time.

[0016] In a driving method according to at least one embodiment of the present disclosure, sending second data to the data register based on a second clock signal may further include: sampling the second parallel data at the rising edges of the eighth clock signal and the tenth clock signal to generate fourth parallel data; and sending the fourth parallel data to the data register.

[0017] In another aspect of this disclosure, a data driving device includes: a receiver configured to receive a data signal and a first clock signal from a timing controller; a first clock generator configured to generate a second clock signal having a 180° phase difference based on the received first clock signal; and a serial-to-parallel converter configured to send first data to a data register based on the first clock signal, the first data being odd-numbered bits of the data signal, and to send second data to the data register based on the second clock signal, the second data being even-numbered bits of the data signal.

[0018] In embodiments of this disclosure, the first clock generator may be configured to: generate a third clock signal having a period corresponding to twice the period of the first clock signal; and generate a fifth clock signal delayed from the third clock signal by 1-CLK time, wherein the 1-CLK time may be based on the first clock signal.

[0019] In embodiments of this disclosure, a first clock generator may be configured to: generate a fourth clock signal having a period corresponding to twice the period of the second clock signal; and generate a sixth clock signal delayed from the fourth clock signal by 1-CLK time. Attached Figure Description

[0020] The accompanying drawings, included to provide a further understanding of this disclosure and incorporated in and forming part of this application, illustrate embodiments of this disclosure and, together with the description, serve to explain the principles of this disclosure. In the drawings: Figure 1This is a diagram illustrating the configuration of a display device according to an embodiment of the present disclosure; Figure 2 This is a diagram showing the configuration of a data driving device according to an embodiment of the present disclosure; Figure 3 This is a diagram illustrating the operation of a serial-to-parallel converter and a second clock generator according to an embodiment of the present disclosure; Figure 4 This is a diagram showing the clock signal and data sampling timing in the serial-to-parallel converter during the first data transmission step according to an embodiment of this disclosure; and Figure 5 This is a diagram showing the clock signal and data sampling timing in the serial-to-parallel converter during the second data transmission step according to an embodiment of this disclosure. Detailed Implementation

[0021] This disclosure can be modified in various ways and various implementations can be provided. Therefore, this disclosure will be described below by way of a detailed description of specific embodiments shown in the accompanying drawings. However, the detailed description is not intended to limit this disclosure to the specific embodiments, and it should be understood that this disclosure includes all changes, equivalents, or substitutions within the spirit and scope of this disclosure.

[0022] The suffixes “module” and “unit” used here are only for distinguishing constituent elements and should therefore not be interpreted as indicating that the constituent elements are physically and chemically distinct or separable from each other, or implying that the constituent elements are distinguishable or separable from each other.

[0023] While terms including ordinal numbers such as “first” and “second” can be used to describe various constituent elements, constituent elements are not limited to these terms. These terms may be used simply as names to distinguish one constituent element from another, and the meaning of the order between constituent elements can be identified by the context of the description of the constituent elements, in place of the names.

[0024] The word “and / or” is used to include any combination of multiple items associated with it. For example, the phrase “A or B” would be understood to include all three cases: “A”, “B”, and “A and B”.

[0025] When an element is described as “connected” or “linked” to another element, it should be understood that the element may be directly connected or linked to the other element, or the other element may exist in between.

[0026] It should be noted that the terminology used herein is for describing particular embodiments only and is not intended to limit this disclosure. Incidentally, unless clearly used otherwise, singular expressions include plural meanings. In this application, the terms "comprising," "including," etc., are intended to indicate the presence of features, numbers, steps, operations, elements, portions, or combinations thereof, and do not exclude another feature, number, step, operation, element, portion, or any combination thereof or any addition thereof.

[0027] Unless otherwise defined, the terms used herein (including technical or scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. The terms used herein should be interpreted not only based on the definitions in any dictionary but also on their meanings as used in the art to which this disclosure pertains. Furthermore, unless explicitly defined, the terms used herein should not be interpreted in an overly idealistic or formal manner.

[0028] Furthermore, the terms "unit," "control unit," "control device," or "controller" are merely broad terms used to designate an apparatus for controlling a function associated with it, and therefore do not imply a general functional unit. For example, the device may include: a communication device configured to communicate with another controller or sensor for controlling a function to be performed by it; a recording medium readable by a computer and configured to store an operating system, logical commands, input / output information, etc.; and at least one processor configured to perform comparisons, discriminations, calculations, determinations, etc., required to control the function to be performed.

[0029] Additionally, the processor may include semiconductor integrated circuits and / or electronic components configured to perform at least one or more of comparison, discrimination, calculation, and determination to implement programmed functions. For example, the processor may be one or a combination of a computer, a microprocessor, a central processing unit (CPU), an application-specific integrated circuit (ASIC), a circuit, and a logic circuit.

[0030] The processor can be electrically connected to the memory. The processor can read data from the memory and write the read data. The memory and the processor can be integrated together or physically separated from each other.

[0031] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0032] Figure 1 This is a diagram illustrating the configuration of a display device according to an embodiment of the present disclosure.

[0033] Reference Figure 1The display driving device 100 may include a display panel 120, a timing controller 130, a gating driving device 140, a data driving device 110, etc.

[0034] Display panel 120 may be a liquid crystal display (LCD) panel or a self-emissive device panel, such as an organic light-emitting diode (OLED) panel.

[0035] When the display panel 120 is an LCD panel, it may include a backlight, liquid crystal, and a common electrode, and pixel electrodes and driving transistors may be disposed at each pixel. When a scan signal is applied to the gate of the driving transistor, the driving transistor is turned on, so that a data voltage can be provided to the pixel electrode. Then, according to the data voltage, an electric field is formed between the pixel electrode and the common electrode, changing the alignment direction of the liquid crystal. Therefore, the transmittance of light supplied from the backlight is changed, and the brightness of the pixel can be adjusted accordingly.

[0036] At the display panel 120, multiple data lines DL and multiple gate lines GL can be arranged in a matrix. Each data line DL can be connected to the source terminal of the driving transistor of its corresponding pixel, and each gate line GL can be connected to the gate terminal of the driving transistor of its corresponding pixel. When the scan signal SCN is provided to the gate line GL, the driving transistor is turned on, allowing the data voltage VD provided through the data line DL to be transmitted to the pixel electrode.

[0037] Display panel 120 can be a self-emissive device panel, such as an OLED panel. In addition to OLED panels, self-emissive device panels can also use other types of self-emissive devices, such as microLED panels.

[0038] At each pixel of an OLED panel, a scan transistor, a driving transistor, and the OLED itself can be positioned. When a scan signal SCN is applied to the gate of the scan transistor, the scan transistor turns on, and the data voltage VD can be supplied to the driving transistor through the scan transistor. In the OLED panel, the data voltage VD can be supplied to the gate of the driving transistor. The magnitude of the data voltage VD determines the intensity of the conduction current of the driving transistor, and the brightness of the OLED connected to the driving transistor can be adjusted according to the intensity of the conduction current.

[0039] Parasitic capacitors can be formed on the data line DL. These parasitic capacitors can be formed between the data line DL and the cathode of the OLED or between the data line DL and the anode of the OLED. On the side of the data driving device 110 that provides the data voltage VD, the parasitic capacitor can be considered a load. As the capacitance of the parasitic capacitor increases, the data driving device 110 should provide higher power to the data line DL.

[0040] The timing controller 130 can receive image data from an external device (e.g., a device referred to as a host or application processor (AP)). The timing controller 130 can convert the image data formatted for the external device into RGB image data in a format that can be processed by the data drive device 110. The timing controller 130 can then send the converted RGB image data to the data drive device 110.

[0041] Image data RGB may include pixel data indicating the grayscale value of each pixel P. Pixel data for a pixel P may be, for example, 8 bits of data and may represent a grayscale value selected from 0 to 255. Timing controller 130 may generate pixel data based on pixels and may send the pixel data to data drive device 110 provided that the pixel data is included in image data RGB.

[0042] The timing controller 130 can transmit control signals to devices associated with driving the display panel, such as the data driver 110 and the gating driver 140. The timing controller 130 can send a data control signal DCS to the data driver 110 and a gating control signal GCS to the gating driver.

[0043] Control signals DCS and GCS can include setting information for the individual devices associated with them. For example, timing controller 130 can receive setting information from external devices, identify the setting information of each device, and then send the setting information if the setting information is included in the corresponding control signal DCS or GCS.

[0044] The control signals DCS and GCS may include timing signals for controlling the various devices. Timing signals may include, for example, a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, etc. Based on the timing signals, the data drive device 110 or the strobe drive device 140 can distinguish frames and horizontal periods.

[0045] The gating drive 140 can provide a scan signal SCN to a pixel P disposed on the display panel 120. It can select the pixel to which the scan signal SCN, indicating conduction, is provided, and can provide a data voltage VD to the selected pixel.

[0046] The gating drive 140 can provide a scan signal SCN via gating lines GL. Multiple gating lines GL can be provided at the display panel 120. Each gating line GL can be connected to pixels P arranged in a row in one direction (e.g., horizontally). The gating drive 140 can provide a scan signal SCN indicating activation to one of the multiple gating lines GL, thus allowing selection of the pixel P connected to the selected gating line GL. The gating drive 140 can provide the scan signal SCN indicating activation in each horizontal cycle, while changing the gating line GL to which the scan signal SCN is provided.

[0047] The data drive device 110 can drive the pixel P disposed on the display panel 120.

[0048] The data driving device 110 can receive image data RGB from the timing controller 130. Then, the data driving device 110 can identify the pixel data of each pixel P included in the image data RGB, generate a data voltage VD corresponding to the pixel data, and provide the data voltage VD to the pixel P.

[0049] Pixel data can represent the grayscale value of pixel P, and the data driving device 110 can generate a data voltage VD corresponding to the grayscale value.

[0050] Pixel data can be stored in the latch circuit of the data driver 110 and then output as a digital signal. Furthermore, the data driver 110 can use a gamma reference voltage to convert the digital signal into an analog voltage.

[0051] There is a difference between the gray level corresponding to physical brightness and the gray level corresponding to the brightness perceived by a human. Correcting this difference is called gamma correction. When converting a digital signal to an analog voltage, the data drive device 110 can apply gamma correction simultaneously. For example, the data drive device 110 can use the voltage used for digital-to-analog conversion as the voltage for applying gamma correction, i.e., the gamma reference voltage, and apply both digital-to-analog conversion and gamma correction simultaneously.

[0052] Figure 2 This is a diagram showing the configuration of a data driving device according to an embodiment of the present disclosure.

[0053] Reference Figure 2 According to embodiments of the present disclosure, the data driving device 110 includes a receiver 111, a tS / tH delay unit 112, a serial-to-parallel converter 113, a second clock generator 114, a data register 115, and a channel 116.

[0054] certainly, Figure 2The components shown represent only those that are relevant to this implementation, and in actual implementation, additional components may be included in the data drive device 110.

[0055] Receiver 111 receives signals transmitted from timing controller 130. In the examples of this disclosure, the transmitted signals may include mini-LVDS signals.

[0056] Mini-LVDS signals are low-voltage differential signals that include both data and clock information. The transmission voltage range of mini-LVDS signals is typically low (e.g., approximately ±0.35 V), which reduces power consumption and minimizes signal interference; however, the signal may be weak at receiver 111. Therefore, receiver 111 can use voltage conversion and amplification circuitry to convert the received signal to a voltage level usable by logic circuitry. Receiver 111 can either convert the differential mini-LVDS signal into a single signal or amplify the voltage level of the converted signal to a level recognizable by digital logic circuitry (e.g., 0.35 V). 1.8 V or 3.3 V).

[0057] Receiver 111 typically includes a clock and data recovery (CDR). However, according to embodiments of this disclosure, receiver 111 may not include a CDR. In the absence of a CDR in receiver 111, timing controller 130 may transmit data signals and clock signals separately. Here, the data signal is the bit information required to display pixels, and the clock signal may be a reference signal used for data sampling and synchronization.

[0058] The tS / tH delay unit 112 is a component that ensures system stability by adjusting the timing of the data signal and clock signal received from the receiver 111. The tS / tH delay unit 112 adds a delay to the input data signal so that the input data signal satisfies the setup time (tS) and hold time (tH) conditions. The setup time (tS) is the time required to stably prepare the data before the clock edge, and the hold time (tH) is the time required to stably hold the data after the clock edge.

[0059] The tS / tH delay unit 112 can be implemented in various systems, such as an RC delay circuit system configured to delay the signal in an analog manner using resistors and capacitors, a buffer chain system configured to delay the signal by multiple buffers connected in series, or a programmable delay system as a variable delay circuit with controllable delay time.

[0060] A first clock generator 10 may be included in a serial-to-parallel converter 113. Based on the clock signal transmitted via receiver 111 and tS / tH delay unit 112, the first clock generator 10 generates multiple new clock signals. The newly generated multiple clock signals are transmitted to a serial-to-parallel data converter 20 for use in data sampling during the conversion of serial data into parallel data. In this disclosure, the parallel data converted based on the clocks generated in the first clock generator 10 is referred to as first parallel data and second parallel data.

[0061] The second clock generator 114 generates multiple new clock signals based on the clock signal received from the receiver 111. These newly generated clock signals are transmitted to the serial-to-parallel data converter 20 and used to sample first and second parallel data converted in the serial-to-parallel data converter 20 based on the clock signal generated by the first clock generator 10. In this disclosure, the parallel data converted based on the clock generated by the second clock generator 114 is referred to as third and fourth parallel data.

[0062] The second clock generator 114 can send clock signals not only to the serial-to-parallel data converter 20, but also to the data register 115 and each channel 116. Of course, in a practical implementation, the second clock generator 114 can also send clock signals to multiple logic circuits that require clock signals. Each channel 116 may include latch circuits, digital-to-analog converters, output buffers, etc.

[0063] A serial-to-parallel data converter 20 may be included in a serial-to-parallel converter 113. When multiple clock signals generated in the first clock generator 10 are input to the serial-to-parallel data converter 20, these multiple clock signals are synchronized with the bits of the serial data signal input to the serial-to-parallel data converter 20, such that the bit data is sampled on the rising or falling edge of the clock. Therefore, the serial data signal can be converted into parallel data. In this disclosure, the converted parallel data is referred to as first parallel data and second parallel data. The first parallel data and second parallel data are sampled based on the clock generated in the second clock generator 114 to generate additional parallel data. In this disclosure, this additional parallel data is referred to as third parallel data and fourth parallel data. The serial-to-parallel data converter 20 may send the third parallel data and fourth parallel data to the data register 115.

[0064] Here, parallel data can be formed in various ways, such as a method where each parallel data line receives a new data bit whenever new serial data is received, a method where specific data is copied across multiple parallel data lines to enable multiprocessing or to allow the same data to be used simultaneously on multiple output lines, and a method where multiple independent serial data streams are input and then each stream forms a parallel data line. In embodiments of this disclosure, the method for forming parallel data can be a method where each parallel data line receives a new data bit whenever new serial data is received. This method can also be a method of continuously receiving input serial data and continuously generating new parallel data according to a clock signal.

[0065] Data register 115 stores the parallel data (third parallel data and fourth parallel data) received from serial-to-parallel data converter 20 and maintains the parallel data (third parallel data and fourth parallel data) in a stable state for subsequent processing. Here, the method of storing parallel data in the data register may include storing all data of a frame in the data register, or storing selected data from a plurality of data in a frame in the data register. According to embodiments of this disclosure, since the serial-to-parallel data converter 20 converts all pixel data of a frame into parallel data for its subsequent processing, the data register 115, which receives the converted parallel data, can store all data of a frame. However, this disclosure is not limited to the methods described above.

[0066] Data register 115 can operate based on a clock signal synchronized during the output of serial-to-parallel converter 113, and can send the data stored therein to the respective channels 116. Each channel 116 may include latch circuitry, digital-to-analog converters, output buffers, etc.

[0067] Figure 3 This is a diagram illustrating the operation of a serial-to-parallel converter and a second clock generator according to an embodiment of the present disclosure.

[0068] Reference Figure 3 The data drive device 110 includes a serial-to-parallel converter 113 and a second clock generator 114, and the serial-to-parallel converter 113 includes a first clock generator 10 and a serial-to-parallel data converter 20.

[0069] Furthermore, the serial-to-parallel converter 113 and the second clock generator 114 can be configured to operate through separate first data transmission steps S1 and S2. Here, the first data is the odd-numbered bits of the data signal transmitted from the receiver 111, and the second data is the even-numbered bits of the data signal transmitted from the receiver 111. The first and second data, which are serial data, are converted into parallel data in the serial-to-parallel converter 113 and can then be transmitted to the data register 115.

[0070] The first data transmission step S1 can be operated based on the first clock signal CLK, and the second data transmission step S2 can be operated based on the second clock signal CLKB.

[0071] In the operation of the first data transmission step S1, the first clock generator 10 includes x2_1S 11 and DLY 1CLK_1S 21.

[0072] In the operation of the first data transmission step S1, the receiver 111 sends a first clock signal to the first clock generator 10. Although not in Figure 1 As shown, however, the tS / tH delay unit 112 exists between the receiver 111 and the first clock generator 10 to adjust the timing of the data signal and clock signal received from the receiver 111.

[0073] In the operation of the first data transmission step S1, the first clock generator 10 receives the first clock signal from the receiver 111 and generates a third clock signal having a period corresponding to twice the period of the first clock signal.

[0074] In the operation of the first data transmission step S1, the DLY 1CLK_1S 21 of the first clock generator 10, acting as a delay circuit, delays the third clock signal received from x2_1S 11 by 1-CLK time to generate the fifth clock signal. Here, the 1-CLK time is based on the basic clock signal transmitted from the receiver 111, i.e., the first clock signal.

[0075] In the operation of the first data transmission step S1, the third clock signal x2_1S 11 from the first clock generator 10 and the fifth clock signal DLY 1CLK_1S 21 are input to the serial-to-parallel data converter 20 and synchronized with the data signal input to the serial-to-parallel data converter 20, such that data is sampled at the rising or falling edge of the clock. Therefore, the data signal can be converted into a parallel data format. In this disclosure, the parallel data converted based on the clock generated in the first clock generator 10 in the first data transmission step S1 is referred to as "first parallel data".

[0076] In related technologies, since there is no process for generating another signal based on a clock signal with an increased period or a delayed clock signal generated from a clock signal sent from a receiver, data must be sampled by mixing a clock signal and an inverted clock signal. This results in insufficient timing margin, making it difficult to apply to high-frequency products. However, in this disclosure, a third clock signal is generated with a period corresponding to twice the period of the first clock signal, and the third clock signal is delayed to generate a fifth clock signal. Based on the third and fifth clock signals, a serial-to-parallel converter 113 samples the serial data and converts the sampled serial data into parallel data (referred to as first parallel data in this disclosure), thereby doubling the timing margin during sampling compared to the conventional case. Therefore, frequency characteristics can be enhanced.

[0077] Receiver 111 can send a first clock signal to the second clock generator 114.

[0078] In the operation of the first data transmission step S1, the second clock generator 114 includes x2_1C 31, x4_1C 41, x8_1C 51, x16_1C 61, DLY 1CLK_1C 71 and PAIR_1 81.

[0079] In the operation of the first data transmission step S1, x2_1C 31, x4_1C 41, x8_1C 51, and x16_1C 61 of the second clock generator 114 are clock cycle multipliers configured to increase the period of the first clock signal transmitted from the receiver 111. x2_1C 31, x4_1C 41, x8_1C 51, and x16_1C 61 can increase the clock period by two, four, eight, and sixteen times, respectively. Each clock cycle multiplier can be selected and activated according to the data sampling method of the serial-to-parallel data converter 20. Data sampling of the serial-to-parallel data converter 20 according to an embodiment of the present disclosure is performed based on x4_1C 41 as an example.

[0080] In the operation of the first data transmission step S1, the x4_1C 41 of the second clock generator 114 can quadruple the period of the first clock signal, where x4_1C 41 is a circuit configured to quadruple the clock period. After quadruple the first clock signal, the second clock generator 114 delays the first clock signal by 1-CLK time in the delay circuit DLY 1CLK_1C 71 to generate the seventh clock signal. Then, the second clock generator 114 delays the seventh clock signal by 1-CLK time in the DLY 1CLK_1C 71, which is also a delay circuit, to generate the ninth clock signal.

[0081] In the operation of the first data transmission step S1, the seventh clock signal and the ninth clock signal are input to the serial-to-parallel data converter 20. In the serial-to-parallel data converter 20, the seventh clock signal and the ninth clock signal can be used to sample the first parallel data on the rising or falling clock edge, and convert the sampled data into third parallel data. The serial-to-parallel data converter 20 can then send the third parallel data to the data register 115.

[0082] In this scenario, with a 1-CLK time delay between the seventh and ninth clock signals, the seventh and ninth clock signals can sample the first parallel data. In related technologies, the two clock signals used for sampling the parallel data have a 0.5 CLK delay, resulting in insufficient timing margin. Consequently, there are difficulties in supporting high frequencies. However, in this disclosure, with a 1-CLK time delay between the seventh and ninth clock signals, the seventh and ninth clock signals sample the first parallel data, and similarly, the timing margin can be doubled, thereby enhancing frequency characteristics.

[0083] PAIR_1 81 can be a component configured to select a clock with a different period generated in the second clock generator 114 based on a first clock signal, and to send the selected clock to other logic circuits that require a clock signal (e.g., channel 116, etc.). For example, PAIR_1 81 can be configured to select either a "high" value or a "low" value. Here, a "high" value corresponds to 6 PAIRs, while a "low" value corresponds to 3 PAIRs. When PAIR_1 81 selects a "high" value, 6 lines of data can be transmitted synchronously with the clock signal of x4_1C 41, while when PAIR_1 81 selects a "low" value, 3 lines of data can be transmitted synchronously with the clock signal of x8_1C 51. This is merely an example and can, of course, be modified to suit the user's environment.

[0084] In the operation of the second data transmission step S2, the first clock generator 10 includes x2_2S 12 and DLY 1CLK_2S 22.

[0085] In the operation of the second data transmission step S2, the x2_2S 12 of the first clock generator 10 receives the second clock signal obtained by 180° phase shifting the first clock signal transmitted from the receiver 111, and generates a fourth clock signal having a period corresponding to twice the period of the second clock signal.

[0086] In the operation of the second data transmission step S2, the DLY 1CLK_2S 22 of the first clock generator 10, acting as a delay circuit, can generate a sixth clock signal by delaying the fourth clock signal received from x2_2S 12 by 1-CLK time. Here, the 1-CLK time is based on the basic clock signal transmitted from the receiver 111, i.e., the first clock signal.

[0087] In the operation of the second data transmission step S2, the fourth clock signal output from x2_2S 12 of the first clock generator 10 and the sixth clock signal output from DLY 1CLK_2S 22 are input to the serial-to-parallel data converter 20 and synchronized with the data signal input to the serial-to-parallel data converter 20, such that data is sampled at the rising or falling edge of the clock. Therefore, the data signal is converted into a parallel data format. In this disclosure, the parallel data converted based on the clock generated in the first clock generator 10 in the second data transmission step S2 is referred to as "second parallel data".

[0088] In related technologies, since there is no process for generating another signal based on a clock signal with an increased period or a delayed clock signal generated from a clock signal sent from a receiver, data must be sampled by mixing a clock signal and an inverted clock signal. This results in insufficient timing margin, making it difficult to apply to high-frequency products. However, in this disclosure, a fourth clock signal is generated with a period corresponding to twice the period of the second clock signal, and the fourth clock signal is delayed to generate a sixth clock signal. Based on the fourth and sixth clock signals, a serial-to-parallel converter 113 samples the serial data and converts the sampled serial data into parallel data (referred to as second parallel data in this disclosure), thereby doubling the timing margin during sampling compared to the conventional case. Therefore, frequency characteristics can be enhanced.

[0089] Receiver 111 can send a first clock signal to the second clock generator 114.

[0090] In the operation of the second data transmission step S2, the second clock generator 114 includes x2_2C 32, x4_2C 42, x8_2C 52, x16_2C 62, DLY 1CLK_2C 72 and PAIR_2 82.

[0091] In the operation of the second data transmission step S2, the x2_2C 32, x4_2C 42, x8_2C 52, and x16_2C 62 of the second clock generator 114 are clock generators configured to generate clock signals whose periods correspond to two, four, eight, and sixteen times the period of the second clock signal, respectively. The second clock signal is obtained by phase shifting the first clock signal transmitted from the receiver 111 by 180°. The x2_2C 32, x4_2C 42, x8_2C 52, and x16_2C 62 can increase the clock period to two, four, eight, and sixteen times, respectively. Each clock period multiplier can be selected and activated according to the data sampling method of the serial-to-parallel data converter 20. Data sampling of the serial-to-parallel data converter 20 according to an embodiment of the present disclosure is performed based on x4_2C 42 as an example.

[0092] In the operation of the second data transmission step S2, the x4_2C 42 of the second clock generator 114, which is configured to quadruple the clock period, can quadruple the second clock signal. After quadruple the first clock signal, the second clock generator 114 delays the first clock signal by 1-CLK time in the DLY 1CLK_2C 72, which is a delay circuit, to generate the eighth clock signal. Then, the second clock generator 114 delays the eighth clock signal by 1-CLK time in the DLY 1CLK_2C 72 to generate the tenth clock signal.

[0093] The eighth and tenth clock signals are input to the serial-to-parallel data converter 20 to sample the second parallel data on the rising or falling edge of the clock and convert the sampled data into fourth parallel data. The serial-to-parallel data converter 20 can output the fourth parallel data to the data register 115.

[0094] In this scenario, with a 1-CLK time delay between the eighth and tenth clock signals, the eighth and tenth clock signals can sample the second parallel data. In related technologies, the two clock signals used for sampling the parallel data have a 0.5 CLK delay, resulting in insufficient timing margin. Consequently, there are difficulties in supporting high frequencies. However, in this disclosure, with a 1-CLK time delay between the eighth and tenth clock signals, the eighth and tenth clock signals can sample the second parallel data, thus doubling the timing margin and enhancing frequency characteristics.

[0095] PAIR_2 82 can be a component configured to select a clock with a different period generated in the second clock generator 114 based on a second clock signal, and to transmit the selected clock to other logic circuits (e.g., channel 116, etc.) that require the clock signal. For example, PAIR_2 82 can be configured to select one of the values ​​"high" and "low". Here, the value "high" corresponds to 6 PAIRs, and the value "low" corresponds to 3 PAIRs. When PAIR_2 82 is selected as "high", 6 lines of data can be transmitted synchronously with the clock signal of x4_2C42, while when PAIR_2 82 is selected as "low", 3 lines of data can be transmitted synchronously with the clock signal of x8_2C52. This is merely an example and can, of course, be modified to suit the user's environment.

[0096] Figure 4 This is a diagram of the clock signal and data sampling timing in the serial-to-parallel converter during the first data transmission step according to an embodiment of this disclosure.

[0097] Reference Figure 4 The diagram shows the third, fifth, seventh, and ninth clock signals during the first data transmission step S1.

[0098] The third clock signal in the first data transmission step S1 is generated in the first clock generator 10 and has a period corresponding to twice the period of the first clock signal transmitted from the receiver 111. The serial-to-parallel data converter 20 synchronizes the third clock signal with the first bit (0) and the fifth bit (4) in the LV0 data bits, and stores the first bit (0) and the fifth bit (4) in parallel in the data stream D by sampling. <3> and D <1> In this context, synchronization between the third clock signal and the LV0 data bits can occur on the rising edge of the clock signal.

[0099] The fifth clock signal in the first data transmission step S1 is generated in the first clock generator 10 and is a signal delayed by 1-CLK time from the third clock signal. Here, the 1-CLK time is based on the basic clock signal transmitted from the receiver 111, i.e., the first clock signal. The serial-to-parallel data converter 20 synchronizes the fifth clock signal with the third bit (2) and the seventh bit (6) in the LV0 data bits, and stores the third bit (2) and the seventh bit (6) in parallel in the data stream D by sampling. <2> and D <0> In this disclosure, synchronization between the fifth clock signal and the LV0 data bits can occur on the rising edge of the clock signal. Parallel data D generated based on the third and fifth clock signals... <3> D <2> D <1> and D <0> The signal is called "first parallel data".

[0100] The seventh clock signal, generated in the first data transmission step S1, is generated in the second clock generator 114. The seventh clock signal is a signal with a period corresponding to four times the period of the first clock signal transmitted from the receiver 111 and delayed by 1-CLK time from the first clock signal. The serial-to-parallel data converter 20 combines the seventh clock signal with the data stream D stored in the first parallel data. <3> and D <1> Bit information synchronization in the data stream D stored in the first parallel data. <3> and D <1> The first (0) and fifth (4) bits are sampled, and the sampled first (0) and fifth (4) bits are stored in the data stream S2P_OUT. <3> , <1> Then, the first bit (0) and the fifth bit (4) are output sequentially to data register 115 (first 0 and 4, second 0 and 4, third 0 and 4...). Here, the seventh clock signal is synchronized with the data stream D. <3> and D <1> Synchronization between them can occur at the rising edge of the clock signal.

[0101] In the first data transmission step S1, the ninth clock signal is a signal delayed by 1-CLK from the seventh clock signal. The serial-to-parallel data converter 20 synchronizes the ninth clock signal with the data stored in the data stream D. <2> and D <0> Bit information synchronization in the data stream D stored in the first parallel data. <2> and D <0> The third bit (2) and the seventh bit (6) in the data stream are sampled, and the sampled third bit (2) and the seventh bit (6) are stored in the data stream S2P_OUT. <2> , <0> Then, the third bit (2) and the seventh bit (6) are output sequentially to data register 115 (first 2 and 6, second 2 and 6, third 2 and 6...). The ninth clock signal and data stream D... <2> and D <0> Synchronization between them can occur at the rising edge of the clock signal. In this disclosure, the parallel data stream S2P_OUT is generated based on the seventh clock signal and the ninth clock signal. <3> , <1> and parallel data stream S2P_OUT <2> , <0> It is called "third parallel data".

[0102] Figure 5 This is a diagram showing the clock signal and data sampling timing in the serial-to-parallel converter during the second data transmission step according to an embodiment of this disclosure.

[0103] Reference Figure 5 The diagram shows the fourth, sixth, eighth, and tenth clock signals in the second data transmission step S2.

[0104] The fourth clock signal in the second data transmission step S2 is generated in the first clock generator 10 and has a period corresponding to twice the period of the second clock signal, which is obtained by phase shifting the first clock signal transmitted from the receiver 111 by 180°. The serial-to-parallel data converter 20 synchronizes the fourth clock signal with the second bit (1) and the sixth bit (5) in the LV0 data bits and stores the second bit (1) and the sixth bit (5) in parallel in the data stream D by sampling. <3> and D <1> In the middle. Synchronization between the fourth clock signal and the LV0 data bits can occur on the rising edge of the clock signal.

[0105] The sixth clock signal in the second data transmission step S2 is generated in the first clock generator 10 and is a signal delayed by 1-CLK time from the fourth clock signal. Here, the 1-CLK time is based on the basic clock signal transmitted from the receiver 111, i.e., the first clock signal. The serial-to-parallel data converter 20 synchronizes the sixth clock signal with the fourth bit (3) and the eighth bit (7) in the LV0 data bits and stores the fourth bit (3) and the eighth bit (7) in parallel in the data stream D by sampling. <2> and D <0> In this disclosure, synchronization between the sixth clock signal and the LV0 data bits can occur on the rising edge of the clock signal. The parallel data stream D generated based on the fourth and sixth clock signals... <3> D <2> D <1> and D <0> The signal is called "second parallel data".

[0106] The eighth clock signal in the second data transmission step S2 is generated in the second clock generator 114. The eighth clock signal has a period corresponding to four times the period of the second clock signal and is delayed by 1-CLK time from the second clock signal, which is obtained by phase-shifting the first clock signal transmitted from the receiver 111 by 180°. The serial-to-parallel data converter 20 connects the eighth clock signal with data stored in the data stream D. <3> and D <1> Bit information synchronization in the data stream D stored in the second parallel data. <3> and D <1> The second bit (1) and the sixth bit (5) in the data stream are sampled, and the sampled second bit (1) and the sixth bit (5) are stored in the data stream S2P_OUT. <3> , <1> Then, the second bit (1) and the sixth bit (5) are output sequentially to data register 115 (first 1 and 5, second 1 and 5, third 1 and 5...). The eighth clock signal and data stream D... <3> and D <1> Synchronization between them can occur at the rising edge of the clock signal.

[0107] In the second data transmission step S2, the tenth clock signal is a signal delayed by 1-CLK time from the seventh clock signal. The serial-to-parallel data converter 20 synchronizes the ninth clock signal with the data stored in the data stream D. <2> and D <0> Bit information synchronization in the data stream D stored in the first parallel data. <2> and D <0> The fourth bit (3) and the eighth bit (7) are sampled, and the sampled fourth bit (3) and the eighth bit (7) are stored in the data stream S2P_OUT. <2> , <0> Then, the fourth bit (3) and the eighth bit (7) are output sequentially to data register 115 (first 3 and 7, second 3 and 7, third 3 and 7...). The tenth clock signal and data stream D <2> and D <0> Synchronization between them can occur at the rising edge of the clock signal. In this disclosure, the parallel data stream S2P_OUT is generated based on the eighth and tenth clock signals. <3> , <1> and parallel data stream S2P_OUT <2> , <0> It is called "fourth parallel data".

[0108] It will be apparent to those skilled in the art that this disclosure may be practiced in other specific forms without departing from the spirit and essential characteristics thereof. Therefore, the foregoing detailed description should not be construed as limiting in any way, but rather as illustrative. The scope of this disclosure should be determined by a reasonable interpretation of the appended claims, and all modifications within the equivalent scope of this disclosure are included within its scope.

[0109] The method according to the above embodiments can be configured as a program to be executed by a computer and can be stored in a recording medium that can be read by a computer. Examples of recording media that can be read by a computer can include read-only memory (ROM), random access memory (RAM), CD-ROM, magnetic tape, floppy disk, optical data storage, etc., and also include implementations in the form of carrier waves (e.g., transmission via the Internet).

[0110] Computer-readable recording media are distributed to computer systems connected via a network, and computer-readable code can be stored and executed in a distributed manner. Furthermore, the functional programs, code, and code segments used to implement the above methods can be readily deduced by programmers in the art to which this embodiment pertains.

[0111] As is apparent from the above description, according to at least one embodiment of this disclosure, timing margin can be enhanced by separating the clock signal (CLK) and the inverted clock signal (CLKB) during data processing. Therefore, stable operation can be achieved even in high-speed data transmission environments without signal interference.

[0112] The effects that can be obtained through this disclosure are not limited to those described above, and based on the above description, those skilled in the art will more clearly understand other effects of this disclosure not described herein.

[0113] It will be apparent to those skilled in the art that this disclosure may be implemented in various specific forms without departing from the spirit and essential characteristics of this disclosure.

[0114] Therefore, the above detailed description should not be construed as limiting in any way, but rather as illustrative. The scope of this disclosure should be determined by a reasonable interpretation of the appended claims, and all modifications within the scope of equivalence of this disclosure are included within the scope of this disclosure.

[0115] This application claims the benefit of Korean Patent Application No. 10-2025-0016643, filed on February 10, 2025, which is incorporated herein by reference as if fully set forth herein.

Claims

1. A driving method for a data driving device, the driving method comprising the following steps: Receive data signals and a first clock signal from the timing controller; A second clock signal with a 180° phase difference is generated based on the received first clock signal; as well as Based on the first clock signal, first data is sent to the data register, the first data being the odd-numbered bits of the data signal, and based on the second clock signal, second data is sent to the data register, the second data being the even-numbered bits of the data signal.

2. The driving method according to claim 1, wherein The step of sending the first data to the data register based on the first clock signal includes: A third clock signal is generated, the third clock signal having a period corresponding to twice the period of the first clock signal; Generate a fifth clock signal, which is delayed by 1-CLK time from the third clock signal; and At the rising edges of the third and fifth clock signals, the first data is sampled to generate first parallel data. The 1-CLK time is based on the first clock signal.

3. The driving method according to claim 2, wherein, The step of sending the first data to the data register based on the first clock signal further includes: A seventh clock signal is generated, the seventh clock signal having a period corresponding to four times the period of the first clock signal, and the seventh clock signal being delayed from the first clock signal by 1-CLK time; and A ninth clock signal is generated, which is delayed by 1-CLK time from the seventh clock signal.

4. The driving method according to claim 3, wherein, The step of sending the first data to the data register based on the first clock signal further includes: At the rising edges of the seventh and ninth clock signals, the first parallel data is sampled to generate the third parallel data; and The third parallel data is sent to the data register.

5. The driving method according to claim 1, wherein The step of sending the second data to the data register based on the second clock signal includes: A fourth clock signal is generated, the fourth clock signal having a period corresponding to twice the period of the second clock signal; Generate a sixth clock signal, which is delayed by 1-CLK time from the fourth clock signal; and At the rising edges of the fourth and sixth clock signals, the second data is sampled to generate second parallel data. The 1-CLK time is based on the first clock signal.

6. The driving method according to claim 5, wherein The step of sending the second data to the data register based on the second clock signal further includes: Generate an eighth clock signal, the eighth clock signal having a period corresponding to four times the period of the second clock signal, and the eighth clock signal being delayed from the second clock signal by 1-CLK time; and A tenth clock signal is generated, which is delayed by 1-CLK time from the eighth clock signal.

7. The driving method according to claim 6, wherein The step of sending the second data to the data register based on the second clock signal further includes: At the rising edges of the eighth and tenth clock signals, the second parallel data is sampled to generate the fourth parallel data; and The fourth parallel data is sent to the data register.

8. A data driving device, the data driving device comprising: A receiver configured to receive a data signal and a first clock signal from a timing controller; A first clock generator is configured to generate a second clock signal with a 180° phase difference based on a received first clock signal. as well as A serial-to-parallel converter configured to send first data to a data register based on a first clock signal, the first data being odd-numbered bits of the data signal, and to send second data to the data register based on a second clock signal, the second data being even-numbered bits of the data signal.

9. The data driving apparatus of claim 8, wherein, The first clock generator is configured to: Generate a third clock signal, the third clock signal having a period twice that of the first clock signal; and A fifth clock signal is generated, which is delayed by 1-CLK time from the third clock signal. The 1-CLK time is based on the first clock signal.

10. The data driving apparatus of claim 8, wherein, The first clock generator is configured to: Generate a fourth clock signal, the fourth clock signal having a period twice that of the second clock signal; and A sixth clock signal is generated, which is delayed by 1-CLK time from the fourth clock signal. The 1-CLK time is based on the first clock signal.

Images