Display device and electronic device

Abstract

This invention discloses a display device and an electronic device. The display device includes: a pixel portion comprising a plurality of pixel rows, each extending in a first direction and arranged in a second direction and each connected to odd-numbered and even-numbered scan lines; and a scan driver comprising a plurality of scan stages, each connected to the odd-numbered and even-numbered scan lines. Each scan stage includes a buffer transistor. A buffer clock line connected to the buffer transistor extends in the second direction between the buffer transistor and the pixel portion.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2025-0016496, filed on February 10, 2025, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] This disclosure relates to display devices, and more specifically, to display devices and electronic devices including a scan driver having a scan level. Background Technology

[0003] With the development of information technology, the importance of display devices, as a crucial means of connecting users with information, has become increasingly apparent. Consequently, the use of display devices such as liquid crystal displays (LCDs) and organic light-emitting diode (OLEDs) displays has been steadily increasing.

[0004] A display device may include multiple pixels for displaying images. Pixels can display images by emitting light corresponding to the voltage of input data.

[0005] The scan driver is used to select the pixels that receive data voltage. Multiple clock lines can be used to drive the scan driver. The longer the clock line, the greater the electrical load, which may increase the required power consumption. Summary of the Invention

[0006] The display device includes: a pixel portion, wherein rows of pixels, each extending in a first direction, are arranged in a second direction and each of the pixel rows is connected to odd-numbered scan lines and even-numbered scan lines; and a scan driver, including scan stages, each connected to the odd-numbered scan lines and even-numbered scan lines. Each scan stage includes a buffer transistor. A buffer clock line connected to the buffer transistor extends in the second direction between the buffer transistor and the pixel portion.

[0007] Each of the scan stages may include: a logic circuit; a first buffer transistor having a first electrode connected to an odd-numbered buffer clock line, a gate electrode connected to the logic circuit, and a second electrode connected to an odd-numbered scan line; a second buffer transistor having a first electrode connected to an odd-numbered scan line and a gate electrode connected to the logic circuit; a third buffer transistor having a first electrode connected to an even-numbered buffer clock line, a gate electrode connected to the logic circuit, and a second electrode connected to an even-numbered scan line; and a fourth buffer transistor having a first electrode connected to an even-numbered scan line and a gate electrode connected to the logic circuit.

[0008] The first buffer transistor can be disposed on one side of the second buffer transistor in the first direction, and the third buffer transistor can be disposed on one side of the fourth buffer transistor in the first direction.

[0009] The logic circuit can be located on one side of the first buffer transistor, the second buffer transistor, the third buffer transistor, and the fourth buffer transistor in the direction opposite to the first direction.

[0010] The logic circuit can be connected to the carry clock line, and the carry clock line can be located on one side of the logic circuit in the opposite direction to the first direction and can extend in the second direction.

[0011] The logic circuit can be connected to the carry clock line, and the carry clock line can extend in a second direction between the first buffer transistor and the pixel portion.

[0012] The third buffer transistor can be disposed on one side of the first buffer transistor in the second direction, and the even-numbered scan lines can be disposed on one side of the odd-numbered scan lines in the second direction.

[0013] The fourth buffer transistor can be disposed on one side of the second buffer transistor in the second direction.

[0014] The first buffer transistor can be disposed on one side of the third buffer transistor in the second direction, and the odd-numbered scan lines are disposed on one side of the even-numbered scan lines in the second direction.

[0015] The second buffer transistor can be disposed on one side of the fourth buffer transistor in the second direction.

[0016] The electronic device includes: a processor that provides grayscale values ​​for image frames; and a display device that displays the image using the grayscale values. The display device includes: a pixel portion, wherein rows of pixels, each extending in a first direction, are arranged in a second direction and each of the pixel rows is connected to odd-numbered and even-numbered scan lines; and a scan driver including scan stages, each connected to the odd-numbered and even-numbered scan lines. Each scan stage includes a buffer transistor. A buffer clock line connected to the buffer transistor extends in the second direction between the buffer transistor and the pixel portion.

[0017] Each of the scan stages may include: a logic circuit; a first buffer transistor having a first electrode connected to an odd-numbered buffer clock line, a gate electrode connected to the logic circuit, and a second electrode connected to an odd-numbered scan line; a second buffer transistor having a first electrode connected to an odd-numbered scan line and a gate electrode connected to the logic circuit; a third buffer transistor having a first electrode connected to an even-numbered buffer clock line, a gate electrode connected to the logic circuit, and a second electrode connected to an even-numbered scan line; and a fourth buffer transistor having a first electrode connected to an even-numbered scan line and a gate electrode connected to the logic circuit.

[0018] The first buffer transistor can be disposed on one side of the second buffer transistor in the first direction, and the third buffer transistor can be disposed on one side of the fourth buffer transistor in the first direction.

[0019] The logic circuit can be located on one side of the first buffer transistor, the second buffer transistor, the third buffer transistor, and the fourth buffer transistor in the direction opposite to the first direction.

[0020] The logic circuit can be connected to the carry clock line, and the carry clock line can be located on one side of the logic circuit in the opposite direction to the first direction and can extend in the second direction.

[0021] The logic circuit can be connected to the carry clock line, and the carry clock line can extend in a second direction between the first buffer transistor and the pixel portion.

[0022] The third buffer transistor can be disposed on one side of the first buffer transistor in the second direction, and the even-numbered scan lines can be disposed on one side of the odd-numbered scan lines in the second direction.

[0023] The fourth buffer transistor can be disposed on one side of the second buffer transistor in the second direction.

[0024] The first buffer transistor can be disposed on one side of the third buffer transistor in the second direction, and the odd-numbered scan lines can be disposed on one side of the even-numbered scan lines in the second direction.

[0025] The second buffer transistor can be disposed on one side of the fourth buffer transistor in the second direction. Attached Figure Description

[0026] A more complete understanding of this disclosure and its many accompanying aspects will be readily obtained as they become better understood by referring to the following detailed description when considered in conjunction with the accompanying drawings.

[0027] Figure 1 This is a schematic diagram illustrating a display device according to an embodiment of the present disclosure.

[0028] Figure 2 This is a circuit diagram illustrating pixels according to an embodiment of the present disclosure.

[0029] Figure 3 This is a schematic diagram illustrating pixel portions according to an embodiment of the present disclosure.

[0030] Figure 4 This is a schematic diagram illustrating a scan driver according to an embodiment of the present disclosure.

[0031] Figure 5This is a circuit diagram illustrating a scan level according to an embodiment of the present disclosure.

[0032] Figure 6 This is a waveform diagram illustrating a method for driving a scan level according to an embodiment of the present disclosure.

[0033] Figure 7 This is a cross-sectional view of a display device according to an embodiment of the present disclosure.

[0034] Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A and Figure 13B A plan view layout of the scan level is shown according to an embodiment of the present disclosure.

[0035] Figure 14 This is a schematic diagram illustrating a scan driver according to an embodiment of the present disclosure.

[0036] Figure 15 This is a schematic block diagram of an electronic device according to an embodiment.

[0037] Figure 16 , Figure 17 and Figure 18 This is a perspective schematic diagram of an electronic device according to various embodiments. Detailed Implementation

[0038] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings, enabling those skilled in the art to readily implement the present disclosure. The present disclosure may be implemented in various forms and is not necessarily limited to the embodiments described herein.

[0039] Throughout the specification and drawings, the same or similar reference numerals may be used to describe the same or similar elements, and where an element is not described in detail with respect to this figure, it may be understood that the element is at least similar to a corresponding element that has been described elsewhere in this disclosure.

[0040] Although each figure may represent one or more specific embodiments of the present disclosure and is drawn to scale so that relative lengths, thicknesses, and angles can be inferred from them, it should be understood that the present disclosure is not necessarily limited to the relative lengths, thicknesses, and angles shown. These values ​​may be changed within the spirit and scope of the present disclosure, for example to allow for manufacturing limitations, etc.

[0041] Furthermore, the expression "identical" can mean "substantially identical." Therefore, the expression "identical" can include a range tolerable to those skilled in the art. Other expressions may also be those from which "substantially" has been omitted.

[0042] Embodiments of this disclosure relate to a scan driver architecture for a display device that improves power efficiency and operational consistency. The scan stages of the scan driver are organized in a specific manner so that the scan stages can interact with the pixel portions of the display device in a desired way. Each scan stage controls both odd-numbered and even-numbered scan lines and includes multiple buffer transistors carefully arranged to reduce signal delay and voltage skew. This arrangement ensures smoother and more consistent driving throughout the pixel rows of the display device.

[0043] To further minimize power consumption and improve signal stability, a buffer clock line is routed between the buffer transistor and the pixel section of the display device to control the timing of signals transmitted by the buffer transistor. This layout shortens the connection distance and thus reduces the electrical load on the buffer clock line. By doing so, the design minimizes timing mismatches and power losses typically associated with long interconnects and varying signal propagation delays in conventional scan driver constructions.

[0044] Scan stages can be equipped with logic circuitry and a dedicated arrangement of, for example, four buffer transistors per stage aligned in a specific spatial orientation. The logic circuitry receives carry signals and carry clock signals, enabling precise control of the signal flow between adjacent scan lines. Carry clock lines coordinating the timing between scan stages are also arranged in a way that reduces their wiring complexity and improves efficiency. These design improvements allow the scan driver to efficiently deliver scan pulses to alternating groups of pixels while maintaining synchronized operation throughout the display panel.

[0045] The embodiments disclosed herein are not necessarily limited to display panels, but can be integrated into electronic devices with high-performance displays, such as smartphones, tablet computers, wearable devices, automotive displays, and consumer electronics. By embedding a processor for generating grayscale data and using this scan driver design, the system achieves reduced power consumption and increased reliability. The flexibility and modularity of this design also support a wide variety of panel layouts and device types without sacrificing performance.

[0046] Figure 1 This is a schematic diagram illustrating a display device 11 according to an embodiment of the present disclosure.

[0047] refer to Figure 1 According to embodiments of the present disclosure, the display device 11 may include a timing controller 22, a data driver 23, a scan driver 24, and a pixel portion 25. The display device 11 may communicate with the processor 12.

[0048] Processor 12 can provide input grayscale and control signals for each image (or image frame). As used herein, the term "grayscale" refers to a digital image data value that represents the intensity or brightness level of a pixel / subpixel in display device 11. These values ​​are used to control the data voltage applied to the pixel, which in turn determines the brightness (i.e., the brightness of light emitted by each pixel). Although the term "grayscale" can refer to a black and white image in other contexts, in this context, "grayscale" is used equivalently for a color image because each subpixel (red, green, and blue) receives its own grayscale value to control its brightness. These grayscale values ​​for each color channel collectively determine the final color and brightness of the pixel.

[0049] Processor 12 may correspond to a graphics processing unit (GPU), a central processing unit (CPU), or an application processor (AP). Control signals may include vertical synchronization signals, horizontal synchronization signals, and data enable signals.

[0050] The vertical synchronization signal can include multiple pulses and can indicate the end of the previous frame period and the beginning of the current frame period based on the time of occurrence of each pulse. The interval between adjacent pulses of the vertical synchronization signal can correspond to a frame period. The horizontal synchronization signal can include multiple pulses and can indicate the end of the previous horizontal period and the beginning of a new horizontal period based on the time of occurrence of each pulse. The interval between adjacent pulses of the horizontal synchronization signal can correspond to a horizontal period. The data enable signal can have an enable level for a specific horizontal period and a disable level for the remaining horizontal periods. A data enable signal at the enable level can indicate the supply of input grayscale in the corresponding horizontal period.

[0051] The timing controller 22 can supply control signals to the scan driver 24 and the data driver 23. Additionally, the timing controller 22 can provide input grayscale values ​​to the data driver 23. The timing controller 22 can also provide the data driver 23 with output grayscale values ​​obtained by compensating or rendering the input grayscale values ​​to suit the pixel portion 25.

[0052] The data driver 23 can use the received grayscale and control signals to generate data voltages to be supplied to the data lines DL1, DL2, DL3, ..., DLs. For example, the data driver 23 can use a clock signal to sample the grayscale and apply the data voltage corresponding to the grayscale to the data lines DL1 to DLs, where "s" can be a positive integer.

[0053] The scan driver 24 can receive clock signals and scan start signals from the timing controller 22 to generate scan signals that will be provided to scan lines SL1, SL2, SL3, ... and SLm, where "m" can be a positive integer.

[0054] Scan driver 24 can sequentially supply scan signals with on-level pulses to scan lines SL1 to SLm. Scan driver 24 may include scan stages constructed in the form of shift registers. Scan driver 24 can generate scan signals by sequentially transmitting scan start signals in the form of on-level pulses to the next scan stage under the control of a clock signal.

[0055] The pixel section 25 includes pixels PX. Each pixel PX can be connected to a corresponding data line and scan line. A pixel PX that receives a scan signal at a conduction level via a scan line can receive a data voltage from the connected data line. The pixel PX that receives the data voltage can store the data voltage and emit light with a corresponding brightness.

[0056] Therefore, the processor 12 and the display device 11, including the timing controller 22, data driver 23, scan driver 24, and pixel array (pixel portion) 25, work together to convert grayscale image data into light output. By coordinating timing and voltage control, the system drives the pixels PX to emit light and form the desired image.

[0057] Figure 2 This is a circuit diagram illustrating a pixel PX according to an embodiment of the present disclosure.

[0058] refer to Figure 2 The pixel PX includes transistors PT1 and PT2, storage capacitor Cst, and light-emitting device LD.

[0059] In the following description, a circuit composed of N-type transistors will be used as an example. However, those skilled in the art will be able to design a circuit composed of P-type transistors by changing the polarity of the voltage applied to the gate terminal. Similarly, those skilled in the art will be able to design a circuit composed of a combination of P-type and N-type transistors. P-type transistors are collectively referred to as transistors in which the amount of current conducted increases as the voltage difference between the gate electrode and the source electrode increases in the negative direction. N-type transistors are collectively referred to as transistors in which the amount of current conducted increases as the voltage difference between the gate electrode and the source electrode increases in the positive direction. Transistors can be constructed in various forms such as thin-film transistors (TFTs), field-effect transistors (FETs), and bipolar junction transistors (BJTs).

[0060] The gate electrode of the first transistor PT1 can be connected to the first electrode of the storage capacitor Cst, the first electrode of the first transistor PT1 can be connected to the first power line ELVDDL, and the second electrode can be connected to the second electrode of the storage capacitor Cst. The first transistor PT1 can be referred to as the driving transistor.

[0061] The gate electrode of the second transistor PT2 can be connected to the i-th scan line (also called scan line) SLi, the first electrode can be connected to the j-th data line (also called data line) DLj, and the second electrode can be connected to the gate electrode of the first transistor PT1, where "i" can be a positive integer less than or equal to "m" and "j" can be a positive integer less than or equal to "s". The second transistor PT2 can be referred to as the scan transistor.

[0062] The first electrode of the storage capacitor Cst can be connected to the gate electrode of the first transistor PT1, and the second electrode of the storage capacitor Cst can be connected to the second electrode of the first transistor PT1.

[0063] A light-emitting device (LD) can have an anode electrode connected to the second electrode of the first transistor PT1 and a cathode electrode connected to the second electric field line ELVSSL. The LD can be constructed as an organic light-emitting diode (OLED), an inorganic light-emitting diode, or a quantum dot / well light-emitting diode, etc. Although... Figure 2 The pixel PX is shown as including a single light-emitting device LD, but in embodiments, the pixel PX may include multiple light-emitting devices connected in series, parallel, or series-parallel.

[0064] A first electrical voltage can be applied to a first electrical line ELVDDL, and a second electrical voltage can be applied to a second electrical line ELVSSL. For example, during an image display period, the first electrical voltage can be greater than the second electrical voltage.

[0065] When a scan signal at a conduction level (high level) is applied through the scan line SL1, the second transistor PT2 is turned on. At this time, the data voltage applied to the data line DLj is stored in the first electrode of the storage capacitor Cst.

[0066] A positive drive current corresponding to the voltage difference between the first and second electrodes of the storage capacitor Cst flows between the first and second electrodes of the first transistor PT1. Accordingly, the light-emitting device LD emits light with a brightness corresponding to the data voltage.

[0067] Next, when a scan signal at a cutoff level (here, low level) is applied through the scan line SLi, the second transistor PT2 is turned off, and the data line DLj and the first electrode of the storage capacitor Cst are electrically disconnected. Therefore, even when the data voltage of the data line DLj changes, the voltage stored in the first electrode of the storage capacitor Cst does not change.

[0068] The embodiments can be applied not only to Figure 2The pixel PX can be applied to pixels in other pixel circuits. For example, when the display device 11 further includes an emission driver, the pixel PX can further include a transistor connected to an emission line.

[0069] Therefore, a pixel PX includes two transistors, a driving transistor PT1 and a scanning transistor PT2, a storage capacitor Cst, and a light-emitting device LD, such as an OLED. When a scan signal is applied through the scan line SL1, the scanning transistor PT2 is turned on, allowing the data voltage from the data line DLj to be stored in the storage capacitor Cst. This stored voltage then controls the driving transistor PT1 to drive current through the light-emitting device LD, causing the LD to emit light. Even after the scanning transistor PT2 is turned off, the storage capacitor Cst maintains this voltage, thereby maintaining the brightness of the pixel PX.

[0070] Figure 3 This is a schematic diagram illustrating a pixel portion 25 according to an embodiment of the present disclosure.

[0071] refer to Figure 3 According to embodiments of the present disclosure, the pixel portion 25 may be connected to the data lines DL1, DL2, DL3, ... of the data driver 23 and the scan lines SL1, SL2, SL3, SL4, ... of the scan driver 24.

[0072] The first direction DR1 and the second direction DR2 are perpendicular to each other and can define a plane. The third direction DR3 is perpendicular to the first direction DR1 and the second direction DR2 and can define a height.

[0073] The pixel portion 25 may include multiple pixels PX11, PX12, PX13, PX14, PX15, PX16, ..., PX21, PX22, PX23, PX24, PX25, PX26, ...

[0074] Pixel rows extending in the first direction DR1 can be arranged in the second direction DR2. For example, the first pixel row may include multiple pixels PX11, PX12, PX13, PX14, PX15, PX16, ... The second pixel row may include multiple pixels PX21, PX22, PX23, PX24, PX25, PX26, ... The first pixel row, the second pixel row, and subsequent pixel rows can be arranged in the second direction DR2.

[0075] Each pixel in a pixel row can be connected to both odd-numbered and even-numbered scan lines. For example, pixels PX11 through PX16... in the first pixel row can be connected to both odd-numbered scan lines SL1 and even-numbered scan lines SL2. One or more pixels PX11, PX12, PX13... in the first pixel row can be connected to odd-numbered scan lines SL1, and pixels PX14, PX15, PX16... other than one or more pixels PX11, PX12, PX13... can be connected to even-numbered scan lines SL2. For example, adjacent pixels PX11, PX12, and PX13 in the first pixel row that emit different colors of light can form a group. The groups in the first pixel row can be alternately connected to both odd-numbered and even-numbered scan lines SL2. Similarly, one or more pixels PX21, PX22, PX23, ... in the second pixel row can be connected to odd-numbered scan lines SL3, and other pixels PX24, PX25, PX26, ... besides one or more pixels PX21, PX22, PX23, ... can be connected to even-numbered scan lines SL4. For example, adjacent pixels PX21, PX22, and PX23 in the second pixel row that emit different colors of light can form a group. The groups in the second pixel row can be alternately connected to odd-numbered scan lines SL3 and even-numbered scan lines SL4.

[0076] According to this embodiment, the display device 11 can supply data voltage to the pixels PX11, ... arranged in high resolution by using a small number of data lines DL1, DL2, DL3, ... without having a demultiplexer.

[0077] Figure 4 This is a schematic diagram illustrating a scan driver 24 according to an embodiment of the present disclosure.

[0078] refer to Figure 4The scan driver 24 may include scan levels ST1, ST2, ST3, ST4, ST5, ST6, ST7, ST8, ..., each connected to an odd-numbered scan line and an even-numbered scan line. For example, the first scan level ST1 may be connected to an odd-numbered scan line SL1 and an even-numbered scan line SL2. The second scan level ST2 may be connected to an odd-numbered scan line SL3 and an even-numbered scan line SL4. The third scan level ST3 may be connected to an odd-numbered scan line SL5 and an even-numbered scan line SL6. The fourth scan level ST4 may be connected to an odd-numbered scan line SL7 and an even-numbered scan line SL8. The fifth scan level ST5 may be connected to an odd-numbered scan line SL9 and an even-numbered scan line SL10. The sixth scan level ST6 may be connected to an odd-numbered scan line SL11 and an even-numbered scan line SL12. The seventh scan level ST7 may be connected to an odd-numbered scan line SL13 and an even-numbered scan line SL14. The eighth scan level ST8 can be connected to odd-numbered scan lines SL15 and even-numbered scan lines SL16. The scan driver 24 can further include a ninth scan level and subsequent scan levels.

[0079] Each common component in scan levels ST1 to ST8 will be described with reference to the first scan level ST1, and in the absence of a component described in detail for this figure, it will be understood that the component is at least similar to a corresponding component that has been described elsewhere in this disclosure.

[0080] The first scan level ST1 may include logic circuit LGP and buffer transistors T9_O, T10_O, T9_E, and T_10E. The logic circuit LGP can determine whether to turn on the buffer transistors T9_O, T10_O, T9_E, and T_10E based on the carry signal and the carry clock signal. Because the logic circuit LGP of each of the first scan level ST1 and the second scan level ST2 does not have a previous scan level, it can receive a scan start signal instead of a carry signal. For example, the timing controller 22 supplies a scan start signal at an on level to the scan start line FLM, so that the scan driver 24 can sequentially supply scan signals at an on level. Although the first scan level ST1 and the second scan level ST2 are shown to receive the same scan start signal in this embodiment, in an embodiment, the first scan level ST1 and the second scan level ST2 may receive different scan start signals. In this case, the first scan level ST1 and the second scan level ST2 are connected to different scan start lines. Compared to the scan start signal received by the first scan stage ST1, the scan start signal received by the second scan stage ST2 can be delayed by a predetermined amount of time.

[0081] The first electrode of the first buffer transistor T9_O can be connected to the odd-numbered buffer clock line CK3O, the gate electrode can be connected to the logic circuit LGP, and the second electrode can be connected to the odd-numbered scan line SL1 (see...). Figure 5 The first electrode of the second buffer transistor T10_O can be connected to the odd-numbered scan line SL1, and its gate electrode can be connected to the logic circuit LGP. The first electrode of the third buffer transistor T9_E can be connected to the even-numbered buffer clock line CK3E, its gate electrode can be connected to the logic circuit LGP, and its second electrode can be connected to the even-numbered scan line SL2. The first electrode of the fourth buffer transistor T10_E can be connected to the even-numbered scan line SL2, and its gate electrode can be connected to the logic circuit LGP.

[0082] The first buffer transistor T9_O may be disposed in the first direction DR1 relative to the second buffer transistor T10_O. As used herein, the phrase "may be disposed in a certain direction relative to an element" may mean that the described item is disposed on one side of the element in said direction. The third buffer transistor T9_E may be disposed in the first direction DR1 relative to the fourth buffer transistor T10_E.

[0083] The logic circuit LGP can be positioned in the opposite direction to the first direction DR1 relative to the first buffer transistor T9_O, the second buffer transistor T10_O, the third buffer transistor T9_E, and the fourth buffer transistor T10_E.

[0084] The third buffer transistor T9_E can be disposed on the second direction DR2 relative to the first buffer transistor T9_O, and the even-numbered scan line SL2 can be disposed on the second direction DR2 relative to the odd-numbered scan line SL1. The fourth buffer transistor T10_E can be disposed on the second direction DR2 relative to the second buffer transistor T10_O.

[0085] Carry clock lines CRCK1, CRCK2, CRCK3, and CRCK4 can be positioned relative to the logic circuit LGP in the opposite direction to the first direction DR1, and can extend in the second direction DR2. The logic circuit LGP of scan stages ST1 to ST8, ... can be connected to the carry clock lines CRCK1, CRCK2, CRCK3, and CRCK4. The carry clock lines CRCK1 to CRCK4 determine the timing of the carry signal generation. The carry clock signals applied to the carry clock lines CRCK1 to CRCK4 can be sequentially phase-delayed (see...). Figure 6 ).

[0086] Odd-numbered scan levels ST1, ST3, ST5, ST7, ... can be connected to the first carry clock line CRCK1 and the third carry clock line CRCK3. Carry clock lines CRCK1 and CRCK3 can be alternately connected to the first transistor T1 (see...). Figure 5 The gate electrode of ) and the fourth transistor T4 (see Figure 5 The gate electrode of the [missing information]. The first scan stage ST1 can apply a carry signal at an on level to the first carry line CR1 in response to a scan start signal at an on level applied to the first carry line FLM. The third scan stage ST3 can apply a carry signal at an on level applied to the third carry line CR3 in response to a carry signal at an on level applied to the first carry line CR1. The fifth scan stage ST5 can apply a carry signal at an on level applied to the fifth carry line CR5 in response to a carry signal at an on level applied to the third carry line CR3. The seventh scan stage ST7 can apply a carry signal at an on level applied to the seventh carry line CR7 in response to a carry signal at an on level applied to the fifth carry line CR5.

[0087] Similarly, even-numbered scan stages ST2, ST4, ST6, ST8, ... can be connected to the second carry clock line CRCK2 and the fourth carry clock line CRCK4. Carry clock lines CRCK2 and CRCK4 can be alternately connected to the gate electrode of the first transistor T1 and the gate electrode of the fourth transistor T4. The second scan stage ST2 can apply a carry signal at an on level to the second carry line CR2 in response to a scan start signal at an on level applied to the scan start line FLM. The fourth scan stage ST4 can apply a carry signal at an on level to the fourth carry line CR4 in response to a carry signal at an on level applied to the second carry line CR2. The sixth scan stage ST6 can apply a carry signal at an on level to the sixth carry line CR6 in response to a carry signal at an on level applied to the fourth carry line CR4. The eighth scan level ST8 can apply a carry signal at the on level to the eighth carry line CR8 in response to a carry signal at the on level applied to the sixth carry line CR6.

[0088] Buffer clock lines CK1O, CK1E, CK2O, CK2E, CK3O, CK3E, CK4O, and CK4E can extend along the second direction DR2 between buffer transistors T9_O and T9_E and pixel portion 25. Buffer clock lines CK1O to CK4E determine the level and timing of the scan signal output to buffer transistors T9_O and T9_E. The buffer clock signals applied to buffer clock lines CK1O, CK1E, CK2O, CK2E, CK3O, CK3E, CK4O, and CK4E can be sequentially delayed at predetermined time intervals (see...). Figure 6 ).

[0089] In this embodiment, the system operates on a four-scan-level basis, with each scan level connected to adjacent odd-numbered and even-numbered buffer clock lines. For example, the third scan level ST3 can be connected to the odd-numbered first buffer clock line CK1O and the even-numbered first buffer clock line CK1E. The fourth scan level ST4 can be connected to the odd-numbered second buffer clock line CK2O and the even-numbered second buffer clock line CK2E. The fifth scan level ST5 can be connected to the odd-numbered third buffer clock line CK3O and the even-numbered third buffer clock line CK3E. The sixth scan level ST6 can be connected to the odd-numbered fourth buffer clock line CK4O and the even-numbered fourth buffer clock line CK4E.

[0090] According to this embodiment, the connection distance between the buffer clock lines CK1O, CK1E, CK2O, CK2E, CK3O, CK3E, CK4O, or CK4E and the buffer transistors T9_O or T9_E can be minimized. Therefore, the load deviation of the buffer clock lines CK1O, CK1E, CK2O, CK2E, CK3O, CK3E, CK4O, and CK4E can be reduced, and the deviation of the scan signal output from the buffer transistors T9_O and T9_E can also be reduced. Due to the reduced load, power consumption is also reduced.

[0091] Figure 5 This is a circuit diagram illustrating a scan level according to an embodiment of the present disclosure.

[0092] refer to Figure 5 According to embodiments of this disclosure, the first scan stage ST1 may include a plurality of transistors T1, T2, T3, T4, T5, T6, T7, T8, T9_O, T9_E, T10_O, T10_E, T11, T12, T13, and T14, as well as a plurality of capacitors C1 and C2. Scan stages other than the first scan stage ST1 may have the same circuit structure, and therefore, since elements are not described in detail for this figure, it is understood that the elements are at least similar to corresponding elements already described elsewhere in this disclosure.

[0093] The circuit described below, consisting of N-type transistors, will be used as an example. However, those skilled in the art will be able to design circuits consisting of P-type transistors by changing the polarity of the voltage applied to the gate terminals. Similarly, those skilled in the art will be able to design circuits consisting of a combination of P-type and N-type transistors.

[0094] The gate electrode of the first transistor T1 can be connected to the first carry clock line CRCK1, the first electrode can be connected to the scan start line FLM, and the second electrode can be connected to the first node N1. The first transistor T1 may include sub-transistors T1_1 and T1_2 connected in series.

[0095] The gate electrode of the second transistor T2 can be connected to the reset line ESR, the first electrode can be connected to the first node N1, and the second electrode can be connected to the first low-voltage line VGL1. The second transistor T2 may also include a back gate electrode connected to the gate electrode. The second transistor T2 may include sub-transistors T2_1 and T2_2 connected in series. The electrodes between sub-transistors T1_1 and T1_2, and between sub-transistors T2_1 and T2_2, can be connected to each other.

[0096] When the display device 11 is powered on, a reset signal at the on level (high level) can be applied to the reset line ESR. The reset signal can be applied to all scan levels together. Thereafter, during operation of the display device 11, the reset signal at the off level (low level) can be held in the reset line ESR.

[0097] The gate electrode of the third transistor T3 can be connected to the second node N2, the first electrode can be connected to the first high-voltage line VGH1, and the second electrode can be connected to the electrode between sub-transistors T1_1 and T1_2, and the electrode between sub-transistors T2_1 and T2_2. The third transistor T3 may also include a back gate electrode connected to the gate electrode. The third transistor T3 may include sub-transistors T3_1 and T3_2 connected in series.

[0098] The fourth transistor T4 may include a gate electrode connected to the third carry clock line CRCK3, a first electrode connected to the first node N1, and a second electrode connected to the first electrode of the fifth transistor T5.

[0099] The gate electrode of the fifth transistor T5 can be connected to the third node N3, the first electrode can be connected to the second electrode of the fourth transistor T4, and the second electrode of the fifth transistor T5 can be connected to the first carry line CR1.

[0100] The sixth transistor T6 may include a gate electrode, a first electrode connected to a first high-voltage line VGH1, and a second electrode connected to a third node N3. The sixth transistor T6 may also include a back gate electrode connected to the gate electrode.

[0101] The second capacitor C2 can be connected between the gate electrode of the sixth transistor T6 and the second electrode of the sixth transistor T6.

[0102] The gate electrode of the seventh transistor T7 can be connected to the second node N2, the first electrode can be connected to the third carry clock line CRCK3, and the second electrode can be connected to the first carry line CR1. The seventh transistor T7 may also include a back gate electrode connected to the gate electrode.

[0103] The first capacitor C1 can be connected between the gate electrode of the seventh transistor T7 and the second electrode of the seventh transistor T7.

[0104] The gate electrode of the eighth transistor T8 can be connected to the third node N3, the first electrode can be connected to the first carry line CR1, and the second electrode can be connected to the second low voltage line VGL2. The eighth transistor T8 may also include a back gate electrode connected to the second electrode of the eighth transistor T8. The voltage level of the second low voltage applied to the second low voltage line VGL2 may be lower than the voltage level of the first low voltage applied to the first low voltage line VGL1.

[0105] The gate electrode of the odd-numbered ninth transistor T9_O can be connected to the second node N2, the first electrode can be connected to the odd-numbered third buffer clock line CK3O, and the second electrode can be connected to the first scan line SL1. The odd-numbered ninth transistor T9_O may also include a back gate electrode connected to the gate electrode. The odd-numbered ninth transistor T9_O can be... Figure 4 The first buffer transistor T9_O.

[0106] The gate electrode of the odd-numbered tenth transistor T10_O can be connected to the third node N3, the first electrode can be connected to the first scan line SL1, and the second electrode can be connected to the first low-voltage line VGL1. The odd-numbered tenth transistor T10_O may also include a back gate electrode connected to the gate electrode. The odd-numbered tenth transistor T10_O can be... Figure 4 The second buffer transistor T10_O.

[0107] The gate electrode of the even-numbered ninth transistor T9_E can be connected to the second node N2, the first electrode can be connected to the even-numbered third buffer clock line CK3E, and the second electrode can be connected to the second scan line SL2. The even-numbered ninth transistor T9_E may also include a back gate electrode connected to the gate electrode. The even-numbered ninth transistor T9_E can be... Figure 4 The third buffer transistor T9_E.

[0108] The gate electrode of the even-numbered tenth transistor T10_E can be connected to the third node N3, the first electrode can be connected to the second scan line SL2, and the second electrode can be connected to the first low voltage line VGL1. The even-numbered tenth transistor T10_E may also include a back gate electrode connected to the gate electrode. The even-numbered tenth transistor T10_E can be... Figure 4 The fourth buffer transistor T10_E.

[0109] The gate electrode of the eleventh transistor T11 can be connected to the second node N2, the first electrode can be connected to the gate electrode of the sixth transistor T6, and the second electrode can be connected to the first low-voltage line VGL1. The eleventh transistor T11 may also include a back gate electrode connected to the gate electrode.

[0110] The gate electrode of the twelfth transistor T12 can be connected to the second node N2, the first electrode can be connected to the second low-voltage line VGL2, and the second electrode can be connected to the third node N3. The twelfth transistor T12 may also include a back gate electrode connected to the gate electrode.

[0111] The gate electrode of the thirteenth transistor T13 can be connected to the first high-voltage line VGH1, the first electrode can be connected to the gate electrode of the sixth transistor T6, and the second electrode can be connected to the first high-voltage line VGH1. The thirteenth transistor T13 may include sub-transistors T13_1 and T13_2 connected in series. The thirteenth transistor T13 may also include a back gate electrode connected to the gate electrode.

[0112] The gate electrode of the fourteenth transistor T14 can be connected to the second high voltage line VGH2, the first electrode can be connected to the first node N1, and the second electrode can be connected to the second node N2.

[0113] Figure 6 This is a waveform diagram illustrating a method for driving a scan level according to an embodiment of the present disclosure.

[0114] refer to Figure 6 The embodiment shows the scan start signal of the scan start line FLM, the first carry clock signal of the first carry clock line CRCK1, the third carry clock signal of the third carry clock line CRCK3, the odd-numbered third buffer clock signal of the odd-numbered third buffer clock line CK3O, the even-numbered third buffer clock signal of the even-numbered third buffer clock line CK3E, the voltage of the second node N2 of the first scan level ST1, the first scan signal of the first scan line SL1, the second scan signal of the second scan line SL2, the voltage of the second node N2 of the second scan level ST2, the third scan signal of the third scan line SL3, the fourth scan signal of the fourth scan line SL4, and the first carry signal of the first carry line CR1.

[0115] At time t1a, the first transistor T1 is turned on by the first carry clock signal, which is at the on level (high level). Therefore, a scan start signal at the on level (high level) is applied to the first node N1. At this time, the fourteenth transistor T14 is turned on due to the second high voltage of the second high voltage line VGH2. Therefore, a voltage at the on level (high level) can also be applied to the second node N2. Accordingly, the seventh transistor T7 and the ninth transistors T9_O and T9_E can be turned on.

[0116] At time t2a, the first carry signal, which is at the on level (high level), is output via the third carry clock signal, which is at the on level (high level). Additionally, the first scan signal, which is at the on level (high level), is output to the first scan line SL1 via the odd-numbered ninth transistor T9_O, via the odd-numbered third buffer clock signal, which is at the on level (high level).

[0117] At time t3a, the second scan signal, which is at the even-numbered third buffer clock signal that is at the on level (high level), is output to the second scan line SL2 via the even-numbered ninth transistor T9_E.

[0118] Figure 7 This is a cross-sectional view of a display device 11 according to an embodiment of the present disclosure.

[0119] refer to Figure 7 According to embodiments of the present disclosure, the display device 11 may include a plurality of insulating layers INL1, INL2, INL3, INL4, INL5 and INL6, a plurality of electrode layers CEL1, CEL2, CEL3, CEL4 and CEL5, an active layer ACL, a pixel defining layer PDL and a spacer SPC.

[0120] Although not shown, a substrate may exist beneath the first insulating layer INL1. The substrate may comprise various materials such as glass, polymers, or metals. Depending on the product being applied, the substrate may be selected as a rigid or flexible substrate. When the substrate is constructed to include polymeric organic materials, it may be composed of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, or cellulose acetate propionate, etc. The substrate may also be composed of glass fiber reinforced plastic (FRP).

[0121] The insulating layers INL1, INL2, INL3, INL4, INL5, and INL6, the pixel defining layer PDL, and the spacer SPC can be composed of organic insulating layers, inorganic insulating layers, or organic / inorganic insulating layers, and can be a single layer or multiple layers. For example, insulating layers INL1 to INL6 may include silicon nitride (SiN). x ), silicon dioxide (SiO) x ), silicon oxynitride (SiO) x N y It includes at least one of acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin.

[0122] Electrode layers CEL1, CEL2, CEL3, CEL4, and CEL5 can each be a single layer or multiple layers, and can be composed of known conductors such as gold (Au), silver (Ag), aluminum (Al), molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and platinum (Pt).

[0123] The first electrode layer CEL1 may be located on the first insulating layer INL1. The first electrode layer CEL1 may include the back gate electrode of the transistor and one electrode of the capacitor.

[0124] The second insulating layer INL2 may be located on the first electrode layer CEL1. The active layer ACL may be located on the second insulating layer INL2. The active layer ACL may include the channel TCH of the transistor, the first electrode TE1, and the second electrode TE2. The active layer ACL may be a semiconductor layer. The semiconductor layer may be composed of oxide semiconductor or polysilicon semiconductor. The first electrode TE1 and the second electrode TE2 may be doped with impurities to conduct electricity. In addition, the active layer ACL may include one electrode of a capacitor.

[0125] The third insulating layer INL3 may be located on the active layer ACL. The second electrode layer CEL2 may be located on the third insulating layer INL3. The second electrode layer CEL2 may include the gate electrode of a transistor and one electrode of a capacitor.

[0126] The fourth insulating layer INL4 can be located on the second electrode layer CEL2. The third electrode layer CEL3 can be located on the fourth insulating layer INL4. The third electrode layer CEL3 can be connected to the active layer ACL or the first electrode layer CEL1 through contact holes. According to an embodiment, the third electrode layer CEL3 can be connected to the second electrode layer CEL2 through contact holes. The third electrode layer CEL3 can form various wirings, the gate electrode of a transistor, and the electrode of a capacitor.

[0127] The fifth insulating layer, INL5, can be located on the third electrode layer, CEL3. The fourth electrode layer, CEL4, can be located on the fifth insulating layer, INL5. The fourth electrode layer, CEL4, can be connected to the third electrode layer, CEL3, via a through-hole. The through-hole electrode, VIA1, can be disposed in the through-hole. Electrode lines requiring a large area, such as power lines or voltage supply lines, can be disposed in the fourth electrode layer, CEL4.

[0128] The sixth insulating layer, INL6, can be located on the fourth electrode layer, CEL4. The fifth electrode layer, CEL5, can be located on the sixth insulating layer, INL6. The fifth electrode layer, CEL5, can include the anode electrode of the light-emitting device (LD).

[0129] The pixel defining layer (PDL) may be located on the fifth electrode layer (CEL5). The pixel defining layer (PDL) may include an opening defining the emission region of the light-emitting device (LD).

[0130] Spacer components (SPCs) can be disposed on the pixel limiting layer (PDL). SPCs may exist for the purpose of preventing or mitigating leakage current or preventing or mitigating light diffusion by cutting off the common layer of the light-emitting diode (LD).

[0131] Therefore, the structure and operation of the pixel section and scan driver in the display device can be as described above. Pixels are arranged in rows and connected to odd-numbered and even-numbered scan lines, thereby achieving efficient data delivery without a demultiplexer. The scan driver includes scan stages, each with logic circuitry and buffer transistors, that sequentially activate the scan lines using a carry signal and a buffered clock signal. The detailed circuitry of each scan stage may include multiple transistors and capacitors designed to control signal timing and stability. Furthermore, the stacked physical structure of the display device, including insulating layers, electrode layers, semiconductor active layers, and light-emitting devices, is designed to support precise electrical performance and minimize light leakage or interference.

[0132] Figures 8A to 13B A plan view layout of the scan level is shown according to an embodiment of the present disclosure.

[0133] For ease of description, the layout of the first scan level ST1 and the second scan level ST2 disposed on the second direction DR2 relative to the first scan level ST1 is shown as an example.

[0134] Figure 8A and Figure 8B A portion of the first electrode layer CEL1 is shown. Figure 8B The portion shown can be relative to Figure 8A The portion shown is positioned on the first direction DR1.

[0135] refer to Figure 8A and Figure 8BThe first electrode layer CEL1 may include a scan start line FLM, a first carry line CR1, first scan lines to fourth scan lines SL1, SL2, SL3 and SL4, a bridging component CK3E_B for the even-numbered third buffer clock line CK3E, a bridging component CK3O_B for the odd-numbered third buffer clock line CK3O, a bridging component CK4E_B for the even-numbered fourth buffer clock line CK4E, and a bridging component CK4O_B for the odd-numbered fourth buffer clock line CK4O. Bridging components CK3E_B, CK3O_B, CK4E_B and CK4O_B can each connect their respective buffer clock lines to their corresponding buffer transistors.

[0136] Figure 9A and Figure 9B This shows a portion of the active layer ACL. Figure 9B The portion shown can be relative to Figure 9A The portion shown is positioned on the first direction DR1.

[0137] refer to Figure 9A and Figure 9B The active layer ACL may include the channels T1_1c and T1_2c of the sub-transistors T1_1 and T1_2 of the first transistor T1, the channels T2_1c and T2_2c of the sub-transistors T2_1 and T2_2 of the second transistor T2, the channels T3_1c and T3_2c of the sub-transistors T3_1 and T3_2 of the third transistor T3, the channel T4c of the fourth transistor T4, the channel T5c of the fifth transistor T5, the channel T6c of the sixth transistor T6, the channel T7c of the seventh transistor T7, the channel T8c of the eighth transistor T8, and the channel of the odd-numbered ninth transistor T9_O. Channel T9_Oc, channel T9_Ec of the even-numbered ninth transistor T9_E, channel T10_Oc of the odd-numbered tenth transistor T10_O, channel T10_Ec of the even-numbered tenth transistor T10_E, channel T11c of the eleventh transistor T11, channel T12c of the twelfth transistor T12, channels T13_1c and T13_2c of the sub-transistors T13_1 and T13_2 of the thirteenth transistor T13, channel T14c of the fourteenth transistor T14, first electrode C1E of the first capacitor C1, and first electrode C2E of the second capacitor C2.

[0138] exist Figure 9A and Figure 9B In the embodiment shown, the channel T9_Oc of the first buffer transistor T9_O can be disposed on the second direction DR2 relative to the channel T9_Ec of the third buffer transistor T9_E. Odd-numbered scan lines SL1 can be disposed on the second direction DR2 relative to even-numbered scan lines SL2 (see [reference]). Figure 8BThe channel T10_Oc of the second buffer transistor T10_O can be disposed on the second direction DR2 relative to the channel T10_Ec of the fourth buffer transistor T10_E.

[0139] For example, the location of the buffer transistor in this embodiment may be different. Figure 4 The positions are shown in the diagram. However, by changing the positions of the bridge CK3E_B for the even-numbered third buffer clock line CK3E and the bridge CK3O_B for the odd-numbered third buffer clock line CK3O, those skilled in the art can easily implement various layouts. Figure 4 The embodiments shown in (see) Figure 8B ).

[0140] Figure 10A and Figure 10B A portion of the second electrode layer CEL2 is shown. Figure 10B The portion shown can be relative to Figure 10A The portion shown is positioned on the first direction DR1.

[0141] Figure 11A and Figure 11B A portion of the third electrode layer CEL3 is shown. Figure 11B The portion shown can be relative to Figure 11A The portion shown is positioned on the first direction DR1.

[0142] refer to Figure 11A and Figure 11B The third electrode layer CEL3 may include a reset line ESR, carry clock lines CRCK1, CRCK2, CRCK3 and CRCK4, voltage lines VGH1, VGH2, VGL1 and VGL2, and buffer clock lines CK1O, CK2O, CK3O, CK4O, CK1E, CK2E, CK3E and CK4E extending in the second direction DR2.

[0143] Figure 12A and Figure 12B A portion of the fourth electrode layer CEL4 and the through-hole electrode VIA1 is shown. Figure 12B The portion shown can be relative to Figure 12A The portion shown is positioned on the first direction DR1.

[0144] refer to Figure 12A and Figure 12B The fourth electrode layer CEL4 may include sub-voltage lines VGH1s, VGL1s, and VGL2s with large areas. For example, sub-voltage line VGH1s may be connected to a first high-voltage line VGH1. Sub-voltage line VGL1s may be connected to a first low-voltage line VGL1. Sub-voltage line VGL2s may be connected to a second low-voltage line VGL2.

[0145] Figure 13A It shows that Figure 9A , Figure 10A , Figure 11A and Figure 12A Overlapping layout. However, to improve visibility, in Figure 12A The structure shown only shows the through-hole electrode VIA1, and the structure of the fourth electrode layer CEL4 is excluded.

[0146] Figure 13B It shows that Figure 9B , Figure 10B , Figure 11B and Figure 12B Overlapping layout. However, to improve visibility, in Figure 12B The structure shown only shows the through-hole electrode VIA1, and the structure of the fourth electrode layer CEL4 is excluded.

[0147] Therefore, based on the above-mentioned stacked physical layout of the scan level in the display device, the focus is on how transistors, scan lines and buffer clock lines are distributed across multiple electrodes and active layer arrangements, such as different components of bridges, clock lines and sub-transistor channels, positioned relative to each other in the first and second directions, and the layout can be adjusted to support alternative circuit constructions without changing the basic electrical design.

[0148] Figure 14 This is a diagram illustrating a scan driver 24' according to an embodiment of the present disclosure.

[0149] refer to Figure 14 The carry clock lines CRCK1 to CRCK4 extend in the second direction DR2 between buffer transistors T9_O and T9_E and pixel portion 25, which differs from the... Figure 4 The scan driver 24 in the embodiment. Figure 14 The embodiments illustrate that can be used for Figure 4 The embodiments are subject to various modifications.

[0150] According to embodiments, the display device can be applied to various electronic devices. According to embodiments, the electronic device includes the aforementioned display device, and may further include modules or devices with additional functions in addition to the display device.

[0151] Figure 15 This is a schematic block diagram of an electronic device 10 according to an embodiment. (See reference) Figure 15 According to an embodiment, the electronic device 10 may include a display module (or display device) 11, a processor 12, a memory 13, and a power module 14.

[0152] Processor 12 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller. In embodiments, processor 12 may be provided as two or more parts from a functional or structural perspective. For example, processor 12 may include a main processor in the form of a first driver chip including a CPU and an auxiliary processor in the form of a second driver chip including a controller that receives image signals from the main processor and processes the image signals to conform to the interface specifications of display module 11. Processor 12 may provide grayscale of image frames. Display module (or display device) 11 may use the received grayscale to display the image.

[0153] The memory 13 may include at least one of non-volatile memory and volatile memory. The memory 13 may store data information required for the operation of the processor 12 or the display module 11. When the processor 12 executes the application stored in the memory 13, image data signals and / or input control signals are transmitted to the display module 11, and the display module 11 can process the received signals and output image information through the display screen.

[0154] The power module 14 may include a power supply module such as a power adapter or battery device, and a power conversion module that converts the power supplied by the power supply module to generate the power required for the operation of the electronic device 10. The power conversion performed by the power conversion module may include, but is not limited to, DC-DC conversion, AC-DC conversion, and DC-AC conversion.

[0155] The electronic device 10 may further include an input module 15, a non-image output module 16, and / or a communication module 17.

[0156] Input module 15 can provide input information to processor 12 and / or display module 11. Input module 15 may include various sensor modules as well as physical buttons, keyboards, and microphones. Examples of sensor modules may include touch sensors, pressure sensors, proximity sensors, position sensors, digitizers, motion recognition sensors, camera sensors, light receiving sensors, photoelectric conversion sensors, temperature sensors, and biometric sensors such as blood pressure sensors, blood glucose sensors, electrocardiogram sensors, and heart rate sensors.

[0157] The non-image output module 16 can receive information other than the image received from the processor 12 and provide that information to the user. Examples of non-image output modules 16 include acoustic modules, haptic modules, or light-emitting modules, and may include other functional modules specific to electronic devices (e.g., a cooling module for a refrigerator).

[0158] The communication module 17 is responsible for sending and receiving information between the electronic device 10 and external devices, and may include a receiving unit and a sending unit. The communication module 17 may include various wireless communication modules such as mobile communication modules, Wi-Fi modules, and Bluetooth modules, or various wired communication modules.

[0159] At least one of the aforementioned components of the electronic device 10 may be included in the display device according to the above embodiment. Additionally, one or more individual modules that are functionally included in a single module may be included in the display device, and other individual modules may be provided separately from the display device. For example, the display device includes a display module 11, and the processor 12, memory 13, and power module 14 may be provided as other devices in the electronic device 10 besides the display device. In another example, the power module 14 may be provided in the display device and supply power to the processor 12 and memory 13 provided in the electronic device 10 besides the display device, but this is not necessarily limited to the above examples.

[0160] Figures 16 to 18 This is a perspective schematic diagram of an electronic device according to various embodiments. Figures 16 to 18 Examples of various electronic devices applied to a display device according to an embodiment are illustrated.

[0161] Figure 16 The illustrations show a smartphone 10_1a, a tablet computer 10_1b, a laptop / notebook computer 10_1c, a television 10_1d, and a computer monitor 10_1e as examples of electronic devices.

[0162] In addition to the display module, the smartphone 10_1a may include a communication module and an input module such as a touch sensor. The smartphone 10_1a can process information received through the communication module or the input module and display that information through the display module of the display device.

[0163] Similar to the smartphone 10_1a, each of the tablet computer 10_1b, laptop / notebook computer 10_1c, television 10_1d, and computer monitor 10_1e also includes a display module and an input module, and in some cases may further include a communication module.

[0164] Figure 17 The illustration shows an electronic device, including a display module, being used in a wearable electronic device. The wearable electronic device could be smart glasses 10_2a, a head-mounted display 10_2b, or a smartwatch 10_2c, etc.

[0165] The smart glasses 10_2a and the head-mounted display 10_2b may include a display module that outputs and displays images, and a reflector that reflects and provides the reflected images to the user's eyes, thereby providing the user with virtual reality or augmented reality images.

[0166] The smartwatch 10_2c includes a biometric sensor as an input device, and can provide the user with biometric information identified by the biometric sensor through a display module.

[0167] Figure 18 The illustration shows an electronic device, including a display module, being applied to a vehicle. For example, the electronic device 10_3 can be applied to a car dashboard or central instrument panel, or it can be applied to a central information display (CID) placed on the vehicle's dashboard or an interior mirror display that replaces the side mirrors.

[0168] The electronic devices used in the display devices according to the embodiments can include not only devices such as the main display screens of digital billboards, electronic billboards, and portable game consoles, but also various household appliances such as refrigerators, washing machines, dryers, air conditioners, and robotic vacuum cleaners that display information through the display module. Additionally, when the display module has the function of transmitting light, the display module can be applied to electronic devices such as smart windows or transparent display devices that simultaneously display a background and an image. According to the embodiments, the type of electronic device is not necessarily limited to the examples described above, and various other electronic devices not shown can be used.

[0169] In addition to the other advantages described above, the display device and electronic device according to embodiments of the present disclosure may include a scan driver capable of reducing power consumption.

[0170] Although this disclosure has been described with reference to embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made to this disclosure without departing from the scope and spirit of this disclosure.

Claims

1. A display device, comprising: The pixel portion includes multiple rows of pixels, each extending in a first direction and each connected to scan lines numbered odd and even. as well as A scan driver includes multiple scan levels, each connected to the odd-numbered scan lines and the even-numbered scan lines. Each of the plurality of scan levels includes a buffer transistor, and The buffer clock line connected to the buffer transistor extends in a second direction that intersects the first direction between the buffer transistor and the pixel portion.

2. The display device according to claim 1, wherein Each of the plurality of scan levels includes: Logic circuits; The first buffer transistor includes a first electrode connected to an odd-numbered buffer clock line, a gate electrode connected to the logic circuit, and a second electrode connected to the corresponding odd-numbered scan line. The second buffer transistor includes a first electrode connected to the corresponding odd-numbered scan line and a gate electrode connected to the logic circuit. The third buffer transistor includes a first electrode connected to an even-numbered buffer clock line, a gate electrode connected to the logic circuit, and a second electrode connected to a corresponding even-numbered scan line; and The fourth buffer transistor includes a first electrode connected to the corresponding even-numbered scan line and a gate electrode connected to the logic circuit.

3. The display device according to claim 2, wherein, The first buffer transistor is disposed on one side of the second buffer transistor in the first direction. The third buffer transistor is disposed on one side of the fourth buffer transistor in the first direction, and The logic circuit is disposed on one side of the first buffer transistor, the second buffer transistor, the third buffer transistor, and the fourth buffer transistor in a direction opposite to the first direction.

4. The display device according to claim 3, wherein The logic circuit is connected to the carry clock line, and The carry clock line is disposed on one side of the logic circuit in the direction opposite to the first direction and extends in the second direction.

5. The display device according to claim 3, wherein The logic circuit is connected to the carry clock line, and The carry clock line extends in the second direction between the first buffer transistor and the pixel portion.

6. The display device according to claim 3, wherein, The third buffer transistor is disposed on one side of the first buffer transistor in the second direction, and The even-numbered scan lines are located on one side of the odd-numbered scan lines in the second direction.

7. The display device of claim 6, wherein, The fourth buffer transistor is disposed on one side of the second buffer transistor in the second direction.

8. The display device according to claim 3, wherein The first buffer transistor is disposed on one side of the third buffer transistor in the second direction, and The odd-numbered scan lines are located on one side of the even-numbered scan lines in the second direction.

9. The display device of claim 8, wherein, The second buffer transistor is disposed on one side of the fourth buffer transistor in the second direction.

10. An electronic device comprising: The display device according to any one of claims 1 to 9.

Images