Method for evaluating pattern transfer accuracy, evaluation device, and semiconductor manufacturing system

Abstract

This application discloses a method, apparatus, and semiconductor manufacturing system for evaluating pattern transfer accuracy. The method involves scanning the semiconductor microstructure to be evaluated to obtain surface contour data; comparing the surface contour data with target contour data of the semiconductor microstructure to obtain process error data; and generating feedback data on the pattern transfer accuracy of the semiconductor microstructure based on the process error data. The process error data directly reflects the accuracy of the structural dimensions formed by image transfer during the production process. The feedback data can be used to calibrate the deviation between the actual pattern and the target pattern of the semiconductor microstructure, which helps improve the accuracy and real-time performance of pattern transfer accuracy evaluation. It also facilitates further evaluation and analysis of pattern transfer accuracy using the feedback data, thereby enabling visual localization of the root cause of pattern transfer problems and improving the practicality of pattern transfer accuracy evaluation.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to methods, apparatus and systems for evaluating pattern transfer accuracy. Background Technology

[0002] In the current semiconductor device manufacturing process, methods such as photolithography and etching are typically used for pattern transfer to form semiconductor devices with patterned structures. The accuracy of pattern transfer directly affects the device yield.

[0003] However, existing methods for evaluating pattern transfer accuracy typically involve calibrating a photolithography model using a test wafer during the R&D phase. This calibrated model is then used to assess the pattern transfer accuracy. However, this method only evaluates the actual semiconductor microstructure generated based on the transfer accuracy of the test wafer, detaching it from the actual production environment and failing to reflect process fluctuations in real-world manufacturing. Existing methods may also indirectly assess the pattern transfer accuracy of semiconductor microstructures through electrical parameter testing and simple critical dimension measurements. However, these methods cannot directly assess the pattern transfer accuracy of semiconductor microstructures or visualize the sources of pattern distortion. Therefore, a more accurate method for evaluating the pattern transfer accuracy of semiconductor microstructures is urgently needed. Summary of the Invention

[0004] To address the aforementioned technical problems, this application provides a method, apparatus, and semiconductor manufacturing system for evaluating graphics transfer accuracy.

[0005] To address the aforementioned problems, this application provides a first technical solution: a method for evaluating pattern transfer accuracy, comprising: scanning a semiconductor microstructure to be evaluated to obtain surface contour data of the semiconductor microstructure; comparing the surface contour data with target contour data of the semiconductor microstructure to obtain process error data of the semiconductor microstructure; and generating feedback data on the pattern transfer accuracy of the semiconductor microstructure based on the process error data.

[0006] In some embodiments, the surface contour data includes contour edge data of the semiconductor microstructure; comparing the surface contour data with the target contour data of the semiconductor microstructure to obtain process error data of the semiconductor microstructure includes: obtaining target edge data of the design layout of the semiconductor microstructure; comparing the contour edge data with the target edge data to obtain edge error data of the semiconductor microstructure.

[0007] In some embodiments, the surface profile data includes key structural dimension data of the semiconductor microstructure; comparing the surface profile data with the target profile data of the semiconductor microstructure to obtain process error data of the semiconductor microstructure includes: obtaining target dimension data of key structures in the design layout of the semiconductor microstructure; comparing the key structural dimension data with the target dimension data to obtain key dimension error data of the semiconductor microstructure.

[0008] In some embodiments, the feedback data includes performance impact data; the step of generating feedback data on the pattern transfer accuracy of the semiconductor microstructure based on the process error data includes: extracting correction data of the semiconductor microstructure from the process error data; and performing electrical performance simulation analysis based on the correction data to obtain performance impact data on the pattern transfer accuracy of the semiconductor microstructure.

[0009] In some embodiments, the feedback data further includes risk assessment data; after the step of performing electrical performance simulation analysis based on the corrected data to obtain performance impact data on the pattern transfer accuracy of the semiconductor microstructure, the evaluation method further includes: outputting risk assessment data on the pattern transfer accuracy of the semiconductor microstructure based on the process error data and / or the performance impact data.

[0010] In some embodiments, after the step of generating feedback data on the pattern transfer accuracy of the semiconductor microstructure based on the process error data, the evaluation method further includes: generating an evaluation report of the semiconductor microstructure based on the process error data, the performance impact data, and the risk assessment data.

[0011] In some embodiments, comparing the surface contour data with the target contour data of the semiconductor microstructure to obtain the process error data of the semiconductor microstructure includes: calculating a transformation parameter between the surface contour data and the target contour data based on the mapping relationship between the data points in the surface contour data and the data points in the target contour data; performing data transformation on the surface contour data based on the transformation parameter to align the anchor points of the surface contour data with the anchor points of the target contour data; and calculating the deviation between the aligned surface contour data and the target contour data to obtain the process error data.

[0012] In some embodiments, the semiconductor microstructure includes a semiconductor device structure formed on a substrate by a semiconductor process, or the semiconductor microstructure includes a semiconductor device structure formed on a substrate by a semiconductor process and a mask pattern of the semiconductor device structure.

[0013] In some embodiments, scanning the semiconductor microstructure to be evaluated to obtain surface contour data of the semiconductor microstructure includes: selecting the semiconductor device structure processed by the semiconductor process from the semiconductor manufacturing system according to a preset selection rule; and scanning the semiconductor device structure to obtain the surface contour data.

[0014] To address the aforementioned problems, this application provides a second technical solution: a device for evaluating pattern transfer accuracy, comprising a scanning module and an analysis module; the scanning module is configured to receive a semiconductor microstructure and scan the semiconductor microstructure to obtain surface contour data of the semiconductor microstructure; the analysis module is connected to the scanning module and is configured to compare the surface contour data with target contour data of the semiconductor microstructure to obtain process error data of the semiconductor microstructure, and generate feedback data for pattern transfer of the semiconductor microstructure based on the process error data.

[0015] To address the aforementioned problems, this application provides a third technical solution: a semiconductor manufacturing system comprising a processing apparatus and the aforementioned evaluation apparatus; the processing apparatus is configured to process a wafer to obtain a semiconductor microstructure; the evaluation apparatus is configured to scan and analyze the semiconductor microstructure to obtain feedback data on the pattern transfer of the semiconductor microstructure.

[0016] In some embodiments, the processing apparatus is configured to perform photolithography or etching on the wafer to obtain the semiconductor microstructure, and the evaluation apparatus is configured to obtain feedback data of the semiconductor microstructure; and / or, the processing apparatus is configured to process the wafer to obtain a semiconductor microstructure including at least a device layer and an interconnect layer, and the evaluation apparatus is configured to obtain feedback data of the semiconductor microstructure.

[0017] This application provides a method, apparatus, and semiconductor manufacturing system for evaluating pattern transfer accuracy. The method involves scanning the semiconductor microstructure to be evaluated to obtain surface contour data; comparing the surface contour data with target contour data of the semiconductor microstructure to obtain process error data; and generating feedback data on the pattern transfer accuracy of the semiconductor microstructure based on the process error data. Therefore, by comparing the surface contour data of the semiconductor microstructure with the target contour data, the obtained process error data can directly reflect the accuracy of the structural dimensions formed by image transfer during the production process. The feedback data generated based on the process error data can be used to calibrate the deviation between the actual pattern and the target pattern of the semiconductor microstructure, which improves the accuracy and real-time performance of pattern transfer accuracy evaluation. This facilitates further evaluation and analysis of pattern transfer accuracy using the feedback data, thereby enabling the visual localization of the root cause of pattern transfer problems and improving the practicality of pattern transfer accuracy evaluation. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein: Figure 1 This is a flowchart illustrating an embodiment of the graphic transfer accuracy evaluation method provided in this application; Figure 2 This application provides Figure 1 A flowchart illustrating the first embodiment of generating feedback data on graphic transfer accuracy; Figure 3 This application provides Figure 1 A flowchart illustrating the second embodiment for generating feedback data on graphic transfer accuracy; Figure 4 This is a schematic diagram of the interface of the first embodiment of the evaluation report provided in this application; Figure 5 This is a schematic diagram of the interface of the second embodiment of the evaluation report provided in this application; Figure 6 This is a schematic diagram of the interface of the third embodiment of the evaluation report provided in this application; Figure 7 This application provides Figure 1 A flowchart illustrating an embodiment for obtaining process error data; Figure 8 This is a schematic diagram of an embodiment of the graphic transfer accuracy evaluation device provided in this application; Figure 9 This is a schematic diagram of an embodiment of the semiconductor manufacturing system provided in this application.

[0019] In the diagram, 1 represents a semiconductor manufacturing system; 10 represents an evaluation device; 11 represents a scanning module; 12 represents an analysis module; and 20 represents a processing device. Detailed Implementation

[0020] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0021] It should be noted that if the embodiments of this application involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicators will also change accordingly.

[0022] Furthermore, if the embodiments of this application involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. If the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed in this application.

[0023] This application first provides a method for evaluating pattern transfer accuracy. This method is used to evaluate the pattern transfer accuracy of semiconductor microstructures in the semiconductor manufacturing process, including but not limited to evaluating the pattern transfer accuracy of semiconductor microstructures in photolithography and / or etching processes.

[0024] Please see Figure 1 , Figure 1 This is a flowchart illustrating an embodiment of the graphic transfer accuracy evaluation method provided in this application. Figure 1 As shown, the evaluation method includes the following steps: Step S1: Scan the semiconductor microstructure to be evaluated to obtain surface profile data of the semiconductor microstructure.

[0025] In evaluating the pattern transfer accuracy of semiconductor microstructures, the semiconductor microstructure to be evaluated is first acquired, and its surface contour data is obtained by scanning the microstructure. The surface contour data may include, but is not limited to, relevant dimensional data reflecting the edge contours and / or pattern contours of the semiconductor microstructure, scanned image data, etc., such as data related to the edge contours and / or pattern contours of fabricated semiconductor device structures, and the edge contours and / or pattern contours of mask layouts used for semiconductor processing.

[0026] The aforementioned methods for scanning semiconductor microstructures include, but are not limited to, laser contour scanning, white light interferometry scanning, and structured light three-dimensional scanning. Alternatively, semiconductor microstructures can be scanned using devices such as scanning electron microscopes (SEM), transmission electron microscopes (TEM), X-ray microscopes (X-ray microscopy / Micro-CT, XRM), scanning tunneling microscopes (STM), and atomic force microscopes (AFM) to obtain surface contour data of the semiconductor microstructures.

[0027] Step S2: Compare the surface contour data with the target contour data of the semiconductor microstructure to obtain the process error data of the semiconductor microstructure.

[0028] The target contour data of a semiconductor microstructure can be, but is not limited to, the contour dimensions of the target pattern of the semiconductor microstructure on the design layout, or the design image data of the semiconductor microstructure. After obtaining the surface contour data of the semiconductor microstructure to be evaluated, the surface contour data is compared with the target contour data to obtain the process error data of the semiconductor microstructure. The process error data is used to reflect the error between the manufactured pattern of the semiconductor microstructure in the actual process and the designed target pattern. For example, the process error data includes, but is not limited to, at least one of the errors between the edge dimensions of the actual pattern of the semiconductor microstructure and the edge dimensions of the target pattern, and the errors between the critical structural dimensions of the actual pattern of the semiconductor microstructure and the critical structural dimensions of the target pattern. For example, the critical structural dimensions of the semiconductor microstructure can be, but are not limited to, at least one of the following: transistor gate length, width of metal wires and spacing of each wire, contact hole / via size, width of isolation structure, and overlay error of via.

[0029] Step S3: Generate feedback data on the pattern transfer accuracy of semiconductor microstructures based on process error data.

[0030] After obtaining the process error data of the semiconductor microstructure, feedback data on the pattern transfer accuracy of the semiconductor microstructure is generated based on the process error data. This feedback data may, but is not limited to, indicate at least one of the following: the impact of process errors during pattern transfer of the semiconductor microstructure, the degree of risk of process errors, and strategies for correcting pattern transfer errors, so as to facilitate users to further evaluate and analyze the pattern transfer accuracy through the feedback data.

[0031] In this embodiment, the evaluation method compares the surface contour data of the semiconductor microstructure with the target contour data, so that the process error data obtained by comparison can directly reflect the accuracy of the structural dimensions formed by image transfer during the production process. This allows the feedback data generated based on the process error data to be used to calibrate the deviation between the actual pattern and the target pattern of the semiconductor microstructure, which is beneficial to improving the accuracy and real-time performance of pattern transfer accuracy evaluation. It also facilitates further evaluation and analysis of pattern transfer accuracy through feedback data, thereby enabling the visual location of the root cause of pattern transfer problems and improving the practicality of pattern transfer accuracy evaluation.

[0032] In some embodiments, surface profile data includes profile edge data of the semiconductor microstructure; process error data includes edge error data of the semiconductor microstructure.

[0033] Step S2 includes: acquiring target edge data of the design layout of the semiconductor microstructure; comparing the contour edge data with the target edge data to obtain edge error data of the semiconductor microstructure.

[0034] Specifically, after obtaining the target edge data of the semiconductor microstructure design layout, edge error data of the semiconductor microstructure is obtained by comparing the contour edge data with the target edge data. The edge error data indicates the error range between the edge position of the actual pattern of the semiconductor microstructure and the edge position of the target pattern. In possible implementations, the edge error data can be represented by at least one error parameter, including but not limited to edge placement error (EPE), modified edge placement error (MEPE), and edge-to-edge placement error (EEPE).

[0035] In some methods, the target edge data refers to the edge dimension data of the actual pattern of the semiconductor microstructure, or the edge dimension data of the target pattern of the semiconductor microstructure. This edge dimension data can be, but is not limited to, the dimension between the edge of the pattern and a reference point. For example, the reference point can be a fixed point such as a corner or center point of the semiconductor microstructure. Therefore, the edge error data of the semiconductor microstructure can be obtained directly by comparing the dimensions of the target edge data and the contour edge data.

[0036] In other methods, the contour edge data is a scanned image containing the edge features of the actual pattern of the semiconductor microstructure, and the target edge data is a designed image containing the edge features of the target pattern of the semiconductor microstructure. When comparing the contour edge data and the target edge data, feature point matching between the contour edge data and the target edge data can be performed using a transformation model, but is not limited to, to automatically align the contours of the semiconductor microstructure in the images of the contour edge data and the target edge data. Then, an error comparison is performed between the target edge data and the contour edge data. The methods for achieving contour alignment between the contour edge data and the target edge data include, but are not limited to, at least one method such as phase correlation / Fourier translation registration, normalized cross-correlation, feature point-based registration, mutual information-based registration, optical flow, non-rigid registration, and dedicated marker alignment.

[0037] Therefore, by comparing the contour edge data of the actual pattern of the semiconductor microstructure with the target edge data of the designed pattern, edge error data of the semiconductor microstructure can be obtained. This allows the edge error data to accurately reflect the edge placement error in the photolithography process, thereby achieving precise visualization and positioning of the source of pattern distortion. This facilitates the rapid identification of process fluctuation points by the location of the largest error and targeted optimization, thereby improving the production yield of semiconductor devices.

[0038] In some embodiments, surface profile data includes key structural dimension data of the semiconductor microstructure; process error data includes key dimension error data of the semiconductor microstructure.

[0039] Step S2 includes: obtaining target size data of key structures in the design layout of semiconductor microstructures; comparing the key structure size data with the target size data to obtain key size error data of semiconductor microstructures.

[0040] Specifically, the critical structural dimension data of a semiconductor microstructure refers to the dimensional data of key structures that require precise control during the device manufacturing process of the semiconductor microstructure. After obtaining the critical structural dimension data of the semiconductor microstructure after scanning, the same type of critical structural dimension data is compared with the corresponding target dimension data in the design layout to obtain the critical dimension error data of the semiconductor microstructure. The critical dimension error data is used to indicate the error range between the edge position of the actual pattern of the semiconductor microstructure and the edge position of the target pattern. In possible implementations, the critical dimension error data can be represented by the critical dimension (CD) of the semiconductor device, including but not limited to the error data of at least one of the following: transistor gate length, width of metal wires and spacing of each wire, contact hole / via size, width of isolation structure, and overlay error of via.

[0041] In one possible approach, key structural features such as gates, source / drain regions, wire positions, isolation structures, and contact holes can be analyzed and their key structural dimensions obtained by recognizing scanned images of actual semiconductor microstructures. For example, image processing algorithms can be used to identify key structural features and extract their dimensional data. The target dimensional data can be design process parameters from the design pattern. The target dimensional data can be pre-stored in memory and retrieved during pattern transfer accuracy evaluation; alternatively, the target dimensional data can be obtained by scanning the design image of the target pattern; or, the target dimensional data can be defined by user input. The specific method of obtaining the target dimensional data can be adjusted according to user needs and is not specifically limited here.

[0042] Therefore, by comparing the key structural dimension data and target dimension data of semiconductor microstructures, the precise quantification of key dimension deviations can be achieved. This facilitates the visualization and location of pattern transfer distortion during the pattern transfer process. It also enables subsequent correlation between the key dimension error data and the impact of geometric deviations on circuit performance, allowing for the calibration of deviation factors during the pattern transfer process and improving the yield control of the semiconductor manufacturing process.

[0043] In some embodiments, the feedback data includes performance impact data. See also Figure 2 , Figure 2 This application provides Figure 1 A flowchart illustrating the first embodiment for generating feedback data on graphic transfer accuracy. (See attached diagram.) Figure 2 As shown, in the evaluation method of this embodiment, step S3 further includes the following steps: Step S31: Extract correction data for semiconductor microstructure from process error data.

[0044] Specifically, process error data is used to indicate the dimensional deviation between the actual and target patterns of a semiconductor microstructure. Correction data for the semiconductor microstructure can be extracted from the process error data. This correction data describes the deviation between the actual semiconductor microstructure in the process and the ideally designed semiconductor structure.

[0045] Step S32: Perform electrical performance simulation analysis based on the corrected data to obtain performance impact data on the pattern transfer accuracy of semiconductor microstructures.

[0046] A general analytical model is provided for semiconductor microstructures. This model is used to describe, through mathematical relationships, the electrical characteristics of a semiconductor microstructure with an infinite geometric size fitted using a minimum set of parameters under ideal design conditions. After extracting correction data of the actual pattern of the semiconductor microstructure from the process error data, the analytical model is modified and adjusted based on the correction data. This modified model can then be used to simulate and solve the semiconductor microstructure to be evaluated, thereby obtaining data on the performance impact of geometric deviations on the electrical properties of the semiconductor microstructure during pattern transfer.

[0047] For example, when the process error data includes edge error data, a first correction parameter corresponding to the edge size of the semiconductor microstructure can be obtained based on the edge error data, so as to adjust the model parameters of the analysis model based on the first correction parameter; and / or, when the process error data includes critical size error data, a second correction parameter corresponding to the critical size of the semiconductor microstructure can be obtained based on the critical size error data, so as to adjust the model parameters of the analysis model based on the second correction parameter.

[0048] Therefore, by extracting correction data of semiconductor microstructures from process error data, electrical performance simulation analysis of semiconductor microstructures can be performed based on the correction data. This enables a quantitative assessment of circuit performance changes caused by pattern distortion, which helps improve the accuracy of root cause analysis and further enhances yield control in semiconductor manufacturing processes.

[0049] Optionally, the feedback data includes performance impact data and risk assessment data. Please see [link to relevant documentation]. Figure 3 , Figure 3 This application provides Figure 1 A flowchart illustrating the second embodiment for generating feedback data on graphic transfer accuracy. (See attached diagram.) Figure 3 As shown, in the evaluation method of this embodiment, step S3 further includes the following steps: Step S31: Extract correction data for semiconductor microstructure from process error data.

[0050] Step S32: Perform electrical performance simulation analysis based on the corrected data to obtain performance impact data on the pattern transfer accuracy of semiconductor microstructures.

[0051] The contents of steps S31-S32 are similar to those described above, and will not be repeated here.

[0052] Step S33: Based on process error data and / or performance impact data, output risk assessment data for the pattern transfer accuracy of semiconductor microstructures.

[0053] Specifically, risk assessment data can be described, but is not limited to, risk levels and risk severity. In one example, risk levels may include a first level, a second level, and a third level; for example, the first level is low risk, the second level is medium risk, and the third level is high risk, allowing users to directly obtain the dimensional deviation risk of the current semiconductor microstructure through the risk level. One possible approach is to use different colored indicator lights on the prompt page to represent the risk levels. For example, a green indicator light could be used when the semiconductor microstructure is assessed as being at the first level, a yellow indicator light at the second level, and a red indicator light at the third level. In another example, risk assessment data can be described by risk severity. In this case, the risk severity of the semiconductor microstructure can be predicted based on at least one of process error data and performance impact data, allowing users to directly obtain the dimensional deviation risk of the current semiconductor microstructure through the risk level. For example, the risk severity can be represented by a percentage system.

[0054] Therefore, by using process error data, we can obtain performance impact data and risk assessment data of semiconductor microstructures caused by pattern transfer deviations during actual production and manufacturing. This allows users to directly locate and intervene in the source of pattern distortion based on the risk assessment data and performance impact data, which is beneficial for proactive intervention before yield declines and further improves yield control in the semiconductor manufacturing process.

[0055] Furthermore, after step S3, the evaluation method of this embodiment also includes: generating an evaluation report of the semiconductor microstructure based on process error data, performance impact data, and risk assessment data.

[0056] Specifically, an assessment report is generated by integrating process error data, performance impact data, and risk assessment data. This assessment report may be presented, but is not limited to, through an interactive interface including charts, or in a text report format.

[0057] In the first example, the evaluation report can include process error data, performance impact data, and risk assessment data of the semiconductor microstructure in its text content. Furthermore, it can generate adjustment recommendations for the semiconductor microstructure based on the aforementioned performance impact data and risk assessment data. Please refer to [link to relevant documentation]. Figure 4 , Figure 4 This is a schematic diagram of the interface of the first embodiment of the evaluation report provided in this application. Figure 4 As shown, this example displays the assessment report via a pop-up window. The main contents of the assessment report include: a summary section representing the risk assessment data via a traffic light icon; a section representing the key findings of the process error data via the first prompt text; a section representing the circuit performance impact prediction via the second prompt text; and a section providing adjustment suggestions via the third prompt text.

[0058] In the second example, an evaluation report can be generated by combining scanned images obtained during semiconductor microstructure scanning with textual data such as process error data, performance impact data, and risk assessment data. Please see [link to relevant documentation]. Figure 5 , Figure 5 This is a schematic diagram of the interface of the second embodiment of the evaluation report provided in this application. Figure 5 As shown, the semiconductor microstructure is a patterned structure formed through an etching process. The scanned image includes the original scanned image and the extracted contour lines from the original scanned image. This example uses multiple columns in the evaluation report to visually demonstrate the results of the multi-dimensional evaluation of pattern transfer accuracy. For example, the evaluation report includes an image panel, a process measurement results panel, a circuit performance impact simulation panel, and a comprehensive risk assessment panel. The image panel displays a scanned image of the actual pattern of the current semiconductor microstructure; the process measurement results panel displays process error data through a fourth prompt text, such as edge error data as value A and critical dimension error data as value B; the circuit performance impact simulation panel displays performance impact data through a fifth prompt text, such as simulation delay parameters and power consumption parameters; the comprehensive risk assessment panel displays risk assessment data through a sixth prompt text and indicator light graphics, such as the sixth prompt text indicating a medium risk level. Please see [link to relevant documentation]. Figure 6 , Figure 6 This is a schematic diagram of the interface of the third embodiment of the evaluation report provided in this application. Figure 6As shown, the semiconductor microstructure is a mask layout used in the semiconductor device structure patterning process. The scanned image includes the original scanned image and the outline extracted from the original scanned image. The evaluation report of this example includes an image panel, an evaluation results panel, and a component association panel. The image panel is used to display the scanned image of the actual pattern of the current mask layout; the evaluation results panel is used to display the analyzed process error data, performance impact data, and risk assessment data through the seventh prompt text, for example, the process error data is C, the performance impact data is D, and the risk assessment is medium; the component association panel is used to associate the current mask layout with its corresponding device type, for example, it can be used to show the association between the current mask layout and an NMOS device.

[0059] Therefore, by integrating multi-dimensional data on pattern transfer accuracy assessment into an evaluation report generated based on process error data, performance impact data, and risk assessment data, a comprehensive analysis of the root causes of pattern transfer problems can be achieved. This allows users to intuitively locate the source of distortion based on the evaluation report, which helps improve the efficiency of root cause analysis and further enhances yield control in the semiconductor manufacturing process.

[0060] In some embodiments, see Figure 7 , Figure 7 This application provides Figure 1 A schematic diagram of a process for obtaining process error data is shown below. Figure 7 As shown, step S2 above includes: Step S21: Based on the mapping relationship between the data points in the surface contour data and the data points in the target contour data, calculate the transformation parameters between the surface contour data and the target contour data.

[0061] Specifically, after obtaining surface contour data and target contour data, data points in the surface contour data and target contour data are identified to determine the coordinates of preset reference points. Based on the coordinate data of the preset reference points, the data points of the surface contour data and the target contour data are placed in the same coordinate system. For example, through the transformation relationship between the first coordinate data of the preset reference points in the surface contour data and the second coordinate data of the preset reference points in the target contour data, the surface contour data is mapped to the set coordinate system of the target contour data to obtain the mapping relationship between the data points in the surface contour data and the data points in the target contour data.

[0062] After obtaining the mapping relationship between the data points in the surface contour data and the data points in the target contour data, the transformation parameters between the surface contour data and the target contour data are calculated based on this mapping relationship. These transformation parameters can be used to represent the relevant data of the geometric transformations required when fitting the actual graphic of the surface contour data to the designed graphic of the target contour data. For example, the transformation parameters can be represented by a transformation matrix.

[0063] Step S22: Perform data transformation on the surface contour data based on the transformation parameters so that the anchor points of the surface contour data are aligned with the anchor points of the target contour data.

[0064] After obtaining the transformation parameters, a data transformation is performed on one of the surface contour data and the target contour data based on the transformation parameters to align the anchor points of the surface contour data with the anchor points of the target contour data. The data transformation includes, but is not limited to, geometric transformations such as translation, rotation, and scaling. The anchor points can be, but are not limited to, alignment marks on semiconductor microstructures or wafers, the apex corner of chip boundaries, the center point of repeating units, or at least one of the following:

[0065] Step S23: Calculate the deviation between the aligned surface contour data and the target contour data to obtain process error data.

[0066] In one approach, after aligning the anchor points of the surface profile data with the anchor points of the target profile data, process error data can be obtained by, but is not limited to, directly calculating the distance between the edge coordinates of the surface profile data and the edge coordinates of the target profile data, or calculating the distance between the key feature coordinates of the surface profile data and the key feature coordinates of the target profile data. The aforementioned distances include, but are not limited to, at least one of Euclidean distance, Manhattan distance, Chebyshev distance, Hausdorff distance, and Mahalanobis distance. In another approach, process error data can also be obtained by measuring and analyzing the overall deviation of the semiconductor microstructure by calculating the overlap area between the actual surface profile data and the designed target profile data, as well as image grayscale differences.

[0067] In a possible implementation, steps S21-S23 above can be integrated into an error quantization model. For example, this error quantization model could be a data model specifically designed for identifying and comparing the contours of semiconductor microstructures, trained using datasets from semiconductor design and manufacturing. Alternatively, at least one of steps S21-S23 above can also be calculated using an electronic design automation (EDA) platform, without specific limitations.

[0068] Therefore, by calculating the transformation parameters between surface contour data and target contour data based on the mapping relationship between data points in surface contour data and data points in target contour data, and performing data transformation on surface contour data based on the transformation parameters to align the anchor points of surface contour data with the anchor points of target contour data, and calculating the deviation between the aligned surface contour data and target contour data to obtain process error data, the surface contour data and target contour data can be accurately aligned in the same coordinate system and error can be measured. This is beneficial to further improve the accuracy of graphic transfer accuracy evaluation and improve the reliability of graphic transfer accuracy evaluation.

[0069] In some embodiments, the semiconductor microstructure includes a semiconductor device structure formed on a substrate by a semiconductor process, or the semiconductor microstructure includes a semiconductor device structure formed on a substrate by a semiconductor process and a mask pattern of the semiconductor device structure.

[0070] Specifically, in one embodiment, the evaluation method described above can be used to evaluate the pattern transfer accuracy of a semiconductor device structure formed during a semiconductor process. The semiconductor device structure is the actual device unit obtained by forming a pattern on a substrate through a semiconductor process. The semiconductor device structure includes, but is not limited to, at least one of the following: transistor gate, source / drain regions, interconnect structures, isolation structures, and contact holes.

[0071] In another embodiment, the evaluation method described above can be used to evaluate the pattern transfer accuracy of a semiconductor device structure and its mask layout formed during a semiconductor process. For example, this evaluation method can scan the semiconductor device structure after the semiconductor process to obtain surface contour data, and then use this surface contour data to obtain process error data and feedback data for the semiconductor device structure under the current semiconductor process. Alternatively, the evaluation method can also scan the mask layout used in the semiconductor process to obtain surface contour data, and then use this surface contour data to obtain process error data and feedback data for the semiconductor device structure during the current masking process. Here, the aforementioned mask layout specifically refers to a pattern device used as a mask in a photolithography process. By comparing the surface contour data of the mask layout with the target contour data of its design layout, the matching between the mask design and the actual manufacturing result can be verified, thereby quantifying the pattern transfer accuracy of the manufactured semiconductor device structure.

[0072] Optionally, step S1 above further includes the following steps: selecting a semiconductor device structure processed by semiconductor technology from the semiconductor manufacturing system according to a preset selection rule; scanning the semiconductor device structure to obtain surface contour data.

[0073] Specifically, a semiconductor manufacturing system may include a production device for processing wafers using semiconductor processes. This production device may process the wafers using, but is not limited to, semiconductor processes such as etching and photolithography. The evaluation method in this embodiment can scan the corresponding processed semiconductor device structure from the semiconductor manufacturing system according to preset selection rules to obtain the surface contour data of the semiconductor device structure. This surface contour data is then used to evaluate and analyze the pattern transfer accuracy of the processed semiconductor device structure. This ensures that the evaluation results accurately reflect the production errors of the semiconductor process, facilitating subsequent location of the root cause of the fault in the production process based on process error data and / or feedback data. This enables a quantitative evaluation of circuit performance changes caused by pattern distortion, further improving yield control in the semiconductor manufacturing process.

[0074] This application also proposes an evaluation device for graphics transfer accuracy, please refer to [link to relevant documentation]. Figure 8 , Figure 8 This is a schematic diagram of an embodiment of the graphic transfer accuracy evaluation device provided in this application. Figure 8 As shown, the evaluation device 10 includes a scanning module 11 and an analysis module 12.

[0075] The scanning module 11 is configured to receive the semiconductor microstructure and scan it to obtain surface contour data of the semiconductor microstructure. The analysis module 12 is connected to the scanning module 11 and is configured to compare the surface contour data with the target contour data of the semiconductor microstructure to obtain process error data of the semiconductor microstructure, and generate feedback data of pattern transfer of the semiconductor microstructure based on the process error data.

[0076] In some embodiments, the analysis module 12 can be used to obtain edge error data of the semiconductor microstructure by comparing the contour edge data with the target edge data through the acquisition of target edge data of the design layout of the semiconductor microstructure.

[0077] In some embodiments, the analysis module 12 can be used to obtain critical structure size data of the semiconductor microstructure by comparing the target size data with the target size data of the critical structure in the design layout of the semiconductor microstructure.

[0078] In some embodiments, the analysis module 12 can be used to extract correction data of semiconductor microstructures from process error data, and perform electrical performance simulation analysis based on the correction data to obtain performance impact data on the pattern transfer accuracy of semiconductor microstructures.

[0079] In some embodiments, the analysis module 12 can be used to output risk assessment data on the pattern transfer accuracy of semiconductor microstructures based on process error data and / or performance impact data.

[0080] In some embodiments, the analysis module 12 can be used to generate an evaluation report of the semiconductor microstructure based on process error data, performance impact data, and risk assessment data.

[0081] This application also proposes a semiconductor manufacturing system; please refer to [link to relevant documentation]. Figure 9 , Figure 9 This is a schematic diagram of an embodiment of the semiconductor manufacturing system provided in this application. Figure 9 As shown, the semiconductor manufacturing system 1 includes a processing apparatus 20 and an evaluation apparatus 10 as described in any of the above embodiments. The processing apparatus 20 is configured to process a wafer to obtain a semiconductor microstructure. The evaluation apparatus 10 is configured to scan and analyze the semiconductor microstructure to obtain feedback data on the pattern transfer of the semiconductor microstructure.

[0082] Specifically, the processing apparatus 20 is any production processing apparatus 20 in the semiconductor manufacturing process. For example, the processing apparatus 20 can be used to pattern a wafer to form a preset pattern and obtain a semiconductor microstructure. For example, the processing apparatus 20 includes, but is not limited to, devices used for pattern processing such as lithography machines and etching machines. During operation, after the processing apparatus 20 processes the wafer to obtain the semiconductor microstructure, the processed semiconductor microstructure is further scanned by the evaluation apparatus 10 to evaluate the pattern transfer accuracy of the semiconductor microstructure during processing using the scanned surface contour data. The evaluation apparatus 10 can be configured to scan and evaluate each processed semiconductor microstructure, or the semiconductor manufacturing system 1 can select semiconductor microstructures in the manufacturing process using preset selection rules, so that the evaluation apparatus 10 scans and evaluates the selected semiconductor microstructures.

[0083] Therefore, by scanning the processed semiconductor microstructure output by the evaluation device 10, the pattern transfer accuracy of the semiconductor microstructure in the actual production environment can be accurately evaluated. This allows the evaluation results to truly reflect the production line status, facilitating the subsequent location of the root cause of the fault to the position correction in the production process based on process error data and / or feedback data. This enables a quantitative evaluation of the circuit performance changes caused by pattern distortion, further improving the yield control of the semiconductor manufacturing process.

[0084] In some embodiments, the processing apparatus 20 is configured to perform photolithography or etching on a wafer to obtain a semiconductor microstructure, and the evaluation apparatus 10 is configured to obtain feedback data of the semiconductor microstructure.

[0085] Specifically, in one embodiment, after the processing apparatus 20 is configured to perform photolithography on the wafer, the evaluation apparatus 10 can scan and analyze the pattern of the semiconductor microstructure exposed after photolithography to obtain process error data and feedback data of the semiconductor microstructure. Therefore, users can easily adjust the Optical Proximity Correction (OPC) model of the processing apparatus 20 during photolithography using the process error data and feedback data. This allows the adjusted OPC model to further compensate for the distortion between the designed pattern and the actual pattern, reducing errors in pattern manufacturing during subsequent processing and minimizing the impact of pattern distortion on circuit performance, thereby further improving the yield control of the semiconductor manufacturing process.

[0086] In another approach, after the processing apparatus 20 is configured to etch the wafer, the evaluation apparatus 10 can evaluate and analyze the actual pattern formed on the surface of the semiconductor microstructure after etching to obtain process error data and feedback data of the semiconductor microstructure. Therefore, users can accurately evaluate the precision of the processing apparatus 20 during etching using process error data and feedback data, thereby achieving a quantitative assessment of circuit performance changes caused by pattern distortion, reducing errors in pattern manufacturing during subsequent processing, minimizing the impact of pattern distortion on circuit performance, and further improving yield control in the semiconductor manufacturing process.

[0087] In some embodiments, the processing apparatus 20 is configured to process a wafer to obtain a semiconductor microstructure including at least a device layer and an interconnect layer, and the evaluation apparatus 10 is configured to obtain feedback data of the semiconductor microstructure.

[0088] Specifically, the processing apparatus 20 is configured to process at least a device layer and an interconnect layer on the wafer to obtain a semiconductor microstructure including the device layer and the interconnect layer. The device layer and the interconnect layer form patterns on the surface of the semiconductor microstructure, and the evaluation apparatus 10 is configured to scan and analyze the semiconductor microstructure with the device layer and the interconnect layer to evaluate the manufacturing accuracy and error of the surface pattern of the semiconductor microstructure, thereby achieving a quantitative evaluation of the circuit performance changes caused by pattern distortion, and further improving the yield control of the semiconductor manufacturing process.

[0089] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A method for evaluating the accuracy of graphic transfer, characterized in that, include: The semiconductor microstructure to be evaluated is scanned to obtain surface profile data of the semiconductor microstructure. The surface contour data is compared with the target contour data of the semiconductor microstructure to obtain the process error data of the semiconductor microstructure. Feedback data on the pattern transfer accuracy of the semiconductor microstructure is generated based on the process error data.

2. The evaluation method according to claim 1, characterized in that, The surface contour data includes the contour edge data of the semiconductor microstructure; The step of comparing the surface contour data with the target contour data of the semiconductor microstructure to obtain the process error data of the semiconductor microstructure includes: Obtain the target edge data of the design layout of the semiconductor microstructure; The contour edge data is compared with the target edge data to obtain the edge error data of the semiconductor microstructure.

3. The evaluation method according to claim 1, characterized in that, The surface profile data includes key structural dimension data of the semiconductor microstructure; The step of comparing the surface contour data with the target contour data of the semiconductor microstructure to obtain the process error data of the semiconductor microstructure includes: Obtain the target size data of key structures in the design layout of the semiconductor microstructure; The key structural dimension data is compared with the target dimension data to obtain the key dimension error data of the semiconductor microstructure.

4. The evaluation method according to claim 1, characterized in that, The feedback data includes performance impact data; the feedback data for generating the pattern transfer accuracy of the semiconductor microstructure based on the process error data includes: Extract correction data for the semiconductor microstructure from the process error data; Based on the corrected data, electrical performance simulation analysis is performed to obtain performance impact data on the pattern transfer accuracy of the semiconductor microstructure.

5. The evaluation method according to claim 4, characterized in that, The feedback data also includes risk assessment data; After the step of performing electrical performance simulation analysis based on the corrected data to obtain performance impact data on the pattern transfer accuracy of the semiconductor microstructure, the evaluation method further includes: Based on the process error data and / or the performance impact data, output risk assessment data for the pattern transfer accuracy of the semiconductor microstructure.

6. The evaluation method according to claim 5, characterized in that, After the step of generating feedback data on the pattern transfer accuracy of the semiconductor microstructure based on the process error data, the evaluation method further includes: An evaluation report for the semiconductor microstructure is generated based on the process error data, the performance impact data, and the risk assessment data.

7. The evaluation method according to claim 1, characterized in that, The step of comparing the surface contour data with the target contour data of the semiconductor microstructure to obtain the process error data of the semiconductor microstructure includes: Based on the mapping relationship between the data points in the surface contour data and the data points in the target contour data, the transformation parameters between the surface contour data and the target contour data are calculated; The surface contour data is transformed based on the transformation parameters so that the anchor points of the surface contour data are aligned with the anchor points of the target contour data. The deviation between the aligned surface contour data and the target contour data is calculated to obtain the process error data.

8. The evaluation method according to any one of claims 1-7, characterized in that, The semiconductor microstructure includes a semiconductor device structure formed on a substrate using semiconductor processes, or... The semiconductor microstructure includes a semiconductor device structure formed on a substrate by semiconductor processes and a mask pattern of the semiconductor device structure.

9. The evaluation method according to claim 8, characterized in that, The scanning of the semiconductor microstructure to be evaluated to obtain surface profile data of the semiconductor microstructure includes: The semiconductor device structure processed by the semiconductor process is selected from the semiconductor manufacturing system according to the preset selection rules; The semiconductor device structure is scanned to obtain the surface profile data.

10. A device for evaluating the accuracy of graphic transfer, characterized in that, include: The scanning module is configured to receive a semiconductor microstructure and scan the semiconductor microstructure to obtain surface contour data of the semiconductor microstructure. An analysis module, connected to the scanning module, is configured to compare the surface contour data with the target contour data of the semiconductor microstructure to obtain process error data of the semiconductor microstructure, and generate feedback data for pattern transfer of the semiconductor microstructure based on the process error data.

11. A semiconductor manufacturing system, characterized in that, include: The processing apparatus is configured to process wafers to obtain semiconductor microstructures; The pattern transfer accuracy evaluation apparatus as described in claim 10 is configured to scan and analyze the semiconductor microstructure to obtain feedback data on the pattern transfer of the semiconductor microstructure.

12. The semiconductor manufacturing system according to claim 11, characterized in that, The processing apparatus is configured to perform photolithography or etching on the wafer to obtain the semiconductor microstructure, and the evaluation apparatus is configured to obtain feedback data of the semiconductor microstructure; and / or The processing apparatus is configured to process the wafer to obtain a semiconductor microstructure including at least a device layer and an interconnect layer, and the evaluation apparatus is configured to obtain feedback data of the semiconductor microstructure.

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