A method for fabricating a semiconductor device

Abstract

This invention provides a method for fabricating a semiconductor device. Before forming a first conductivity type device region well region and a second conductivity type device region well region, a hard mask layer is first formed. During the steps of forming the first conductivity type device region well region and the second conductivity type device region well region, an opening is formed in the hard mask layer. Then, the medium voltage device region is etched using the hard mask layer as a barrier layer. This eliminates the need for a mask to be etched back into the gate dielectric layer of the medium voltage device region, reduces the number of mask layers, and lowers costs.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology and relates to a method for manufacturing a semiconductor device. Background Technology

[0002] High dielectric constant metal gate (HKMG) technology is an advanced semiconductor fabrication technique used to improve the performance and reliability of integrated circuits.

[0003] like Figure 1 The diagram shows a schematic of an embedded high-voltage HKMG device, including a low-voltage region 010, a medium-voltage region 011, and a high-voltage region 012. The high-voltage region 012 and the medium-voltage region 011 use a thicker gate dielectric layer 013 compared to the low-voltage region 010. To improve process compatibility, the medium-voltage region 011 and the high-voltage region 012 require active area etch-back to achieve a balance in the metal gate 014 height between the high-voltage region 012, the medium-voltage region 011, and the low-voltage region 010 during the metal gate chemical mechanical polishing (MG CMP) process. In existing technologies, the high-voltage and medium-voltage gate dielectric layers of embedded high-voltage HKMG devices require the use of masks to define their positions and undergo etch-back processes, resulting in a large number of mask layers, higher costs, and hindering the device's competitiveness.

[0004] Therefore, how to provide a method for fabricating semiconductor devices to reduce the number of mask layers and lower costs has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method for manufacturing semiconductor devices to solve the problems of high mask layer count and high cost in the prior art.

[0006] To achieve the above and other related objectives, the present invention provides a method for fabricating a semiconductor device, comprising the following steps:

[0007] S1: A semiconductor substrate is provided, wherein a sacrificial layer is formed on the upper surface of the semiconductor substrate, wherein the semiconductor substrate is divided into a first voltage device region, a second voltage device region and a third voltage device region, and the second voltage device region includes a first conductivity type device region and a second conductivity type device region;

[0008] S2: A hard mask layer is formed on the sacrificial layer, a first photoresist layer is formed on the hard mask layer, and the first photoresist layer is patterned using a first mask to form a first opening, the first opening exposing the hard mask layer located above the first conductivity type device region;

[0009] S3: Based on the patterned first photoresist layer, the hard mask layer is etched to form a second opening, and ion implantation is performed on the first conductivity type device region based on the second opening to form a first conductivity type device region well region.

[0010] S4: A second photoresist layer is formed on the hard mask layer, and the second photoresist layer is patterned using a second mask to form a third opening, the third opening exposing the hard mask layer located above the second conductivity type device region;

[0011] S5: Based on the patterned second photoresist layer, the hard mask layer is etched to form a fourth opening, and ion implantation is performed on the second conductivity type device region based on the fourth opening to form a second conductivity type device region well region.

[0012] S6: Using the hard mask layer that forms the second opening and the fourth opening as a mask, etch away the sacrificial layer located above the second voltage device region, and etch the second voltage device region to a predetermined depth to form a second voltage device region groove.

[0013] S7: A second voltage device region gate dielectric layer is formed in the second voltage device region groove.

[0014] Optionally, the sacrificial layer is made of silicon oxide, and the hard mask layer is made of silicon nitride.

[0015] Optionally, during the etching of the hard mask layer to form the second opening, the sacrificial layer is used as the etching stop layer; during the etching of the hard mask layer to form the fourth opening, the sacrificial layer is used as the etching stop layer.

[0016] Optionally, in step S6, the sacrificial layer located above the second voltage device region is removed using a wet etching method.

[0017] Optionally, the etching solution used in the wet etching method includes an HF solution.

[0018] Optionally, before forming the hard mask layer, the method further includes the step of forming a third voltage device region gate dielectric layer in the third voltage device region.

[0019] Optionally, the thickness of the gate dielectric layer in the second voltage device region is less than the thickness of the gate dielectric layer in the third voltage device region.

[0020] Optionally, the first conductivity type device region is an N-type device region and the second conductivity type device region is a P-type device region; or the first conductivity type device region is a P-type device region and the second conductivity type device region is an N-type device region.

[0021] Optionally, in step S6, after forming the second voltage device region groove, a hard mask layer of a predetermined thickness remains on the semiconductor substrate; in step S7, the remaining hard mask layer is removed first, and then the second voltage device region gate dielectric layer is formed.

[0022] Optionally, the remaining hard mask layer can be removed using a wet etching method.

[0023] As described above, in the semiconductor device fabrication method of the present invention, a hard mask layer is formed before forming the first conductivity type device region well region and the second conductivity type device region well region. During the step of forming the first conductivity type device region well region and the second conductivity type device region well region, an opening is formed in the hard mask layer. Then, the medium voltage device region is etched using the hard mask layer as a barrier layer. This eliminates the need for a mask to be etched back into the gate dielectric layer of the medium voltage device region, reduces the number of mask layers, and lowers the cost. Attached Figure Description

[0024] Figure 1 The diagram shown is of an embedded high-voltage HKMG device.

[0025] Figure 2 The diagram shows a process where, after forming the high-voltage gate dielectric layer, a first mask is used to define the medium-voltage N-type device well region and ion implantation is performed.

[0026] Figure 3 This diagram illustrates the process of defining a medium-pressure region P-type device well region using a second mask after forming an N-type device well region, followed by ion implantation.

[0027] Figure 4 This diagram illustrates the location of the gate dielectric layer in the medium-voltage region after the formation of the P-type device well region, defined using a third mask.

[0028] Figure 5 This diagram illustrates the etch-back of the active region of the gate dielectric layer in the medium-voltage region.

[0029] Figure 6 The diagram shown is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention.

[0030] Figure 7 The diagram shown is a schematic representation of a semiconductor substrate provided in an embodiment of the present invention.

[0031] Figure 8 The diagram shown is a schematic of a hard mask layer and a first photoresist layer formed on a sacrificial layer in an embodiment of the present invention, and the first photoresist layer is graphically illustrated.

[0032] Figure 9 This diagram illustrates the etching of a hard mask layer and the implantation of a first conductivity type device well region in an embodiment of the present invention.

[0033] Figure 10 The diagram shown is a schematic representation of the formation of a second photoresist layer in an embodiment of the present invention.

[0034] Figure 11 This diagram illustrates the etching of a hard mask layer and the implantation of a second conductivity type device well region in an embodiment of the present invention.

[0035] Figure 12 The diagram shown is a schematic diagram of removing the second photoresist layer in an embodiment of the present invention.

[0036] Figure 13 This is a schematic diagram showing the etching of a second voltage device region groove in a semiconductor substrate according to an embodiment of the present invention.

[0037] Figure 14 This is a schematic diagram showing the formation of the gate dielectric layer of the second voltage device region in an embodiment of the present invention.

[0038] Component designation explanation

[0039] 01 Semiconductor substrate

[0040] 010 Low-pressure area

[0041] 011 Medium Pressure Area

[0042] 012 High-voltage area

[0043] 013 Gate dielectric layer

[0044] 014 Metal grid

[0045] 02 High-voltage region grid dielectric layer

[0046] 03 First photoresist layer

[0047] 04 N-type device well region

[0048] 05 Second photoresist layer

[0049] 06 P-type device well region

[0050] 07 Hard Mask Layer

[0051] 08 Third photoresist layer

[0052] 1 Semiconductor substrate

[0053] 100 First Voltage Device Region

[0054] 101 Second Voltage Device Area

[0055] 1010 First conductivity type device region

[0056] 1011 Second conductivity type device region

[0057] 1012 First conductivity type device region well region

[0058] 1013 Second conductivity type device region well region

[0059] 102 Third Voltage Device Area

[0060] 1020 Third Voltage Device Region Gate Dielectric Layer

[0061] 2. Sacrificial Layer

[0062] 3 Shallow trench isolation structure

[0063] 4 Hard mask layer

[0064] 5 First photoresist layer

[0065] 6 First opening

[0066] 7 Second opening

[0067] 8 Second photoresist layer

[0068] 9. Third opening

[0069] 10. Fourth opening

[0070] 11 Second voltage device region groove

[0071] 12 Second voltage device region gate dielectric layer

[0072] Steps S1 to S7 Detailed Implementation

[0073] like Figures 2 to 5 As shown, in the prior art, after forming the high-voltage region gate dielectric layer 02, the process operations performed on the medium-voltage region include:

[0074] (a) such as Figure 2 As shown, a first photoresist layer 03 is formed on a semiconductor substrate 01, and a first mask is used to pattern the first photoresist layer 03 to define the position of the N-type device well region 04 in the medium-voltage region and perform ion implantation.

[0075] (ii) Figure 3 As shown, a second photoresist layer 05 is formed on a semiconductor substrate 01, and a second mask is used to pattern the second photoresist layer 05 to define the position of the P-type device well region 06 in the medium-voltage region and perform ion implantation.

[0076] (III) Figure 4 As shown, a hard mask layer 07 and a third photoresist layer 08 are formed on a semiconductor substrate 01, and the third photoresist layer 08 is patterned using a third mask to define the gate dielectric layer etch-back area in the medium-voltage region.

[0077] (iv) such as Figure 5 As shown, the hard mask layer 07 is etched to form an opening, and the area of ​​the pre-formed medium-voltage gate dielectric layer in the semiconductor substrate 01 is etched back.

[0078] In the prior art, three mask layers are required for well injection and gate dielectric layer etchback in the medium-voltage region. The large number of mask layers results in high device fabrication costs. The purpose of this application is to eliminate the mask layer for gate dielectric layer etchback in the medium-voltage region, thereby reducing the number of mask layers and lowering costs.

[0079] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0080] Please see Figures 6 to 14 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0081] This embodiment provides a method for fabricating a semiconductor device. Please refer to [link / reference]. Figure 6 This includes the following steps:

[0082] S1: A semiconductor substrate is provided, wherein a sacrificial layer is formed on the upper surface of the semiconductor substrate, wherein the semiconductor substrate is divided into a first voltage device region, a second voltage device region and a third voltage device region, and the second voltage device region includes a first conductivity type device region and a second conductivity type device region;

[0083] S2: A hard mask layer is formed on the sacrificial layer, a first photoresist layer is formed on the hard mask layer, and the first photoresist layer is patterned using a first mask to form a first opening, the first opening exposing the hard mask layer located above the first conductivity type device region;

[0084] S3: Based on the patterned first photoresist layer, the hard mask layer is etched to form a second opening, and ion implantation is performed on the first conductivity type device region based on the second opening to form a first conductivity type device region well region.

[0085] S4: A second photoresist layer is formed on the hard mask layer, and the second photoresist layer is patterned using a second mask to form a third opening, the third opening exposing the hard mask layer located above the second conductivity type device region;

[0086] S5: Based on the patterned second photoresist layer, the hard mask layer is etched to form a fourth opening, and ion implantation is performed on the second conductivity type device region based on the fourth opening to form a second conductivity type device region well region.

[0087] S6: Using the hard mask layer that forms the second opening and the fourth opening as a mask, etch away the sacrificial layer located above the second voltage device region, and etch the second voltage device region to a predetermined depth to form a second voltage device region groove.

[0088] S7: A second voltage device region gate dielectric layer is formed in the second voltage device region groove.

[0089] The method for fabricating the semiconductor device of this embodiment will now be described in detail with reference to the accompanying drawings.

[0090] First, please refer to Figure 7 Step S1: Provide a semiconductor substrate 1, wherein a sacrificial layer 2 is formed on the upper surface of the semiconductor substrate 1, wherein the semiconductor substrate 1 is divided into a first voltage device region 100, a second voltage device region 101 and a third voltage device region 102, and the second voltage device region 101 includes a first conductivity type device region 1010 and a second conductivity type device region 1011.

[0091] As an example, the semiconductor substrate 1 can be any suitable semiconductor substrate, such as a silicon (Si) substrate, a germanium (Ge) substrate, a silicon germanide (SiGe) substrate, a gallium arsenide (GaAs) substrate, a silicon carbide (SiC) substrate, a gallium nitride (GaN) substrate, a diamond substrate, or a silicon-on-insulator (SOI) substrate, etc., selected according to requirements; specifically, in this embodiment, the semiconductor substrate 1 is a silicon substrate.

[0092] As an example, the sacrificial layer 2 is a silicon oxide layer, which is formed by thermal oxidation of the upper surface of the semiconductor substrate 1, or by deposition process on the upper surface of the semiconductor substrate 1, depending on the requirements.

[0093] As an example, the semiconductor device in this embodiment is an embedded high-voltage HKMG device, the first voltage device region 100 is a low-voltage device region, the second voltage device region 101 is a medium-voltage device region, and the third voltage device region 102 is a high-voltage device region.

[0094] As an example, in this embodiment, the first conductivity type device area 1010 is an N-type device area, and the second conductivity type device area 1011 is a P-type device area. In another example, the first conductivity type device area 1010 is a P-type device area, and the second conductivity type device area 1011 is an N-type device area, which can be selected according to requirements.

[0095] As an example, the semiconductor substrate 1 is provided with a shallow trench isolation structure 3 (STI) to isolate the first voltage device region 100, the second voltage device region 101, and the third voltage device region 102; and the second voltage device region 101 may also be provided with the shallow trench isolation structure 3 to isolate the first conductivity type device region 1010 and the second conductivity type device region 1011; in addition, the first conductivity type device region 1010 may also be provided with the shallow trench isolation structure 3 to divide the first conductivity type device region 1010 into multiple functional regions, and the second conductivity type device region 1011 may also be provided with the shallow trench isolation structure 3 to divide the second conductivity type device region 1011 into multiple functional regions, which can be selected according to requirements.

[0096] Next, please refer to Figure 8 Step S2: A hard mask layer 4 is formed on the sacrificial layer 2, a first photoresist layer 5 is formed on the hard mask layer 4, and the first photoresist layer 5 is patterned using a first mask to form a first opening 6. The first opening 6 exposes the hard mask layer 4 located above the first conductivity type device region 1010.

[0097] As an example, before forming the hard mask layer 4, the method further includes the step of forming a third voltage device region gate dielectric layer 1020 (high voltage gate dielectric layer) in the third voltage device region 102. Specifically, the semiconductor substrate 1 located in the third voltage device region 102 is etched back to form a third voltage device region groove, and the third voltage device region gate dielectric layer 1020 is formed in the third voltage device region groove.

[0098] As an example, the hard mask layer 4 is formed using physical vapor deposition, chemical vapor deposition, or other suitable methods, and the hard mask layer 4 is made of silicon nitride.

[0099] As an example, the first photoresist layer 5 is formed on the hard mask layer 4 by spin coating, spraying, immersion coating or other suitable methods, and then the first photoresist layer 5 is patterned by exposure, development and other processes to form the first opening 6.

[0100] Next, please refer to Figure 9Step S3: Based on the patterned first photoresist layer 5, the hard mask layer 4 is etched to form a second opening 7, and ion implantation is performed on the first conductive type device region 1010 based on the second opening 7 to form a first conductive type device region well region 1012.

[0101] As an example, the hard mask layer 4 is etched using a dry etching method or a wet etching method to form the second opening 7. During the formation of the second opening 7, the sacrificial layer 2 is used as an etching stop layer to avoid damaging the semiconductor substrate 1.

[0102] As an example, ion implantation is performed using the hard mask layer 4 after the second opening 7 is formed as a mask to form the first conductivity type device region well region 1012. In this embodiment, the first conductivity type device region 1010 is an N-type device region and the first conductivity type device region well region 1012 is a P-well. In another example, when the first conductivity type device region 1010 is a P-type device region, the first conductivity type device region well region 1012 is an N-well, and the selection is made according to the requirements.

[0103] As an example, after forming the first conductivity type device well region 1012, the process also includes removing the first photoresist layer 5 using a process such as ashing.

[0104] Next, please refer to Figure 10 Step S4: A second photoresist layer 8 is formed on the hard mask layer 4, and the second photoresist layer 8 is patterned using a second mask to form a third opening 9, the third opening 9 exposing the hard mask layer 4 located above the second conductivity type device region 1011.

[0105] As an example, the second photoresist layer 8 is formed on the hard mask layer 4 by spin coating, spraying, immersion coating or other suitable methods, and then the second photoresist layer 8 is patterned by exposure, development and other processes to form the third opening 9.

[0106] Next, please refer to Figure 11 Step S5: Based on the patterned second photoresist layer 8, the hard mask layer 4 is etched to form a fourth opening 10. Based on the fourth opening 10, ion implantation is performed on the second conductivity type device region 1011 to form a second conductivity type device region well region 1013.

[0107] As an example, ion implantation is performed using the hard mask layer 4 after the fourth opening 10 is formed as a mask to form the second conductivity type device region well region 1013. In this embodiment, the second conductivity type device region 1011 is a P-type device region and the second conductivity type device region well region 1013 is an N-type well. In another example, when the second conductivity type device region 1011 is an N-type device region, the second conductivity type device region well region 1013 is a P-type well, and the selection is made according to the requirements.

[0108] Next, please refer to Figures 12 to 13 Step S6: Using the hard mask layer 4 that forms the second opening 7 and the fourth opening 10 as a mask, the sacrificial layer 2 located above the second voltage device region 101 is etched away, and the second voltage device region 101 at a preset depth is etched to form the second voltage device region groove 11.

[0109] As an example, such as Figure 12 As shown, after forming the second conductivity type device well region 1013, the second photoresist layer 8 is removed by processes such as ashing.

[0110] As an example, the sacrificial layer 2 located above the second voltage device region 101 is removed by wet etching, and the wet etching solution is an HF solution.

[0111] As an example, during the process of removing the sacrificial layer 2 located above the second voltage device region 101 by the wet etching solution, the boundary morphology between the first conductivity type device region well region 1012 and the second conductivity type device region well region 1013 can be repaired.

[0112] As an example, the sacrificial layer 2 is made of silicon dioxide, and the shallow trench isolation structure 3 is also made of silicon dioxide. When removing the sacrificial layer 2 using a wet etching solution, the amount of wet etching solution used needs to be considered. It is necessary to ensure that the sacrificial layer 2 is completely removed, and also to consider the amount of silicon dioxide loss in the shallow trench isolation structure to control the remaining height of the shallow trench isolation structure 3, so as to avoid the shallow trench isolation structure 3 losing too much silicon dioxide and failing to achieve the isolation effect.

[0113] As an example, after removing the sacrificial layer 2 located above the second voltage device region 101, the second voltage device region 101 is etched back using the hard mask layer 4 as a mask to form the second voltage device region groove 11. After the second voltage device region 101 is etched back, the semiconductor substrate 1 retains the hard mask layer 4 of a predetermined thickness to prevent insufficient thickness of the hard mask layer 4 from damaging the first voltage device region 100 and the third voltage device region 102.

[0114] Next, please refer to Figure 14 Step S7: Form a second voltage device region gate dielectric layer 12 in the second voltage device region groove 11.

[0115] As an example, before forming the second voltage device region gate dielectric layer 12, the method further includes the step of removing the remaining hard mask layer 4, that is, removing the remaining hard mask layer 4 before forming the second voltage device region gate dielectric layer 12.

[0116] As an example, the remaining hard mask layer 12 can be removed using either wet etching or dry etching. Preferably, in this embodiment, the remaining hard mask layer 12 is removed using wet etching to reduce etching damage.

[0117] As an example, since the second voltage device region 101 is a medium-voltage device region and the third voltage device region 102 is a high-voltage device region, the thickness of the gate dielectric layer 12 in the second voltage device region is less than the thickness of the gate dielectric layer 1020 in the third voltage device region.

[0118] In summary, in the semiconductor device fabrication method of the present invention, a hard mask layer is formed before forming the first conductivity type device region well region and the second conductivity type device region well region. During the steps of forming the first conductivity type device region well region and the second conductivity type device region well region, openings are formed in the hard mask layer. Then, the medium-voltage device region is etched using the hard mask layer as a barrier layer. This eliminates the need for a mask to be etched back into the gate dielectric layer of the medium-voltage device region, reducing the number of mask layers and lowering costs. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0119] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a semiconductor device, characterized in that, Includes the following steps: S1: A semiconductor substrate is provided, wherein a sacrificial layer is formed on the upper surface of the semiconductor substrate, wherein the semiconductor substrate is divided into a first voltage device region, a second voltage device region and a third voltage device region, and the second voltage device region includes a first conductivity type device region and a second conductivity type device region; S2: A hard mask layer is formed on the sacrificial layer, a first photoresist layer is formed on the hard mask layer, and the first photoresist layer is patterned using a first mask to form a first opening, the first opening exposing the hard mask layer located above the first conductivity type device region; S3: Based on the patterned first photoresist layer, the hard mask layer is etched to form a second opening, and ion implantation is performed on the first conductivity type device region based on the second opening to form a first conductivity type device region well region. S4: A second photoresist layer is formed on the hard mask layer, and the second photoresist layer is patterned using a second mask to form a third opening, the third opening exposing the hard mask layer located above the second conductivity type device region; S5: Based on the patterned second photoresist layer, the hard mask layer is etched to form a fourth opening, and ion implantation is performed on the second conductivity type device region based on the fourth opening to form a second conductivity type device region well region. S6: Using the hard mask layer that forms the second opening and the fourth opening as a mask, etch away the sacrificial layer located above the second voltage device region, and etch the second voltage device region to a predetermined depth to form a second voltage device region groove. S7: A second voltage device region gate dielectric layer is formed in the second voltage device region groove.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that: The sacrificial layer is made of silicon oxide, and the hard mask layer is made of silicon nitride.

3. The method for fabricating a semiconductor device according to claim 1, characterized in that: During the etching process of the hard mask layer to form the second opening, the sacrificial layer is used as the etching stop layer; During the etching process of the hard mask layer to form the fourth opening, the sacrificial layer is used as the etching stop layer.

4. The method for fabricating a semiconductor device according to claim 1, characterized in that: In step S6, the sacrificial layer located above the second voltage device region is removed using a wet etching method.

5. The method for fabricating a semiconductor device according to claim 4, characterized in that: The etching solution used in the wet etching method includes an HF solution.

6. The method for fabricating a semiconductor device according to claim 1, characterized in that: Before forming the hard mask layer, the method further includes the step of forming a third voltage device region gate dielectric layer in the third voltage device region.

7. The method for fabricating a semiconductor device according to claim 6, characterized in that: The thickness of the gate dielectric layer in the second voltage device region is less than the thickness of the gate dielectric layer in the third voltage device region.

8. The method for fabricating a semiconductor device according to claim 1, characterized in that: The first conductivity type device region is an N-type device region, and the second conductivity type device region is a P-type device region; or the first conductivity type device region is a P-type device region, and the second conductivity type device region is an N-type device region.

9. The method for fabricating a semiconductor device according to claim 1, characterized in that: In step S6, after forming the second voltage device region groove, a hard mask layer of a predetermined thickness remains on the semiconductor substrate; in step S7, the remaining hard mask layer is removed first, and then the gate dielectric layer of the second voltage device region is formed.

10. The method for fabricating a semiconductor device according to claim 9, characterized in that: The remaining hard mask layer is removed using a wet etching method.

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