Ldpc decoder of a ccsds near-earth satellite standard and decoding method thereof

Abstract

The application provides an LDPC decoder of a CCSDS near-earth satellite standard and a decoding method thereof, and relates to the field of wireless communication and signal coding and decoding, wherein the decoder comprises a frame synchronization module, a channel LLR storage module, a control module, a variable node updating module, a check node updating module, a data rearrangement module, an address generation module, a data shift module, a node message storage module and an output module. The application divides the cyclic submatrix of the CCSDS near-earth satellite code group into smaller non-cyclic submatrices, improves the decoding parallelism, stores the node messages of the same cyclic submatrix after block division in the same address of the RAM, and alternately writes the variable node and check node messages into the RAM, thereby saving the storage resources; the check function is realized with low overhead by expanding one bit of the node message to store the decision result; and the error code performance is improved by optimizing the two kinds of node updating modules.

Description

Technical Field

[0001] This application relates to the fields of wireless communication and signal encoding and decoding, and in particular to an LDPC decoder and decoding method for the CCSDS near-Earth satellite standard. Background Technology

[0002] Low-Density Parity-Check (LDPC) codes were first proposed by R. Gallager in his doctoral dissertation in 1961. LDPC codes have been proven to be a class of forward error-correcting codes that approximate the Shannon limit, possessing excellent error-correcting performance and parallel computing capabilities, making them suitable for hardware implementation.

[0003] The Consultative Committee for Space Data Systems (CCSDS) is the leading international organization for developing space communication standards. In its near-Earth space communication standards, CCSDS recommends 7 / 8 rate LDPC codes as the channel coding scheme. The core code types of this standard include constant-length codes (8176, 7154). These LDPC codes feature a low error rate plateau and fast decoding convergence, making them highly suitable for space communication applications.

[0004] The LDPC code used in the CCSDS standard has a quasi-cyclic (QC) structure, and its parity check matrix is ​​composed of cyclic submatrices. Taking the (8176, 7154) code as an example, the parity check part of the generator matrix consists of 28 511×511 cyclic submatrices.

[0005] Existing LDPC decoders for near-Earth satellite communication have the following drawbacks: Parallelism issue: Traditional code group decoders divide parallelism according to the cyclic submatrix, resulting in low parallelism and high storage overhead.

[0006] Design of the verification unit: The logic of implementing the verification unit in traditional decoders is complex and consumes a lot of hardware resources.

[0007] Error rate performance: Low quantization bit width leads to a significant performance degradation. Summary of the Invention

[0008] The purpose of this invention is to address the technical shortcomings of existing CCSDS near-Earth satellite standard LDPC decoders, such as low parallelism, high storage resource consumption, complex verification logic, and limited throughput, by providing a CCSDS near-Earth satellite standard LDPC decoder and its decoding method.

[0009] The above-mentioned objective of this application is achieved through the following technical solution: The frame synchronization module, channel LLR storage module, variable node update module, and check node update module are connected in sequence; the output module is connected to the variable node update module. The address generation module, node message storage module, data shifting module, and data rearrangement module are connected in sequence. The frame synchronization module, channel LLR storage module, variable node update module, check node update module, address generation module, node message storage module, data shifting module, and data rearrangement module are all connected to the control module; Frame synchronization module: used to receive the initial log-likelihood ratio of CCSDS near-Earth satellite code group signals and identify the frame header; Channel LLR storage module: Stores the initial log-likelihood ratio after frame synchronization; Node message storage module: used to store intermediate messages generated by the variable node update module and the verification node update module during the decoding process; Data rearrangement module: Sorts intermediate messages read from or written to the node message storage module according to their current state; Variable node update module: Receives data from the data rearrangement module, updates variable messages, makes a judgment to obtain a judgment result, and stores the judgment result in an extended bit; Verification node update module: Receives data from the data rearrangement module, updates the verification messages, extracts the highest bit of each message for verification, and outputs the verification node information; Address generation module: Used to generate addresses for reading messages from different node storage modules; Data shifting module: used to correct address misalignment at the boundaries of non-cyclic submatrices; Control module: Used to generate control signals for each module and read / write addresses for each random access memory; Output module: Stores the decision results of the variable node update module and outputs the decision results when in the output state.

[0010] Optionally, the LDPC decoder includes: The cyclic submatrix in the parity check matrix of the CCSDS near-Earth satellite code group is further divided into smaller acyclic submatrixes.

[0011] Optionally, the LDPC decoder includes: The cyclic submatrix of the CCSDS near-Earth satellite code group's check matrix is ​​511-dimensional, and it is split into 7 non-cyclic submatrixes of 73 dimensions according to adjacent columns. The intermediate messages of the seven acyclic submatrices are stored in the same address of the same random access memory, and the check node information and intermediate messages are alternately stored in the same random access memory. The CCSDS near-Earth satellite code group consists of 2×16 cyclic submatrices with a column weight of 2. If the quantization bit width is Q, then the node message storage module contains 64 random access memories with a bit width of 7×(Q+1) and a depth of 73.

[0012] Optionally, the LDPC decoder includes: The verification function is achieved by extending the intermediate message by one bit to store the judgment result; the quantization bit width is selected as Q bits, the intermediate message bit width is extended by one bit to Q+1 bits, the highest bit is assigned the judgment result in the variable node update module, and the highest bit is extracted in the verification node update module to realize single-line verification.

[0013] Optionally, the output of the variable node update module is equipped with a limiter to limit the data after the variable node update calculation; the limiter restricts the output of the adder to a preset dynamic range. The variable node update module includes 112 variable node update sub-modules. The variable node update sub-modules use a 5-stage pipeline for update calculation. The adder uses a two-stage pipeline. The second-stage pipeline adds the input data pairwise, and the third-stage pipeline adds the results of the pairwise additions again. After the addition is completed, a limiter is used to limit the addition result. The data at the current position is subtracted from the limited result to obtain the subtractor output. In the fifth-stage pipeline, the decision result is assigned to the extended highest bit of each subtractor output. The correction factor set in the verification node update module is 0.75, which is achieved by adding the data to the left by shifting it one bit and then shifting it to the right by two bits. The verification node update module includes 14 verification node update sub-modules; the verification node update sub-modules use a 13-level pipeline to update messages.

[0014] Optionally, the verification node update module is equipped with a comparator tree structure to obtain the minimum value, the second smallest value, and the minimum value index among the 32 input data. The comparator tree contains a total of 8 pipelines, each of which is a pipeline level. The 6th pipeline obtains the minimum value and the minimum value index, and the 8th pipeline obtains the second smallest value.

[0015] Optionally, the LDPC decoder adopts a pipelined frame architecture, and the channel LLR storage module contains 112 random access memories with a depth of 146, which are used to store two frames of data simultaneously. During the decoding process, the log-likelihood ratio of the received signal is stored and the decision result is output simultaneously.

[0016] A high-parallelism, low-storage-overhead LDPC decoding method for the CCSDS near-Earth satellite standard, the method comprising: S1: The decoder is in a waiting frame synchronization state. After recognizing the frame header, it proceeds to step S2. S2: The decoder is in the initial message receiving state. It writes the 8176 data output after frame synchronization into the memory in address order. After one memory cell is filled with 73 data, it writes into the next memory cell. S3: The decoder is in the message initialization state, performs node message initialization, and writes the initialized node messages into the memory; S4: The decoder is in the check node update state. It reads the node message from the memory, and obtains the variable node message at the correct position through address processing, data shifting and data rearrangement. It updates the check node message and writes the updated message back to the memory. At the same time, it checks the decision result of the previous round. Each submatrix has a total of 73 rows and a row parallelism of 14. It checks 14 rows at the same time. If the check module of each submatrix has successfully checked all 73 rows, it indicates that the decision result is correct. Then it jumps to step S6. Otherwise, it enters step S5 to continue the iteration. S5: The decoder is in the variable node update state. It reads the node message from the memory, obtains the check node message at the correct position through data shifting and data rearrangement, updates the variable node message, makes a judgment on the decision result, merges the decision result with the variable node message and writes it back to the memory, and determines whether the maximum number of iterations has been reached. If it has, proceed to step S6; otherwise, jump to step S4 and increment the number of iterations by one. S6: The decoder returns to the waiting frame header state, the output flag is pulled high, indicating that there is data to be output; the decision results at the 73-second interval during writing are read out sequentially. The beneficial effects of the technical solution provided in this application are: 1. The CCSDS near-Earth satellite codeword decoder designed in this invention improves the parallelism of the decoder by further dividing the cyclic submatrix into smaller acyclic submatrixes. The node messages of the seven submatrixes are stored in the same address in RAM, and the check node information and variable node information are alternately stored in the same RAM, greatly saving storage resources and improving throughput.

[0017] 2. The CCSDS near-Earth satellite codeword decoder designed in this invention utilizes the addressing logic for obtaining variable node information in the verification node update module by extending the node message by one bit to store the decision result. This eliminates the need for additional addressing logic and storage units, does not affect timing, and achieves the verification function with low overhead. Adding the verification function allows for earlier termination of iterative decoding, improving throughput and reducing power consumption.

[0018] 3. The CCSDS near-Earth satellite codeword decoder designed in this invention employs a decoder design method with less performance loss in bit error rate. By adding a clipping operation to the output of the variable node update module, greater performance gains are achieved with less resource consumption. Furthermore, in the check node update module, a correction method that avoids direct right shifting is used, which can obtain more accurate data when the data is skewed, and implement the correction algorithm with less loss, thereby improving bit error rate performance.

[0019] 4. The CCSDS near-Earth satellite codeword decoder designed in this invention uses a pipelined frame architecture. During the decoding process, the received signal LLR data and decision result output steps can be performed simultaneously, realizing pipelined frames. The decoder does not need to wait for the previous frame's decoding or decision result output to complete before inputting data. In multi-frame decoding, this saves data input and output time and improves throughput.

[0020] In summary, the CCSDS near-Earth satellite codeword decoder designed in this invention achieves a high throughput, high error rate, and low resource consumption LDPC decoder by dividing the cyclic submatrix and storage method, implementing a simplified verification algorithm, optimizing the node message calculation hardware, and adding a pipelined frame architecture. Attached Figure Description

[0021] The present application will be further described below with reference to the accompanying drawings and embodiments. In the accompanying drawings: Figure 1 This is a block diagram of the LDPC decoder implementation provided by the present invention; Figure 2 This is a schematic diagram illustrating the further subdivision of CCSDS near-Earth satellite codewords provided by the present invention; Figure 3 This is a structural block diagram of the variable node update submodule provided by the present invention; Figure 4 This is a structural block diagram of the verification node update submodule provided by the present invention; Figure 5 This is a structural block diagram of the comparator tree in the verification node update submodule provided by the present invention; Figure 6 This is a shortened codeword structure diagram of the CCSDS near-Earth satellite standard provided by the present invention; Figure 7 A comparison chart of the bit error rates of the simulation and hardware implementation of the CCSDS near-Earth satellite standard provided by this invention. Detailed Implementation

[0022] To provide a clearer understanding of the technical features, objectives, and effects of this application, the specific embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0023] Please refer to Figure 1 , Figure 1 This is a block diagram of an LDPC decoder implementation for a CCSDS near-Earth satellite standard, as described in this application, including: The frame synchronization module, channel LLR storage module, variable node update module, and check node update module are connected in sequence; the output module is connected to the variable node update module. The address generation module, node message storage module, data shifting module, and data rearrangement module are connected in sequence. The frame synchronization module, channel LLR storage module, variable node update module, check node update module, address generation module, node message storage module, data shifting module, and data rearrangement module are all connected to the control module; Frame synchronization module: used to receive the initial log-likelihood ratio of CCSDS near-Earth satellite code group signals and identify the frame header; Channel LLR storage module: Stores the initial log-likelihood ratio after frame synchronization; Node message storage module: used to store intermediate messages generated by the variable node update module and the verification node update module during the decoding process; Data rearrangement module: Sorts intermediate messages read from or written to the node message storage module according to their current state; Variable node update module: Receives data from the data rearrangement module, updates variable messages, makes a judgment to obtain a judgment result, and stores the judgment result in an extended bit; Verification node update module: Receives data from the data rearrangement module, updates the verification messages, extracts the highest bit of each message for verification, and outputs the verification node information; Address generation module: Used to generate addresses for reading messages from different node storage modules; Data shifting module: used to correct address misalignment at the boundaries of non-cyclic submatrices; Control module: Used to generate control signals for each module and read / write addresses for each random access memory; Output module: Stores the decision results of the variable node update module and outputs the decision results when in the output state.

[0024] In one embodiment, the control module, used to control the decoder's state, is implemented using a state machine and includes a waiting frame synchronization state, an initial message reception state, a node information initialization state, a check node update state, and a variable node update state. The control module also generates addresses for reading and writing each RAM and control signals for each module. In the initial message reception state, the control module generates the read address for the channel LLR storage module. In the node message initialization state, the control module generates the read / write addresses for the channel LLR storage module and the node message storage module, as well as the enable signal for the variable node update module. In the check node update state, the control module generates the read / write address for the node message storage module, as well as the enable signal for the check node update module, and determines whether the check was successful based on the checksum output by the check node update module. In the variable node update state, the control module generates the read / write addresses for the channel LLR storage module and the node message storage module, as well as the enable signal for the variable node update module, and determines whether the maximum number of iterations has been reached based on the current iteration count. During decoding output, the control module generates read output module address data, ensuring that the output data follows the result order.

[0025] As one embodiment, the data rearrangement module, since the node message module stores data column-wise, can sequentially assign data to each variable node update module when reading and writing variable node messages. When reading and writing verification nodes, the input and output of each verification node need to be reordered to obtain the correct data in the same row.

[0026] As one embodiment, the address generation module generates read and write addresses when reading and writing node message storage modules because the verification node messages and variable node messages are alternately stored in the same RAM block and the node message storage module stores them according to the columns of the verification matrix. When the verification node is updated, the address offset required to read and write different RAM blocks is different.

[0027] In one embodiment, the data shifting module is not needed in the original parallel decoder divided according to the cyclic submatrix. However, since the newly divided submatrix is ​​not quasi-cyclic, the node message module stores the data column-wise, and the update of the variable node message will not be affected. When verifying the update of the node message, after the address exceeds 73 and returns to 0, the position of the node information that needs to be indexed becomes the next non-cyclic submatrix. Therefore, the data shifting module needs to perform data shifting when encountering address boundary problems when verifying the update of the node message to ensure the correct data indexing.

[0028] The LDPC decoder includes: The cyclic submatrix in the parity check matrix of the CCSDS near-Earth satellite code group is further divided into smaller acyclic submatrixes.

[0029] As one example, the cyclic submatrix is ​​further divided into smaller non-cyclic submatrices to improve the parallelism of the decoder.

[0030] The LDPC decoder includes: The cyclic submatrix of the CCSDS near-Earth satellite code group's parity check matrix is ​​511-dimensional. It is split into 7 non-cyclic submatrixes of 73 dimensions according to adjacent columns, which increases the parallelism by 7 times. The intermediate messages of the seven acyclic submatrices are stored in the same address of the same random access memory, and the check node information and intermediate messages are alternately stored in the same random access memory. The CCSDS near-Earth satellite code group consists of 2×16 cyclic submatrices with a column weight of 2. If the quantization bit width is Q, then the node message storage module contains 64 random access memories with a bit width of 7×(Q+1) and a depth of 73.

[0031] The LDPC decoder includes: The verification function is achieved by extending the intermediate message by one bit to store the judgment result; the quantization bit width is selected as Q bits, the intermediate message bit width is extended by one bit to Q+1 bits, the highest bit is assigned the judgment result in the variable node update module, and the highest bit is extracted in the verification node update module to realize single-line verification.

[0032] As one embodiment, a method of storing the decision result by extending the node message by one bit achieves low-overhead verification. The quantization bit width is chosen to be Q bits, and the node message bit width is extended by one bit to Q+1 bits. The highest bit is assigned the decision result in the variable node update module, and the highest bit is extracted in the verification node update module to perform single-line verification. Since the decision is made during variable node updates, but the verification is performed row-by-row, this method utilizes the addressing logic for obtaining variable node information in the verification node update module, eliminating the need for additional addressing logic and storage units, and without affecting timing. This method achieves low-overhead verification logic.

[0033] The output of the variable node update module is equipped with a limiter, which is used to limit the data after the variable node update calculation; the limiter restricts the output result of the adder to a preset dynamic range. The variable node update module includes 112 variable node update sub-modules. The variable node update sub-modules use a 5-stage pipeline for update calculation. The adder uses a two-stage pipeline. The second-stage pipeline adds the input data pairwise, and the third-stage pipeline adds the results of the pairwise additions again. After the addition is completed, a limiter is used to limit the addition result. The data at the current position is subtracted from the limited result to obtain the subtractor output. In the fifth-stage pipeline, the decision result is assigned to the extended highest bit of each subtractor output. The correction factor set in the verification node update module is 0.75, which is achieved by adding the data to the left by shifting it one bit and then shifting it to the right by two bits. The verification node update module includes 14 verification node update sub-modules; the verification node update sub-modules use a 13-level pipeline to update messages.

[0034] As one embodiment, the variable node update module of the present invention has some improvements compared to traditional decoders. After partitioning the cyclic submatrix, as shown... Figure 2 As shown, the column parallelism is 112, and 112 variable node update submodules are instantiated. The specific implementation of the variable node update submodule is as follows. Figure 3 As shown, a 5-stage pipeline is used. Since the node message is extended by one bit to store the decision result, it is first truncated and then converted to a signed number. The adder uses a two-stage pipeline: the second stage adds pairs of data, and the third stage adds the sums, increasing the clock frequency. For high-parallelism decoders, increasing the quantization bit width leads to a rapid increase in resource consumption, while decreasing the bit width can cause data overflow during addition, especially in variable node updates where five data points need to be added. Overflow can cause the sign bit to flip, leading to incorrect decision results and a significant decrease in bit error rate performance. Therefore, in the variable node update submodule of this invention, a limiter is used to limit the bit width after addition, achieving bit error rate performance essentially consistent with fixed-point quantization in the simulation program. In the subtractor, the output is the adder result minus the data at the current position. In the 5th stage pipeline, the decision result is assigned to the extended highest bit of each subtractor output.

[0035] As one embodiment, the check node update module in this invention has some improvements compared to traditional decoders. After partitioning the cyclic submatrix, as shown... Figure 2 With a line parallelism of 14, 14 check node update submodules were instantiated. Each check node update submodule uses the following... Figure 4 The structure uses a 13-stage pipeline for message updates. This invention uses a bit extension on the high-order bits of the node message (the intermediate message generated by the variable node update module) to store the decision result of the variable node update module, which is then verified by the verification node update module. Therefore, a verification module is innovatively added to the verification node update module, implemented using 32 single-bit XOR logic, which is simple and consumes few resources. Furthermore, in the module for obtaining the minimum, second-smallest, and minimum value index among the 32 input data, a comparator tree is used, with the specific structure as follows... Figure 5As shown, each layer is a pipeline, with a total of 8 pipeline stages. This approach allows for higher operating clock speeds. The minimum value and its index are obtained in the 6th pipeline stage, and the second smallest value is obtained in the 8th pipeline stage; other data is discarded. In the correction calculation module, if the output position is the minimum value position, the second smallest value is used as input for correction; otherwise, the minimum value is used as input. This invention uses a corrected minimum sum algorithm with a correction factor of 0.75. Instead of simply shifting the data one bit to the left and adding the results to the right by two bits, this method provides more accurate data when the data is skewed, achieving a correction algorithm with less loss. Finally, the two's complement is calculated using the registered sign bit and absolute value data, and then output.

[0036] As one example, since the column weight of CCSDS near-Earth satellite codewords is 4, the variable nodes implement the addition of the initial data of the four variable nodes and their corresponding columns. Typically, decoders set the quantization bit depth relatively small to minimize resource consumption, which can lead to data overflow during data addition and cause errors in the decision result. By adding a limiting operation to the output of the variable node update module, greater performance gains are achieved with less resource consumption. Furthermore, in the check node update module, the correction factor is set to 0.75. Instead of shifting the data one bit to the left and then shifting it two bits to the right, this method provides more accurate data when the data is skewed, achieving the correction algorithm with less loss.

[0037] As one embodiment, since the column weight of the CCSDS near-Earth satellite code group is all 4, a variable node update submodule is designed with four check node message inputs and one channel initialization LLR value input. The four variable node messages are calculated and decided according to the variable node update formula. The intermediate variables are also designed to limit the amplitude to prevent data errors caused by exceeding the bit width. Then the decision result is assigned to the highest bit of the variable node message and the decision result is written to the output module.

[0038] The verification node update module is equipped with a comparator tree structure, which is used to obtain the minimum value, the second smallest value, and the minimum value index among 32 input data. The comparator tree contains a total of 8 pipelines, each of which is a pipeline level. The 6th pipeline obtains the minimum value and the minimum value index, and the 8th pipeline obtains the second smallest value.

[0039] As one example, since the row weight of the CCSDS near-Earth satellite code group is all 32, 32 variable node message inputs are designed. A pipelined comparator tree is used to obtain the minimum value, the second smallest value, and the position of the minimum value. The check node message is updated and calculated according to the check node, and its highest bit is extracted for the check of this check node.

[0040] The LDPC decoder adopts a pipelined frame architecture. The channel LLR storage module contains 112 random access memories with a depth of 146, which are used to store two frames of data simultaneously. During the decoding process, the log-likelihood ratio of the received signal is stored and the decision result is output simultaneously.

[0041] As one embodiment, the channel LLR storage module receives data from the frame synchronization module and stores it sequentially into a total of 112 RAMs with a depth of 146, which can store two frames simultaneously and realize pipelined frame decoding.

[0042] As one embodiment, the CCSDS codewords used in this invention include: There are 64 RAMs in total, each requiring two RAMs for storage. The first 32 RAMs store the data for the first row of the cyclic submatrix, and the last 32 RAMs store the data for the second row. As shown in Figure 2, corresponding to the 32 cyclic submatrixes, during the check node message update, the data rearrangement module receives the 64 RAMs of data output from the node message module. Each RAM corresponds to 7 rows of data. The data corresponding to the first row of the first 32 RAMs is placed in the first part, the data corresponding to the second row of the first 32 RAMs is placed in the second part, and so on. The data is rearranged and output to the 14 check node update submodules in this order. After the calculation is completed, the data rearrangement module receives the output data from the check node message update module and writes it to the node message storage module in reverse order. During the variable node message update, the data rearrangement module receives the 64 RAMs of data output from the node message module, places the data corresponding to the first row of the output data of the 1st, 2nd, 33rd, and 34th RAMs in the first part, and so on. The data is rearranged and output to the 112 check node update submodules in this order. After the calculation is completed, the data rearrangement module receives the output data from the variable node message update module and writes it into the node message storage module in reverse order.

[0043] As one embodiment, this invention divides a cyclic submatrix into a non-cyclic submatrix based on adjacent columns to improve parallelism. However, since the submatrix is ​​non-cyclic, data misalignment can occur when the address reaches the boundary, according to traditional processing methods. Therefore, a data shifting module is designed. As shown in Figure 2, taking the first cyclic submatrix as an example, the submatrix in this invention is divided into 7 rows and 7 columns based on adjacent columns. Since the divided submatrix is ​​not a cyclic matrix, it can be seen that the data in one column spans two rows. Because the division is done by column, it has no impact on the column-based processing of variable node updates. When updating the verification node, it can be seen that the data in the first row moves to another column after the address exceeds 73. It is necessary to shift the 7 columns of data at the same address output by the node message module; otherwise, data misalignment will occur. This invention designs a data shifting module to handle the data misalignment problem when the index address exceeds the boundary during the verification node update process.

[0044] As one embodiment, the output module implements a dual-port RAM with a write bit width of 16 bits and a depth of 512, and a read bit width of 1 bit and a depth of 8192. The read address is generated by the control module, and the least significant bit of each address is read, then the second least significant bit of each address is read, and so on, to realize the sequential reading of the decoded bit stream.

[0045] As one embodiment, the CCSDS near-Earth satellite codeword decoder designed in this invention improves the parallelism of the decoder by further dividing the cyclic submatrix into smaller acyclic submatrixes. Storing the node messages of the seven submatrices in the same address of RAM, and alternately storing the verification node information and variable node information in the same RAM, significantly saves storage resources and improves throughput. The CCSDS near-Earth satellite codeword decoder designed in this invention utilizes the addressing logic for obtaining variable node information in the verification node update module by extending the node message by one bit to store the decision result. This eliminates the need for additional addressing logic and storage units, does not affect timing, and achieves low-overhead verification functionality. Adding the verification function allows for early termination of iterative decoding, improving throughput and reducing power consumption. The CCSDS near-Earth satellite codeword decoder designed in this invention uses a pipelined frame architecture. During the decoding process, the received signal LLR data and decision result output steps can be performed simultaneously, realizing pipelined frames. The decoder does not need to wait for the previous frame's decoding or decision result output to complete before inputting data. In multi-frame decoding, this saves data input and output time and improves throughput. The hardware implementation results of the decoder achieved by the above three strategies are shown in Table 1. Using the XC7K325T development board, the maximum number of iterations is 10, the quantization bit width is 6, and the average number of iterations is 5 when the bit signal-to-noise ratio is 4.1. At this time, the average decoder throughput is 1.965Gbps.

[0046] Table 1. Decoder Hardware Implementation Results

[0047] Furthermore, the CCSDS near-Earth satellite codeword decoder designed in this invention employs a decoder design method with less performance loss in bit error rate. By adding a clipping operation to the output of the variable node update module, greater performance gains are achieved with less resource consumption. Additionally, in the check node update module, a correction method that avoids direct right shifting is used, resulting in more accurate data when the data is skewed, and the correction algorithm is implemented with less loss, thus improving bit error rate performance. The tested bit error rate results are as follows: Figure 7 As shown, the bit error rate of the LDPC decoder implemented using the above two strategies is almost the same as that of the quantization simulation decoding algorithm.

[0048] As one embodiment, the CCSDS near-Earth satellite standard LDPC decoder implemented in this invention improves the parallelism of the decoder by further dividing the cyclic submatrix of the CCSDS near-Earth satellite code group into smaller acyclic submatrixes. Furthermore, it saves significant storage resources by storing node messages located in the same cyclic submatrix after block division in the same address of RAM, and by alternately writing variable node and check node messages into RAM. The method of extending the node message by one bit to store the decision result enables the check function with low resource overhead. Optimization of the two node update modules improves error performance. The LDPC decoder design proposed in this invention reduces resource consumption and improves the decoder's throughput.

[0049] A high-parallelism, low-storage-overhead LDPC decoding method for the CCSDS near-Earth satellite standard, the method comprising: S1: The decoder is in a waiting frame synchronization state. After recognizing the frame header, it proceeds to step S2. S2: The decoder is in the initial message receiving state. It writes the 8176 data output after frame synchronization into the memory in address order. After one memory cell is filled with 73 data, it writes into the next memory cell. S3: The decoder is in the message initialization state, performs node message initialization, and writes the initialized node messages into the memory; S4: The decoder is in the check node update state. It reads the node message from the memory, and obtains the variable node message at the correct position through address processing, data shifting and data rearrangement. It updates the check node message and writes the updated message back to the memory. At the same time, it checks the decision result of the previous round. Each submatrix has a total of 73 rows and a row parallelism of 14. It checks 14 rows at the same time. If the check module of each submatrix has successfully checked all 73 rows, it indicates that the decision result is correct. Then it jumps to step S6. Otherwise, it enters step S5 to continue the iteration. S5: The decoder is in the variable node update state. It reads the node message from the memory, obtains the check node message at the correct position through data shifting and data rearrangement, updates the variable node message, makes a judgment on the decision result, merges the decision result with the variable node message and writes it back to the memory, and determines whether the maximum number of iterations has been reached. If it has, proceed to step S6; otherwise, jump to step S4 and increment the number of iterations by one. S6: The decoder returns to the waiting frame header state, the output flag is pulled high, indicating that there is data to be output; the decision results at the writing position interval of 73 are read out in sequence.

[0050] As one embodiment, the CCSDS near-Earth satellite standard's high-parallelism, low-storage-overhead LDPC decoder implementation, with decoding steps scheduled by the control module, includes the following steps: Step 1: The decoder is in a waiting frame synchronization state. After recognizing the frame header, it proceeds to Step 2. Step 2: When the decoder is in the initial message receiving state, the control module generates read / write enable and address signals for the channel LLR storage module. The 8176 data outputs from the frame synchronization module are written into the RAM of the node message storage module in address order. When one RAM is full, 73 data are written to the next RAM.

[0051] Step 3: The decoder is in the node message initialization state. The control module generates read / write enable and address signals for the channel LLR storage module and the node message storage module. The enabled variable node update module initializes the node message and writes the initialized node message into the node message storage module.

[0052] Step 4: The decoder is in the check node update state. The control module generates read / write enable and address signals for the node message storage module. The read / write data is processed through the address generation module, data shifting module, and data rearrangement module to obtain the variable node message at the correct position. The check node update module is enabled to update the check node message and write it to the node message storage module. At the same time, the result of the previous variable node update module's decision is checked. Each submatrix has 73 rows with a row parallelism of 14. 14 rows are checked simultaneously. If the check module of each submatrix successfully checks all 73 rows, it indicates that the decision result is correct, and the process jumps directly to step 6. Otherwise, iterates and proceeds to step 5.

[0053] Step 5: The decoder is in the variable node update state. The control module generates read / write enable signals and address signals for the channel LLR storage module and the node message storage module. The read / write data is processed by the data shifting and rearranging module to obtain the correct position of the check node message. The variable node update module is enabled to update the variable node message and make a decision on the result. The decision result and the variable node message are merged and written to the node message storage module. It is then determined whether the maximum number of iterations has been reached. If it has, proceed to step 6; otherwise, jump to step 4 and increment the iteration count by one.

[0054] Step Six: The decoder returns to the waiting frame header state, and the output flag is pulled high, indicating that there is data to be output. The control module generates the read / write enable and address signals for the output module, and reads out the decision results at a 73-second interval during writing in sequence.

[0055] The above are merely exemplary embodiments of this disclosure and should not be construed as limiting the scope of this disclosure. Any equivalent changes and modifications made in accordance with the teachings of this disclosure shall still fall within the scope of this disclosure.

[0056] This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not described in this disclosure. The specification and embodiments are to be considered exemplary only, and the scope and spirit of this disclosure are defined by the claims.

Claims

1. A high-parallelism, low-storage-overhead LDPC decoder for the CCSDS near-Earth satellite standard, characterized in that, include: The frame synchronization module, the channel LLR storage module, the variable node update module, and the check node update module are connected in sequence. The output module connects to the variable node update module; The address generation module, node message storage module, data shifting module, and data rearrangement module are connected in sequence. The frame synchronization module, channel LLR storage module, variable node update module, check node update module, address generation module, node message storage module, data shifting module, and data rearrangement module are all connected to the control module; Frame synchronization module: used to receive the initial log-likelihood ratio of CCSDS near-Earth satellite code group signals and identify the frame header; Channel LLR storage module: Stores the initial log-likelihood ratio after frame synchronization; Node message storage module: used to store intermediate messages generated by the variable node update module and the verification node update module during the decoding process; Data rearrangement module: Sorts intermediate messages read from or written to the node message storage module according to their current state; Variable node update module: Receives data from the data rearrangement module, updates variable messages, makes a judgment to obtain a judgment result, and stores the judgment result in an extended bit; Verification node update module: Receives data from the data rearrangement module, updates the verification messages, extracts the highest bit of each message for verification, and outputs the verification node information; Address generation module: Used to generate addresses for reading messages from different node storage modules; Data shifting module: used to correct address misalignment at the boundaries of non-cyclic submatrices; Control module: Used to generate control signals for each module and read / write addresses for each random access memory; Output module: Stores the decision results of the variable node update module and outputs the decision results when in the output state.

2. The LDPC decoder as described in claim 1, characterized in that, The LDPC decoder includes: The cyclic submatrix in the parity check matrix of the CCSDS near-Earth satellite code group is further divided into smaller acyclic submatrixes.

3. The LDPC decoder as described in claim 2, characterized in that, The LDPC decoder includes: The cyclic submatrix of the CCSDS near-Earth satellite code group's check matrix is ​​511-dimensional, and it is split into 7 non-cyclic submatrixes of 73 dimensions according to adjacent columns. The intermediate messages of the seven acyclic submatrices are stored in the same address of the same random access memory, and the check node information and intermediate messages are alternately stored in the same random access memory. The CCSDS near-Earth satellite code group consists of 2×16 cyclic submatrices with a column weight of 2. If the quantization bit width is Q, then the node message storage module contains 64 random access memories with a bit width of 7×(Q+1) and a depth of 73.

4. The LDPC decoder as described in claim 1, characterized in that, The LDPC decoder includes: The verification function is achieved by extending the intermediate message by one bit to store the judgment result; the quantization bit width is selected as Q bits, the intermediate message bit width is extended by one bit to Q+1 bits, the highest bit is assigned the judgment result in the variable node update module, and the highest bit is extracted in the verification node update module to realize single-line verification.

5. An LDPC decoder as described in claim 1, characterized in that, The output of the variable node update module is equipped with a limiter, which is used to limit the data after the variable node update calculation; the limiter restricts the output result of the adder to a preset dynamic range. The variable node update module includes 112 variable node update sub-modules. The variable node update sub-modules use a 5-stage pipeline for update calculation. The adder uses a two-stage pipeline. The second-stage pipeline adds the input data pairwise, and the third-stage pipeline adds the results of the pairwise additions again. After the addition is completed, a limiter is used to limit the addition result. The data at the current position is subtracted from the limited result to obtain the subtractor output. In the fifth-stage pipeline, the decision result is assigned to the extended highest bit of each subtractor output. The correction factor set in the verification node update module is 0.75, which is achieved by adding the data to the left by shifting it one bit and then shifting it to the right by two bits. The verification node update module includes 14 verification node update sub-modules; the verification node update sub-modules use a 13-level pipeline to update messages.

6. An LDPC decoder as described in claim 1, characterized in that, The verification node update module is equipped with a comparator tree structure, which is used to obtain the minimum value, the second smallest value, and the minimum value index among 32 input data. The comparator tree contains a total of 8 pipelines, each of which is a pipeline level. The 6th pipeline obtains the minimum value and the minimum value index, and the 8th pipeline obtains the second smallest value.

7. An LDPC decoder as described in claim 1, characterized in that, The LDPC decoder adopts a pipelined frame architecture. The channel LLR storage module contains 112 random access memories with a depth of 146, which are used to store two frames of data simultaneously. During the decoding process, the log-likelihood ratio of the received signal is stored and the decision result is output simultaneously.

8. A high-parallelism, low-storage-overhead LDPC decoding method for the CCSDS near-Earth satellite standard, based on the LDPC decoder as described in any one of claims 1-7, characterized in that, The method includes: S1: The decoder is in a waiting frame synchronization state. After recognizing the frame header, it proceeds to step S2. S2: The decoder is in the initial message receiving state. It writes the 8176 data output after frame synchronization into the memory in address order. After one memory cell is filled with 73 data, it writes into the next memory cell. S3: The decoder is in the message initialization state, performs node message initialization, and writes the initialized node messages into the memory; S4: The decoder is in the check node update state. It reads the node message from the memory, and obtains the variable node message at the correct position through address processing, data shifting and data rearrangement. It updates the check node message and writes the updated message back to the memory. At the same time, it checks the decision result of the previous round. Each submatrix has a total of 73 rows and a row parallelism of 14. It checks 14 rows at the same time. If the check module of each submatrix has successfully checked all 73 rows, it indicates that the decision result is correct. Then it jumps to step S6. Otherwise, it enters step S5 to continue the iteration. S5: The decoder is in the variable node update state. It reads the node message from the memory, obtains the check node message at the correct position through data shifting and data rearrangement, updates the variable node message, makes a judgment on the decision result, merges the decision result with the variable node message and writes it back to the memory, and determines whether the maximum number of iterations has been reached. If it has, proceed to step S6; otherwise, jump to step S4 and increment the number of iterations by one. S6: The decoder returns to the waiting frame header state, the output flag is pulled high, indicating that there is data to be output; the decision results at the writing position interval of 73 are read out in sequence.

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