A real-time unmanned aerial vehicle signal detection system and method

Abstract

The application relates to an unmanned aerial vehicle signal real-time detection system and method, a computer device and a computer readable storage medium, which are characterized in that a frequency domain processing channel for a flight control frequency hopping feature and a time domain correlation processing channel for a picture transmission signal cycle prefix are heterogeneously arranged in the same field programmable gate array (FPGA) system on chip, the problems of insufficient real-time performance of a unified processing architecture and unbalanced logic resource allocation caused by feature differences between a flight control frequency hopping signal and a picture transmission signal are solved, and comprehensive detection with microsecond-level low time delay and low power consumption is realized; meanwhile, the synchronization safety of cross-clock domain data interaction is guaranteed through a dual-port block memory mechanism, and the detection sensitivity and identification accuracy in a complex channel environment are greatly improved in combination with a multi-mode fusion strategy.

Description

Technical Field

[0001] This application relates to the field of unmanned aerial vehicle (UAV) signal processing, and in particular to a real-time UAV signal detection system, method, computer device, and computer-readable storage medium. Background Technology

[0002] With the rapid development of the low-altitude economy, the number of consumer and professional drones continues to grow. In scenarios such as airport airspace protection, key area security, and urban public safety, illegal drone intrusion incidents are frequent, creating an urgent need for real-time passive detection capabilities for drone radio signals. The goal of drone radio signal detection is to achieve real-time perception and alerting of intruding drones by passively monitoring the drone's remote control link (i.e., flight control signals) and image transmission link (i.e., image transmission signals) without actively emitting any signals.

[0003] At the signal characteristics level, the UAV flight control link and image transmission link exhibit distinctly different physical characteristics: flight control signals are typically narrowband, frequency-hopping, or pulsed control signals, operating in the 2.4GHz or 900MHz unlicensed frequency bands, with a typical frequency hopping rate of 50 to 200 hops / second, a single frequency dwell time of 5 to 20ms, and an instantaneous bandwidth usually within 2MHz. The core identifiable characteristic of this type of signal is the timing pattern of frequency hopping. Image transmission signals are typically wideband orthogonal frequency division multiplexing (OFDM) signals, operating in the 5.8GHz band, occupying a bandwidth typically of 10 to 40MHz, and employing a cyclic prefix mechanism to resist multipath interference. There is a strict periodic correlation between the cyclic prefix and the effective symbols of OFDM signals. Existing UAV signal detection technologies mostly use unified DSP or GPU software solutions to process these two types of signals.

[0004] In related technologies, a single processing architecture struggles to meet the dual real-time requirements of frequency hopping detection of flight control signals and time-domain delay autocorrelation detection of image transmission signals in terms of algorithm structure and timing. High-power computing platforms limit the deployment of portable battery-powered devices. Meanwhile, parallel correlation calculations of multiple reference sequences and multi-channel synchronous processing lead to a severe imbalance in the allocation of FPGA logic resources, and cross-clock domain data interaction between the FPGA logic end and the processor end is prone to metastability and synchronization security issues, for which no effective solution has yet been proposed. Summary of the Invention

[0005] This application provides a real-time detection system, method, computer device, and computer-readable storage medium for unmanned aerial vehicle (UAV) signals, which at least solves the problem in the related art where a single processing architecture cannot simultaneously meet the dual real-time requirements of frequency hopping detection of flight control signals and time-domain delay autocorrelation detection of image transmission signals in terms of algorithm structure and timing.

[0006] In a first aspect, embodiments of this application provide a real-time unmanned aerial vehicle (UAV) signal detection system, including a response module, a signal processing module, and a fusion decision module integrated on the FPGA programmable logic terminal and the processor terminal, wherein: The response module is used to receive radio signals in the target frequency band and output I / Q baseband signals, and distribute the I / Q baseband signals to the signal processing module; The signal processing module, located at the programmable logic terminal of the FPGA, is used to downsample and perform frame-by-frame frequency domain transformation on the I / Q baseband signal through the flight control signal processing channel, extract the frequency index of the maximum spectral energy of each frame to construct a time-series frequency point sequence, and output the flight control frequency hopping determination result based on the change in adjacent frame indexes and the dwell time of a single frequency point in the time-series frequency point sequence. In addition, through the image transmission signal processing channel parallel to the flight control signal processing channel, the I / Q baseband signal and its delayed signal are subjected to conjugate correlation and sliding window accumulation, the periodic correlation peak of the cyclic prefix of the orthogonal frequency division multiplexing signal is extracted, and the image transmission judgment result is output according to the dynamic threshold. The fusion decision module, located on the processor, is used to receive the flight control frequency hopping determination result and the image transmission determination result, and output the UAV detection result according to the preset parameter library and fusion strategy.

[0007] In some embodiments, the flight control signal processing channel includes: a decimation filtering unit, a frequency domain transformation unit, a peak index extraction unit, and a frequency hopping determination unit, wherein: The decimation filtering unit employs a cascaded integrator comb filter to downsample the I / Q baseband signal, obtaining a downsampled signal with a preset sampling rate that matches the bandwidth of the flight control signal. The frequency domain transformation unit is used to perform frame-by-frame fast Fourier transform on the downsampled signal and output the energy spectrum of each frequency point. The peak index extraction unit adopts a pipelined comparison tree structure to perform parallel comparisons of the energy values ​​of each frequency point within a preset clock cycle, and to determine the index of the frequency point with the maximum energy in the current frame and its corresponding maximum energy value. The frequency hopping determination unit is used to store the maximum energy frequency index into a sliding buffer to construct a time-series frequency sequence, and output the flight control frequency hopping determination result when it detects that the change in the adjacent frame index is greater than a preset change threshold and the dwell time of a single frequency point meets the preset dwell frame number range.

[0008] In some embodiments, the image transmission signal processing channel includes: a delay line unit, a conjugate multiplication unit, a sliding window accumulation unit, and a threshold comparison unit, wherein: The delay line unit is implemented using a block random access memory and is used to output a delayed signal with a preset sampling point. The conjugate multiplication unit is used to calculate the conjugate product of the currently input I / Q baseband signal and the delayed signal; The sliding window accumulation unit is used to perform recursive calculations based on the historical conjugate product values ​​output by the conjugate multiplication unit, thereby realizing the relevant accumulation within a preset sliding window length and obtaining the relevant accumulation result at the current moment. The threshold comparison unit is used to estimate the background noise power by performing a moving average on the I / Q baseband signal, and dynamically determine the dynamic threshold based on the background noise power. When the correlation accumulation result exceeds the dynamic threshold, the image transmission judgment result is output.

[0009] In some embodiments, the image transmission signal processing channel includes: The conjugate multiplication unit is specifically used to calculate the conjugate product. ; The sliding window accumulation unit is specifically used for calculation. ; Where x(t) is the I / Q baseband signal at the current moment. The delayed signal, Let t be the delay length, t be the index of the current sampling point, L be the sliding window length, and W(t) be the sum of the sliding window at the current time t.

[0010] In some embodiments, the system further includes a cross-clock domain cache module, wherein: The cross-clock domain cache module is implemented using a dual-port block random access memory. The flight control signal processing channel and the image transmission signal processing channel are located in the write clock domain. The flight control frequency hopping determination result and the image transmission determination result are written into the cross-clock domain cache module. The fusion decision module is located in the read clock domain and reads the corresponding decision result from the cross-clock domain cache module across clock domains.

[0011] In some embodiments, the parameter library stores at least one of frequency hopping dwell time range, frequency change threshold, cyclic prefix length, and symbol length; The fusion strategies supported by the fusion decision module include: Union mode: An alarm is triggered if any one of the flight control signal processing channels or the image transmission signal processing channel outputs a positive result. Intersection mode: An alarm is triggered when both the flight control signal processing channel and the image transmission signal processing channel output a positive result simultaneously. Weighted mode: The current flight control frequency hopping matching confidence and the normalized amplitude of the image transmission related peak are weighted and fused. An alarm is triggered when the weighted result exceeds the comprehensive threshold.

[0012] In some embodiments, when the logic resources of the FPGA programmable logic terminal are limited, the flight control signal processing channel is used to perform auxiliary frequency domain pre-screening by multiplexing the internal frequency domain transformation unit through the time slot control state machine. The delay line unit, conjugate multiplication unit and sliding window accumulation unit in the image transmission signal processing channel keep running at full speed without interruption.

[0013] Secondly, embodiments of this application provide a real-time detection method for UAV signals, implemented through a response module, a signal processing module, and a fusion decision module integrated into the FPGA programmable logic terminal and the processor terminal. The method includes: The response module receives radio signals in the target frequency band and outputs I / Q baseband signals, and distributes the I / Q baseband signals to the flight control signal processing channel and the image transmission signal processing channel. The signal processing module performs downsampling and frame-by-frame frequency domain transformation on the I / Q baseband signal, extracts the frequency index of the maximum spectral energy of each frame to construct a time-series frequency point sequence, and outputs the flight control frequency hopping determination result based on the change in adjacent frame indices and the dwell time of a single frequency point in the time-series frequency point sequence. In addition, through the image transmission signal processing channel parallel to the flight control signal processing channel, the I / Q baseband signal and its delayed signal are subjected to conjugate correlation and sliding window accumulation, the periodic correlation peak of the cyclic prefix of the orthogonal frequency division multiplexing signal is extracted, and the image transmission judgment result is output according to the dynamic threshold. The fusion decision module receives the flight control frequency hopping determination result and the image transmission determination result, and outputs the UAV detection result according to the preset parameter library and fusion strategy.

[0014] Thirdly, embodiments of this application provide a computer device including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the method described in the second aspect above.

[0015] Fourthly, embodiments of this application provide a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the method described in the second aspect above.

[0016] Compared to related technologies, the UAV signal real-time detection system, method, computer device, and computer-readable storage medium provided in this application address the issues of insufficient real-time performance and unbalanced logic resource allocation in the unified processing architecture caused by the characteristic differences between flight control frequency hopping signals and image transmission signals by heterogeneously setting up a frequency domain processing channel for flight control frequency hopping characteristics and a time domain correlation processing channel for image transmission signal cyclic prefix within the same field-programmable gate array (FPGA) on-chip system. This achieves comprehensive detection with microsecond-level low latency and low power consumption. At the same time, a dual-port block memory mechanism ensures the synchronization security of cross-clock domain data interaction, and a multi-mode fusion strategy significantly improves detection sensitivity and recognition accuracy in complex channel environments. Attached Figure Description

[0017] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1 This is a structural block diagram of a real-time unmanned aerial vehicle (UAV) signal detection system according to an embodiment of this application; Figure 2 This is a system hardware architecture block diagram according to an embodiment of this application; Figure 3 This is a schematic diagram of the flight control signal processing channel pipeline according to an embodiment of this application; Figure 4 This is a schematic diagram of the image transmission signal processing channel structure according to an embodiment of this application; Figure 5 This is a flowchart of a real-time drone signal detection method according to an embodiment of this application; Figure 6 This is a schematic diagram showing the results of FPGA resource usage and critical path timing analysis; Figure 7 This is a schematic diagram showing the results of a comparative test of the detection performance of FCS single-channel, ITS single-channel, and dual-channel fusion according to an embodiment of this application. Figure 8 This is a schematic diagram of the internal structure of a computer device according to an embodiment of this application. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this application clearer, the application is described and illustrated below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application. All other embodiments obtained by those skilled in the art based on the embodiments provided in this application without inventive effort are within the scope of protection of this application.

[0019] Obviously, the accompanying drawings described below are merely some examples or embodiments of this application. Those skilled in the art can apply this application to other similar scenarios based on these drawings without any inventive effort. Furthermore, it is understood that although the efforts made in this development process may be complex and lengthy, for those skilled in the art related to the content disclosed in this application, any changes to design, manufacturing, or production based on the technical content disclosed in this application are merely conventional technical means and should not be construed as insufficient disclosure of the content of this application.

[0020] In this application, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment that is mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described in this application may be combined with other embodiments without conflict.

[0021] Unless otherwise defined, the technical or scientific terms used in this application shall have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms “a,” “an,” “an,” “the,” and similar words used in this application do not indicate quantity limitation and may indicate singular or plural. The terms “comprising,” “including,” “having,” and any variations thereof used in this application are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or device that includes a series of steps or modules (units) is not limited to the listed steps or units, but may also include steps or units not listed, or may include other steps or units inherent to these processes, methods, products, or devices. The terms “connected,” “linked,” “coupled,” and similar words used in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. “Multiple” used in this application refers to two or more. “And / or” describes the relationship between related objects, indicating that three relationships may exist; for example, “A and / or B” can represent: A alone, A and B simultaneously, and B alone. The character " / " generally indicates that the preceding and following objects are in an "or" relationship. The terms "first," "second," and "third" used in this application are merely to distinguish similar objects and do not represent a specific ordering of the objects.

[0022] This embodiment provides a real-time signal detection system for unmanned aerial vehicles (UAVs). Figure 1 This is a structural block diagram of a real-time unmanned aerial vehicle (UAV) signal detection system according to an embodiment of this application, such as... Figure 1As shown, the system includes a response module 10 (specifically including a radio frequency receiving module and a data distribution module), a signal processing module 11 (specifically including a flight control signal processing channel (FCS channel) and an image transmission signal processing channel (ITS channel)) and a fusion decision module 12, which are integrated on the FPGA programmable logic terminal and the processor terminal.

[0023] in addition, Figure 2 This is a system hardware architecture block diagram according to an embodiment of this application, such as... Figure 2 As shown, the real-time signal detection system for unmanned aerial vehicles includes: a response module (specifically including a radio frequency receiving module and a data distribution module), a flight control signal processing channel (FCS channel), an image transmission signal processing channel (ITS channel), and a fusion decision module.

[0024] It should be noted that in this embodiment, the above modules are integrated on the same system-on-a-chip (SoC) platform. Preferably, the Zynq-7020 SoC platform is used, wherein the data distribution module, flight control signal processing channel and image transmission signal processing channel are deployed on the FPGA programmable logic end (PL end), and the fusion decision module is deployed on the processor end (PS end, such as ARM Cortex-A9 dual-core processor).

[0025] The radio frequency (RF) receiver module is used to receive radio signals within the target frequency band and output I / Q baseband signals. This RF receiver module uses a wideband RF transceiver chip (such as AD9361), supports signal reception in the 70MHz to 6GHz frequency band, and has a maximum instantaneous bandwidth of 56MHz.

[0026] Furthermore, this module can be configured with parameters such as center frequency, gain, and sampling rate via the SPI interface. It down-converts and digitizes radio signals within the target frequency band, outputting I / Q quadrature baseband signals, which are then transmitted to the FPGA programmable logic terminal via a low-voltage differential signaling (LVDS) interface. The system can support dual-band synchronous reception of flight control frequency bands (e.g., 2.4GHz) and image transmission frequency bands (e.g., 5.8GHz) via an RF receiver module, or extend to multi-band coverage through time-division switching.

[0027] The data distribution module, located at the FPGA programmable logic level, distributes I / Q baseband signals to the flight control signal processing channel and the image transmission signal processing channel. Optionally, this module is implemented using an AXI-Stream crossbar switch, which performs digital gain control and DC bias cancellation to improve input signal quality. Additionally, the AXI-Stream bus supports a back-pressure mechanism to ensure that data stream is not lost during brief congestion in downstream processing channels.

[0028] The flight control signal processing channel, located at the FPGA programmable logic end, is designed for the frequency domain characteristics of flight control frequency hopping signals and adopts a hardware pipeline architecture. Figure 3 This is a schematic diagram of the flight control signal processing pipeline according to an embodiment of this application. Figure 3 As shown, this channel includes a decimation filtering unit, a frequency domain transformation unit, a peak index extraction unit, and a frequency hopping determination unit, wherein: The decimation filtering unit employs a cascaded integrator comb (CIC) decimation filter, consisting entirely of addition, subtraction, and shift operations, without consuming DSP multiplier resources. Its function is to reduce the broadband sampling rate of the I / Q baseband signal (e.g., 40 MSPS) to a preset sampling rate (e.g., 1 to 4 MSPS) that matches the bandwidth of the flight control signal before frequency domain transformation, thereby reducing the computational load of subsequent frequency domain transformation units and lowering the noise floor.

[0029] The frequency domain transformation unit uses a fixed-point fast Fourier transform (FFT) logic core to perform frame-by-frame frequency domain transformation on the downsampled signal and output the energy spectrum of each frequency point.

[0030] The peak index extraction unit employs a pipelined comparison tree structure, performing parallel comparisons of the energy values ​​of N frequency points within O(log₂N) clock cycles, and outputting the index of the frequency point with the highest energy in the current frame and its corresponding energy value. The maximum frequency point indices of consecutive frames constitute a time-series frequency point sequence. The frequency hopping determination unit stores the maximum frequency point index in a sliding buffer and extracts the index change between adjacent frames. .

[0031] When the number of stable residing frames at a frequency point meets the preset range and the subsequent change is greater than the preset change threshold, the frequency hopping step size feature preset in the parameter library is used for matching. If the matching is successful, the flight control frequency hopping determination result is output, and the frequency hopping time, current frequency point index and energy value are recorded.

[0032] The image transmission signal processing channel is located at the FPGA programmable logic level and runs in parallel with the flight control signal processing channel. This channel implements a hardware pipeline for an improved autocorrelation frame detection algorithm, taking into account the cyclic prefix correlation characteristics of the image transmission OFDM signal, without including any FFT operations. Figure 4 This is a schematic diagram of the image transmission signal processing channel structure according to an embodiment of this application. The channel includes a delay line unit, a conjugate multiplication unit, a sliding window accumulation unit, and a threshold comparison unit, wherein: The delay line unit is configured as a shift register using the FPGA's internal block random access memory (BRAM) to output a delay. Delay signal at each sampling point Delay depth The cyclic prefix length can be dynamically configured via parameter registers to adapt to different protocols.

[0033] It should be noted that the conjugate multiplication unit calculates the conjugate product of the current I / Q baseband signal and the delayed signal using a hardware multiplier. The calculation formula is as follows: The calculation of the real and imaginary parts is accomplished by a combination of a real multiplier and an adder / subtractor, and the calculation formula is as follows: .

[0034] The sliding window accumulation unit uses a recursive architecture with a time complexity of O(1) to implement the relevant accumulation within the preset sliding window length L. The calculation formula is as follows: This implementation avoids the point-by-point accumulation of data within the window, requiring only adders and subtractors, thus greatly saving FPGA logic resources.

[0035] The threshold comparison unit estimates the background noise power by averaging the I / Q baseband signals and dynamically determines the dynamic threshold based on the background noise power and the configurable detection factor. When the output amplitude of the sliding window accumulation unit exceeds the dynamic threshold, the image transmission judgment result is output.

[0036] In addition, the system also includes a cross-clock domain buffer module, implemented using a dual-port block random access memory. Since the flight control signal processing channel and the image transmission signal processing channel are located in the high-frequency write clock domain (e.g., 100MHz) at the PL end, while the fusion decision module is located in the read clock domain (e.g., 666MHz) at the PS end, the cross-clock domain buffer module has built-in synchronization logic to ensure the data integrity of the flight control frequency hopping decision result and the image transmission decision result during transmission, and to avoid metastability.

[0037] The fusion decision module, located on the processor, outputs the final UAV detection results based on a preset parameter library and fusion strategy. The parameter library stores frequency hopping dwell time ranges, frequency change thresholds, cyclic prefix lengths, and symbol lengths. The fusion strategy supports the following three modes: Union mode (an alarm is triggered if any channel outputs a positive result, suitable for scenarios with extremely low tolerance for false negatives). Intersection mode (both channels output positive results simultaneously to trigger an alarm, suitable for scenarios with extremely low tolerance for false alarm rates); Weighted mode (weighted fusion based on flight control frequency hopping matching confidence and image transmission related peak normalization amplitude, triggering alarm when the comprehensive threshold is exceeded, suitable for complex channel scenarios).

[0038] In specific implementation scenarios, when the FPGA programmable logic faces extreme resource constraints (such as using a Zynq-7010 chip with halved logic resources), the flight control signal processing channel can reuse its internal frequency domain transformation unit through a time-slot control state machine to perform auxiliary frequency domain pre-screening. Simultaneously, the delay line unit, conjugate multiplication unit, and sliding window accumulation unit in the image transmission signal processing channel continue to operate uninterrupted at full speed. This time-slot multiplexing mechanism, with only a slight reduction in frequency resolution, does not alter the core processing logic of flight control frequency hopping determination and image transmission correlation peak determination.

[0039] The system employs a heterogeneous dual-stream parallel architecture with a field-programmable gate array (FPGA) to separately construct a flight control signal processing channel based on frequency domain transformation and a video transmission signal processing channel based on time domain correlation. A dual-port block memory facilitates cross-clock domain interaction with the processor for multi-mode fusion decision-making. This addresses technical issues such as insufficient real-time performance of single-processor architectures, uneven allocation of logic resources, metastability in cross-clock domain data interaction, and high power consumption of traditional computing platforms. Ultimately, it achieves microsecond-level end-to-end processing latency, optimizes hardware resource utilization, improves overall detection rate through dual-path fusion, reduces overall power consumption, and supports online updates of protocol parameters for new UAV models.

[0040] This embodiment also provides a method for real-time detection of drone signals. Figure 5 This is a flowchart of a real-time drone signal detection method according to an embodiment of this application, such as... Figure 5 As shown, the process includes the following steps: Step S401: Receive radio signals within the target frequency band and convert them into I / Q baseband signals.

[0041] After system power-on initialization, the processor configures the center frequency, sampling rate, and hardware automatic gain control function of the RF receiver chip via the SPI interface. The RF receiver module down-converts and digitizes the over-the-air signal.

[0042] Preferably, this embodiment implements the real-time UAV signal detection method of the present invention based on the Zynq-7020 SoC platform (PL logic scale: 53,200 LUTs, 106,400FF, 140 BRAM-36K, 220 DSP48E1; PS: dual-core ARM Cortex-A9, main frequency 666 MHz).

[0043] In an exemplary embodiment, the system power-on initialization process is as follows: S1, PS terminal loads FPGA bitstream (loaded via PCAP for approximately 120 ms). S2, PS side configures AD9361 via SPI interface: center frequency set to 2.437 GHz (flight control channel), or switched to 5.805 GHz (image transmission channel), IQ sampling rate set to 40 MSPS, hardware automatic gain control (AGC) enabled; S3, the PS end writes the FCS channel parameter register (e.g., FFT points N=256, CIC decimation ratio R_cic=10, frequency hopping threshold Δk_th=4, dwell frame range [2, 50]) and ITS channel parameter register (delay length) through the AXI-Lite interface. Sampling points, sliding window length L=512, detection factor γ=4.0). S4, the PS end loads known UAV protocol parameters (frequency hopping pattern, CP length list, etc.) from the parameter library Flash into the BRAM parameter table; S5 enables the AXI-Stream crossbar switch of the data distribution module, starts data stream distribution, and the system enters real-time detection operation state.

[0044] The complete initialization process takes approximately 450 ms, which meets the system power-on ready time requirement (<1 s).

[0045] Step S402: Distribute the I / Q baseband signals to the flight control signal processing channel and the image transmission signal processing channel at the FPGA programmable logic terminal.

[0046] Preferably, in this embodiment, the data distribution module uses an AXI-Stream bus crossbar switch to perform real-time parallel replication of the data stream and simultaneously performs digital gain control and DC bias cancellation on the received data stream to improve the input signal quality. The AXI-Stream bus has a built-in backpressure mechanism to ensure that the input data stream is not lost when there is a brief computational congestion in the downstream channel.

[0047] In step S403, the flight control signal processing channel performs decimation filtering, frame-by-frame frequency domain transformation, and peak index extraction on the input signal to form a time-series frequency point sequence, and outputs the flight control frequency hopping determination result based on the index change of adjacent frames and dwell time.

[0048] Taking the detection of a certain type of drone (such as Mavic 3) as an example, its flight control link operates at 2.400~2.483 GHz, with a frequency hopping rate of about 100 hops / second (dwell time of about 10 ms), and each frequency hopping step is 1~83 channels (channel spacing of 1 MHz).

[0049] The CIC decimation filter is configured with order M=5, decimation ratio R_cic=10, and differential delay D=1, reducing 40 MSPS to 4 MSPS. The gain introduced by the CIC filter is (R_cic·D)^M=10^5, which is compensated at the output by shift truncation. After CIC downsampling, the flight control signal occupies approximately 2 MHz of the 4 MHz bandwidth, and the signal-to-noise ratio is improved by approximately 10·log⁻¹. 10 (R_cic)≈10dB.

[0050] The FFT unit is configured as follows: 256-point fixed-point FFT (Xilinx FFT IP, pipelined architecture), with a single-frame processing time of 256 / 4×10 at a sampling rate of 4 MSPS. 6 With a frame shift step size of 32 points (50% overlap) and a time-frequency resolution of 4 MHz / 256≈15.6 kHz / point, the resolution requirement of 1 MHz channel spacing (approximately 64 points / channel) is met.

[0051] The pipeline comparison tree performs 8 levels of parallel comparison on the energy values ​​of 256 frequency points (log2256=8), outputs the index of the frequency point with the maximum energy in the current frame, k_max, and the pipeline delay is 8 clock cycles (clock frequency 100 MHz, i.e. 80 ns), which does not affect real-time processing.

[0052] The frequency hopping determination logic is as follows: A sliding buffer with a depth of 50 frames is maintained to store the historical k_max sequence. When a frequency hopping event is detected where k_max is stable at a certain frequency point (Δk < Δk_th = 4) for consecutive M_dwell ∈ [2, 50] frames, followed by a hop where Δk ≥ Δk_th, a frequency hopping event is determined, and the hopping time, the frequency point before the hop, and the frequency point after the hop are output. When the cumulative number of frequency hoppings per second falls within the preset range of the parameter library (e.g., 90~110 hops / second for Mavic3), the flight control frequency hopping signal is determined to exist.

[0053] In step S404, the image transmission signal processing channel performs conjugate correlation and sliding window accumulation on the input signal and its delayed signal, and outputs the image transmission judgment result based on the comparison result between the accumulated value and the dynamic threshold.

[0054] Taking the DJI Mavic 3 image transmission link as an example, its image transmission signal operates at 5.805 GHz, with OFDM parameters: effective symbol length N_u=512 sampling points (sampling rate 20 MSPS), cyclic prefix length N_cp=64 sampling points, and total OFDM frame length N_sym=576 sampling points.

[0055] Delay line configuration: The sampling points use BRAM (18K bits, each BRAM can store 4K 16-bit complex sampling points, and two BRAMs are configured to implement a 576×32-bit delay line).

[0056] Conjugate multiplication unit: for complex input x(t) = I(t) + jQ(t) and delayed signal ,calculate: ; It is implemented using four 18×18-bit signed multipliers (consuming two DSP48E1s) and outputs a 36-bit fixed-point complex product.

[0057] O(1) Sliding window accumulation: Set the BRAM delay line to store history at L=N_u=512 points. Values, recursion:

[0058] Only two complex number additions and subtractions are required per clock cycle, which fully meets the real-time throughput requirement of 20 MSPS.

[0059] Dynamic threshold: Background noise power is determined by... The 1024-point moving average estimation and the detection threshold η(t) = γ·σ²_noise can be adaptively adjusted under different noise environments indoors and outdoors, and the measured false alarm rate is controlled within 5%.

[0060] In step S405, the fusion decision module outputs the final detection result based on the flight control frequency hopping judgment result, the image transmission judgment result, and the parameter library.

[0061] Both the FCS and ITS channels operate at a 100 MHz clock domain on the PL side, while the ARM core on the PS side operates at a 666 MHz clock domain. Data interaction between the two clock domains employs a True Dual-Port BRAM mechanism: the PL side writes the processing results in the write clock domain (100 MHz), and the PS side reads them in the read clock domain (666 MHz). The BRAM incorporates cross-clock domain synchronization logic to ensure data integrity.

[0062] The PS terminal uses a 1 ms polling period to read the latest decision status registers of FCS and ITS in BRAM through the AXI-Lite interface and executes the following fusion logic: S1. If the FCS channel has accumulated the number of valid frequency hopping events N_hop∈[N_hop_min, N_hop_max] (parameter library configuration value) in the last second, and the frequency hopping step size distribution matches the known model, then set FCS_flag=1; S2, if the ITS channel has accumulated the number of related peak events N_peak ≥ N_peak_min (parameter library configuration value) in the last 100 ms, then set ITS_flag=1; S3 calculates the final alarm decision based on the currently configured fusion mode (union / intersection / weighted) and reports the results (including detection time, signal type, and frequency information) to the host computer via the UART / Ethernet interface.

[0063] The measured end-to-end delay (from signal arrival at the antenna to alarm output) is approximately 18 ms in the union mode and approximately 23 ms in the intersection mode, both of which meet the engineering requirements for real-time detection.

[0064] Furthermore, this invention was synthesized and implemented in the Xilinx Vivado 2022.1 environment, with the target device being Zynq-7020 (XC7Z020-CLG484-1). Figure 6 This is a schematic diagram of FPGA resource usage and critical path timing analysis results, such as... Figure 6 As shown in Table 1, the usage statistics for each major resource are as follows: Table 1: FPGA Resource Usage Table

[0065] Critical path timing: FCS channel worst-case negative margin (WNS) = +0.43 ns (clock frequency 100 MHz), ITS channel WNS = +0.31 ns, and the overall system timing converges. Overall resource utilization is moderate, with approximately 70% of logic resources still available for functional expansion (such as multi-frequency parallel coverage).

[0066] To further verify the system engineering performance and environmental adaptability of this method, the following presents test data analysis on a specific hardware platform and a function reuse strategy under resource-constrained scenarios: In an outdoor testing environment, simulated UAV signals (Mavic3 flight control frequency hopping signal and Phantom4 image transmission OFDM signal) with different SNRs were injected using a signal generator. The detection performance of FCS single-channel, ITS single-channel, and dual-channel fusion (union / intersection mode) was compared and tested. Figure 7 This is a schematic diagram illustrating the results of a comparative test of the detection performance of FCS single-channel, ITS single-channel, and dual-channel fusion (union / intersection mode) according to embodiments of this application. Figure 7 As shown: With SNR=0 dB, the FCS single-channel detection rate is 73% and the ITS single-channel detection rate is 69%; the dual-channel parallel fusion detection rate is 91% (false alarm rate 4.7%), which is about 18 percentage points higher than the optimal single channel; the dual-channel intersection fusion false alarm rate is reduced to 0.8%, which is suitable for high-precision alarm scenarios.

[0067] exist Under these conditions, the detection rate of FCS single channel decreased to 51%, and that of ITS single channel decreased to 47%; the detection rate of dual-channel parallel fusion remained at 72%, verifying the robust advantage of dual-channel complementarity.

[0068] Furthermore, to further analyze the adaptability and resource allocation strategies of this method under different hardware platforms, the following describes the system's function reuse mechanism and performance trade-offs in scenarios with limited logical resources: In platforms with more limited logic resources (such as Zynq-7010, where LUT resources are only 50% of those in Zynq-7020), a time-slot control state machine can be used to reuse the frequency domain analysis unit to perform auxiliary frequency domain pre-screening (such as broadband energy detection), while the delay line unit, conjugate multiplication unit, and sliding window accumulation unit in the ITS channel continue to run at full speed. Time-slot multiplexing does not affect the core processing logic of the FCS channel's frequency hopping determination based on time-series frequency point sequences and the ITS channel's image transmission determination based on time-domain correlation peaks. It only reduces the pre-screening granularity (frequency resolution decreases from 15.6 kHz to 31.2 kHz), resulting in an overall detection performance decrease of about 3-5 percentage points, which is acceptable in resource-constrained scenarios.

[0069] Through the steps S401 to S405 above, by heterogeneously setting up a frequency domain processing channel for flight control frequency hopping characteristics and a time domain correlation processing channel for image transmission signal cyclic prefix within the same field-programmable gate array (FPGA) on-chip system, the problems of insufficient real-time performance and unbalanced allocation of logic resources in the unified processing architecture caused by the characteristic differences between flight control frequency hopping signals and image transmission signals are solved, achieving comprehensive detection with microsecond-level low latency and low power consumption. At the same time, the dual-port block memory mechanism ensures the synchronization security of cross-clock domain data interaction, and the multi-mode fusion strategy significantly improves the detection sensitivity and recognition accuracy in complex channel environments.

[0070] In one embodiment, Figure 8 This is a schematic diagram of the internal structure of a computer device according to an embodiment of this application. For example... Figure 8 As shown, a computer device is provided, which can be an in-vehicle computing unit or a cloud server. The computer device includes a processor, a network interface, internal memory, and non-volatile memory connected via an internal bus. The non-volatile memory stores parameters related to the operating system, computer programs, and a large language model. The processor provides computing power to execute deep neural network inference and control algorithm operations. When the processor executes the stored computer program, it implements a real-time UAV signal detection method as described in any of the above embodiments.

[0071] Those skilled in the art will understand that Figure 8The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0072] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by hardware related to computer program instructions. This computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0073] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A real-time signal detection system for unmanned aerial vehicles (UAVs), characterized in that, This includes a response module, a signal processing module, and a fusion decision module integrated into the FPGA programmable logic and processor, wherein: The response module is used to receive radio signals in the target frequency band and output I / Q baseband signals, and distribute the I / Q baseband signals to the signal processing module; The signal processing module, located at the programmable logic terminal of the FPGA, is used to downsample and perform frame-by-frame frequency domain transformation on the I / Q baseband signal through the flight control signal processing channel, extract the frequency index of the maximum spectral energy of each frame to construct a time-series frequency point sequence, and output the flight control frequency hopping determination result based on the change in adjacent frame indexes and the dwell time of a single frequency point in the time-series frequency point sequence. The signal processing module is also used to perform conjugate correlation and sliding window accumulation on the I / Q baseband signal and its delayed signal through a picture transmission signal processing channel that is parallel to the flight control signal processing channel, extract the periodic correlation peak of the cyclic prefix of the orthogonal frequency division multiplexing signal, and output the picture transmission judgment result according to the dynamic threshold. The fusion decision module, located on the processor, is used to receive the flight control frequency hopping determination result and the image transmission determination result, and output the UAV detection result according to the preset parameter library and fusion strategy.

2. The system according to claim 1, characterized in that, The flight control signal processing channel includes: a decimation filtering unit, a frequency domain transformation unit, a peak index extraction unit, and a frequency hopping determination unit, wherein: The decimation filtering unit employs a cascaded integrator comb filter to downsample the I / Q baseband signal, obtaining a downsampled signal with a preset sampling rate that matches the bandwidth of the flight control signal. The frequency domain transformation unit is used to perform frame-by-frame fast Fourier transform on the downsampled signal and output the energy spectrum of each frequency point. The peak index extraction unit adopts a pipelined comparison tree structure to perform parallel comparisons of the energy values ​​of each frequency point within a preset clock cycle, and to determine the index of the frequency point with the maximum energy in the current frame and its corresponding maximum energy value. The frequency hopping determination unit is used to store the maximum energy frequency index into a sliding buffer to construct a time-series frequency sequence, and output the flight control frequency hopping determination result when it detects that the change in the adjacent frame index is greater than a preset change threshold and the dwell time of a single frequency point meets the preset dwell frame number range.

3. The system according to claim 1, characterized in that, The image transmission signal processing channel includes: a delay line unit, a conjugate multiplication unit, a sliding window accumulation unit, and a threshold comparison unit, wherein: The delay line unit is implemented using a block random access memory and is used to output a delayed signal with a preset sampling point. The conjugate multiplication unit is used to calculate the conjugate product of the currently input I / Q baseband signal and the delayed signal; The sliding window accumulation unit is used to perform recursive calculations based on the historical conjugate product values ​​output by the conjugate multiplication unit, thereby realizing the relevant accumulation within a preset sliding window length and obtaining the relevant accumulation result at the current moment. The threshold comparison unit is used to estimate the background noise power by performing a moving average on the I / Q baseband signal, and dynamically determine the dynamic threshold based on the background noise power. When the correlation accumulation result exceeds the dynamic threshold, the image transmission judgment result is output.

4. The system according to claim 3, characterized in that, In the image transmission signal processing channel: The conjugate multiplication unit is specifically used to calculate the conjugate product. ; The sliding window accumulation unit is specifically used for calculation. ; Where x(t) is the I / Q baseband signal at the current moment. The delayed signal, Let t be the delay length, t be the index of the current sampling point, L be the sliding window length, and W(t) be the sum of the sliding window at the current time t.

5. The system according to claim 1, characterized in that, The system also includes a cross-clock domain caching module, wherein: The cross-clock domain cache module is implemented using a dual-port block random access memory. The flight control signal processing channel and the image transmission signal processing channel are located in the write clock domain. The flight control frequency hopping determination result and the image transmission determination result are written into the cross-clock domain cache module. The fusion decision module is located in the read clock domain and reads the corresponding decision result from the cross-clock domain cache module across clock domains.

6. The system according to claim 1, characterized in that, The parameter library stores at least one of the following: frequency hopping dwell time range, frequency point change threshold, cyclic prefix length, and symbol length; The fusion strategies supported by the fusion decision module include: Union mode: An alarm is triggered if any one of the flight control signal processing channels or the image transmission signal processing channel outputs a positive result. Intersection mode: An alarm is triggered when both the flight control signal processing channel and the image transmission signal processing channel output a positive result simultaneously. Weighted mode: The current flight control frequency hopping matching confidence and the normalized amplitude of the image transmission related peak are weighted and fused. An alarm is triggered when the weighted result exceeds the comprehensive threshold.

7. The system according to claim 1, characterized in that, When the logic resources of the FPGA programmable logic terminal are limited, the flight control signal processing channel is used to perform auxiliary frequency domain pre-screening by multiplexing the internal frequency domain transformation unit through the time slot control state machine. The delay line unit, conjugate multiplication unit and sliding window accumulation unit in the image transmission signal processing channel keep running at full speed without interruption.

8. A method for real-time detection of UAV signals, characterized in that, The method, implemented by integrating a response module, a signal processing module, and a fusion decision module into the FPGA programmable logic terminal and the processor terminal, includes: The response module receives radio signals in the target frequency band and outputs I / Q baseband signals, and distributes the I / Q baseband signals to the flight control signal processing channel and the image transmission signal processing channel. The signal processing module performs downsampling and frame-by-frame frequency domain transformation on the I / Q baseband signal, extracts the frequency index of the maximum spectral energy of each frame to construct a time-series frequency point sequence, and outputs the flight control frequency hopping determination result based on the change in adjacent frame indices and the dwell time of a single frequency point in the time-series frequency point sequence. In addition, through the image transmission signal processing channel parallel to the flight control signal processing channel, the I / Q baseband signal and its delayed signal are subjected to conjugate correlation and sliding window accumulation, the periodic correlation peak of the cyclic prefix of the orthogonal frequency division multiplexing signal is extracted, and the image transmission judgment result is output according to the dynamic threshold. The fusion decision module receives the flight control frequency hopping determination result and the image transmission determination result, and outputs the UAV detection result according to the preset parameter library and fusion strategy.

9. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, The processor executes the computer program to implement the method as described in claim 8.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the method as described in claim 8.

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