GaN HEMT device and process for fabricating the same

Abstract

The application provides a GaN HEMT device and a preparation process thereof, and relates to the technical field of semiconductors. The GaN HEMT device comprises a barrier layer, a gate structure and a field plate. The gate structure is arranged above the barrier layer. The bottom of the field plate covers the barrier layer, the top of the field plate covers the gate structure, and the distance between the field plate and the gate structure is greater than the distance between the field plate and the barrier layer. According to the application, the distance between the field plate and the gate structure is increased, so that the gate charge can be optimized without affecting the electric field distribution.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a GaN HEMT device and its fabrication process. Background Technology

[0002] Gallium nitride high electron mobility transistors (GaN HEMTs) are constructed by epitaxially growing a gallium nitride (GaN) channel layer and an aluminum gallium nitride (AlGaN) barrier layer on a silicon (Si) or silicon carbide (SiC) substrate. A two-dimensional electron gas is formed at the interface using the heterojunction polarization effect to create a conductive channel, and current control is achieved through the source (S), drain (D), and gate (G). Enhancement-mode GaN HEMTs are built upon GaN HEMTs by introducing a p-type doped layer (p-GaN) under the gate or by etching to thin the barrier layer, thereby raising the barrier under the gate.

[0003] The field plate is a key optimized component in GaN HEMT devices. It refers to a small metal cantilever that extends from the gate or source metal through the dielectric layer to the gate-drain junction. The field plate redistributes the surface electric field using its own potential, smoothing out the high electric field peak that was originally concentrated at the gate edge, thereby improving the breakdown voltage of GaN HEMT devices and suppressing current collapse.

[0004] However, existing field plate structures make it difficult to optimize the gate charge without affecting the electric field distribution. Summary of the Invention

[0005] This invention provides a GaN HEMT device and its fabrication process to address the shortcomings of existing field plate structures that make it difficult to optimize gate charge without affecting the electric field distribution.

[0006] The present invention provides a GaN HEMT device, including a barrier layer, a gate structure, and a field plate. The gate structure is disposed above the barrier layer, the bottom of the field plate covers the barrier layer, the top of the field plate covers the gate structure, and the distance between the field plate and the gate structure is greater than the distance between the field plate and the barrier layer.

[0007] According to a GaN HEMT device provided by the present invention, an under-gate doped layer is disposed between the gate structure and the barrier layer.

[0008] According to a GaN HEMT device provided by the present invention, the distance between the field plate and the gate structure and the distance between the field plate and the sidewall of the under-gate doped layer are both greater than the distance between the field plate and the barrier layer.

[0009] According to a GaN HEMT device provided by the present invention, the gate structure includes a gate metal, a first insulating medium disposed on top of the gate metal, and a second insulating medium disposed on both sides of the gate metal; the hardness and density of the second insulating medium are greater than or equal to the hardness and density of the first insulating medium.

[0010] According to a GaN HEMT device provided by the present invention, the sum of the longitudinal width of the gate metal and the longitudinal width of the second insulating dielectric on both sides of the gate metal is the same as the longitudinal width of the under-gate doped layer. The top of the field plate covers the connection between the gate metal and the second insulating dielectric near the side of the field plate. The distance between the under-gate doped layer and the field plate has the greatest influence coefficient on the gate charge.

[0011] According to a GaN HEMT device provided by the present invention, a second insulating medium with a thickness not exceeding a thickness threshold is provided on top of the first insulating medium.

[0012] According to a GaN HEMT device provided by the present invention, the top of the field plate extends along a first direction covering the gate structure, and the bottom of the field plate extends along a second direction covering the barrier layer, wherein the first direction is opposite to the second direction, and the distance between the top and bottom of the field plate is determined based on the gate structure.

[0013] According to a GaN HEMT device provided by the present invention, given that the height of the field plate is determined, the distance between the top of the field plate and the top of the gate structure is greater than the height of the field plate, and the longitudinal height of the first gate structure is determined, the longitudinal distance between the top of the field plate and the barrier layer is determined based on the distance between the top of the field plate and the top of the gate structure and the longitudinal height of the gate structure. Then, based on the longitudinal distance between the top of the field plate and the barrier layer and the longitudinal distance between the bottom of the field plate and the barrier layer, the distance between the top of the field plate and the bottom of the field plate is obtained.

[0014] This invention also provides a GaN HEMT device fabrication process, comprising: Obtain the gate charge optimization requirements and field plate height of the GaN HEMT device, and determine the design structure of the GaN HEMT device based on the gate charge optimization requirements and the field plate height; Based on the design structure of the GaN HEMT device, the GaN HEMT device was fabricated. The GaN HEMT device includes a barrier layer, a gate structure, and a field plate. The gate structure is disposed above the barrier layer. The bottom of the field plate covers the barrier layer, and the top of the field plate covers the gate structure. The distance between the field plate and the gate structure is greater than the distance between the field plate and the barrier layer.

[0015] According to the present invention, a GaN HEMT device is provided, wherein a gate-under-gate doped layer is disposed between the gate structure and the barrier layer of the GaN HEMT device, and the fabrication of the GaNHEMT device based on the design structure of the GaN HEMT device includes: The barrier layer and the gate-below doped layer are prepared using an epitaxial growth process. The gate metal and the first insulating dielectric are fabricated on the barrier layer using a hard mask etching process. A second insulating dielectric layer is prepared on both sides of the gate metal and on top of the first insulating dielectric using a sidewall deposition process, and the second insulating dielectric layer is processed using a full-surface etching process to obtain the second insulating dielectric. The gate metal and the second insulating dielectric on both sides of the gate metal are used as a mask to etch the under-gate doped layer; The GaN HEMT device is obtained by fabricating the lower dielectric, the field plate, and the upper dielectric using a deposition process.

[0016] This invention provides a GaN HEMT device and its fabrication process. The GaN HEMT device includes a barrier layer, a gate structure, and a field plate. The gate structure is disposed above the barrier layer. The bottom of the field plate covers the barrier layer, and the top of the field plate covers the gate structure. The distance between the field plate and the gate structure is greater than the distance between the field plate and the barrier layer. By increasing the distance between the field plate and the gate structure, this invention optimizes the gate charge without affecting the electric field distribution. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the structure of an existing enhanced GaN HEMT device.

[0019] Figure 2 This is a schematic diagram of the fabrication process of existing enhancement-mode GaN HEMT devices.

[0020] Figure 3 This is a schematic diagram of the structure of the GaN HEMT device provided by the present invention.

[0021] Figure 4 This is a schematic diagram of the structure of the enhanced GaN HEMT device provided by the present invention.

[0022] Figure 5 This is a schematic flowchart of the GaN HEMT device fabrication process provided by the present invention.

[0023] Figure 6 This is a schematic diagram of the fabrication process of the enhanced GaN HEMT device provided by the present invention.

[0024] Figure label: 1-Barrier layer, 2-Gate metal, 3-Field plate, 301-Top of field plate, 302-Bottom of field plate, 4-Undergate doped layer, 5-Lower dielectric, 6-Upper dielectric. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0026] During their research, the inventors discovered that in GaN HEMT devices, the distances between the field plate and the gate, as well as the distances between the field plate and the AlGaN barrier layer, are essentially the same. In enhancement-mode GaN HEMT devices, the shape of the field plate, the distance L1 between the field plate and the gate, the distance L3 (i.e., the field plate height) between the field plate and the AlGaN barrier layer, and the distance L2 between the field plate and the sidewall of the p-GaN doped layer are affected by the thickness of the dielectric under the field plate. When the thickness of the dielectric under the field plate needs to be kept at the optimal thickness, the distances between the field plate and the gate, the distances between the field plate and the AlGaN barrier layer (i.e., the field plate height), and the distances between the field plate and the sidewall of the p-GaN doped layer are essentially the same. The gate charge is large and difficult to optimize. Optimization would lead to changes in the dielectric under the field plate and the field plate height.

[0027] Figure 1 This is a schematic diagram of the structure of an existing enhancement-mode GaN HEMT device. Figure 2 This is a schematic diagram illustrating the fabrication process of existing enhancement-mode GaN HEMT devices, as shown below. Figure 1 and Figure 2As shown, in existing enhancement-mode GaN HEMT devices, the distances L1 between the field plate and the gate, L3 between the field plate and the AlGaN barrier layer, and L2 between the field plate and the sidewall of the p-GaN doped layer are basically the same. The distance between the field plate and the AlGaN barrier layer is a key factor in determining the electric field distribution. Therefore, it is difficult for existing field plate structures to optimize the gate charge without affecting the electric field distribution.

[0028] To address this, the present invention proposes a GaN HEMT device and its fabrication process, which solves the problem that existing field plate structures are difficult to optimize gate charge without affecting the electric field distribution. The following is a detailed description in conjunction with the accompanying drawings.

[0029] Figure 3 This is a schematic diagram of the GaN HEMT device provided by the present invention, as shown below. Figure 3 As shown, the present invention provides a GaNHEMT device, including a barrier layer 1, a gate structure and a field plate 3. The gate structure is disposed above the barrier layer 1. The bottom of the field plate 3 covers the barrier layer 1, and the top of the field plate 3 covers the gate structure. The distance between the field plate 3 and the gate structure is greater than the distance between the field plate 3 and the barrier layer 1.

[0030] The bottom of the field plate 302 is parallel to the barrier layer 1, extending horizontally to cover part of the barrier layer 1. The top of the field plate 301 is parallel to the upper surface of the gate structure, extending horizontally to cover part of the gate structure. The distance L1 between the field plate 3 and the gate structure refers to the longitudinal distance between the lower surface of the top of the field plate 301 and the upper surface of the gate structure. The distance L3 between the field plate 3 and the barrier layer 1 refers to the longitudinal distance between the lower surface of the bottom of the field plate 302 and the upper surface of the barrier layer 1. The extension directions of the top of the field plate 301 and the bottom of the field plate 302 are different.

[0031] It is understood that the present invention adjusts the relationship between the distance L1 between the field plate 3 and the gate structure and the distance L3 between the field plate 3 and the barrier layer 1, so that the distance L1 between the field plate 3 and the gate structure is greater than the distance L3 between the field plate 3 and the barrier layer 1. This solves the problem of large gate charge caused by the distance between the field plate 3 and the gate and the distance between the field plate 3 and the AlGaN barrier layer 1 being basically the same, and optimizes the gate charge without affecting the electric field distribution.

[0032] Figure 4 This is a schematic diagram of the structure of the enhanced GaN HEMT device provided by the present invention, as shown below. Figure 4 As shown, in an optional embodiment, a gate-below doped layer 4 is disposed between the gate structure and the barrier layer 1. The gate-below doped layer 4 is used to characterize the doped layer below the gate structure, and the gate-below doped layer 4 may be made of p-GaN material.

[0033] In this embodiment of the invention, a gate-below doped layer 4 is provided between the gate structure and the barrier layer 1 to obtain an enhancement-mode GaN HEMT device. The gate-below doped layer 4 has the same lateral dimension as the gate structure, which changes the structure of the field plate 3, making it easier to adjust the relationship between the distance L1 between the field plate 3 and the gate structure and the distance L3 between the field plate 3 and the barrier layer 1.

[0034] In an enhancement-mode GaN HEMT device, the bottom of the field plate 302 is parallel to the barrier layer 1 and extends horizontally to cover part of the barrier layer 1. The top of the field plate 301 is parallel to the upper surface of the gate structure and extends horizontally to cover part of the gate structure. The field plate 3 structure between the top of the field plate 301 and the bottom of the field plate 302 is longitudinally parallel to the sidewall of the gate structure and the sidewall of the under-gate doped layer 4, respectively. The distance L1 between the field plate 3 and the gate structure refers to the longitudinal distance between the lower surface of the top of the field plate 301 and the upper surface of the gate structure. The distance L2 between the field plate 3 and the sidewall of the under-gate doped layer 4 refers to the horizontal distance between the field plate 3 and the sidewall of the under-gate doped layer 4. The distance L3 between the field plate 3 and the barrier layer 1 refers to the longitudinal distance between the lower surface of the bottom of the field plate 302 and the upper surface of the barrier layer 1. In an enhancement-mode GaN HEMT device, the distance L1 between the field plate 3 and the gate structure is greater than the distance L3 between the field plate 3 and the barrier layer 1, or the distance L1 between the field plate 3 and the gate structure and the distance L2 between the field plate 3 and the sidewall of the under-gate doped layer 4 are both greater than the distance L3 between the field plate 3 and the barrier layer 1.

[0035] It is understood that the present invention adjusts the relationship between the distance L1 between the field plate 3 and the gate structure and the distance L3 between the field plate 3 and the barrier layer 1 in the enhancement-mode GaN HEMT device, or simultaneously adjusts the relationship between the distance L1 between the field plate 3 and the gate structure, the distance L2 between the field plate 3 and the sidewall of the under-gate doped layer 4 and the distance L3 between the field plate 3 and the barrier layer 1, so that at least the distance L1 between the field plate 3 and the gate structure is greater than the distance L3 between the field plate 3 and the barrier layer 1. This solves the problem that the distances between the field plate 3 and the gate, the distances between the field plate 3 and the AlGaN barrier layer 1, and the distances between the field plate 3 and the sidewall of the p-GaN doped layer are basically the same, resulting in a large gate charge. The gate charge can be optimized without affecting the electric field distribution.

[0036] As an optional embodiment, the distance between the field plate 3 and the gate structure, and the distance between the field plate 3 and the sidewall of the under-gate doped layer 4, are both greater than the distance between the field plate 3 and the barrier layer 1. The distance L3 between the field plate 3 and the barrier layer 1 is the same as the height of the existing field plate 3.

[0037] Optionally, the distance L1 between the field plate 3 and the gate structure is the same as the distance L2 between the field plate 3 and the sidewall of the under-gate doped layer 4.

[0038] Optionally, the distance L1 between the field plate 3 and the gate structure is different from the distance L2 between the field plate 3 and the sidewall of the under-gate doped layer 4.

[0039] Optionally, the distance L1 between the field plate 3 and the gate structure, and the distance L2 between the field plate 3 and the sidewall of the under-gate doped layer 4 are both greater than the distance L3 between the field plate 3 and the barrier layer 1.

[0040] It is understood that the present invention simultaneously adjusts the relationship between the distance L1 between the field plate 3 and the gate structure, the distance L2 between the field plate 3 and the sidewall of the under-gate doped layer 4, and the distance L3 between the field plate 3 and the barrier layer 1, so that the distance L1 between the field plate 3 and the gate structure, and the distance L2 between the field plate 3 and the sidewall of the under-gate doped layer 4 are all greater than the distance L3 between the field plate 3 and the barrier layer 1. This solves the problem that the distance between the field plate 3 and the gate, the distance between the field plate 3 and the AlGaN barrier layer 1, and the distance between the field plate 3 and the sidewall of the p-GaN doped layer are basically the same, resulting in a large gate charge. The gate charge can be optimized without affecting the electric field distribution.

[0041] As an optional embodiment, the gate structure includes a gate metal 2, a first insulating medium disposed on top of the gate metal 2, and a second insulating medium disposed on both sides of the gate metal 2; the hardness and density of the second insulating medium are greater than or equal to the hardness and density of the first insulating medium.

[0042] Optionally, the first insulating medium can be made of silicon dioxide (SiO2) material, and the second insulating medium can be made of silicon dioxide (SiO2) material or silicon nitride (SiN) material, for protecting the gate metal 2. Silicon nitride (SiN) material has greater hardness and density than silicon dioxide (SiO2) material.

[0043] Optionally, a second insulating medium with a thickness not exceeding a thickness threshold is provided on top of the first insulating medium. In the gate structure, the second insulating medium covers the gate metal 2 and the first insulating medium during the growth process. The second insulating medium is etched to obtain the final gate structure. Having a second insulating medium with a thickness not exceeding a thickness threshold on top of the first insulating medium can reduce the fabrication difficulty. The thickness threshold is much smaller than the thickness of the first insulating medium.

[0044] It is understood that the embodiments of the present invention provide a first insulating medium and a second insulating medium to protect the gate metal 2. In addition, the second insulating medium can also adjust the distance between the field plate 3 and the sidewall of the gate metal 2 in order to optimize the gate charge.

[0045] As an optional embodiment, the sum of the longitudinal width of the gate metal 2 and the longitudinal width of the second insulating medium on both sides of the gate metal 2 is the same as the longitudinal width of the under-gate doped layer 4. The top of the field plate 3 covers the connection between the gate metal 2 and the second insulating medium near the side of the field plate 3. The distance between the under-gate doped layer 4 and the field plate 3 has the greatest influence coefficient on the gate charge.

[0046] Optionally, the gate metal 2 and the second insulating dielectric on both sides of the gate metal 2 are used as a mask to etch the under-gate doped layer 4. Optionally, the under-gate doped layer 4 is a p-type GaN doped layer.

[0047] Optionally, the top of the field plate 301 covers the connection between the gate metal 2 and the second insulating medium near the side of the field plate 3, so as to avoid covering too much of the second gate structure, which would affect the performance of the enhancement-mode GaN HEMT device.

[0048] Optionally, since the distance between the under-gate doped layer 4 and the field plate 3 has the greatest influence on the gate charge of the enhancement-mode GaN HEMT device, during the design simulation of the enhancement-mode GaN HEMT device, after determining the size of the field plate 3, the performance of the enhancement-mode GaN HEMT device can be further improved by adjusting the lateral distance between the field plate 3 and the under-gate doped layer 4.

[0049] It is understood that the embodiments of the present invention limit the influence coefficients of the longitudinal width of the gate metal 2 and the sum of the longitudinal widths of the second insulating dielectrics on both sides of the gate metal 2, the longitudinal width of the under-gate doped layer 4, the top coverage position of the field plate 3, and the gate charge of the enhancement-type GaN HEMT device, which is beneficial to improving the performance of the enhancement-type GaN HEMT device.

[0050] As an optional embodiment, the top of the field plate 3 extends along a first direction covering the gate structure, and the bottom of the field plate 3 extends along a second direction covering the barrier layer 1, the first direction being opposite to the second direction, and the distance between the top and bottom of the field plate 3 is determined based on the gate structure.

[0051] Optionally, the field plate 3 is disposed between the gate and drain of the GaN HEMT device. The first direction is away from the drain of the GaN HEMT device and extends towards the first gate structure to protect the first gate structure and reduce Miller capacitance. The second direction is close to the drain of the GaN HEMT device to increase the breakdown voltage and suppress current collapse.

[0052] Optionally, the area between the top 301 and the bottom 302 of the field plate is a longitudinal plate without bending, in order to reduce the difficulty of preparation.

[0053] Optionally, given that the height of the field plate 3 is determined, the distance between the top of the field plate 3 and the top of the gate structure is greater than the height of the field plate 3, and the longitudinal height of the first gate structure is determined, the longitudinal distance between the top of the field plate 3 and the barrier layer 1 is determined based on the distance between the top of the field plate 3 and the top of the gate structure and the longitudinal height of the gate structure. Then, based on the longitudinal distance between the top of the field plate 3 and the barrier layer 1 and the longitudinal distance between the bottom of the field plate 3 and the barrier layer 1, the distance between the top of the field plate 3 and the bottom of the field plate 3 is obtained.

[0054] Specifically, in this embodiment of the invention, the height of the field plate 3, that is, the longitudinal distance between the bottom 302 of the field plate and the barrier layer 1, is not adjusted. Therefore, the longitudinal distance between the bottom 302 of the field plate and the barrier layer 1 can be referenced to the existing height of the field plate 3. When the height of the field plate 3 is determined, the distance between the top 301 of the field plate and the top of the gate structure is greater than the height of the field plate 3, and the longitudinal height of the gate structure is determined, the longitudinal distance between the top 301 of the field plate and the barrier layer 1 can be determined based on the distance between the top 301 of the field plate and the top of the gate structure and the longitudinal height of the gate structure. Then, based on the longitudinal distance between the top 301 of the field plate and the barrier layer 1 and the longitudinal distance between the bottom 302 of the field plate and the barrier layer 1, the distance between the top 301 of the field plate and the bottom 302 of the field plate can be determined.

[0055] In enhancement-mode GaN HEMT devices, this embodiment of the invention does not adjust the height of the field plate 3, that is, the longitudinal distance between the bottom 302 of the field plate and the barrier layer 1. Therefore, the longitudinal distance between the bottom 302 of the field plate and the barrier layer 1 can be referenced to the existing height of the field plate 3. When the height of the field plate 3 is determined, the distance between the top 301 of the field plate and the top of the gate structure is greater than the height of the field plate 3, the longitudinal height of the gate structure is determined, and the longitudinal height of the under-gate doped layer 4 is determined, the longitudinal distance between the top of the field plate 3 and the barrier layer 1 can be determined based on the distance between the top 301 of the field plate and the top of the gate structure, the longitudinal height of the gate structure, and the longitudinal height of the under-gate doped layer 4. Then, based on the longitudinal distance between the top of the field plate 3 and the barrier layer 1 and the longitudinal distance between the bottom of the field plate 3 and the barrier layer 1, the distance between the top of the field plate 3 and the bottom of the field plate 3 can be determined.

[0056] It is understood that the present invention extends the top of the field plate 3 along the first direction covering the gate structure and extends the bottom of the field plate 3 along the second direction covering the barrier layer 1, thereby comprehensively protecting the gate structure and reducing Miller capacitance, as well as increasing the breakdown voltage and suppressing current collapse, thus improving the performance of GaN HEMT devices. At the same time, the distance between the top of the field plate 301 and the bottom of the field plate 302 is determined according to the size of the gate structure, which can reduce the calculation difficulty.

[0057] As an optional embodiment, a lower dielectric 5 is provided between the field plate 3 and the gate structure, and an upper dielectric 6 is provided above the field plate 3.

[0058] Optionally, the lower medium 5 and the upper medium 6 can be made of the same material or different materials, including but not limited to silicon dioxide (SiO2) and silicon nitride (SiN).

[0059] Optionally, the lower dielectric 5 is used to adjust the distance between the field plate 3 and the gate structure, and the upper dielectric 6 is used to adjust the overall thickness of the dielectric layer.

[0060] It is understood that the present invention provides a lower dielectric 5 between the field plate 3 and the gate structure, and an upper dielectric 6 above the field plate 3, which is beneficial for adjusting the position of the field plate 3 and the gate structure, thereby optimizing the gate charge.

[0061] The fabrication process of the GaN HEMT device provided by the present invention is described below. The fabrication process of the GaN HEMT device described below can be referred to in correspondence with the GaN HEMT device described above.

[0062] Figure 5 This is a schematic flowchart of the GaN HEMT device fabrication process provided by the present invention, as shown below. Figure 5 As shown, the present invention also provides a GaN HEMT device fabrication process, including steps S100-S200.

[0063] Step S100: Obtain the gate charge optimization requirements and field plate height of the GaN HEMT device, and determine the design structure of the GaN HEMT device based on the gate charge optimization requirements and the field plate height.

[0064] Optionally, the field plate height can be the existing field plate height, which can be referenced to the longitudinal distance between the field plate and the barrier layer in existing GaN HEMT devices.

[0065] Optionally, gate charge optimization requirements include reducing the gate charge and improving the performance of the semiconductor device without changing the field plate height in the drift region. The field plate height in the drift region remains constant, meaning that parameters such as the off-state breakdown voltage and dynamic resistance of the semiconductor device remain unchanged.

[0066] As described above, the inventors discovered during the research process that the distance between the field plate and the gate, the distance between the field plate and the AlGaN barrier layer (i.e., the field plate height), and the distance between the field plate and the sidewall of the p-GaN doped layer are basically the same, resulting in a large gate charge. In order to meet the gate charge optimization requirements, the distance between the field plate and the gate and the distance between the field plate and the sidewall of the p-GaN doped layer in the semiconductor device were optimized to obtain the design structure of the GaN HEMT device.

[0067] Specifically, the GaN HEMT device includes a barrier layer, a gate structure, and a field plate. The gate structure is disposed above the barrier layer, the bottom of the field plate covers the barrier layer, the top of the field plate covers the gate structure, and the distance between the field plate and the gate structure is greater than the distance between the field plate and the barrier layer.

[0068] Optionally, an under-gate doped layer is disposed between the gate structure and the barrier layer.

[0069] Optionally, the distance between the field plate and the gate structure, and the distance between the field plate and the sidewall of the under-gate doped layer, are both greater than the distance between the field plate and the barrier layer.

[0070] Optionally, the gate structure includes a gate metal, a first insulating medium disposed on top of the gate metal, and a second insulating medium disposed on both sides of the gate metal; the hardness and density of the second insulating medium are greater than or equal to the hardness and density of the first insulating medium.

[0071] Optionally, the sum of the longitudinal width of the gate metal and the longitudinal width of the second insulating medium on both sides of the gate metal is the same as the longitudinal width of the under-gate doped layer. The top of the field plate covers the connection between the gate metal and the second insulating medium near the side of the field plate. The distance between the under-gate doped layer and the field plate has the greatest influence coefficient on the gate charge.

[0072] Optionally, the top of the first insulating medium is provided with a second insulating medium having a thickness not exceeding a thickness threshold.

[0073] Optionally, the top of the field plate extends along a first direction covering the gate structure, and the bottom of the field plate extends along a second direction covering the barrier layer, the first direction being opposite to the second direction, and the distance between the top and bottom of the field plate is determined based on the gate structure.

[0074] Optionally, given that the height of the field plate is determined, the distance between the top of the field plate and the top of the gate structure is greater than the height of the field plate, and the longitudinal height of the first gate structure is determined, the longitudinal distance between the top of the field plate and the barrier layer is determined based on the distance between the top of the field plate and the top of the gate structure and the longitudinal height of the gate structure. Then, based on the longitudinal distance between the top of the field plate and the barrier layer and the longitudinal distance between the bottom of the field plate and the barrier layer, the distance between the top of the field plate and the bottom of the field plate is obtained.

[0075] Step S200: Based on the design structure of the GaN HEMT device, the GaN HEMT device is fabricated.

[0076] It is understood that the present invention can optimize the gate charge without affecting the electric field distribution by increasing the distance between the field plate and the gate structure, or by increasing the distance between the field plate and the gate structure and the under-gate doped layer respectively.

[0077] As an example, the gate structure includes a gate metal, a first insulating dielectric disposed on top of the gate metal, and a second insulating dielectric disposed on both sides of the gate metal. The fabrication steps for the non-enhanced GaN HEMT device are as follows.

[0078] The first barrier layer was prepared using an epitaxial growth process.

[0079] Specifically, when fabricating a barrier layer on a GaN channel layer using epitaxial growth technology, it is important to note that when growing on a heterogeneous substrate (such as Si), a complex AlN / AlGaN buffer layer structure must be designed to absorb lattice mismatch and thermal mismatch stress, and the dislocation density must be strictly controlled. During the fabrication of the barrier layer, the uniformity of Al composition (typically 15%–30%) and layer thickness (approximately 10–30 nm) must be precisely controlled, and the growth temperature must be optimized to obtain a high-concentration, high-mobility two-dimensional electron gas (2DEG) and a target threshold voltage (Vth).

[0080] The gate metal and the first insulating dielectric are fabricated on the barrier layer using a hard mask etching process.

[0081] Specifically, the process for defining the gate metal based on the hard mask etching process includes: first, photolithography and etching of the first insulating medium in the gate region to form a hard mask window; then, deposition of gate metal (such as Ni / Au) over the entire wafer; finally, removal of the hard mask and the metal above it by wet etching or lift-off process, leaving only the gate within the window. During the fabrication process, the etching selectivity must be strictly controlled to prevent over-etching from damaging the underlying barrier layer.

[0082] A second insulating dielectric layer is prepared on both sides of the gate metal and on top of the first insulating dielectric using a sidewall deposition process, and the second insulating dielectric layer is processed using a full-surface etching process to obtain the second insulating dielectric.

[0083] Specifically, in the process of preparing the second insulating dielectric layer on both sides of the gate metal and on top of the first insulating dielectric based on the deposition sidewall process, the key is to utilize the physical properties of conformal deposition and anisotropic etching to form the second insulating dielectric layer on both sides of the gate metal.

[0084] During the process of processing the second insulating dielectric layer using the whole-surface etching process, the key is to precisely control the etching to stop at the surface of the barrier layer. By using the etching selectivity ratio, an over-etching time window is set to prevent the breakdown of the extremely thin barrier layer and damage to the 2DEG channel.

[0085] The GaN HEMT device is obtained by fabricating the lower dielectric, the field plate, and the upper dielectric using a deposition process.

[0086] Specifically, for the dielectric material fabricated using the deposition process, the deposition temperature must be below the tolerance limit of the gate metal to prevent metal degradation. The field plate is defined by photolithography, and metals such as Ni / Au are deposited using electron beam evaporation or sputtering. A clear outline is formed through lift-off or etching, and it is strictly forbidden for the field plate edges to be suspended. Then, the dielectric material is deposited a second time on the field plate, and the thickness of the dielectric material is controlled to prevent device frequency characteristic degradation due to excessive capacitive coupling.

[0087] Figure 6 This is a schematic diagram of the fabrication process of the enhanced GaN HEMT device provided by the present invention, as shown below. Figure 6 As shown, in an optional embodiment, a gate-under doped layer is disposed between the gate structure and the barrier layer of the GaN HEMT device. The gate structure includes a gate metal, a first insulating dielectric disposed on top of the gate metal, and a second insulating dielectric disposed on both sides of the gate metal. The fabrication of the GaNHEMT device based on the design structure of the GaN HEMT device includes the following steps.

[0088] The barrier layer and the gate-below doped layer are prepared using an epitaxial growth process.

[0089] Specifically, when fabricating a barrier layer on a GaN channel layer using epitaxial growth technology, it is important to note that when growing on a heterogeneous substrate (such as Si), a complex AlN / AlGaN buffer layer structure must be designed to absorb lattice mismatch and thermal mismatch stress, and the dislocation density must be strictly controlled. During the fabrication of the barrier layer, the uniformity of Al composition (typically 15%–30%) and layer thickness (approximately 10–30 nm) must be precisely controlled, and the growth temperature must be optimized to obtain a high-concentration, high-mobility two-dimensional electron gas (2DEG) and a target threshold voltage (Vth).

[0090] The gate metal and the first insulating dielectric are fabricated on the barrier layer using a hard mask etching process.

[0091] Specifically, the process for defining the gate metal based on the hard mask etching process includes: first, photolithography and etching of the second insulating medium in the gate region to form a hard mask window; then, deposition of gate metal (such as Ni / Au) over the entire wafer; finally, removal of the hard mask and the metal above it by wet etching or lift-off process, leaving only the gate within the window. During the fabrication process, the etching selectivity must be strictly controlled to prevent over-etching from damaging the underlying barrier layer.

[0092] A second insulating dielectric layer is prepared on both sides of the gate metal and on top of the first insulating dielectric using a sidewall deposition process, and the second insulating dielectric layer is processed using a full-surface etching process to obtain the second insulating dielectric.

[0093] Specifically, in the process of preparing the second insulating dielectric layer on both sides of the gate metal and on top of the first insulating dielectric based on the deposition sidewall process, the key is to utilize the physical properties of conformal deposition and anisotropic etching to form the second insulating dielectric layer on both sides of the gate metal.

[0094] During the process of processing the second insulating dielectric layer using the whole-surface etching process, the key is to precisely control the etching to stop at the surface of the barrier layer. By using the etching selectivity ratio, an over-etching time window is set to prevent the extremely thin second barrier layer from being penetrated, which would cause damage to the 2DEG channel.

[0095] The gate metal and the second insulating dielectric on both sides of the gate metal are used as a mask to etch the under-gate doped layer.

[0096] It should be noted that the sum of the longitudinal width of the gate metal and the longitudinal width of the second insulating dielectric on both sides of the gate metal is the same as the longitudinal width of the under-gate doped layer.

[0097] An enhanced GaN HEMT device is obtained by fabricating a lower dielectric, a field plate, and an upper dielectric using a deposition process.

[0098] Specifically, for the dielectric material fabricated using the deposition process, the deposition temperature must be below the tolerance limit of the gate metal to prevent metal degradation. The field plate is defined by photolithography, and metals such as Ni / Au are deposited using electron beam evaporation or sputtering. A clear outline is formed through lift-off or etching, and it is strictly forbidden for the field plate edges to be suspended. Then, the dielectric material is deposited a second time on the field plate, and the thickness of the dielectric material is controlled to prevent device frequency characteristic degradation due to excessive capacitive coupling.

[0099] Since the sidewall etching rate is lower than that of planar plasma etching, and a first insulating dielectric is provided above the gate metal, the gate metal is wrapped by a certain thickness of the first and second insulating dielectrics after the under-gate doped layer is etched. At this time, the dielectric is deposited and a field plate is fabricated. The distance from the field plate to the sidewall of the under-gate doped layer and the gate metal is increased. This can reduce the gate charge without changing the height of the field plate in the drift region, thereby improving the performance of the semiconductor device.

[0100] It should be noted that the semiconductor device fabrication process provided in the embodiments of the present invention has the same technical effects as the above-mentioned semiconductor devices, and will not be described again.

[0101] In this document, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” “lower,” “left,” and “right” are used for ease of description to describe the relationship between one component or feature as shown in the accompanying drawings and one or more other components or features. In addition to the orientations depicted in the accompanying drawings, the spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 80 degrees or in other orientations), and the spatial relative descriptive terms used herein may be interpreted accordingly. It should be understood that when a component is referred to as “connected to” or “coupled to” another component, the component may be directly connected to or coupled to the other component, or there may be an intermediate component.

[0102] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A GaN HEMT device, characterized by, It includes a barrier layer, a gate structure, and a field plate. The gate structure is disposed above the barrier layer. The bottom of the field plate covers the barrier layer, and the top of the field plate covers the gate structure. The distance between the field plate and the gate structure is greater than the distance between the field plate and the barrier layer.

2. The GaN HEMT device of claim 1, wherein, An under-gate doped layer is disposed between the gate structure and the barrier layer.

3. The GaN HEMT device of claim 2, wherein, The distance between the field plate and the gate structure, and the distance between the field plate and the sidewall of the under-gate doped layer, are both greater than the distance between the field plate and the barrier layer.

4. The GaN HEMT device of claim 2, wherein, The gate structure includes a gate metal, a first insulating medium disposed on top of the gate metal, and a second insulating medium disposed on both sides of the gate metal; the hardness and density of the second insulating medium are greater than or equal to the hardness and density of the first insulating medium.

5. The GaN HEMT device of claim 4, wherein, The sum of the longitudinal width of the gate metal and the longitudinal width of the second insulating medium on both sides of the gate metal is the same as the longitudinal width of the under-gate doped layer. The top of the field plate covers the connection between the gate metal and the second insulating medium near the side of the field plate. The distance between the under-gate doped layer and the field plate has the greatest influence coefficient on the gate charge.

6. The GaN HEMT device according to claim 4 or 5, characterized in that, The top of the first insulating medium is provided with a second insulating medium whose thickness does not exceed a thickness threshold.

7. The GaN HEMT device according to claim 1, characterized in that, The top of the field plate extends along a first direction covering the gate structure, and the bottom of the field plate extends along a second direction covering the barrier layer, the first direction being opposite to the second direction, and the distance between the top and bottom of the field plate is determined based on the gate structure.

8. The GaN HEMT device according to claim 7, characterized in that, Given a fixed field plate height, a distance greater than the top of the field plate and the top of the gate structure, and a fixed vertical height of the first gate structure, the vertical distance between the top of the field plate and the barrier layer is determined based on the distance between the top of the field plate and the top of the gate structure, and the vertical height of the gate structure. Then, based on the vertical distance between the top of the field plate and the barrier layer, and the vertical distance between the bottom of the field plate and the barrier layer, the distance between the top of the field plate and the bottom of the field plate is obtained.

9. A fabrication process for a GaN HEMT device, characterized in that, include: Obtain the gate charge optimization requirements and field plate height of the GaN HEMT device, and determine the design structure of the GaN HEMT device based on the gate charge optimization requirements and the field plate height; Based on the design structure of the GaN HEMT device, the GaN HEMT device was fabricated. The GaN HEMT device includes a barrier layer, a gate structure, and a field plate. The gate structure is disposed above the barrier layer. The bottom of the field plate covers the barrier layer, and the top of the field plate covers the gate structure. The distance between the field plate and the gate structure is greater than the distance between the field plate and the barrier layer.

10. The GaN HEMT device fabrication process according to claim 9, characterized in that, A gate-below doped layer is disposed between the gate structure and the barrier layer of the GaN HEMT device. The fabrication of the GaN HEMT device based on the design structure of the GaN HEMT device includes: The barrier layer and the gate-below doped layer are prepared using an epitaxial growth process. The gate metal and the first insulating dielectric are fabricated on the barrier layer using a hard mask etching process. A second insulating dielectric layer is prepared on both sides of the gate metal and on top of the first insulating dielectric using a sidewall deposition process, and the second insulating dielectric layer is processed using a full-surface etching process to obtain the second insulating dielectric. The gate metal and the second insulating dielectric on both sides of the gate metal are used as a mask to etch the under-gate doped layer; The GaN HEMT device is obtained by fabricating the lower dielectric, the field plate, and the upper dielectric using a deposition process.

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