Topcon cell and preparation method thereof

Abstract

The application discloses a kind of TopCon battery and preparation method thereof, method includes providing N-type silicon substrate;N-type silicon substrate includes front surface and back surface;Prepare front surface field layer and textured structure on front surface;Prepare first tunneling oxide layer, first intrinsic silicon layer and at least one structure layer on the side surface of first intrinsic silicon layer away from N-type silicon substrate in sequence on back surface;Element doping is carried out to structure layer using preset doping process, first doped layer is formed, and element diffusion is formed into second doped layer in first intrinsic silicon layer;N-type silicon substrate is screen printed and high-temperature sintering is carried out, to form first electrode in contact with front surface field layer on front surface, and second electrode in contact with first doped layer on back surface is formed.Using the above method, the passivation effect of the battery is improved, the recombination is reduced, and the conversion efficiency of the battery is improved.

Description

Technical Field

[0001] This invention relates to the technical field of photovoltaic cells, and more particularly to a TopCon cell and its preparation method. Background Technology

[0002] With the increasing global demand for clean energy, solar energy, as an inexhaustible energy source, has attracted much attention.

[0003] In the development of solar cell technology, TopCon cells typically form a tunneling oxide layer and a doped polycrystalline silicon layer on the back side. However, during the element doping process to form polycrystalline silicon, the single-layer ultrathin tunneling oxide layer has poor blocking effect, allowing dopants to penetrate the silicon substrate through the tunneling oxide layer, resulting in uneven diffusion, poor passivation, and low cell conversion efficiency. Summary of the Invention

[0004] This invention provides a TopCon battery and its fabrication method, which involves forming at least one structural layer on the surface of a first intrinsic silicon layer, and then using a pre-defined doping process to diffuse elements into the structural layer and the first intrinsic silicon layer to form a first doped layer and a second doped layer, without entering the first tunneling oxide layer. This allows the first tunneling oxide layer to act as a barrier, ensuring the uniformity of element diffusion and improving the passivation effect and conversion efficiency of the battery.

[0005] In a first aspect, the present invention provides a method for preparing a TopCon battery, comprising:

[0006] Provides N-type silicon substrates; N-type silicon substrates include a front side and a back side;

[0007] A front surface field layer and a textured surface structure are fabricated on the front side;

[0008] A first tunneling oxide layer, a first intrinsic silicon layer, and at least one structural layer are sequentially stacked on the back side.

[0009] Using a pre-defined doping process, the structural layer is doped with elements to form a first doped layer, and the elements are diffused into the first intrinsic silicon layer to form a second doped layer.

[0010] An N-type silicon substrate is screen-printed and sintered at high temperature to form a first electrode on the front side that contacts the front surface field layer, and a second electrode on the back side that contacts the first doped layer.

[0011] Optionally, at least one structural layer includes a second tunneling oxide layer and a second intrinsic silicon layer;

[0012] A first tunneling oxide layer, a first intrinsic silicon layer, and at least one structural layer are sequentially stacked on the back side, comprising:

[0013] A first tunneling oxide layer is formed on the back side using a first deposition process;

[0014] Using a second deposition process, under first preset conditions, a first intrinsic silicon layer is formed on the side of the first tunneling oxide layer facing away from the N-type silicon substrate;

[0015] Using a third deposition process, a second tunneling oxide layer is formed on the surface of the first intrinsic silicon layer on the side opposite to the N-type silicon substrate;

[0016] Using a fourth deposition process, under second preset conditions, a second intrinsic silicon layer is formed on the side of the second tunneling oxide layer facing away from the N-type silicon substrate;

[0017] Using a pre-defined doping process, the structural layer is elementally doped to form a first doped layer, and the elements diffuse into the first intrinsic silicon layer to form a second doped layer, including:

[0018] Using a phosphorus diffusion process, phosphorus is doped into the second intrinsic silicon layer to form the first doped layer, and phosphorus is diffused into the first intrinsic silicon layer through the second tunneling oxide layer to form the second doped layer and the second mask layer.

[0019] Remove the second mask layer.

[0020] Optionally, the first preset conditions include a deposition temperature of 581°C-621°C and a pressure of 22 mbar-27 mbar.

[0021] Optionally, the second preset conditions include a deposition temperature of 580°C-620°C and a pressure of 22 mbar-27 mbar.

[0022] Optionally, a front surface field layer and a textured structure are fabricated on the front side, including:

[0023] Boron diffusion process is used to dope boron on the front side to form a front surface field layer.

[0024] Using a flocking process, flocking is performed on the front surface and the back surface to form a flocked structure.

[0025] Optionally, before forming the first tunneling oxide layer on the back side using the first deposition process, the method further includes:

[0026] The textured surface on the back is removed to expose the N-type silicon substrate on the back.

[0027] Optionally, before screen printing and high-temperature sintering the N-type silicon substrate to form a first electrode in contact with the front surface field layer on the front side and a second electrode in contact with the first doped layer on the back side, the method further includes:

[0028] A first protective layer is prepared on the surface of the textured structure facing away from the N-type silicon substrate, and a second protective layer is prepared on the surface of the first doped layer facing away from the N-type silicon substrate.

[0029] In a second aspect, the present invention provides a TopCon battery, including an N-type silicon substrate. The N-type silicon substrate includes a front side and a back side. The front side includes a front surface field layer, a textured structure, and a first electrode in contact with the front surface field layer. The back side includes a first tunneling oxide layer, a second doped layer, at least one structural layer, and a second electrode stacked sequentially. The at least one structural layer includes the second tunneling oxide layer and the first doped layer. The second electrode is in contact with the first doped layer.

[0030] Optionally, the TopCon battery also includes a first protective layer and a second protective layer;

[0031] The first protective layer is located on the surface of the textured structure facing away from the N-type silicon substrate; the second protective layer is located on the surface of the first doped layer facing away from the N-type silicon substrate.

[0032] Optionally, the thickness of the first tunneling oxide layer is greater than the thickness of the second tunneling oxide layer, and the thickness of the second doped layer is less than the thickness of the first doped layer.

[0033] Optionally, the thickness of the first tunneling oxide layer is 1.8 nm to 2.2 nm.

[0034] Optionally, the thickness of the second doped layer is 10nm-50nm.

[0035] Optionally, the thickness of the second tunneling oxide layer is 0.1 nm to 0.3 nm.

[0036] Optionally, the thickness of the first doped layer is 95nm-135nm.

[0037] The technical solution of this invention provides an N-type silicon substrate, comprising a front side and a back side. A front surface field layer and a textured structure are fabricated on the front side. A first tunneling oxide layer, a first intrinsic silicon layer, and at least one structural layer on the surface of the first intrinsic silicon layer away from the N-type silicon substrate are sequentially stacked on the back side. Using a predetermined doping process, the structural layer is elementally doped to form a first doped layer, and the element diffuses into the first intrinsic silicon layer to form a second doped layer. The N-type silicon substrate is then screen-printed and sintered at high temperature to form a first electrode on the front side that contacts the front surface field layer, and a second electrode on the back side that contacts the first doped layer. By forming at least one structural layer on the surface of the first intrinsic silicon layer, and by using a predetermined doping process to allow element diffusion into the structural layer and the first intrinsic silicon layer to form the first and second doped layers without entering the first tunneling oxide layer, the first tunneling oxide layer acts as a barrier, ensuring the uniformity of element diffusion and improving the passivation effect and conversion efficiency of the battery.

[0038] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 A flowchart illustrating a method for fabricating a TopCon battery according to an embodiment of the present invention;

[0041] Figure 2 This is a process flow diagram of the fabrication process of a TopCon battery provided in an embodiment of the present invention;

[0042] Figure 3 This is a schematic diagram of the structure of a TopCon battery provided in an embodiment of the present invention;

[0043] Figure 4 A flowchart illustrating a second method for preparing a TopCon battery according to an embodiment of the present invention;

[0044] Figure 5 A flowchart illustrating a third method for preparing a TopCon battery according to an embodiment of the present invention. Detailed Implementation

[0045] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0046] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, preparation method, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0047] In one embodiment, Figure 1 This is a flowchart illustrating a method for fabricating a TopCon battery according to an embodiment of the present invention. Figure 2 This is a process flow diagram of the fabrication process of a TopCon battery provided in an embodiment of the present invention. Figure 3 This is a schematic diagram of a TopCon battery structure provided by an embodiment of the present invention. This embodiment is applicable to situations in TopCon batteries where the goal is to improve the passivation rate of iron ions and dislocations, reduce the degradation rate, and thus improve the stability and conversion efficiency of the battery. Figures 1 to 3 As shown, the method includes:

[0048] S110 provides an N-type silicon substrate.

[0049] Among them, reference Figure 2 As shown in Figure a), the N-type silicon substrate 1 includes a front side and a back side.

[0050] S120, Prepare the front surface field layer and textured structure on the front side.

[0051] The front surface field layer 31 refers to a highly doped region formed on the front surface of the N-type silicon substrate 1 through elemental doping. Typically, a p+ front surface field layer is formed on the front surface of the N-type silicon substrate 1 through boron doping to prevent photogenerated carrier recombination on the surface, thereby increasing carrier lifetime and diffusion length, and enhancing the collection efficiency of photogenerated carriers. The textured structure 32 refers to a pyramid-shaped or fluffy microstructure formed on the surface of the front surface field layer 31 through processes such as etching. This reduces sunlight reflection, increases optical path and light absorption, and improves the short-circuit current of the battery.

[0052] For details, please refer to Figure 2 As shown in Figure b), when forming the front surface field layer 31, a boron diffusion process can be used to dope the N-type silicon substrate 1 on the front side, thereby forming the front surface field layer 31. The front surface field layer 31 and the N-type silicon substrate 1 form a PN junction, which is responsible for separating photogenerated carriers (electron-hole pairs) to achieve photoelectric conversion. After forming the front surface field layer 31, a texturing process is used to texturize the surface of the front surface field layer 31 on the side away from the N-type silicon substrate 1, forming a pyramid-shaped textured structure 32.

[0053] S130. A first tunneling oxide layer, a first intrinsic silicon layer, and at least one structural layer are sequentially stacked on the back side.

[0054] The first tunneling oxide layer 21 is typically a very thin insulating layer made of silicon dioxide (SiO2). It allows majority carriers (electrons) to pass through smoothly via the tunneling effect while preventing the recombination of minority carriers (holes), thus achieving selective carrier transport, reducing surface recombination, increasing the open-circuit voltage and fill factor of the battery, and improving photoelectric conversion efficiency. The first intrinsic silicon layer is a silicon material layer with amorphous intrinsic semiconductor characteristics. Intrinsic semiconductors refer to semiconductor materials that have neither donor impurities (n-type dopants) nor acceptor impurities (p-type dopants), and their conductivity mainly depends on the generation and recombination of electron-hole pairs within the material itself. The structural layer 23 may include, but is not limited to, the second tunneling oxide layer and the second intrinsic silicon layer, and is a film structure used to improve the passivation effect of the battery and prevent elemental doping from entering the first tunneling oxide layer 21.

[0055] S140. Using a preset doping process, the structural layer is doped with elements to form a first doped layer, and the elements are diffused into the first intrinsic silicon layer to form a second doped layer.

[0056] Among them, the first doped layer 232 and the second doped layer 22 are both phosphorus-doped polycrystalline silicon layers, which are special semiconductor layers with high doping concentration formed by doping with phosphorus.

[0057] For details, please refer to Figure 2As shown in Figure c), a first tunneling oxide layer 21, a first intrinsic silicon layer, and at least one structural layer 23 on the side of the first intrinsic silicon layer away from the N-type silicon substrate are sequentially deposited on the back side using a deposition process. Then, the structural layer 23 is elementally doped using a predetermined doping process to form a first doped layer 232 with a certain concentration. The elements are then diffused into the first intrinsic silicon layer under predetermined high-temperature conditions, forming a second doped layer 22 with a certain concentration after doping. The methods for depositing the first tunneling oxide layer 21 and the first intrinsic silicon layer include, but are not limited to, low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, atomic layer deposition, or physical vapor deposition. The specific method can be determined according to the actual situation and is not limited here.

[0058] It should be noted that in this embodiment, after the formation of the first intrinsic silicon layer, element doping is not performed directly. Instead, element doping is performed after at least one structural layer 23 is formed on the surface of the first intrinsic silicon layer. This allows the elements to first diffuse into at least one structural layer 23, pass through the structural layer 23, and then diffuse into the first intrinsic silicon layer without breaking through into the first tunneling oxide layer 21. This results in the formation of a first doped layer 232 after the structural layer 23 is doped, and a second doped layer 22 after the first intrinsic silicon layer is doped. This ensures that the first tunneling oxide layer 21 can play a good blocking role between the N-type silicon substrate 1 and the second doped layer 22, thereby improving the passivation effect.

[0059] S150. Screen printing and high-temperature sintering are performed on an N-type silicon substrate to form a first electrode on the front side that contacts the front surface field layer, and a second electrode on the back side that contacts the first doped layer.

[0060] Screen printing is one of the core processes in the manufacturing of TopCon solar cells, primarily used for electrode formation. During printing, paste is precisely extruded through the mesh of a screen onto an N-type silicon substrate 1 to form the desired electrode pattern. Typically, the paste used for screen printing can include, but is not limited to, silver paste or aluminum paste. The screen-printed pattern includes metal grid lines. High-temperature sintering is used to process the electrode material screen-printed onto the cell surface at high temperatures to form good ohmic contact. The material of the metal grid lines of the first electrode 6 and the second electrode 7 can be the same or different; in this embodiment, both the first electrode 6 and the second electrode 7 are made of silver.

[0061] For details, please refer to Figure 2As shown in Figure d), the purpose of forming electrodes on the front and back sides is to convert photogenerated carriers generated by solar energy into current that flows to the external circuit. In this embodiment, screen printing is performed on the surface of the first doped layer 232 on both the front and back sides, forming metal grid lines on the surface of the first doped layer 232 and the textured structure 32 on the front side. The metal grid lines include fine grids and main grids. After forming the metal grid lines, they need to be sintered at high temperature. The conditions for high-temperature sintering can be determined according to the actual situation and are not limited here. After high-temperature sintering, the metal grid lines can enter the first doped layer 232 and the textured structure 32, so that the metal grid lines contact the first doped layer 232 and the textured structure 32 on the front side to form ohmic contacts. Specifically, after high-temperature sintering, a first electrode 6 in contact with the front surface field layer 31 is formed on the front side, and a second electrode 7 in contact with the first doped layer 232 is formed on the back side, thereby fabricating a TopCon cell. Furthermore, the first electrode 6 and the second electrode 7 have opposite polarities. When the first electrode 6 is a positive electrode, the corresponding second electrode 7 is a negative electrode; when the first electrode 6 is a negative electrode, the corresponding second electrode 7 is a positive electrode. In this embodiment, the first electrode 6 is a positive electrode and the second electrode 7 is a negative electrode.

[0062] The technical solution of this invention involves providing an N-type silicon substrate, which includes a front side and a back side. A front surface field layer and a textured structure are fabricated on the front side. A first tunneling oxide layer, a first intrinsic silicon layer, and at least one structural layer on the surface of the first intrinsic silicon layer away from the N-type silicon substrate are sequentially stacked on the back side. Using a predetermined doping process, the structural layer is elementally doped to form a first doped layer, and the element diffuses into the first intrinsic silicon layer to form a second doped layer. The N-type silicon substrate is then screen-printed and sintered at high temperature to form a first electrode on the front side that contacts the front surface field layer, and a second electrode on the back side that contacts the first doped layer. By forming at least one structural layer on the surface of the first intrinsic silicon layer, and by using a predetermined doping process to allow element diffusion into the structural layer and the first intrinsic silicon layer to form the first and second doped layers without entering the first tunneling oxide layer, the first tunneling oxide layer acts as a barrier, ensuring the uniformity of element diffusion and improving the passivation effect and conversion efficiency of the battery.

[0063] It is understood that Table 1 is a performance comparison table between a TopCon battery prepared by a conventional process and a TopCon battery prepared in this application, as provided in the embodiments of the present invention. Referring to Table 1, it can be seen that the doped layer of the stacked structure used in this embodiment improves the conversion efficiency Eta by 0.06%, the turn-on voltage Uoc by 1mV, the fill factor FF by 0.19, the short-circuit current Isc by 0.003A, the series resistance Rs remains the same, the parallel resistance Rsh is increased by 11Ω, and the reverse leakage current Irev2 is increased by 0.008A, which greatly improves the performance of the TopCon battery.

[0064]

[0065]

[0066] Figure 4 This is a flowchart illustrating a second method for fabricating a TopCon battery according to an embodiment of the present invention. This embodiment refines the fabrication method of the TopCon battery described above. For details not covered in this embodiment, please refer to the above embodiments; they will not be repeated here. Figure 3 and Figure 4 As shown, the method includes:

[0067] S210 provides an N-type silicon substrate.

[0068] S220, Prepare a front surface field layer and a textured surface structure on the front side.

[0069] S230. Using the first deposition process, a first tunneling oxide layer is formed on the back side.

[0070] The first deposition process may include, but is not limited to, low-pressure chemical vapor deposition or plasma-enhanced chemical vapor deposition.

[0071] Specifically, using the first deposition process, a first tunneling oxide layer 21 with a thickness of 2nm is generated on the surface of the N-type silicon substrate 1 by introducing a certain flow rate and volume of oxygen or nitrous oxide gas into the reaction chamber of the first deposition process under high temperature and low pressure deposition conditions, through the chemical reaction between the gas and the silicon wafer surface.

[0072] S240. Using a second deposition process, under first preset conditions, a first intrinsic silicon layer is formed on the side of the first tunneling oxide layer facing away from the N-type silicon substrate.

[0073] Optionally, the first preset conditions include a deposition temperature of 581°C-621°C and a pressure of 22 mbar-27 mbar.

[0074] The second deposition process may be the same as or different from the first deposition process; no restrictions are imposed here.

[0075] Specifically, during the formation of the first intrinsic silicon layer, a certain flow rate and volume of silane gas can be introduced into the reaction chamber of the second deposition process. Under deposition conditions of a deposition temperature of 581℃-621℃ and a reaction chamber pressure of 22mbar-27mbar, silicon atoms and hydrogen atoms are generated by the thermal decomposition of silane. The silicon atoms are deposited on the surface of the first tunneling oxide layer 21 to form the first intrinsic silicon layer.

[0076] S250. Using a third deposition process, a second tunneling oxide layer is formed on the surface of the first intrinsic silicon layer on the side opposite to the N-type silicon substrate.

[0077] The third deposition process can be the same as or different from the first deposition process; no restrictions are placed here. Furthermore, the method for depositing the second tunneling oxide layer 231 is the same as the method for forming the first tunneling oxide layer 21, and the steps described above can be referenced; they will not be repeated here. The thickness of the second tunneling oxide layer 231 is less than the thickness of the first tunneling oxide layer 21.

[0078] S260. Using the fourth deposition process, under the second preset conditions, a second intrinsic silicon layer is formed on the side of the second tunneling oxide layer facing away from the N-type silicon substrate.

[0079] Optionally, the second preset conditions include a deposition temperature of 580°C-620°C and a pressure of 22 mbar-27 mbar.

[0080] The fourth deposition process can be the same as or different from the second deposition process; no restrictions are placed here.

[0081] Specifically, during the formation of the second intrinsic silicon layer, a certain flow rate and volume of silane gas can be introduced into the reaction chamber of the fourth deposition process. Under deposition conditions of a deposition temperature of 580℃-620℃ and a reaction chamber pressure of 22mbar-27mbar, silicon atoms and hydrogen atoms are generated through the thermal decomposition of silane. The silicon atoms are deposited on the surface of the second tunneling oxide layer 231, thus forming the second intrinsic silicon layer. The thickness of the second intrinsic silicon layer is greater than that of the first intrinsic silicon layer.

[0082] S270. Using a phosphorus diffusion process, phosphorus is doped into the second intrinsic silicon layer to form a first doped layer, and phosphorus is diffused into the first intrinsic silicon layer through the second tunneling oxide layer to form a second doped layer and a second mask layer.

[0083] Among them, phosphorus diffusion process is a process of forming a polycrystalline silicon layer on an N-type silicon substrate 1 by phosphorus diffusion.

[0084] Specifically, after forming the first and second intrinsic silicon layers, phosphorus doping is required. This is achieved by introducing phosphorus oxychloride and oxygen at specific flow rates and volumes into the reaction chamber of the phosphorus diffusion process. Under certain diffusion conditions, the chemical reaction between phosphorus oxychloride, oxygen, and the N-type silicon substrate 1 allows phosphorus to diffuse sequentially into the second intrinsic silicon layer, the second tunneling oxide layer 231, and the first intrinsic silicon layer at high temperatures. This results in the second intrinsic silicon layer being doped to form the first doped layer 232, and the first intrinsic silicon layer being doped to form the second doped layer 22. Because phosphorus cannot completely diffuse into the second intrinsic silicon layer, the second tunneling oxide layer 231, and the first intrinsic silicon layer during diffusion, some residue will remain on their surfaces. This residual phosphorus will react chemically with the introduced oxygen to generate a second mask layer of a certain thickness, namely a phosphorosilicate glass layer (PSG).

[0085] S280, Remove the second mask layer.

[0086] Specifically, methods for removing the second mask layer may include, but are not limited to, chain acid removal. Solutions used in chain acid removal may include, but are not limited to, hydrofluoric acid, nitric acid, and hydrochloric acid.

[0087] S290. Screen printing and high-temperature sintering are performed on an N-type silicon substrate to form a first electrode on the front side that contacts the front surface field layer, and a second electrode on the back side that contacts the first doped layer.

[0088] The technical solution of this invention involves: forming a first tunneling oxide layer on the back side using a first deposition process; forming a first intrinsic silicon layer on the side of the first tunneling oxide layer facing away from the N-type silicon substrate using a second deposition process under a first preset condition; forming a second tunneling oxide layer on the side of the first intrinsic silicon layer facing away from the N-type silicon substrate using a third deposition process; forming a second intrinsic silicon layer on the side of the second tunneling oxide layer facing away from the N-type silicon substrate using a fourth deposition process under a second preset condition; doping the second intrinsic silicon layer with phosphorus using a phosphorus diffusion process to form a first doped layer, and diffusing phosphorus through the second tunneling oxide layer into the first intrinsic silicon layer to form a second doped layer and a second mask layer; and finally removing the second mask layer. Using the above method, the first and second doped layers are prepared, improving passivation effect and battery conversion efficiency.

[0089] Figure 5 This is a flowchart illustrating a third method for fabricating a TopCon battery according to an embodiment of the present invention. This embodiment refines the TopCon battery fabrication method compared to the previous embodiments. For details not covered in this embodiment, please refer to the previous embodiments; further elaboration is not required here. Figure 3 and Figure 5 As shown, the method includes:

[0090] S310 provides an N-type silicon substrate.

[0091] S320 utilizes a boron diffusion process to dope boron on the front side to form a front surface field layer.

[0092] Specifically, when forming the front surface field layer 31 on the front side, a boron diffusion process can be used. By introducing a certain flow rate of boron trichloride gas and oxygen into the reaction chamber of the boron diffusion process, under certain diffusion conditions, the chemical reaction between boron trichloride, oxygen and N-type silicon substrate 1 is used to diffuse boron into the N-type silicon substrate 1 on the front side, thereby forming a front surface field layer with a certain thickness on the front side.

[0093] It should be noted that, because boron cannot completely diffuse into the N-type silicon substrate 1 during diffusion, some residue will remain on its surface. The residual boron will react chemically with the introduced oxygen to form a mask layer, namely a borosilicate glass layer (BSG). In order to form a textured surface structure in the subsequent texturing process, the formed borosilicate glass layer needs to be removed using methods such as chain acid method, leaving only the front surface field layer 31.

[0094] S330 utilizes a flocking process to flock the front surface layer and the back surface to form a flocked structure.

[0095] The flocking process may include, but is not limited to, trough flocking and other processes.

[0096] Specifically, during the texturing process on the front side, a certain volume of a mixed solution of sodium hydroxide and texturing additives is added to the reaction chamber of the texturing process. Under preset texturing conditions, a pyramid-shaped textured structure is simultaneously prepared on the front and back sides to increase the surface area of ​​the N-type silicon substrate 1 and improve the light absorption efficiency.

[0097] S340: Remove the textured surface on the back to expose the N-type silicon substrate on the back.

[0098] Specifically, after forming the textured structure on the back side, the textured structure needs to be removed to expose the N-type silicon substrate 1, as the first tunneling oxide layer 21 needs to be prepared subsequently. This prepares the substrate for the subsequent preparation of the first tunneling oxide layer 21 and the second doped layer 22. The methods for removing the textured structure can include, but are not limited to, wet chemical etching and alkaline polishing, and the specific method can be determined based on the actual situation; no restrictions are imposed here.

[0099] S350. A first tunneling oxide layer, a first intrinsic silicon layer, and at least one structural layer are sequentially stacked on the back side.

[0100] S360. Using a preset doping process, the structural layer is doped with elements to form a first doped layer, and the elements are diffused into the first intrinsic silicon layer to form a second doped layer.

[0101] S370. A first protective layer is prepared on the surface of the textured structure facing away from the N-type silicon substrate, and a second protective layer is prepared on the surface of the first doped layer facing away from the N-type silicon substrate.

[0102] The first protective layer 4 includes a passivation layer and an antireflection layer, and the second protective layer 5 includes an antireflection layer. These layers reduce sunlight reflection, increase sunlight absorption, improve battery conversion efficiency, reduce surface recombination, increase carrier mobility, and enhance overall battery performance. The passivation layer may contain, but is not limited to, aluminum oxide, silicon oxide, or a combination of aluminum oxide and silicon oxide. The antireflection layer may contain, but is not limited to, silicon nitride, a combination of silicon nitride and silicon oxide, or silicon oxynitride.

[0103] Specifically, after forming the textured structure on the front side, a first protective layer 4 needs to be prepared on the side of the textured structure 32 facing away from the N-type silicon substrate 1 to reduce surface reflection of the TopCon cell, increase the surface area of ​​the TopCon cell, reduce sunlight reflection, improve the cell's light trapping effect and absorption rate of sunlight, generate more photogenerated carriers, and improve the conversion efficiency of the TopCon cell. This layer can be formed through deposition processes, which are not limited here. After preparing the first protective layer 4 on the side of the textured structure 32 facing away from the N-type silicon substrate 1, a second protective layer 5 needs to be prepared on the side of the first doped layer 232 facing away from the N-type silicon substrate 1. Using deposition processes such as plasma-enhanced chemical vapor deposition (PECVD), at a certain deposition temperature, silane (SiH4), ammonia (NH3), and nitrogen (N2) are used as source gases to deposit a silicon nitride antireflection layer of a certain thickness on the back side, further improving the passivation and antireflection performance of the cell.

[0104] S380. Screen printing and high-temperature sintering are performed on an N-type silicon substrate to form a first electrode on the front side that contacts the front surface field layer, and a second electrode on the back side that contacts the first doped layer.

[0105] The technical solution of this invention utilizes a boron diffusion process to dope boron on the front side to form a front surface field layer; a texturing process is used to texturize both the front surface field layer and the back side to form a textured structure; the textured structure on the back side is removed to expose the N-type silicon substrate; a first protective layer is prepared on the side of the textured structure facing away from the N-type silicon substrate, and a second protective layer is prepared on the side of the first doped layer facing away from the N-type silicon substrate. Using the above method, TopCon solar cells are fabricated, improving the passivation effect and conversion efficiency of the cells.

[0106] Based on the same inventive concept, continue to refer to Figure 3The present invention provides a TopCon battery, including an N-type silicon substrate 1. The N-type silicon substrate 1 includes a front side and a back side. The front side includes a front surface field layer 31, a textured structure 32, and a first electrode 6 in contact with the front surface field layer 32. The back side includes a first tunneling oxide layer 21, a second doped layer 22, at least one structural layer 23, and a second electrode 7, which are stacked sequentially. The at least one structural layer 23 includes a second tunneling oxide layer 231 and a first doped layer 232. The second electrode 7 is in contact with the first doped layer 232.

[0107] The front surface field layer 31 refers to a highly doped region formed on the front surface of the N-type silicon substrate 1 through elemental doping. Typically, a p+ front surface field layer is formed on the front surface of the N-type silicon substrate 1 through boron doping to prevent photogenerated carrier recombination on the surface, thereby increasing carrier lifetime and diffusion length, and enhancing the collection efficiency of photogenerated carriers. The textured structure 32 refers to a pyramid-shaped or velvety microstructure formed on the surface of the front surface field layer 31 through processes such as etching. This reduces sunlight reflection, increases optical path and light absorption, and improves the short-circuit current of the battery. The first tunneling oxide layer 21 and the second tunneling oxide layer 231 are typically very thin insulating layers composed of silicon dioxide (SiO2) to allow majority carriers (electrons) to pass smoothly through the tunneling effect while preventing the recombination of minority carriers (holes). The first doped layer 232 and the second doped layer 22 are both phosphorus-doped polycrystalline silicon layers, a special type of semiconductor layer with a high doping concentration formed by doping with phosphorus.

[0108] It is understood that the technical solutions provided in the embodiments of the present invention have the corresponding functional modules and beneficial effects of the execution method, which will not be elaborated here.

[0109] Optional, continue to refer to Figure 3 The TopCon cell also includes a first protective layer 4 and a second protective layer 5; the first protective layer 4 is located on the side surface of the textured structure 32 facing away from the N-type silicon substrate 1; the second protective layer 5 is located on the side surface of the first doped layer 232 facing away from the N-type silicon substrate 1.

[0110] The first protective layer 4 includes a passivation layer and an antireflection layer, and the second protective layer 5 includes an antireflection layer. These layers reduce sunlight reflection, increase sunlight absorption, improve battery conversion efficiency, reduce surface recombination, increase carrier mobility, and enhance overall battery performance. The passivation layer may contain, but is not limited to, aluminum oxide, silicon oxide, or a combination of aluminum oxide and silicon oxide. The antireflection layer may contain, but is not limited to, silicon nitride, a combination of silicon nitride and silicon oxide, or silicon oxynitride.

[0111] Optional, continue to refer to Figure 3The thickness of the first tunneling oxide layer 21 is greater than the thickness of the second tunneling oxide layer 231, so that the first tunneling oxide layer 21 can block atoms from passing through, while the second tunneling oxide layer 231 can allow phosphorus atoms to pass through, ensuring diffusion uniformity. The thickness of the second doped layer 22 is less than the thickness of the first doped layer 232, so that phosphorus atoms generated by phosphorus diffusion can pass through the second intrinsic silicon layer, the second tunneling oxide layer 231 and the first intrinsic silicon layer in sequence to form the first doped layer 232 and the second doped layer 232. At this time, the concentrations of the first doped layer 22 and the second doped layer 232 reach the preset concentrations.

[0112] Optional, continue to refer to Figure 3 The thickness of the first tunneling oxide layer 21 is 1.8nm-2.2nm. For example, the thickness of the first tunneling oxide layer 21 can be 1.8nm, 1.9nm, 2.0nm, 2.1nm or 2.2nm, etc., which can be determined according to the actual situation and are not limited here.

[0113] Optional, continue to refer to Figure 3 The thickness of the second doped layer 22 is 10nm-50nm. For example, the thickness of the second doped layer 22 can be 10nm, 20nm, 30nm, 40nm or 50nm, etc., which can be determined according to the actual situation and is not limited here.

[0114] Optional, continue to refer to Figure 3 The thickness of the second tunneling oxide layer 231 is 0.1nm-0.3nm. For example, the thickness of the second tunneling oxide layer 231 can be 0.1nm, 0.15nm, 0.2nm, 0.25nm or 0.3nm, etc., which can be determined according to the actual situation and is not limited here.

[0115] Optional, continue to refer to Figure 3 The thickness of the first doped layer 232 is 95nm-135nm. For example, the thickness of the first doped layer 232 can be 95nm, 105nm, 115nm, 125nm or 135nm, etc., which can be determined according to the actual situation and is not limited here.

[0116] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0117] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A method for preparing a TopCon battery, characterized in that, include: Provides N-type silicon substrates; The N-type silicon substrate includes a front side and a back side; A front surface field layer and a textured surface structure are prepared on the front side; A first tunneling oxide layer, a first intrinsic silicon layer, and at least one structural layer are sequentially stacked on the back side. Using a preset doping process, the structural layer is doped with elements to form a first doped layer, and the elements are diffused into the first intrinsic silicon layer to form a second doped layer. The N-type silicon substrate is screen-printed and sintered at high temperature to form a first electrode on the front side that contacts the front surface field layer, and a second electrode on the back side that contacts the first doped layer.

2. The preparation method according to claim 1, characterized in that, The at least one structural layer includes a second tunneling oxide layer and a second intrinsic silicon layer; The back side is prepared by sequentially stacking a first tunneling oxide layer, a first intrinsic silicon layer, and at least one structural layer on the surface of the first intrinsic silicon layer away from the N-type silicon substrate, comprising: The first tunneling oxide layer is formed on the back side using a first deposition process; Using a second deposition process, under first preset conditions, a first intrinsic silicon layer is formed on the side of the first tunneling oxide layer facing away from the N-type silicon substrate; Using a third deposition process, a second tunneling oxide layer is formed on the surface of the first intrinsic silicon layer on the side facing away from the N-type silicon substrate; Using a fourth deposition process, under second preset conditions, a second intrinsic silicon layer is formed on the side of the second tunneling oxide layer facing away from the N-type silicon substrate; Using a predetermined doping process, the structural layer is elementally doped to form a first doped layer, and the elements are diffused into the first intrinsic silicon layer to form a second doped layer, including: Using a phosphorus diffusion process, the second intrinsic silicon layer is phosphorus-doped to form the first doped layer, and phosphorus element is diffused into the first intrinsic silicon layer through the second tunneling oxide layer to form the second doped layer and the second mask layer. Remove the second mask layer.

3. The preparation method according to claim 2, characterized in that, The first preset conditions include a deposition temperature of 581℃-621℃ and a pressure of 22mbar-27mbar.

4. The preparation method according to claim 2, characterized in that, The second preset conditions include a deposition temperature of 580℃-620℃ and a pressure of 22mbar-27mbar.

5. The preparation method according to claim 2, characterized in that, The front surface field layer and textured structure are prepared on the front side, including: Boron doping is performed on the front side using a boron diffusion process to form the front surface field layer on the front side; The front surface layer and the back surface are flocked using a flocking process to form the flocked structure.

6. The preparation method according to claim 5, characterized in that, Before forming the first tunneling oxide layer on the back side using the first deposition process, the process further includes: Remove the textured surface on the back side to expose the N-type silicon substrate on the back side.

7. The preparation method according to claim 1, characterized in that, Before screen printing and high-temperature sintering the N-type silicon substrate to form a first electrode in contact with the front surface field layer on the front side and a second electrode in contact with the first doped layer on the back side, the method further includes: A first protective layer is prepared on the surface of the textured structure facing away from the N-type silicon substrate, and a second protective layer is prepared on the surface of the first doped layer facing away from the N-type silicon substrate.

8. A TopCon battery, characterized in that, The invention includes an N-type silicon substrate, which has a front side and a back side. The front side includes a front surface field layer, a textured structure, and a first electrode in contact with the front surface field layer. The back side includes a first tunneling oxide layer, a second doped layer, a structural layer, and a second electrode stacked sequentially. The structural layer includes a second tunneling oxide layer and a first doped layer. The second electrode is in contact with the first doped layer.

9. The TopCon battery according to claim 8, characterized in that, It also includes a first protective layer and a second protective layer; The first protective layer is located on the surface of the textured structure opposite to the N-type silicon substrate; the second protective layer is located on the surface of the first doped layer opposite to the N-type silicon substrate.

10. The TopCon battery according to claim 8, characterized in that, The thickness of the first tunneling oxide layer is greater than the thickness of the second tunneling oxide layer, and the thickness of the second doped layer is less than the thickness of the first doped layer.

11. The TopCon battery according to claim 8, characterized in that, The thickness of the first tunneling oxide layer is 1.8 nm to 2.2 nm.

12. The TopCon battery according to claim 8, characterized in that, The thickness of the second doped layer is 10nm-50nm.

13. The TopCon battery according to claim 8, characterized in that, The thickness of the second tunneling oxide layer is 0.1 nm to 0.3 nm.

14. The TopCon battery according to claim 8, characterized in that, The thickness of the first doped layer is 95nm-135nm.

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