Edge positioning accuracy closed-loop calibration method and system for automated test equipment

Abstract

The application belongs to the technical field of high-speed chip testing of semiconductors, and discloses a kind of edge positioning precision closed-loop calibration method and system of automatic test equipment, adopt external precision clock source as absolute timing reference, generate global absolute timing mark and distribute to all channels synchronously;First, the joint calibration of comparator decision threshold and edge capture delay is carried out to all receiving channels, so that each receiving channel becomes a high-precision edge measurement unit;Then, using the calibrated receiving channel as a measurement reference, all sending channels are calibrated in reverse through the loopback link, and the sending delay offset and edge distortion compensation parameters are calculated and compensated;Finally, the calibration error convergence is verified by random combination, and the parameters are solidified. The application realizes closed-loop self-calibration of ATE machine without external instruments, significantly improves the edge positioning precision and channel consistency, and reduces the calibration cost and time.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor high-speed chip testing technology, and specifically relates to a closed-loop calibration method and system for edge positioning accuracy of automated testing equipment. Background Technology

[0002] In the field of high-speed semiconductor chip testing, automated test equipment (ATE) is the core equipment for chip mass production and verification, and is widely used for electrical performance testing of high-speed interface devices such as DDR, PCIe, SerDes, and high-speed ADC / DAC. Edge positioning accuracy (EPA), as a core indicator of ATE timing testing, directly determines the accuracy of key test items such as eye diagram measurement, setup / hold time, and jitter tolerance. As chip speeds upgrade to 56G, 112G and higher, the accuracy requirements for EPA have increased to the picosecond or even sub-picosecond level, and traditional calibration techniques are difficult to meet the needs of the new generation of high-speed testing.

[0003] Currently, EPA calibration of ATE equipment mainly relies on three solutions: internal clock self-calibration, external instrument calibration, or independent calibration of the transceiver channel. Internal clock self-calibration uses on-chip clocks such as PLLs and DLLs as a reference, which is susceptible to temperature drift, jitter, and crosstalk, resulting in insufficient reference accuracy and large residual errors after calibration, failing to meet high-speed testing accuracy standards. While calibration using external instruments such as oscilloscopes and timing analyzers can improve accuracy, the equipment is expensive and the operation process is complex, making it impossible to achieve fully automated closed-loop calibration within the ATE machine, significantly reducing production line testing and calibration efficiency.

[0004] Independent calibration schemes for transmit and receive channels calibrate separately, lacking a unified timing reference. This leads to asymmetric delays and uncompensated timing deviations between channels, resulting in cumulative errors during loopback testing and poor consistency between channels. Existing patents and technologies mostly optimize only single dimensions such as internal delay lines and local jitter, without introducing an external ultra-high precision clock as a unified reference or forming a systematic closed-loop architecture that calibrates the receive channel first and then loopback calibrates the transmit channel. They generally suffer from defects such as inconsistent references, error propagation, incomplete calibration coverage, and inability to perform internal self-calibration, making it difficult to fundamentally resolve the contradiction between accuracy, consistency, efficiency, and cost in high-speed ATE-EPA calibration. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of the existing technology and provide a closed-loop calibration method and system for edge positioning accuracy of automated testing equipment. By introducing an external atomic-level precision clock as a unified absolute timing reference and adopting a two-step closed-loop architecture of first receiving channel calibration and then sending channel loopback calibration, this invention comprehensively breaks through the limitations of the existing technology from four aspects: reference, architecture, implementation method and error suppression, bringing significant technical advantages and practical value.

[0006] The technical solution adopted by this invention to solve its technical problem is: to provide a closed-loop calibration method for edge positioning accuracy of automated testing equipment, comprising the following steps:

[0007] S1. The global clock distribution module that connects to the external precision clock source to the ATE generates a global absolute timing mark and synchronously distributes it to all receiving and transmitting channels of the ATE, using the external precision clock source as the absolute timing reference.

[0008] S2. Based on the global absolute timing mark, using the standard edge test signal output by the external precision clock source, perform joint calibration of the decision threshold and edge capture delay of the comparators of all receiving channels, calculate and compensate the edge positioning accuracy error of each receiving channel, and make each receiving channel a high-precision edge measurement unit.

[0009] S3. Using the calibrated receiving channel as the measurement reference, all transmitting channels are calibrated in reverse by looping the output of the transmitting channel to the input of the receiving channel; the target transmitting channel is controlled to send an edge test pulse, which is captured by the calibrated receiving channel and its timing position is measured. The edge positioning accuracy error of each transmitting channel is calculated and compensated based on the measurement results.

[0010] S4. Randomly select a combination of transmitting and receiving channels, perform a loopback edge test, calculate the edge positioning accuracy error of each combination after calibration, calculate the test pass rate, and confirm whether the error of all combinations and the consistency between channels have converged to the preset target range.

[0011] S5. The final calibration parameters, verified and approved in S4, are permanently stored in the non-volatile memory of the ATE. ATE stands for Automated Test Equipment, and EPA stands for Edge Positioning Accuracy Error.

[0012] Furthermore, in S2, the joint calibration of the decision threshold and edge capture delay for the comparators of all receiving channels includes:

[0013] The standard edge test signal output from the external precision clock source is simultaneously connected to all receiving channels to be calibrated;

[0014] The timing control unit uses the global absolute timing mark as a reference to control the comparator of each receiving channel to perform edge scan decision, and successively adjust the decision threshold and acquisition delay;

[0015] Record the actual timing position of the standard edge captured by each receiving channel, and calculate the edge positioning accuracy error of the channel. The error includes delay offset, threshold offset and quantization nonlinearity error.

[0016] The calculated error parameters are written into the calibration register of the receiving channel to complete the calibration.

[0017] Furthermore, the calculation of the delay offset includes: ΔT = measured end-to-end transmission delay of the channel - globally preset standard transmission delay;

[0018] The calculation of the threshold offset includes: ΔV = current real-time steady-state decision threshold voltage - channel optimal theoretical discrimination threshold voltage;

[0019] The calculation of the quantization nonlinear error includes: ΔE = edge true timing point - TDC linear ideal fitting timing point.

[0020] Furthermore, in step S2, when adjusting the decision threshold of the comparator in the receiving channel, an automatic closed-loop tuning mode is adopted, including:

[0021] The timing control unit fine-tunes the decision threshold step by step within a preset threshold range. After each adjustment, it triggers edge capture verification. After multiple consecutive captures of data that completely overlap, the current threshold is latched as the optimal theoretical discrimination threshold and written to the calibration register.

[0022] Furthermore, in step S3, all transmitting channels are reverse-calibrated by looping back the output of the transmitting channel to the input of the receiving channel, including:

[0023] Configure a loopback link to directly connect the output of each transmit channel to the input of the corresponding calibrated receive channel via a loopback link with a fixed delay;

[0024] The timing control unit controls the target transmission channel to send edge test pulses according to the preset standard transmission timing position;

[0025] The calibrated receiving channel captures the pulse and measures the actual timing position of the capture based on the global absolute timing marker;

[0026] According to the formula ΔT TX =T RX -T TX -T LOOP Calculate the transmission delay offset of the transmission channel, where T RX T represents the actual capture position of the receiving channel. TX T is the preset standard transmission location. LOOP For the fixed delay of the loopback link, ΔT TX The calculated transmission delay offset is written to the calibration register of the transmission channel.

[0027] Furthermore, S3 also includes calculating the edge distortion compensation parameters of the transmission channel, including:

[0028] The rise time of the actual transmit edge of the transmit channel is captured by the calibrated receive channel;

[0029] The edge distortion compensation parameter K is calculated based on the deviation between this rise time and the standard edge rise time. r(实) -t r(标) ) / 10;

[0030] Among them, t r(实) t represents the actual edge rise time. r(标) This refers to the standard edge rise time.

[0031] The edge distortion compensation amount Δt = K × 10fs is calculated based on the compensation parameter K, and the compensation parameter and compensation amount are written into the calibration register.

[0032] Furthermore, in S4, the loopback edge test and error convergence determination include:

[0033] Step 1: Test initialization, the timing control unit retrieves the final calibration parameters and loads them into the corresponding registers;

[0034] Step 2: Determine multiple sets of transmit / receive channel combinations according to preset selection rules, and perform loopback edge tests on each set. The test procedure for a single set is as follows:

[0035] The timing control unit controls the transmission channel to transmit standard edge signals at preset standard transmission positions;

[0036] The corresponding receiving channel receives signals and latches the measured capture position values ​​through the internal loopback link of the ATE.

[0037] Calculate the accuracy error of the transmission channel edge position after calibration;

[0038] If the error after calibration is less than the preset accuracy threshold, and the percentage decrease in error after calibration is not less than the preset percentage decrease, then the test is considered to be qualified.

[0039] Step 3: After all selected combinations have been tested, calculate the pass rate, which must not be lower than the preset pass rate threshold;

[0040] Step 4: If all test combinations meet the timing error requirements and the pass rate is up to standard, the calibration is deemed valid; otherwise, locate the abnormal channel, readjust the compensation parameters or re-perform the calibration, and iterate until the error converges.

[0041] Furthermore, the preset selection rules include:

[0042] The number of selected combinations shall be above the preset proportion of the total number of channel combinations, and not less than the preset minimum number of combinations;

[0043] Ensure that each transmitting channel corresponds to multiple different receiving channels, and each receiving channel corresponds to multiple different transmitting channels;

[0044] Channels located at the boundary and middle of the channel number distribution are selected for cross-combination, and transmission channels with calibration parameters close to the preset reasonable range boundary are selected for verification.

[0045] Furthermore, the external precision clock source is a rubidium atomic clock or a cesium atomic clock, whose output clock signal jitter is less than 10 fs RMS and whose long-term stability is better than 1e-12.

[0046] The present invention also provides a closed-loop calibration system for edge positioning accuracy of automated testing equipment, comprising:

[0047] An external precision clock source is used to provide a highly stable, low-jitter clock signal as an absolute timing reference;

[0048] The global clock distribution module is connected to the external precision clock source and is used to distribute the external clock to each module inside the ATE to ensure that the clocks are from the same source.

[0049] The timing control unit is used to generate a global absolute timing mark based on an external clock and control the entire calibration process;

[0050] A receiver channel array, comprising multiple receiver channels, each receiver channel including at least a comparator, a time-to-digital converter, and a calibration register, for performing edge capture and high-precision timing measurements;

[0051] A transmit channel array containing multiple transmit channels, each transmit channel including at least a driver and a programmable delay line for generating programmable edge signals;

[0052] A loopback link is used in calibration mode to establish a low-latency, fixed-latency direct connection between the output of the transmitting channel and the input of the receiving channel.

[0053] The present invention has the following beneficial effects:

[0054] (1) This invention introduces an external atomic-level precision clock as a unified absolute timing reference and adopts a two-step closed-loop architecture of first receiving channel calibration and then sending channel loopback reverse calibration. It comprehensively breaks through the limitations of existing technologies from four aspects: reference, architecture, implementation method and error suppression, bringing significant technical advantages and practical value.

[0055] (2) This invention can improve the edge positioning accuracy (EPA) of the entire ATE channel from greater than 2ps to less than 300fs, which can stably meet the high-precision timing test requirements of 56G, 112G and higher speed semiconductor chips. No external high-precision oscilloscope or timing analyzer is required throughout the process. Calibration can be completed by relying on the closed loop inside the machine. The hardware cost of single ATE calibration is reduced by more than 80%, and the calibration time of the entire channel is shortened from more than 30 minutes to less than 5 minutes, which greatly improves the batch calibration efficiency of the production line.

[0056] (3) This invention enables the TX and RX channels to share the same external clock reference, synchronously complete the joint compensation of comparator decision threshold, acquisition delay, and quantization nonlinearity error, and accurately deduct link deviation by combining a fixed-delay loopback link, so that the timing consistency of the entire channel is controlled within 300fs, which significantly improves the synchronization and accuracy of high-speed parallel testing. The external atomic clock has ultra-high long-term stability, which extends the effective duration of calibration parameters to more than 5000 hours, greatly reduces the calibration frequency, and improves the continuous operation stability of the equipment.

[0057] (4) This invention achieves pure hardware closed-loop self-calibration within the ATE, without the need for manual intervention and cooperation with external instruments, reducing dependence on the operating environment and personnel skills, improving the standardization and reliability of the calibration process, and comprehensively solving the industry pain points of insufficient accuracy, high cost, low efficiency and poor consistency of traditional calibration solutions, providing a high-precision, low-cost and high-efficiency EPA calibration solution for high-speed chip automated testing. Attached Figure Description

[0058] Figure 1 This is a flowchart of a closed-loop calibration method for edge positioning accuracy of an automated testing device according to the present invention;

[0059] Figure 2 This is a flowchart of the receiving channel calibration method for an automated testing equipment edge positioning accuracy closed-loop calibration method according to the present invention.

[0060] Figure 3 This is a flowchart illustrating the transmission channel calibration process of a closed-loop calibration method for edge positioning accuracy of an automated testing device according to the present invention.

[0061] Figure 4 This is a system structure diagram of closed-loop calibration of edge positioning accuracy for an automated testing device according to the present invention;

[0062] Figure 5 This is a system architecture diagram for closed-loop calibration of edge positioning accuracy of an automated testing device according to the present invention. Detailed Implementation

[0063] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0064] Example 1:

[0065] This invention provides a closed-loop calibration method for the edge positioning accuracy of automated test equipment, aiming to address the challenges faced in calibrating the edge positioning accuracy (EPA) of automated test equipment (ATE) in the field of high-speed semiconductor chip testing, especially as chip speeds continue to increase to 56G, 112G and higher, where traditional calibration techniques struggle to meet sub-picosecond level accuracy requirements. This invention introduces an external atomic-level precision clock as a unified absolute timing reference and employs a two-step closed-loop architecture: first, receiving channel calibration, then transmitting channel loopback calibration. This comprehensively overcomes the limitations of existing technologies from four aspects: reference, architecture, implementation method, and error suppression, significantly improving calibration accuracy, consistency, and efficiency while reducing costs.

[0066] The edge positioning accuracy closed-loop calibration method for automated testing equipment according to the present invention includes the following steps:

[0067] S1. Connect an external precision clock source and generate a global absolute timing mark: Connect the external precision clock source to the global clock distribution module of the ATE; the external precision clock source serves as an absolute timing reference, used to generate a global absolute timing mark, and synchronously distribute it to all receiving and transmitting channels of the ATE to ensure the timing synchronization and consistency of the entire system.

[0068] S2. Joint calibration of receiving channels: Based on the global absolute timing mark, the standard edge test signal output by the external precision clock source is used to jointly calibrate the decision threshold and edge capture delay of the comparators of all receiving channels. This step calculates and compensates for the edge positioning accuracy error of each receiving channel, making each receiving channel a high-precision edge measurement unit.

[0069] S3. Reverse Calibration of Transmitting Channels: Using the calibrated receiving channel as a measurement reference, all transmitting channels are reverse-calibrated by looping the output of the transmitting channel back to the input of the receiving channel. Specifically, the target transmitting channel is controlled to send an edge test pulse, which is captured by the calibrated receiving channel and its timing position is measured. The edge positioning accuracy error of each transmitting channel is calculated and compensated based on the measurement results.

[0070] S4. Loopback Edge Test and Error Convergence Judgment: Randomly select a combination of transmitting and receiving channels, perform a loopback edge test, calculate the edge positioning accuracy error of each combination after calibration, statistically analyze the test pass rate, and confirm whether the error of all combinations and the consistency between channels have converged to the preset target range.

[0071] S5. Solidification and storage of calibration parameters: The final calibration parameters that have passed the verification in S4 are solidified and stored in the non-volatile memory of the ATE for subsequent testing.

[0072] S2. Detailed calibration process for the receiving channel.

[0073] In step S2, the comparators of all receiving channels are jointly calibrated for decision threshold and edge capture delay, including the following sub-steps:

[0074] Standard edge test signal input: Simultaneously input the standard edge test signal output from the external precision clock source into all receiving channels to be calibrated.

[0075] Edge scan decision and adjustment: The timing control unit uses the global absolute timing mark as a reference to control the comparator of each receiving channel to perform edge scan decision, and adjusts the decision threshold and acquisition delay one by one.

[0076] Error Calculation and Decoupling: Record the actual timing position of each receiving channel capturing the standard edge, and calculate the edge positioning accuracy error of that channel using the following formula:

[0077] EPA RX =T RX(实) -T STD ;

[0078] Among them, T RX(实) For the actual capture location, T STD This represents the absolute position of the standard edge. Simultaneously, the delay offset, threshold offset, and quantization nonlinearity error of this channel are calculated in a decoupled manner.

[0079] Calculate the EPA error of the RX channel: actual capture position - standard edge absolute position, to obtain the delay offset, threshold offset, and quantization nonlinearity error of each RX channel;

[0080] The decision threshold (voltage) and capture delay (delay line / TDC (Time to Digital Converter)) of the RX comparator are finely adjusted successively to record the actual timing position of each RX channel capturing the standard edge. The preset adjustable threshold range is 120 mV to 380 mV, and the gradient fine-tuning step size is 5 mV. The controllable fine-tuning range of the capture delay is 0 ps to 1200 ps, ​​and the minimum quantization fine step of the back-end cascaded TDC is 15 fs. After each round of threshold + delay co-tuning, the active capture sampling verification of the standard edge is triggered. When the deviation of the original data of the captured timing sampling returns to zero after three consecutive repeated captures and the sampling results are completely overlapped without offset, the actual timing landing point coordinates of the standard edge of the corresponding RX channel under the current steady-state condition are immediately latched. The highest accuracy of timing recording is 100 fs.

[0081] The capture action is as follows: After the standard edge test signal (rise / fall time <10ps, jitter <10fs) output by the external precision clock source is connected to the RX channel, the RX comparator compares the input signal voltage with the successively fine-tuned decision threshold in real time. When the two match precisely, a hardware native capture pulse signal is immediately generated, which synchronously triggers the TDC (time-to-digital converter) to latch the current global absolute timing coordinates, thus completing a single edge capture. After each round of threshold and delay co-adjustment, the capture action needs to be repeated 3 times. Only when the original timing data of the 3 captures are without deviation and completely coincident is the capture confirmed to be valid and the data latched.

[0082] The capture link inherently contains delays that cannot be physically eliminated; these are native hardware characteristics and can be categorized into four types: ① inherent device delay due to the switching of transistors within the RX comparator; ② closed-loop tuning delay after the decision threshold is fine-tuned, causing the loop to reach a steady state; ③ hardware routing delay in the transmission of the capture pulse signal from the RX comparator to the TDC; and ④ native conversion delay in the TDC's quantization encoding of timing coordinates. These four types of delays are randomly superimposed and do not disappear with calibration, but their effects can be offset through compensation.

[0083] "Absolute position" specifically refers to the "global absolute timing coordinates of the standard edge," which, relying on the traceability characteristics of an external precision clock source, possesses three "absolutely unique" attributes, as follows:

[0084] ① The reference source is absolutely unique: the timing reference is derived from an external rubidium atomic clock / cesium atomic clock (jitter < 10 fs RMS, long-term stability > 1e). -12 It replaces the internal PLL / DLL clock of ATE, is not affected by internal clock drift or jitter, and the reference itself has extremely high stability;

[0085] ② Global alignment is absolutely consistent: After the external precision clock is divided / multiplied by the CDU (Global Clock Distribution Module), it is synchronously distributed to all RX channels, TX channels and timing control units. All channels have the same clock source and phase. All RX channels are aligned with the same set of global absolute timing marks when captured, and there is no local temporary reference.

[0086] ③ The coordinate values ​​are absolutely fixed: The timing position of the standard edge test signal is pre-calibrated by an external precision clock source. It is a known fixed value that does not change with the RX channel operating conditions or calibration cycles. It serves as the sole benchmark for the capture position and there is no relative offset. Therefore, it is called "absolute position".

[0087] Calculation of delay offset ΔT: ΔT = Actual measured end-link transmission delay of the channel - Global preset standard transmission delay;

[0088] Calculation of threshold offset ΔV: ΔV = Current real-time steady-state decision threshold voltage - Channel optimal theoretical discrimination threshold voltage;

[0089] Calculation of quantization nonlinear error ΔE: ΔE = actual edge timing point - TDC linear ideal fitting timing point;

[0090] Write calibration parameters: Write the calculated error parameters into the calibration register of the receiving channel to complete the calibration.

[0091] The delay offset, threshold offset, and quantization nonlinearity error are all generated by decomposing the EPA error of the RX channel (EPA error = actual capture position - standard edge absolute position), but their generation mechanisms, physical meanings, and influencing factors are completely different. The specific decomposition is as follows:

[0092] (1) Delay offset

[0093] ① Generation mechanism: Under the premise that the RX channel decision threshold calibration meets the standard (no threshold deviation), the actual transmission delay of the entire RX channel does not match the globally preset standard transmission delay, causing the edge capture timing to be ahead or behind the standard absolute position. The deviation value is the delay offset.

[0094] ② Formula: Delay offset ΔT = Actual measured full-link transmission delay of the channel - Global preset standard transmission delay (unit: fs);

[0095] ③Physical meaning: Specifically characterizes the timing consistency deviation of the RX channel hardware link, reflecting the signal transmission speed problems caused by differences in RX channel routing, device batches, and link impedance. It is a hardware adaptation indicator in pure timing dimension.

[0096] ④ Core features: It is only related to timing transmission and has no relation to timing decision threshold voltage. Precise compensation can be achieved by fine-tuning the delay line settings.

[0097] (2) Threshold offset

[0098] ① Generation mechanism: Under the premise that the RX channel delay calibration meets the standard (no delay deviation), the decision threshold voltage of the RX comparator in real time does not coincide with the globally preset optimal adaptation and discrimination threshold voltage, which causes the edge capture triggering time to be advanced or delayed, indirectly generating timing deviation. After removing the delay deviation, the voltage deviation corresponding to the timing deviation is the threshold offset.

[0099] ② Formula: Threshold offset ΔV = Current real-time steady-state decision threshold voltage - Channel optimal theoretical discrimination threshold voltage (unit: mV);

[0100] ③Physical meaning: Specifically characterizes the voltage discrimination accuracy deviation of the RX comparator, reflects the decision point drift caused by device temperature drift, power supply ripple, and device aging, and directly affects the trigger accuracy of edge capture;

[0101] ④ Core features: It is only related to the voltage amplitude and does not directly affect the timing link transmission. Compensation can be achieved by fine-tuning the built-in voltage reference source of the RX comparator. It has no linkage interference with the timing module (delay line, TDC).

[0102] (3) Quantification of nonlinear error

[0103] ① Generation mechanism: It belongs to the inherent error of TDC hardware and is unrelated to manual parameter tuning or link conditions; because the timing quantization division of TDC is not ideally linear and uniformly arranged, the actual division interval has random deviation. When the actual timing landing point of the edge is in the nonlinear division interval, the deviation generated by TDC forced adjustment latch is the quantization nonlinear error.

[0104] ② Formula: Quantization nonlinear error ΔE = actual edge timing point - TDC linear ideal fitting timing point (unit: fs);

[0105] ③Physical significance: Specifically characterizes the quantization accuracy defects of TDC hardware, reflects the linearity of timing quantization scale, and is an inherent hardware error that cannot be eliminated by hardware parameter tuning;

[0106] ④ Core features: It is unrelated to threshold voltage and link delay, and is determined only by the hardware manufacturing process. It can only be corrected and compensated by algorithm fitting. It does not affect the hardware adaptability of the RX channel, but only affects the acquisition accuracy.

[0107] Automatic closed-loop tuning mode for decision threshold: When adjusting the decision threshold of the comparator in the receiving channel, the device adopts an automatic closed-loop tuning mode. The timing control unit fine-tunes the decision threshold step by step within a preset threshold range, triggering edge capture verification after each adjustment. After multiple consecutive data captures that completely overlap, the current threshold is latched as the optimal theoretical discrimination threshold and written to the calibration register.

[0108] The decision threshold is not manually determined; the entire process adopts an "automatic closed-loop tuning + register latching" mode. The specific steps are as follows:

[0109] Step 1: During calibration initialization, the timing control unit automatically retrieves the globally preset adjustable threshold range (120mV~380mV) and fine-tunes the decision threshold of the RX comparator step by step with a fixed step size of 5mV.

[0110] Step 2: Each time the threshold is fine-tuned, edge capture is triggered synchronously, and the capture status is observed (no missed captures, no false triggers) to filter out the steady-state threshold range;

[0111] Step 3: Combining the three consecutive capture verification mechanisms, determine the optimal theoretical discrimination threshold for the RX channel and automatically write it into the RX calibration register of the ATE;

[0112] Step 4: During subsequent RX operation and calibration, the program automatically retrieves the threshold reference in the register and makes small adaptive corrections based on real-time temperature and pressure conditions. The entire process requires no manual switching or on-site adjustment, avoiding random deviations caused by manual value acquisition.

[0113] The problem of an excessively high decision threshold: The threshold is higher than the optimal adaptation range (>380mV), resulting in an excessively high voltage discrimination point for the RX comparator. The specific impacts are as follows:

[0114] 1. Acquisition lag: During the standard edge uphill climbing phase, it cannot reach the high threshold point in time, and the edge acquisition trigger time is significantly delayed, resulting in a vicious increase in delay offset, which destroys the EPA accuracy of the RX channel (cannot meet the <100fs requirement).

[0115] 2. Acquisition failure: The weak effective edge signal output by the external precision clock source will be truncated by the high threshold, resulting in occasional missed acquisition and sampling failure in a single channel, leading to missing calibration data;

[0116] 3. Decreased anti-interference capability: When strong interference noise is coupled, there is no noise redundancy at high thresholds, the system timing synchronization fault tolerance rate is reduced, resulting in disorder of multi-channel captured data, and the consistency between channels cannot meet the requirement of <200fs.

[0117] The problem of an excessively low decision threshold: If the threshold is lower than the optimal adaptation range (<120mV), the voltage discrimination point of the RX comparator will be too low, with the following specific effects:

[0118] 1. False capture: The RX comparator is too sensitive. Random noise floor, power supply ripple, and device thermal noise in the front-end link will be misjudged as valid edge signals, triggering a large number of invalid capture pulses;

[0119] 2. Error calculation distortion: False capture generates a large amount of garbage time series data, which leads to complete distortion of EPA error and type III offset calculation, and invalidation of calibration parameters;

[0120] 3. Calibration failure: False captures occur during multi-channel synchronization, causing the global absolute timing benchmark to collapse. The RX channel cannot serve as a "high-precision timing measurement ruler," which in turn affects the accuracy of subsequent TX link loopback reverse calibration, ultimately leading to the failure of unified EPA calibration across all channels.

[0121] S3. Detailed calibration process for the transmission channel.

[0122] In step S3, all transmitting channels are reverse-calibrated by looping back the output of the transmitting channel to the input of the receiving channel, including the following sub-steps:

[0123] Loopback Link Configuration: Configure a loopback link to directly connect the output of each transmit channel to the input of the corresponding calibrated receive channel via a loopback link with a fixed delay.

[0124] Sending edge test pulses: The timing control unit controls the target transmission channel to send edge test pulses according to the preset standard transmission timing position.

[0125] Acquisition and Measurement: The calibrated receiving channel captures the pulse and measures the actual timing position of the capture based on the global absolute timing marker.

[0126] Transmission delay offset calculation: The transmission delay offset of the transmission channel is calculated according to the following formula:

[0127] ΔT TX =T RX -T TX -T LOOP ;

[0128] Among them, T RX T represents the actual capture position of the receiving channel. TX T is the preset standard transmission location. LOOP For the fixed delay of the loopback link, ΔT TX This is the transmission delay offset. The calculated transmission delay offset is written to the calibration register of the transmission channel.

[0129] Edge distortion compensation parameter calculation: Step S3 also includes calculating the edge distortion compensation parameters of the transmission channel:

[0130] Rise time capture: The rise time of the actual transmit edge of the transmit channel is captured by the calibrated receive channel.

[0131] Compensation parameter calculation: The edge distortion compensation parameter K is calculated based on the deviation between this rise time and the standard edge rise time.

[0132] K=(t r(实) -t r(标) ) / 10;

[0133] Among them, t r(实) t represents the actual edge rise time. r(标) This is the standard edge rise time.

[0134] Compensation amount calculation and writing: Calculate the edge distortion compensation amount Δt=K×10fs based on the compensation parameter K, and write the compensation parameter and compensation amount into the calibration register.

[0135] S4. Loopback edge test and error convergence determination.

[0136] In step S4, the loopback edge test and error convergence determination include the following steps:

[0137] Test initialization: The timing control unit retrieves the final calibration parameters and loads them into the corresponding registers.

[0138] Multiple combination tests: Multiple transmit / receive channel combinations are determined according to preset selection rules, and loopback edge tests are performed on each combination. The single-group test procedure is as follows:

[0139] The timing control unit controls the transmission channel to send standard edge signals at preset standard transmission positions.

[0140] The corresponding receiving channel receives signals through the internal loopback link of the ATE and latches the measured value of the captured position.

[0141] The edge positioning accuracy error of the calibrated transmission channel is calculated using the following formula:

[0142] EPA TX = T RX(实) -T TX -T LOOP -ΔT TX ;

[0143] Among them, T RX(实) T is the measured acquisition position of the receiving channel. TX T is the preset standard transmission location. LOOP For the fixed delay of the loopback link, ΔT TX This is the compensation value for the transmission delay offset of the transmission channel.

[0144] If the edge positioning accuracy error is less than the preset accuracy threshold, and the percentage decrease in error after calibration is not less than the preset percentage decrease, then the test is deemed to be qualified.

[0145] Pass rate statistics: After all selected combination tests are completed, the pass rate is calculated and must not be lower than the preset pass rate threshold.

[0146] Calibration validity determination and iterative optimization: If all test combinations meet the timing error requirements and the pass rate is up to standard, the calibration is deemed valid; otherwise, the abnormal channel is located, the compensation parameters are readjusted or the calibration is re-executed, and iterative optimization is carried out until the error converges.

[0147] Specific steps for loop edge testing

[0148] By selecting the TX / RX combination, repeating the loopback edge capture and error calculation, comparing the EPA error before and after calibration, and determining the calibration effectiveness, the specific steps are as follows:

[0149] Step 1: Test initialization, the timing control unit retrieves the final calibration parameters (receive channel compensation parameters, transmit channel ΔT) from the ATE non-volatile storage. TX The values ​​(K, Δt) are loaded into all corresponding registers to ensure that the TX / RX channels are in the calibrated working state.

[0150] Step 2: Perform loopback edge testing group by group according to the selected TX / RX combination. Single group test procedure:

[0151] ① The timing control unit sends a test command to control the TX channel of this group according to the preset T. TX (Standard transmission position) Transmit standard edge signal (rise / fall time = 10ps, jitter < 10fs);

[0152] ② This receiving channel receives the edge signal sent by TX through the internal loopback link of ATE, and latches the measured value T of the RX capture position. RX(实) ;

[0153] ③ Substitute into the formula for calculating the EPA error of the transmission channel: Transmission channel EPA error = T RX(实) -T TX -T Loop -ΔT TX (After compensation), calculate the EPA error of the calibrated transmit channel for this combination;

[0154] ④ Retrieve the EPA error of the transmission channel before calibration of this combination (ΔT was not loaded before calibration). TX Error data at K value), record the error difference before and after calibration;

[0155] ⑤ Determine the validity of a single group: If the EPA error of the transmit channel after calibration is <200fs, and the consistency with the RX channel (|TXEPA error - RXEPA error|) is <300fs, and the error after calibration decreases by ≥80% compared with that before calibration, then the test group is deemed to be qualified.

[0156] Step 3: After all selected combinations have been tested, calculate the pass rate (number of qualified combinations / total number of selected combinations). The pass rate must be ≥ 95%.

[0157] Step 4: Error Convergence Judgment and Optimization:

[0158] ① If all test combinations meet the error requirements (TX EPA error <200fs, full channel consistency <300fs) and the pass rate is ≥95%, the calibration is deemed valid and proceeds to step five;

[0159] ② If there are combinations with errors exceeding the threshold (TX EPA error ≥ 200 fs or consistency ≥ 300 fs), or a pass rate < 95%, then locate the TX / RX channel corresponding to the abnormal combination:

[0160] a. If the anomaly is concentrated in a few TX channels, retrieve the ΔT value for those TX channels again. TX The process of calculating the K value is reviewed to verify its accuracy, and the compensation parameters are readjusted and written to the register.

[0161] b. If the anomalies are scattered across multiple combinations, investigate the loopback link T. Loop If there is an offset or the RX channel compensation parameters are invalid, re-perform the RX channel calibration and TX loopback calibration (step 2 → step 3).

[0162] c. Re-execute the "Channel Combination Selection + Loopback Edge Test" process in this chapter, iteratively optimize, until all combination errors converge to the target range and the pass rate is ≥95%.

[0163] Step 5: Test data retention. All EPA errors before and after calibration, test results, and iterative optimization records for all combinations are synchronously stored in the ATE non-volatile storage and saved in association with the final calibration parameters for subsequent troubleshooting and calibration traceability.

[0164] If the error exceeds the threshold (e.g., >300fs), repeat step two → step three to iteratively optimize the compensation parameters until the error of all channels converges to the target range.

[0165] Preset selection rules: The preset selection rules include:

[0166] The number of selected combinations shall be at least a preset proportion of the total number of channel combinations, and shall not be less than the preset minimum number of combinations.

[0167] Ensure that each transmit channel corresponds to multiple different receive channels, and each receive channel corresponds to multiple different transmit channels.

[0168] Channels located at the boundary and middle of the channel number distribution are selected for cross-combination, and transmission channels with calibration parameters close to the preset reasonable range boundary are selected for verification.

[0169] Channel selection rules (balancing randomness and comprehensiveness):

[0170] ① Total quantity requirement: The number of selected combinations must be greater than or equal to 15% of the total number of channel combinations, and must be at least 10 combinations (if the total number of combinations is less than 10, all combinations must be selected).

[0171] ② Distribution requirements: When selecting randomly, ensure that each TX channel corresponds to at least 2 different RX channels, and each RX channel corresponds to at least 2 different TX channels, to avoid testing a single channel in combination with a single channel;

[0172] ③ Priority requirements: Prioritize the selection of cross combinations of "TX channel ends (smallest and largest numbers) + middle number" and "RX channel ends (smallest and largest numbers) + middle number", while randomly selecting some middle channel combinations to cover the entire range of channel distribution;

[0173] ④ Abnormal correlation requirement: If there is ΔT in the previous calibration TX For TX channels with K values ​​close to the upper / lower limit of a reasonable range, it is necessary to prioritize the selection of such TX channels in combination with different RX channels, and focus on verifying their compensation effectiveness.

[0174] 3. Example selection (assuming TX channels 1-8, RX channels 1-8, total 64 combinations):

[0175] Ten combinations were selected: TX1-RX1, TX1-RX8, TX4-RX3, TX4-RX6, TX8-RX1, TX8-RX8, TX2-RX5, TX6-RX2, TX3-RX7, and TX7-RX4. These combinations covered both ends and the middle channel, and also achieved random crossover.

[0176] S5. Fix calibration parameters.

[0177] The final calibration parameters that have passed the verification in step S4 are permanently stored in the non-volatile memory of the ATE to ensure the persistence of the calibration results so that they can be directly retrieved in subsequent tests without the need for repeated calibration.

[0178] This invention also provides a two-step closed-loop calibration system for ATE equipment based on an external precision clock source, used to implement the above method, comprising:

[0179] External precision clock source: Used to provide a highly stable, low-jitter clock signal as an absolute timing reference. Preferably, the external precision clock source is a rubidium atomic clock or a cesium atomic clock, whose output clock signal jitter is less than 10 fs RMS and long-term stability is better than 1e. -12 .

[0180] Global clock distribution module: Connected to the external precision clock source, it is used to distribute the external clock to each module inside the ATE to ensure that the clocks are from the same source.

[0181] Timing control unit: Used to generate global absolute timing marks based on an external clock and control the entire calibration process.

[0182] Receive channel array: Contains multiple receive channels, each of which includes at least a comparator, a time-to-digital converter, and a calibration register for performing edge capture and high-precision timing measurements.

[0183] Transmit channel array: Contains multiple transmit channels, each of which includes at least a driver and a programmable delay line for generating programmable edge signals.

[0184] Loopback link: Used in calibration mode to establish a low-latency, fixed-latency direct connection between the output of the transmitting channel and the input of the receiving channel.

[0185] This invention effectively solves the problems of inconsistent benchmarks, error propagation, incomplete calibration coverage, and inability to perform in-machine self-calibration in traditional ATE equipment EPA calibration by introducing an external atomic-level precision clock source as a unified timing reference and combining it with a two-step closed-loop calibration architecture. This method can achieve EPA calibration accuracy at the picosecond or even sub-picosecond level, significantly improving the accuracy and reliability of high-speed chip testing, while also increasing calibration efficiency and reducing testing costs, demonstrating significant technical advantages and practical value.

[0186] Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A closed-loop calibration method for edge positioning accuracy of an automated testing device, characterized in that, Includes the following steps: S1. The global clock distribution module that connects to the external precision clock source to the ATE generates a global absolute timing mark and synchronously distributes it to all receiving and transmitting channels of the ATE, using the external precision clock source as the absolute timing reference. S2. Based on the global absolute timing mark, using the standard edge test signal output by the external precision clock source, perform joint calibration of the decision threshold and edge capture delay of the comparators of all receiving channels, calculate and compensate the edge positioning accuracy error of each receiving channel, and make each receiving channel a high-precision edge measurement unit. S3. Using the calibrated receiving channel as the measurement reference, all transmitting channels are calibrated in reverse by looping the output of the transmitting channel to the input of the receiving channel; the target transmitting channel is controlled to send an edge test pulse, which is captured by the calibrated receiving channel and its timing position is measured. The edge positioning accuracy error of each transmitting channel is calculated and compensated based on the measurement results. S4. Randomly select a combination of transmitting and receiving channels, perform a loopback edge test, calculate the edge positioning accuracy error of each combination after calibration, calculate the test pass rate, and confirm whether the error of all combinations and the consistency between channels have converged to the preset target range. S5. The final calibration parameters that have passed the verification in S4 are permanently saved to the non-volatile memory of the ATE.

2. The closed-loop calibration method for edge positioning accuracy of an automated testing device according to claim 1, characterized in that, In step S2, the comparators of all receiving channels undergo joint calibration of the decision threshold and edge capture delay, including: The standard edge test signal output from the external precision clock source is simultaneously connected to all receiving channels to be calibrated; The timing control unit uses the global absolute timing mark as a reference to control the comparator of each receiving channel to perform edge scan decision, and successively adjust the decision threshold and acquisition delay; Record the actual timing position of each receiving channel when it captures the standard edge, and calculate the edge positioning accuracy error of that channel using the following formula: EPA RX =T RX(实) -T STD ; Among them, T RX(实) For the actual capture location, T STD This represents the absolute position of the standard edge; Simultaneously, the delay offset, threshold offset, and quantization nonlinearity error of this channel are calculated in a decoupled manner. The calculated error parameters are written into the calibration register of the receiving channel to complete the calibration.

3. The closed-loop calibration method for edge positioning accuracy of an automated testing device according to claim 2, characterized in that: The calculation of the delay offset includes: ΔT = measured end-link transmission delay of the channel - globally preset standard transmission delay; The calculation of the threshold offset includes: ΔV = current real-time steady-state decision threshold voltage - channel optimal theoretical discrimination threshold voltage; The calculation of the quantization nonlinear error includes: ΔE = edge true timing point - TDC linear ideal fitting timing point.

4. The closed-loop calibration method for edge positioning accuracy of an automated testing device according to claim 1, characterized in that, In step S2, when adjusting the decision threshold of the comparator in the receiving channel, an automatic closed-loop tuning mode is adopted, including: The timing control unit fine-tunes the decision threshold step by step within a preset threshold range. After each adjustment, it triggers edge capture verification. After multiple consecutive captures of data that completely overlap, the current threshold is latched as the optimal theoretical discrimination threshold and written to the calibration register.

5. The closed-loop calibration method for edge positioning accuracy of an automated testing device according to claim 1, characterized in that, In step S3, all transmitting channels are reverse-calibrated by looping back the output of the transmitting channel to the input of the receiving channel, including: Configure a loopback link to directly connect the output of each transmit channel to the input of the corresponding calibrated receive channel via a loopback link with a fixed delay; The timing control unit controls the target transmission channel to send edge test pulses according to the preset standard transmission timing position; The calibrated receiving channel captures the pulse and measures the actual timing position of the capture based on the global absolute timing marker; According to the formula ΔT TX =T RX -T TX -T LOOP Calculate the transmission delay offset of the transmission channel, where T RX T represents the actual capture position of the receiving channel. TX T is the preset standard transmission location. LOOP For the fixed delay of the loopback link, ΔT TX The calculated transmission delay offset is written to the calibration register of the transmission channel.

6. The closed-loop calibration method for edge positioning accuracy of an automated testing device according to claim 4, characterized in that, S3 further includes calculating the edge distortion compensation parameters of the transmission channel, including: The rise time of the actual transmit edge of the transmit channel is captured by the calibrated receive channel; The edge distortion compensation parameter K is calculated based on the deviation between this rise time and the standard edge rise time. r(实) -t r(标) ) / 10; Among them, t r(实) t represents the actual edge rise time. r(标) This refers to the standard edge rise time. The edge distortion compensation amount Δt = K × 10fs is calculated based on the compensation parameter K, and the compensation parameter and compensation amount are written into the calibration register.

7. The closed-loop calibration method for edge positioning accuracy of an automated testing device according to claim 1, characterized in that, In step S4, the loopback edge test and error convergence determination include: Step 1: Test initialization, the timing control unit retrieves the final calibration parameters and loads them into the corresponding registers; Step 2: Determine multiple sets of transmit / receive channel combinations according to preset selection rules, and perform loopback edge tests for each set. The test procedure for a single set is as follows: The timing control unit controls the transmission channel to transmit standard edge signals at preset standard transmission positions; The corresponding receiving channel receives the signal through the internal loopback link of the ATE and latches the measured value of the captured position. The edge positioning accuracy error of the calibrated transmission channel is calculated using the following formula: EPA TX =T RX(实) -T TX -T LOOP -ΔT TX ; Among them, T RX(实) T is the measured acquisition position of the receiving channel. TX T is the preset standard transmission location. LOOP For the fixed delay of the loopback link, ΔT TX This is the compensation value for the transmission delay offset of the transmission channel; If the edge positioning accuracy error is less than the preset accuracy threshold, and the percentage decrease in error after calibration is not less than the preset percentage decrease, then the test is deemed to be qualified. Step 3: After all selected combinations have been tested, calculate the pass rate, which must not be lower than the preset pass rate threshold; Step 4: If all test combinations meet the timing error requirements and the pass rate is up to standard, the calibration is deemed valid; otherwise, locate the abnormal channel, readjust the compensation parameters or re-perform the calibration, and iterate until the error converges.

8. The closed-loop calibration method for edge positioning accuracy of an automated testing device according to claim 7, characterized in that, The preset selection rules include: The number of selected combinations shall be above the preset proportion of the total number of channel combinations, and not less than the preset minimum number of combinations; Ensure that each transmitting channel corresponds to multiple different receiving channels, and each receiving channel corresponds to multiple different transmitting channels; Channels located at the boundary and middle of the channel number distribution are selected for cross-combination, and transmission channels with calibration parameters close to the preset reasonable range boundary are selected for verification.

9. The closed-loop calibration method for edge positioning accuracy of an automated testing device according to claim 1, characterized in that, The external precision clock source is a rubidium atomic clock or a cesium atomic clock, whose output clock signal jitter is less than 10 fs RMS and whose long-term stability is better than 1e. -12 .

10. A closed-loop calibration system for edge positioning accuracy of an automated testing device, used to implement the method according to any one of claims 1 to 9, characterized in that, include: An external precision clock source is used to provide a highly stable, low-jitter clock signal as an absolute timing reference; The global clock distribution module is connected to the external precision clock source and is used to distribute the external clock to each module inside the ATE to ensure that the clocks are from the same source. The timing control unit is used to generate a global absolute timing mark based on an external clock and control the entire calibration process; A receiver channel array, comprising multiple receiver channels, each receiver channel including at least a comparator, a time-to-digital converter, and a calibration register, for performing edge capture and high-precision timing measurements; A transmit channel array containing multiple transmit channels, each transmit channel including at least a driver and a programmable delay line for generating programmable edge signals; A loopback link is used in calibration mode to establish a low-latency, fixed-latency direct connection between the output of the transmitting channel and the input of the receiving channel.

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