Interface apparatus for automatic test equipment and automatic test equipment
The interface device with thicker pads and modularized components addresses wear-out issues, ensuring reliable high-speed testing of semiconductor devices by reducing signal loss and distortion.
Patent Information
- Application Number
- JP2024109647
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2024-07-08
- Publication Date
- 2026-01-21
AI Technical Summary
Existing interface devices for automatic test equipment face issues with wear-out of electrical contacts due to repeated attachment and detachment, which affects long-term reliability, especially with the increasing speed and complexity of semiconductor devices.
The interface device incorporates a socket board with thicker second pads for electrical contact with an interposer, along with a modularized front-end module and flexible printed circuit cables, to enhance peel strength and reduce wear, thereby improving long-term reliability.
The solution significantly reduces signal loss and waveform distortion, enabling accurate high-speed testing of semiconductor devices beyond 20 Gbps by shortening transmission distances and enhancing the durability of electrical contacts.
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Figure 2026009633000001_ABST
Abstract
Description
[Technical Field]
[0001] The present disclosure relates to an interface device for automatic test equipment. [Background technology]
[0002] Automatic test equipment (ATE) is used to test various semiconductor devices such as memories, CPUs (Central Processing Units), etc. The ATE supplies test signals to the semiconductor device under test (hereafter referred to as the device under test (DUT)), measures the response of the DUT to the test signals, and determines whether the DUT is good or bad, or identifies any defects.
[0003] In recent years, the speed of DRAM (Dynamic Random Access Memory) has been increasing. The GDDR (Graphics Double Data Rate) memory installed in graphics cards has achieved a transmission speed of 21 Gbps using the NRZ (Non Return to Zero) method in the GDDR6X standard.
[0004] The next generation GDDR7 will use PAM4 (Pulse Amplitude Modulation 4), which will increase transmission speeds to 40Gbps. The NRZ method is also becoming faster every year, and in the next generation it will be increased to around 28Gbps.
[0005] Patent Document 1 discloses an interface device and an automatic test device that can test high-speed devices with high precision. [Prior art documents] [Patent documents]
[0006] [Patent Document 1] Japanese Patent Application Publication No. 2024-014522 Summary of the Invention [Problem to be solved by the invention]
[0007] Patent Document 1 discloses a technology that uses an interposer for electrical connection between a socket board and pin electronics. This technology has the problem that the electrical contacts of the socket board with the interposer wear out as the socket board is repeatedly attached and detached.
[0008] The present disclosure has been made in this context, and one exemplary purpose of an embodiment thereof is to provide an interface device with improved long-term reliability. [Means for solving the problem]
[0009] One aspect of the present disclosure relates to an interface device provided between a test head and a device under test (DUT). The interface device includes a socket board connectable to the DUT on a first surface thereof, and an interposer detachably connected to a second surface of the socket board. The socket board includes a plurality of first pads formed on the second surface for component mounting, and a plurality of second pads formed on the second surface for electrical contact with the interposer. The second pads are thicker than the first pads.
[0010] Any combination of the above components, or mutual substitution of components or expressions between methods, devices, etc., are also valid aspects of the present invention. [Brief explanation of the drawings]
[0011] [Figure 1] FIG. 1 is a diagram illustrating an ATE according to an embodiment. [Figure 2] 1 is a cross-sectional view of an interface device according to one embodiment. [Figure 3] FIG. 2 illustrates a front-end module according to one embodiment. [Figure 4] FIG. 4 is a perspective view showing an example of the configuration of the FEU in FIG. 3. [Figure 5] 4 is a cross-sectional view showing an example of the configuration of the FEU in FIG. 3. [Figure 6] FIG. 1 is a cross-sectional view showing an example of connection between a pin electronics IC and a socket. [Figure 7] FIG. 2 is a cross-sectional view of a socket board according to the embodiment. DETAILED DESCRIPTION OF THE INVENTION
[0012] (Outline of the embodiment) A summary of some exemplary embodiments of the present disclosure is provided. This summary is intended to provide a simplified overview of some concepts of one or more embodiments in order to provide a basic understanding of the embodiments as a prelude to the more detailed description that follows. It is not intended to limit the scope of the invention or disclosure. This summary is not an exhaustive overview of all possible embodiments, and is not intended to identify key elements of all embodiments or to delineate the scope of some or all aspects. For convenience, the term "one embodiment" may refer to one embodiment (example or variant) or multiple embodiments (examples or variants) disclosed herein.
[0013] An interface device according to one embodiment is provided between a test head and a device under test (DUT). The interface device includes a socket board connectable to the DUT on a first surface thereof, and an interposer detachably connected to a second surface of the socket board. The socket board includes a plurality of first pads formed on the second surface for component mounting, and a plurality of second pads formed on the second surface for electrical contact with the interposer. The second pads are thicker than the first pads.
[0014] According to this configuration, by providing different thicknesses for the first pad for component mounting and the second pad that serves as electrical contact with the interposer, the peel strength of the chip component can be increased and the wear resistance of the electrical contact with the interposer can be improved, thereby improving long-term reliability.
[0015] In one embodiment, the thickness of the second pad may be at least twice the thickness of the first pad.
[0016] In one embodiment, the thickness of the second pad may be five times or more the thickness of the first pad.
[0017] In one embodiment, the thickness of the second pad may be eight times or more the thickness of the first pad.
[0018] In one embodiment, the thickness of the first pad may be 0.03 microns ±30% and the thickness of the second pad may be 0.5 microns ±30%.
[0019] An automatic test apparatus according to one embodiment includes a tester main body, a test head, and any of the above-described interface devices connected to the test head.
[0020] (Embodiment) Preferred embodiments will be described below with reference to the drawings. The same or equivalent components, parts, and processes shown in each drawing will be given the same reference numerals, and redundant explanations will be omitted as appropriate. Furthermore, the embodiments are examples and do not limit the disclosure and invention, and all features and combinations thereof described in the embodiments are not necessarily essential to the disclosure and invention.
[0021] In addition, the dimensions (thickness, length, width, etc.) of each component shown in the drawings may be enlarged or reduced as appropriate for ease of understanding. Furthermore, the dimensions of multiple components do not necessarily represent their relative sizes, and even if a component A is depicted as being thicker than another component B in the drawings, it is possible that component A is thinner than component B.
[0022] In this specification, "a state in which component A is connected to component B" includes not only a case in which component A and component B are directly physically connected to each other, but also a case in which component A and component B are indirectly connected to each other via other components that do not substantially affect the electrical connection between them or that do not impair the function or effect achieved by their connection.
[0023] Similarly, "a state in which component C is connected (provided) between component A and component B" includes not only a case in which component A and component C, or component B and component C, are directly connected, but also a case in which they are indirectly connected via other components that do not substantially affect the electrical connection state between them or that do not impair the function or effect achieved by their combination.
[0024] 1 is a diagram showing an ATE 100 according to an embodiment. The ATE 100 includes a tester 120, a test head 130, a handler 150, and an interface device 200.
[0025] The tester 120 performs overall control of the ATE 100. Specifically, the tester 120 executes a test program, controls the test head 130 and the handler 150, and collects measurement results.
[0026] The handler 150 supplies (loads) the DUT1 to the interface device 200, and unloads the tested DUT1 from the interface device 200. The handler 150 also separates the DUT1 into good and bad products.
[0027] The test head 130 includes hardware for generating test signals to be supplied to the DUT 1 and detecting signals (called device signals) from the DUT. It may also include a power supply circuit for generating a power supply voltage to be supplied to the DUT 1 and the interface device 200.
[0028] The interface device 200 includes a socket board 210 , wiring 220 and a front-end module 300 .
[0029] In this embodiment, multiple pin electronics ICs (PE-ICs) 400 are provided in the interface device 200, not in the test head 130. The pin electronics ICs 400 are application specific integrated circuits (ASICs) that integrate drivers that generate test signals and comparators that receive device signals. The test signals and device signals are NRZ signals or PAM4 signals.
[0030] More specifically, a plurality of pin electronics ICs 400 are modularized, and this module is called a front-end module 300.
[0031] The socket board 210 is provided with a plurality of sockets 212. The DUT 1 is attached to the socket 212. The front-end module 300 and the socket 212 are connected via wiring 220.
[0032] The above is the configuration of ATE100.
[0033] According to this ATE 100, by incorporating a front-end module 300, which is made up of multiple pin electronics ICs 400 modularized, into the interface device 200, it becomes possible to place the pin electronics ICs 400 in close proximity to the DUT 1. This makes it possible to significantly shorten the transmission distance of test signals and device signals compared to conventional methods.
[0034] For example, in conventional ATE, the pin electronics IC and the socket board are connected by a coaxial cable approximately 500 mm to 600 mm in length, but in this embodiment, the length of the wiring 220 can be shortened to approximately 100 mm to 150 mm. This significantly reduces the loss of high-frequency components, making it possible to transmit high-speed test signals and device signals. The ATE 100 equipped with this interface device 200 is capable of testing high-speed memories exceeding 20 Gbps.
[0035] Fig. 2 is a cross-sectional view of an interface device 200A according to one embodiment. Fig. 2 shows only the configuration related to one DUT. In this embodiment, the interface device 200A includes a motherboard 230 and a socket board 210 that is detachable from the motherboard 230. The socket board 210 includes a socket 212, a socket printed circuit board (socket PCB) 214, and a socket board-side connector 216.
[0036] The front-end module 300A includes a plurality of printed circuit boards (pin electronics PCBs) 310 on which a plurality of pin electronics ICs 400 are mounted. The plurality of pin electronics PCBs 310 are arranged in a direction perpendicular to the surfaces (front and back surfaces) of the DUT, in other words, the surface S1 of the socket board 210. In this embodiment, the socket board 210 is horizontal to the ground, and therefore the plurality of pin electronics PCBs 310 are arranged parallel to the direction of gravity.
[0037] The front-end module 300A further includes a plate-shaped cooling device (hereinafter referred to as a cold plate) 320. The cold plate 320 has a flow path through which a coolant flows.
[0038] The multiple pin electronics PCBs 310 a , 310 b and the cold plate 320 are stacked such that the pin electronics IC 400 is thermally coupled to the cold plate 320 .
[0039] The motherboard 230 includes a socket board-side connector 232, a spacing frame 234, and a relay connector 236. The front-end module 300A is fixed to the spacing frame 234. The relay connector 236 is electrically and mechanically coupled to the test head-side connector 132.
[0040] As will be described in detail later, the wiring 220 can be a cable (also called an FPC cable) made up of a flexible printed circuit (FPC) instead of a conventional coaxial cable.
[0041] On the other hand, only control signals for the pin electronics IC 400 are transmitted through the wiring 224 between the pin electronics PCB 310 and the relay connector 236, and test signals and device signals are not transmitted through the wiring 224. Therefore, a coaxial cable may be used for the wiring 224.
[0042] FIG. 3 illustrates a front-end module 300B according to one embodiment.
[0043] One DUT 1 is assigned 2×M (M≧1) pin electronics ICs 400. Multiple DUTs and pin electronics ICs 400 are assigned subscripts A to D to distinguish them as needed. In this example, if DUT 1 has 192 I / Os and the pin electronics IC 400 has 24 I / Os, 192 / 24=8 (i.e., M=4) pin electronics ICs 400 are assigned per DUT.
[0044] The front-end module 300B is configured by dividing it into multiple N (N≧2) DUTs 1, and each division unit is called a front-end unit (FEU). In this example, blocks corresponding to four DUTs make up one FEU, and one FEU has 2×M×N=2×4×4=32 pin electronics ICs 400.
[0045] 3 shows two FEUs, the front-end module 300B can actually have more than two FEUs. For example, an ATE capable of 64 simultaneous measurements would have 64 / 4=16 FEUs, and the front-end module 300B as a whole would have 64×192 I / O=12288 I / O.
[0046] Fig. 4 is a perspective view showing an example of the configuration of the FEU in Fig. 3. Sockets 212A-212D corresponding to four DUTs are arranged in a matrix of two rows and two columns. Focusing on one DUT 1A, the eight pin electronics ICs 400A assigned to it are mounted in pairs on four pin electronics PCBs 310a-310d aligned in the X direction. The socket PCB 214 on which the sockets 212 are mounted may be divided for each DUT, or the socket PCBs 214 corresponding to the four DUTs may be integrally configured as a single board.
[0047] Two pin electronics ICs 400A mounted on one pin electronics PCB 310 are arranged side by side in the Y direction. The two pin electronics ICs 400A are arranged at equal distances from the DUT 1A.
[0048] 5 is a cross-sectional view showing an example of the configuration of the FEU of FIG. 3. As shown in FIG. 2, a cold plate 320 is provided between two pin electronics PCBs 310a and 310b. Similarly, a cold plate 320 is provided between two pin electronics PCBs 310c and 310d. As described above, the pin electronics IC 400 is mounted on the pin electronics PCB 310 at a location close to the socket board 210. To improve cooling efficiency, the pin electronics IC 400 can be a bare chip, and the pin electronics IC 400 and the cold plate 320 are thermally coupled via a thermal interface material (TIM) 322.
[0049] When the FEU is viewed in plan along the Y axis, the center of the DUT, that is, the socket 212A, is located at the center of the four (M) pin electronics PCBs 310a to 310d stacked in the X direction.
[0050] This is the composition of the FEU.
[0051] The advantages of this FEU will be explained below. Focus on the DUT1A, which is given the subscript A. By mounting multiple (eight in this example) pin electronics ICs 400A corresponding to one DUT1A, two on each of the four pin electronics PCBs 310a to 310d, it is possible to equalize the distance from each of the eight pin electronics ICs 400A to the socket 212A. This makes it possible to equalize the loss in the transmission line from each pin electronics IC 400A to the socket 212A (DUT1A), enabling accurate testing.
[0052] Next, the electrical connection between the pin electronics IC 400 and the socket 212 will be described.
[0053] 6 is a cross-sectional view showing an example of the connection between a pin electronics IC and a socket (DUT1). An FPC cable 222 is used as the transmission path for transmitting the test signal and device signal, i.e., the wiring 220 between the pin electronics PCB 310 and the socket board 210.
[0054] If a coaxial cable is used as the wiring 220 between the pin electronics PCB 310 and the socket board 210, the rigidity of the coaxial cable restricts the shortest distance between the pin electronics PCB 310 and the socket board 210. In contrast, by using an FPC cable 222, the flexibility of the FPC cable allows the distance h between the pin electronics PCB 310 and the socket board 210 to be shorter than when a coaxial cable is used, thereby shortening the transmission distance of test signals and device signals.
[0055] In conventional test equipment, when a detachable socket board 210 is required, an LIF (Low Insertion Force) connector has generally been used. This LIF connector has a non-negligible loss of about -3 dB in frequency bands higher than 14 GHz, which causes waveform distortion in high-speed transmissions of 28 Gbps or 40 Gbps. By using an FPC cable 222 for the wiring 220, the LIF connector is no longer necessary, and waveform distortion caused by loss (attenuation in the high-frequency band) can be suppressed, enabling accurate testing.
[0056] More specifically, the socket board 210 includes a socket 212 and a socket PCB 214. The socket PCB 214 is a multilayer board including a wiring layer and an insulating layer. Wiring that moves the signal path horizontally is formed in the wiring layer, and via holes VH that move the signal path vertically are formed in the insulating layer. It is preferable that the paths through which the test signals and device signals are transmitted be drawn to the back surface of the socket board 210 without moving horizontally (in the X and Y directions) as much as possible. Conversely, power supply signals and low-frequency control signals may be routed horizontally inside the socket PCB 214.
[0057] The FPC cable 222 and the socket board 210 are connected by a socket board connector 216. The socket board connector 216 includes an interposer 218 and a cable clamp 219.
[0058] The interposer 218 and the socket PCB 214 are detachable. The electrodes exposed on the surface of the interposer 218 are electrically connected to the electrodes exposed on the back surface of the socket PCB 214. The FPC cable 222 is clamped by the cable clamp 219 while in contact with the back surface electrodes of the interposer 218.
[0059] 7 is a cross-sectional view of a socket board 210 according to an embodiment. The socket board 210 has a socket 212 provided on a first surface of a socket PCB 214, which is connected to a DUT. A second surface of the socket board 210 is detachably connected to an interposer 218.
[0060] Furthermore, surface mount devices (SMDs) 213 are mounted on the second surface of the socket board 210. Examples of the SMDs 213 include chip capacitors, chip resistors, and chip inductors. A plurality of first pads (lands) P1 for mounting the SMDs 213 are formed on the second surface of the socket PCB 214.
[0061] Additionally, a plurality of second pads P2 are formed on the second surface of the socket PCB 214 to serve as electrical contacts with the interposer 218. The second pads P2 are electrically connected to corresponding contacts of the interposer 218.
[0062] The first pad P1 has a thickness t1, and the second pad P2 has a thickness t2, and the thicknesses t1 and t2 of the two types of pads P1 and P2 are different (t1≠t2). Specifically, the relationship t2>t1 holds.
[0063] Preferably, the thickness t2 of the second pad P2 is at least twice the thickness t1 of the first pad P1. More preferably, the thickness t2 of the second pad P2 is at least five times the thickness t1 of the first pad P1. Even more preferably, the thickness t2 of the second pad P2 is at least eight times the thickness t1 of the first pad P1.
[0064] For example, the thickness t1 of the first pad P1 is 0.03 microns with a dimensional tolerance of ±30%. In contrast, the thickness t2 of the second pad P2 is 0.5 microns with a dimensional tolerance of ±30%. In this case, the thickness t2 of the second pad P2 is 16 times the thickness t1 of the first pad P1.
[0065] The above is the configuration of the socket board 210.
[0066] With this socket board 210, the first pad P1 for component mounting and the second pad P2 that serves as electrical contact with the interposer 218 have different thicknesses, which increases the peel strength of the SMD 213 and increases the wear resistance of the electrical contact with the interposer 218, thereby improving long-term reliability.
[0067] The interface device 200 may take a variety of forms, and the present disclosure is applicable to any of them.
[0068] SBC (Socket Board Change) type The SBC type is an interface device in which the socket board 210 is replaced depending on the type of DUT.
[0069] CLS (Cable Less) type The CLS type is an interface device in which the interface device 200 can be separated into an upper DSA (Device Specific Adapter) and a lower motherboard, and the DSA is replaced depending on the type of DUT. When the interface device 200 according to this embodiment is applied to the CLS type, two methods are possible.
[0070] One is to place the front-end module 300 on the motherboard side, which is advantageous from the viewpoint of cost because the front-end module 300 can be shared for testing different DUTs.
[0071] Another option is to place the front-end module 300 on the DSA side. In this case, a front-end module 300 is provided for each DSA, which increases the cost of the device. However, this allows the front-end module 300 to be placed closer to the DUT, which is advantageous from the perspective of high-speed testing.
[0072] CCN (Cable Connection) type The CCN type is an interface device in which the entire interface device 200 is replaced depending on the type of DUT. When the interface device 200 according to the present embodiment is applied to the CCN type, it becomes possible to bring the front-end module 300 as close as possible to the DUT, which is advantageous from the viewpoint of high-speed testing.
[0073] Wafer motherboard The interface device 200 may be a wafer motherboard used for wafer-level testing, in which case the interface device 200 may include a probe card instead of a socket board.
[0074] The above-described embodiment is merely an example, and it will be understood by those skilled in the art that various modifications are possible in the combination of the components and the processing steps. Such modifications will be described below.
[0075] (Variation 1) In the embodiment, the pin electronics IC 400 electrically connects the FPC and the printed circuit board using an interposer, but the present disclosure is not limited thereto. A printed circuit board or other wiring may be used as the wiring 220 instead of the FPC cable 222.
[0076] (Variation 2) In the embodiment, the interface device 200 has been described in which the socket board 210 is parallel to the ground, but the present disclosure is not limited thereto. For example, the socket board 210 may be perpendicular to the ground. In this case, the Y direction in Figures 4, 5, etc. is the direction of gravity.
[0077] Although the embodiments of the present disclosure have been described using specific terms, this description is merely an example to facilitate understanding and does not limit the scope of the present disclosure or the claims. The scope of the present invention is defined by the claims, and therefore, embodiments, examples, and modifications not described herein are also included in the scope of the present invention. [Explanation of symbols]
[0078] 1 DUT 100ATE 120 Tester 130 Test Head 200 Interface Device 210 Socket Board 212 sockets 214 Socket PCB 216 Socket board side connector 218 Interposer 219 Cable Clamp 220 Wiring 222 FPC cable 230 motherboard 300 Front End Module 310 pin electronics PCB 312 FPC Connector 314 Interposer 316 Cable Clamp 320 Cold Plate 400 pin electronics IC
Claims
1. An interface device provided between a test head and a device under test (DUT), a socket board connectable to a DUT on a first surface thereof; an interposer detachably connected to the second surface of the socket board; Equipped with The socket board includes: a plurality of first pads formed on the second surface for mounting components; a plurality of second pads formed on the second surface and serving as electrical contacts with the interposer; wherein the second pad is thicker than the first pad.
2. 2. The interface device according to claim 1, wherein the thickness of the second pad is at least twice the thickness of the first pad.
3. 2. The interface device according to claim 1, wherein the thickness of the second pad is at least five times the thickness of the first pad.
4. 2. The interface device according to claim 1, wherein the thickness of the second pad is at least eight times the thickness of the first pad.
5. the thickness of the first pad is 0.03 microns ±30%; 2. The interface device of claim 1, wherein the second pad has a thickness of 0.5 microns ±30%.
6. The tester body and A test head, an interface device according to any one of claims 1 to 5, connected to the test head; An automatic test device comprising:
Citation Information
Patent Citations
Automatic test device and interface device thereof
JP2024014522A