Automatic test equipment for testing an device under test testing method and system

Abstract

The invention relates to an Automatic test equipment (ATE) (2) for testing a device under test (DUT)(20), comprising: a test pin (4), a digital comparator (6), and a source (8) for encoded data, wherein the ATE (2) is configured to communicate with the DUT (20) through the test pin (4). The invention further relates to a method for automatic testing of a DUT device and to a system comprising the ATE and the DUT.

Description

[0001] AUTOMATIC TEST EQUIPMENT FOR TESTING AN DEVICE UNDER TEST TESTING METHOD AND SYSTEM

[0002] DESCRIPTION

[0003] TECHNICAL FIELD

[0004] The invention relates to an automatic test equipment (ATE) for testing a device under test (DUT) and a respective testing method.

[0005] BACKGROUND

[0006] According to the prior art, it is known to test semiconductor devices by means of a 4 point measurement system. In such a case, a voltage is applied via one pair of two pins and a resistance is measured via the other pair of pins . According to further prior art it is also known to include a testing interface for a device under test in a chip, which is connected via an interintegrated circuit . In such a regular testing environment a voltage supplied to the device under test and a clock signal is transmitted via one of the pins and data communication, in particular a Master-in-Slave-out (MISO) signal and a Master-out-Slave-in (MOSI ) signal communication, takes place via the other pin. However, there is a need for reducing the number of necessary connections .

[0007] SUMMARY

[0008] According to one aspect of the invention an automatic test equipment (ATE) for testing a device under test (DUT) is proposed, the ATE comprising:

[0009] a test pin,

[0010] a digital comparator, and

[0011] a source for encoded data,

[0012] wherein the ATE is configured to communicate with the DUT through the test pin. In particular, the digital comparator is arranged for receiving data sent by the DUT with a signal of the source for encoded data . The DUT is in particular provided with a logic unit, a current source a voltage input and a ground input and a single data pin. In particular, the current source might be a transistor connecting the logic unit to the single data pin for outputting a signal .

[0013] The source for encoded data is in particular provided with or connected to a voltage input .

[0014] The advantage of the equipment is to allow testing through a single pin, which reduces the number of necessary connections and allows for a higher flexibility of the design. The current embodiment also allows for low voltage applications .

[0015] According to one embodiment the ATE is configured for sending and receiving data through the test pin. The ATE is in particular configured to send a clock signal through the test pin as well .

[0016] According to one embodiment the encoded data sent by the source for encoded data are G.E . Thomas Manchester encoded data . This allows to reduce the necessary time for data-transfer by one period compared to an encoded data with IEEE standard .

[0017] According to one embodiment the digital comparator is configured for comparing a signal received from the DUT, in particular from the current source of the DUT to a signal received from source for encoded data . The source for encoded data is in particular connected through a resistance R1 to the test pin as well as to the digital comparator .

[0018] According to another aspect of the invention a method for automated testing of a device under test (DUT) through a single test pin is provided, the method comprising a reading method and / or a writing method, wherein the reading method comprises :

[0019] Sending a read-bit (R) ,

[0020] Sending a series of bits comprising an address of the region of interest, receiving a slave acknowledge bit sent by the DUT, receiving a series of data bits from the DUT, followed by a continue-bit (C) or stop-bit (S) ,

[0021] and wherein the writing method comprises :

[0022] Sending a write-bit (W) ,

[0023] Sending a series of bits comprising an address of the region of interest,

[0024] receiving a slave acknowledge bit sent by the DUT, sending a series of data bits to the DUT, followed by a continue-bit (C) or stop-bit (S) .

[0025] The DUT is in particular provided with a logic unit, a current source, a voltage input and a ground input and a single data pin. In particular, the current source might be a transistor connecting the logic unit to the single data pin for outputting a signal . The voltage input of the DUT and of the ATE are in particular on the same voltage level if no signal is applied.

[0026] According to one embodiment the method is performed by the ATE as described above .

[0027] According to one embodiment the encoded data sent to the DUT in particular by the source are G.E . Thomas Manchester encoded data .

[0028] According to one embodiment receiving a slave acknowledge bit sent by the DUT is receiving a slave acknowledge bit sent by a current source of the DUT, in particular through the transistor of the DUT .

[0029] According to one embodiment the DUT is provided with a logic unit, a current source, a voltage input and a ground input and a single data pin, in particular, wherein the current source is a transistor connecting the logic unit to the single data pin for outputting a signal to the ATE .

[0030] According to another aspect of the invention a system is provided comprising an ATE as described above and a DUT as described above . The ATE and the DUT are connected with the test pin to the single data pin. In particular, the voltage input of the DUT and of the ATE are in particular on the same voltage level if no signal is applied.

[0031] BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Exemplary embodiments of the invention are discussed below with reference to the accompanying drawings

[0033] FIG. 1 shows an automatic test equipment (ATE) connected to a device under test (DUT) ,

[0034] FIG. 2 shows an exemplary protocol .

[0035] DETAILED DESCRIPTION

[0036] FIG. 1 shows an automatic test equipment (ATE) 2 for testing a device under test (DUT) 20, which is a coupled to the DUT 20 .

[0037] The ATE 2 comprises a test pin 4, a comparator 6 and a source 8 for encoded data . Furthermore, the ATE 2 comprises a voltage input . The voltage input is connected to the source 8 for encoded data . The comparator 6 is a digital comparator which is connected to the source 8 for encoded data via pin 4, wherein a switch might be provided for opening and closing the connection to the comparator 6. Between the source 8 for encoded data and pin 4 a resistance R1 is switched. In the present example, the resistance R1 might be a resistance of 50 mQ. The source 8 for encoded data is provided with or connected to an voltage input being VDD.

[0038] The ATE 2 is configured to communicate with the DUT 20 through the test pin 4 .

[0039] On the left hand side of the circuit diagram, the DUT 20 is provided with a logic unit 22. The DUT 20 is further provided with an voltage input 26 and a ground input 28 as well as an pin 30. The voltage input 26 is in particular as well connected to VDD or has the same voltage level . The logic unit 22 is connected to the pin 32 as input and has a back connection to the same pin via a current source 24. The current source 24 can be configured as a transistor . The pin 32 is connected with the test pin 4 of the ATE 2. If a logical zero is sent through the pin 32 to the logic unit 22, the current source 24 opens a back signal pass from the logic unit 22 to the ATE 2. The digital comparator 6, which is configured to compare a voltage from the voltage source of the ATE with an input signal from the DUT may detect a voltage drop . This voltage drop is for example a voltage drop of 200 mV .

[0040] For detecting a voltage drop at the comparator 6 of the ATE 2 the current source might provide for example a current of 4 mA.

[0041] FIG. 2 shows an exemplary protocol of the method for testing a device under test (DUT) .

[0042] In the first line a single read is shown. The bits are Manchester G.E . Thomas encoded. Thus, a read bit (R) followed by an address is sent, which is acknowledged by a slave acknowledge (SA) . Therefore, the current source of the DUT is enabled, which pulls down the voltage level of the DUT, thus a DUT pull down is activated. The pull down of the signal acknowledges the receipt of the address as SA signal . The SA is followed by the data reading which is acknowledged by the ATE by sending a master acknowledge (MA) in the form of a GE Thomas Manchester encoded 0. For the single read a stop bit (S) is sent, which finishes the reading DUT pulled down. For a multiread as shown in the second line a continue bit (C) is sent instead of the stop bit .

[0043] FIG. 2 shows as well a single write and a multi-write . Both are started with a write bit (W) . After the slave acknowledge (SA) , the Pull down is not activated during writing. If instead of the encoding according to Manchester G.E . Thomas the IEEE standard is used, an additional period is necessary . LIST OF REFERENCE SIGNS

[0044] Automatic test equipment 2 Test Pin 4 Comparator 6 Source for encoded data 8

[0045] Device Under Test 20 Logic unit 22 Current source 24 Voltage input 26 Ground input 28 Pin 30

Claims

CLAIMS1 . Automatic test equipment (ATE ) ( 2 ) for testing a device under test ( DUT ) ( 20 ) , comprising :a test pin ( 4 ) ,a digital comparator ( 6 ) , anda source ( 8 ) for encoded data,wherein the ATE ( 2 ) is configured to communicate with the DUT ( 20 ) through the test pin ( 4 ) .2 . ATE ( 2 ) according to claim 1 ,wherein the ATE ( 2 ) is configured for sending and receiving data through the test pin ( 4 ) .3 . ATE ( 2 ) according to claim 1 or 2 , wherein test pin ( 4 ) is the only test pin of the ATE ( 2 ) .4 . ATE ( 2 ) according to any of claims 1 to 3 , wherein the encoded data sent by the source ( 8 ) for encoded data are G . E . Thomas Manchester encoded data .

5. ATE ( 2 ) according to any of claims 1 to 4 , wherein the digital comparator ( 6 ) is configured for comparing a signal received from the DUT ( 20 ) to a signal received from source ( 8 ) for encoded data .

6. Method for automated testing of a device under test (DUT ) ( 20 ) through a single test pin ( 4 ) , the method comprising a reading method and / or a writing method, wherein the reading method comprises :Sending a read-bit (R) ,Sending a series of bits comprising an address of the region of interest ,receiving a slave acknowledge bit sent by the DUT ( 20 ) , receiving a series of data bits from the DUT ( 20 ) , followed by a continue-bit ( C ) or stop-bit ( S ) ,and wherein the reading method comprises :Sending a write-bit (W) ,Sending a series of bits comprising an address of the region of interest ,receiving a slave acknowledge bit sent by the DUT ( 20 ) , sending a series of data bits to the DUT ( 20 ) , followed by a continue-bit ( C ) or stop-bit ( S ) .7 . Method according to claim 6 , wherein the method is performed by the ATE ( 2 ) according to any of claims 1 to 5 .8 . Method according to claim 6 or 7 , wherein the encoded data sent to the DUT ( 20 ) , in particular by the source ( 8 ) , are G . E . Thomas Manchester encoded data .

9. Method according to any of claims 6 to 8 , wherein receiving a slave acknowledge bit sent by the DUT ( 20 ) is receiving a slave acknowledge bit sent by a current source ( 24 ) of the DUT ( 20 ) , in particular the current source ( 24 ) being a transistor of the DUT ( 20 ) .10 . Method according to any of claims 6 to 9 , wherein the DUT ( 20 ) is provided with a logic unit ( 22 ) , a current source ( 24 ) , a voltage input ( 26 ) and a ground input ( 28 ) and a single data pin ( 32 ) , in particular, wherein the current source is a transistor connecting the logic unit ( 22 ) to the single data pin ( 32 ) for outputting a signal to the ATE ( 2 ) .11 . System comprising an ATE ( 2 ) according to one of claims 1 to 5 and a DUT ( 20 ) , comprising a logic unit ( 22 ) , a current source ( 24 ) , a voltage input ( 26 ) and a ground input ( 28 ) and a single data pin ( 32 ) .

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