Test power supply adjusting method and device, automatic test equipment and storage medium

Abstract

The invention belongs to the technical field of chip testing, and relates to a testing power supply adjusting method and device, automatic testing equipment and a storage medium. Test program text information is obtained and compiled, a test program compiling result file containing test instruction sequence information and burst data block information is obtained, and a first-level voltage value is preset based on the burst data block information and a preset constraint strategy. And in the chip test execution process, the secondary voltage value is dynamically and finely adjusted based on the primary voltage value and the burst data block information. According to the invention, on the premise that the test precision and the power supply stability are ensured, the power supply voltage of the chip can be quickly adjusted, so that the test efficiency in a high-speed and large-quantity test vector execution scene is remarkably improved, and the problems of low power supply adjustment speed and low test efficiency in the prior art are effectively solved.

Description

Technical Field

[0001] This application belongs to the field of chip testing technology, specifically relating to a test power supply adjustment method, device, automated test equipment, and storage medium. Background Technology

[0002] Automatic Test Equipment (ATE) is a crucial piece of equipment used in the integrated circuit manufacturing process to verify the functionality and performance of chips. Its main function is to provide input stimuli to the Device Under Test (DUT) via test vectors and collect the output response to determine whether the chip meets design requirements, thus distinguishing between qualified and unqualified chips. With the continuous expansion of integrated circuit scale and the increase in operating frequency, the amount of data and computational complexity during testing have increased significantly, placing higher demands on the speed, accuracy, and reliability of test equipment.

[0003] In testing high-density integrated circuits such as memory chips, it is necessary to traverse the memory cell array or specific functional modules and simulate various voltages and operating scenarios to verify the chip's performance under different conditions. These tests often involve the rapid, continuous output of a large number of test vectors, as well as concentrated testing of specific regions (such as burst block mode). Existing technologies suffer from limited testing efficiency and long processing times when executing high-speed, multi-sub-cycle instruction pattern programs. Furthermore, they lack the ability to rapidly adjust the power supply to the DUT, making it difficult to accurately adjust the power supply voltage within a short time, especially in high-frequency scenarios with a large number of test vectors.

[0004] In developing this application, the inventors discovered that the prior art suffers from at least the following problems: insufficient coordination between the test program and power supply adjustment during high-speed, high-volume test vector execution, leading to low overall test efficiency; limited response speed of existing power supply adjustment methods, making it difficult to meet the time requirements of high-frequency testing; and deficiencies in the coordination between power supply and instruction execution in concentrated burst test scenarios, restricting further improvements in chip testing efficiency. Therefore, how to improve test vector execution efficiency and achieve rapid power supply response while ensuring test accuracy remains a pressing issue in the field of semiconductor chip testing. Summary of the Invention

[0005] To address the aforementioned issues, this application provides a test power supply adjustment method, apparatus, automated test equipment, and storage medium. By rapidly adjusting the chip power supply voltage, it significantly improves test efficiency in scenarios involving high-speed and large-volume test vector execution.

[0006] To address the aforementioned technical problems, one technical solution adopted in this application is: providing a test power supply adjustment method, the method comprising: acquiring test program text information to be executed; compiling the test program text information to obtain test program compilation result file information; wherein the test program compilation result file information includes test instruction sequence information and burst data block information; presetting a first-level voltage value based on the burst data block information and a preset constraint strategy; and performing a second-level voltage value fine-tuning process based on the burst data block information and the first-level voltage value when performing chip testing according to the test instruction sequence information.

[0007] In some embodiments, the test program text information is compiled to obtain test program compilation result file information, including: recognizing the test program text information to obtain test instructions and voltage adjustment instructions; generating corresponding test instruction sequence information based on the test instructions; generating corresponding burst data block information based on the voltage adjustment instructions; and obtaining test program compilation result file information based on the test instruction sequence information and burst data block information.

[0008] In some embodiments, the burst data block information includes a target reference voltage value for the secondary voltage. Based on the burst data block information and a preset constraint strategy, a primary voltage value is preset, including: calculating the primary voltage value based on the target reference voltage value and a preset threshold; and executing a preset process based on the primary voltage value. The primary voltage value satisfies a first preset constraint condition, which includes the primary voltage value being greater than the target reference voltage value, the primary voltage value not being greater than the target voltage allowable upper limit, and the primary voltage value not being greater than a preset allowable maximum output voltage.

[0009] In some embodiments, a preset process is executed based on the primary voltage value, including: obtaining a register code corresponding to the primary voltage value based on the primary voltage value; and writing the register code into a preset primary voltage register.

[0010] In some embodiments, the test instruction sequence information includes a secondary voltage fine-tuning instruction. When chip testing is performed according to the test instruction sequence information, a secondary voltage value fine-tuning process is performed based on burst data block information and primary voltage value, including: during chip testing, reading burst data block information corresponding to the secondary voltage fine-tuning instruction according to the secondary voltage fine-tuning instruction; and adjusting the secondary voltage value based on the primary voltage value and the target reference voltage value in the burst data block information.

[0011] In some embodiments, adjusting the secondary voltage value based on the primary voltage value and the target reference voltage value in the burst data block information includes: during chip testing, adjusting the secondary voltage value based on a second preset constraint, the primary voltage value, and the target reference voltage value; wherein the second preset constraint includes the secondary voltage value not being greater than the primary voltage value and the deviation between the secondary voltage value and the target reference voltage value being within a preset tolerance range.

[0012] To solve the above-mentioned technical problems, another technical solution adopted in this application is: providing a test power supply adjustment device, the device comprising: a test program text information acquisition module, used to acquire test program text information to be executed; a test program compilation result file information acquisition module, used to compile the test program text information to obtain test program compilation result file information; wherein, the test program compilation result file information includes test instruction sequence information and burst data block information; a first-level voltage value acquisition module, used to preset the first-level voltage value according to the burst data block information and a preset constraint strategy; and a second-level voltage value fine-tuning process execution module, used to execute the second-level voltage value fine-tuning process based on the burst data block information and the first-level voltage value when performing chip testing according to the test instruction sequence information.

[0013] To solve the above-mentioned technical problems, another technical solution adopted in the embodiments of this application is: to provide an automated testing device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the above-mentioned method.

[0014] To solve the above-mentioned technical problems, another technical solution adopted in the embodiments of this application is: to provide a non-volatile computer-readable storage medium that stores computer-executable instructions, which, when executed by an automated testing device, cause the automated testing device to perform the above-mentioned method.

[0015] To solve the above-mentioned technical problems, another technical solution adopted in the embodiments of this application is: to provide a computer program product, the computer program product including a computer program stored on a non-volatile computer-readable storage medium, the computer program including program instructions, and when the program instructions are executed by an automated testing device, the automated testing device performs the above-mentioned method.

[0016] Unlike related technologies, this application provides a test power supply adjustment method, apparatus, automated test equipment, and storage medium. By acquiring and compiling test program text information, a test program compilation result file containing test instruction sequence information and burst data block information is obtained. A primary voltage value is preset based on the burst data block information and a preset constraint strategy. During chip testing, the secondary voltage value is dynamically fine-tuned based on the primary voltage value and the burst data block information. This application can achieve rapid adjustment of the chip power supply voltage while ensuring test accuracy and power supply stability, thereby significantly improving test efficiency in high-speed, high-volume test vector execution scenarios and effectively solving the problems of slow power supply adjustment speed and low test efficiency in existing technologies. Attached Figure Description

[0017] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements having the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0018] Figure 1 This is a schematic diagram of the structure of a power adjustment system provided in an embodiment of this application; Figure 2 This is a flowchart of a test power supply adjustment method provided in an embodiment of this application; Figure 3 This is a schematic diagram of the structure of a test power supply adjustment device provided in an embodiment of this application; Figure 4 This is a schematic diagram of the hardware structure of an automated test device for performing a test power supply adjustment method, provided in an embodiment of this application. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and thoroughly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0020] It should be noted that, unless otherwise specified, the various features in the embodiments of this application can be combined with each other, all of which are within the protection scope of this application. Furthermore, although functional modules are divided in the device schematic diagram and a logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than the module division in the device schematic diagram or the order in the flowchart.

[0021] When an element is described as "connected" to another element, it can be directly connected to the other element, or there may be one or more intervening elements between them.

[0022] Unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application.

[0023] Please see Figure 1 , Figure 1 This is a schematic diagram of a power adjustment system provided in an embodiment of this application. Figure 1 As shown, the power adjustment system 100 includes: a test program compiler module 110, a test central processing unit module 120, an algorithm graphics generator module 130, and a power supply control module 140. The test central processing unit module 120 is communicatively connected to the test program compiler module 110 and the algorithm graphics generator module 130, respectively. The algorithm graphics generator module 130 is electrically connected to the power supply control module 140, and the power supply control module 140 is connected to the device under test (DUT).

[0024] The test program compiler module 110 (Pattern compiler) is typically a software tool or module running on the ATE (Automatic Test Equipment) to convert manually written chip test program text into hardware-executable instructions and data formats. In this embodiment, the test program compiler module 110's functions include, but are not limited to: reading test program text information; parsing various test instructions and voltage adjustment instructions in the Pattern program (these adjustment instructions are organized in the program as "burst blocks," i.e., a group of centrally executed voltage adjustment operations); generating data blocks; translating the voltage adjustment instructions in each burst block into register format data recognizable by the power supply control module 140 interface; these data sets are called "data blocks," which are then written to the Pattern compilation result file or a separate Burst Block data file; and generating instruction references; in the Pattern program, the execution of each burst block typically corresponds to a specific instruction (which may be called a BSTBLK instruction), which points to the corresponding data block in the compiled binary code, instructing the algorithm pattern generator module 130 to read and apply these data blocks during execution. Output compilation results: Finally, a complete Pattern compilation result program file is formed, which is the test program compilation result file information, including test instruction sequence information and information of each burst data block, for the test central processing unit module 120 and algorithm graphics generator module 130 to load and execute.

[0025] The test central processing unit module 120 (test CPU) is the control core of the system and can be a general-purpose CPU or a dedicated controller. It is used to manage the test process, load instructions, and control the ALPG. In this embodiment, the test central processing unit module 120 includes: a test main control program unit 121, responsible for executing the Pattern compilation result program according to the test strategy; an interface function library unit 122, used to load the test program compilation result file information into the ALPG instruction space of the test central processing unit module 120; and a driver unit 123, responsible for sequentially loading the test instruction sequence information into the instruction space of the ALPG of the algorithm graphics generator module 130, and simultaneously sequentially loading the information of each burst data block into the memory space of the designated ALPG of the algorithm graphics generator module 130.

[0026] The Algorithm Pattern Generator module 130 is a high-speed signal generation module (Algorithmic Pattern Generator, ALPG) in the ATE (Automatic Test Equipment), used to generate excitation and trigger signals according to the test instruction sequence information to actually drive the DUT (Digital Under Test). In this embodiment, the functions of the Algorithm Pattern Generator module 130 include, but are not limited to: reading instructions and data blocks: reading the corresponding burst block data block according to the BSTBLK instruction; generating excitation signals: generating high-speed test vectors according to the test instruction sequence to trigger the secondary voltage fine-tuning; and transmitting voltage control information: writing the burst block data into the register of the power supply control module 140 to realize voltage control of the DUT.

[0027] The power supply control module 140 is the actual power controller or power management device used to provide adjustable voltage and current to the DUT. In this embodiment, the functions of the power supply control module 140 include, but are not limited to: receiving ALPG instruction data: obtaining burst block data from the algorithm graphics generator module 130; writing to registers and outputting voltage: writing data to the interface register of the power supply control module 140 and outputting the corresponding primary and secondary voltages to the DUT; supporting secondary fine-tuning: when the test program is triggered, performing rapid secondary voltage fine-tuning based on the target reference voltage to ensure that the voltage is within the expected range.

[0028] It should be noted that, for the sake of making the following description more intuitive, the Pattern compiler module 110, the test CPU module 120, the ALPG module 130, and the PPS module 140 will be used to replace the test program compiler module 110, the test central processing unit module 120, the algorithm graphics generator module 130, and the power supply control module 140.

[0029] The implementation process of a test power supply adjustment method provided in this application will be described in detail below with reference to specific embodiments.

[0030] Please see Figure 2 , Figure 2 This is a flowchart illustrating a power supply adjustment method according to an embodiment of this application. The method is applied to the power supply adjustment system 100 described above. Figure 2 As shown, the method includes steps S11-S14: S11: Obtain the text information of the test program to be executed.

[0031] S12: Compile the test program text information to obtain test program compilation result file information; wherein, the test program compilation result file information includes test instruction sequence information and burst data block information.

[0032] The step of compiling the test program text information to obtain test program compilation result file information includes: recognizing the test program text information to obtain test instructions and voltage adjustment instructions; generating corresponding test instruction sequence information based on the test instructions; generating corresponding burst data block information based on the voltage adjustment instructions; and obtaining the test program compilation result file information based on the test instruction sequence information and the burst data block information.

[0033] Before performing chip testing, the test CPU module 120 acquires the test program text information to be executed from a storage medium or external input interface. This test program text information is a pattern program text, written by a test engineer, and includes test instructions controlling the DUT operation and voltage adjustment instructions for voltage regulation. The voltage adjustment instructions are typically organized in burst blocks, each containing a set of centrally executed voltage adjustment operations. During the acquisition process, the test CPU module 120 transmits the test program text information to the pattern compiler module 110 and performs data integrity verification to ensure the text information is complete and error-free.

[0034] Subsequently, the Pattern compiler module 110 compiles the test program text information, identifying the test instructions and voltage adjustment instructions within it. For the test instructions, the Pattern compiler 110 generates corresponding test instruction sequence information, which describes the specific instructions and order that the ALPG module 130 should execute in each operation cycle during chip testing to drive the device under test (DUT) to generate a test response. For the voltage adjustment instructions, the Pattern compiler 110 translates each instruction into register format data recognizable by the PPS module 140 interface (e.g., "VSUPPLY1" is converted into interface register data of the PPS module 140 on the DUT power supply pin 1), and organizes all data within the same burst block into a group of burst block data. Each data block includes metadata such as the target reference voltage value, load and current constraint parameters, data block length, and repetition count.

[0035] Finally, the Pattern compiler 110 combines the generated test instruction sequence information with the corresponding burst data block information to form a complete test program compilation result file. This test program compilation result file will be loaded into the instruction space and memory space of the ALPG module 130, enabling rapid access to burst data blocks via the BSTBLK instruction during testing, thus achieving dynamic adjustment of the DUT voltage. After completing the above operations, the Pattern compiler 110 outputs the test program compilation result file to the test CPU module 120 for subsequent instruction loading and chip testing execution.

[0036] In step S11, by acquiring the text information of the test program to be executed, the target of chip testing and the instructions to be executed can be clearly defined, providing basic data for subsequent compilation and voltage control. In step S12, the test program text information is compiled to generate test program compilation result file information, including test instruction sequence information and burst data block information. By organizing the test instructions into test instruction sequence information, it can be ensured that the ALPG module 130 executes the test operation accurately according to the predetermined timing, ensuring the stability and consistency of the test signal; at the same time, the voltage adjustment instructions are translated into burst data block information and organized into structured data, which can be quickly loaded into the ALPG hardware memory, providing reliable data basis for first-level voltage preset and second-level voltage fine-tuning. Therefore, the implementation of steps S11 and S12 can improve the controllability and stability of chip testing, ensure that instruction execution and voltage adjustment are synchronized, and lay the foundation for subsequent optimization of power supply adjustment time.

[0037] S13: Based on the burst data block information and the preset constraint strategy, preset the first-level voltage value.

[0038] The burst data block information includes a target reference voltage value for the secondary voltage. The step of presetting a primary voltage value based on the burst data block information and a preset constraint strategy includes: calculating the primary voltage value based on the target reference voltage value and a preset threshold; and executing a preset process based on the primary voltage value. The primary voltage value satisfies a first preset constraint condition, which includes the primary voltage value being greater than the target reference voltage value, the primary voltage value not being greater than the target voltage's allowable upper limit, and the primary voltage value not being greater than a preset allowable maximum output voltage.

[0039] The step of executing a preset process based on the first-level voltage value includes: obtaining a register code corresponding to the first-level voltage value based on the first-level voltage value; and writing the register code into a preset first-level voltage register.

[0040] First, the burst data block information generated in step S12 is obtained. This burst data block information is a set of data structures translated from voltage adjustment instructions during the compilation process, stored in the compilation result file, and includes at least the following voltage control and constraint parameters: a target reference voltage value used to indicate the secondary voltage adjustment target (…). ), preset voltage threshold (Δfixed or Δmax), and system operation safety limit parameters ( The parameters mentioned above are used to guide the initial setting of the first-level voltage value and subsequent offset interval constraints, so that the first-level voltage value can be used as an approximate initial value for the subsequent second-level voltage fine-tuning process.

[0041] Secondly, based on the target reference voltage value and the preset threshold, the first-level voltage value is calculated according to a preset constraint strategy. This preset constraint strategy ensures that the first-level voltage value meets testing requirements while avoiding voltage regulation response delays, system overshoot, or damage to the device under test (DUT) due to excessive voltage jumps. Specifically, the first-level voltage value must meet the following first preset constraints: 1) The first-level voltage value is greater than the target reference voltage value, so that the second-level voltage fine-tuning process has an adjustment direction that approaches downwards or makes small corrections towards the target point; 2) The first-level voltage value is not greater than the upper limit of the target voltage, ensuring that the subsequent second-level adjustment range is within a controllable range; 3) The first-level voltage value is not greater than the preset maximum allowable output voltage, to avoid exceeding power supply safety limits.

[0042] In actual implementation, the first-level voltage value can be calculated using the following formula:

[0043] in, This is the target reference voltage value for the secondary voltage. To maintain a fixed bias voltage, thus ensuring room for adjustment increments. The maximum allowable bias is defined by the system security policy, i.e. The upper limit of the target voltage. This is the highest voltage value allowed by the entire voltage regulation system, i.e., the preset maximum allowable output voltage.

[0044] Next, based on the calculated first-level voltage value, it is converted into a register code that matches the register interface format of the PPS module 140. This register code is used to configure the coarse-adjustment voltage level to the hardware layer. The encoding result includes, but is not limited to, the first-level voltage control register code (REG_COARSE). Subsequently, the test CPU module 120 calls the driver unit 123 to write the register code into the preset first-level voltage register to complete the first-level voltage preset process. This preset process is performed before chip testing and is placed in a non-critical latency path, which can reduce the latency caused by real-time adjustment calculations during testing.

[0045] It is understandable that if a burst of data block information contains the target reference voltage value... Maximum allowable bias value Preset maximum allowable output voltage And fixed bias The calculated result of the first-level voltage value is:

[0046] Finally, the 0.93V is converted into an encoded value recognizable by the registers of the PPS module 140, such as REG_COARSE = 0x1F, and written to the first-level voltage register by the test CPU module 120 for subsequent fast startup and output.

[0047] By presetting the first-level voltage value based on the target reference voltage value contained in the burst data block information in step S13, combined with a preset constraint strategy, the coarse adjustment and safety range locking of the voltage can be completed before the chip test enters the power adjustment stage. This ensures that the deviation between the first-level voltage value and the final target second-level voltage value is within a controllable range, allowing the subsequent rapid fine-tuning process based on the second-level voltage to achieve output voltage convergence with only minor adjustments, significantly reducing the power adjustment time. Simultaneously, by applying multiple constraints to the first-level voltage value, including the upper limit constraint of the target reference voltage and system safety capability constraints, overvoltage, false voltage, or power transient impacts caused by improper voltage presetting can be effectively avoided, thereby reducing the potential damage risk to the chip under test and improving the reliability and safety of the overall testing process. Furthermore, this first-level presetting strategy can advance the complex voltage calculation and register configuration operations that were originally performed on the critical path of the test to the compilation stage, eliminating the need for real-time calculations and repetitive data communication during the testing stage. This reduces system load and the degree of CPU involvement in the test, ultimately achieving the technical effects of optimized voltage adjustment time, improved chip testing efficiency, and enhanced overall throughput of the testing system.

[0048] S14: When performing chip testing according to the test instruction sequence information, a second-level voltage value fine-tuning process is executed based on the burst data block information and the first-level voltage value.

[0049] The test instruction sequence information includes a secondary voltage fine-tuning instruction. When the chip test is performed according to the test instruction sequence information, the secondary voltage value fine-tuning process is performed based on the burst data block information and the primary voltage value, including: during the chip test, reading the burst data block information corresponding to the secondary voltage fine-tuning instruction according to the secondary voltage fine-tuning instruction; and adjusting the secondary voltage value based on the primary voltage value and the target reference voltage value in the burst data block information.

[0050] The step of adjusting the secondary voltage value based on the primary voltage value and the target reference voltage value in the burst data block information includes: during the chip test, adjusting the secondary voltage value based on a second preset constraint, the primary voltage value, and the target reference voltage value; wherein the second preset constraint includes the secondary voltage value not being greater than the primary voltage value and the deviation between the secondary voltage value and the target reference voltage value being within a preset tolerance range.

[0051] During the ATE's chip testing operation based on the test instruction sequence information, when a secondary voltage fine-tuning instruction contained in the test instruction sequence information is triggered, the ALPG module 130 identifies and parses the secondary voltage fine-tuning instruction. Based on the index information corresponding to the instruction, it reads the target reference voltage value (used to indicate the desired voltage setting under ideal power supply conditions) corresponding to the current test cycle from the burst data block information stored in its internal data buffer. The secondary voltage fine-tuning instruction is an executable instruction (such as the OUT voltage adjustment instruction) used to trigger a precise voltage adjustment process. The burst data block information is a data structure unit pre-generated during the compilation stage, used to store the target reference voltage value, adjustment strategy parameters, and limit threshold information.

[0052] After reading the target reference voltage value, the ALPG module 130 sends a register trigger command to the PPS module 140, controlling the digital-to-analog converter (DAC) and voltage amplification unit inside the PPS module 140 for voltage output to enter the secondary voltage adjustment mode. Based on the preset primary voltage value (i.e., the coarse adjustment voltage value completed in step S13 to ensure that the initial voltage state is close to the target reference voltage), combined with the target reference voltage value contained in the burst data block information, the PPS module 140 performs a fast and fine-tuning operation of the secondary voltage value and starts the internal closed-loop regulation control logic, which includes a real-time voltage sampling unit, a feedback error calculation unit, and a closed-loop regulation execution unit, so as to dynamically calibrate and quickly converge the target voltage at the hardware level.

[0053] During the adjustment of the secondary voltage value, the PPS module 140 executes voltage regulation logic based on a preset second constraint. This second preset constraint is used to ensure the safety and stability of the voltage value during the fine-tuning process, specifically including but not limited to: the secondary voltage value must be less than or equal to the primary voltage value to avoid abnormal current surges caused by reverse voltage crossings; the deviation between the secondary voltage value and the target reference voltage value must be within a preset tolerance range to ensure that the final output voltage meets the test requirements and achieves rapid error convergence, thereby avoiding prolonged oscillation adjustment or repeated triggering of adjustment commands due to exceeding the adjustment range. The preset tolerance range can be set according to actual conditions and is not limited here.

[0054] Under the premise of meeting the above constraints, the PPS module 140 performs real-time voltage sampling and error convergence determination until the secondary voltage value converges to near the target reference voltage value and meets the preset convergence threshold. Then, the adjusted secondary voltage value is stably output to the corresponding power supply pin of the device under test (DUT) to support the accurate execution of subsequent test steps.

[0055] In practical applications, for example, if the target reference voltage is 1.200V and the first-level voltage is 1.240V (meeting the "target reference voltage + Δfixed" constraint), with a preset tolerance range of ±5mV, after the PPS module 140 performs fine-tuning, the second-level voltage will quickly converge to the range of 1.195V~1.205V and remain stable. The entire fine-tuning process can generally be completed in microseconds to milliseconds, thereby significantly reducing the voltage stabilization waiting time in the chip testing process and improving the testing throughput.

[0056] Based on the aforementioned coordinated control of the primary voltage coarse adjustment and the secondary voltage fine adjustment, this step, by re-executing the target test command sequence after the final voltage setting, verifies the output test response data and judges the results. This ensures that the set secondary final operating voltage not only meets the theoretical calculation constraints but also maintains functional stability, timing consistency, and controllable bit error rate under actual test operation conditions, thereby achieving closed-loop verification and quality confirmation of the voltage setting results. This result verification mechanism effectively avoids unreliable voltage setting problems caused by test errors, noise disturbances, transient response deviations, or inaccurate model estimations, ensuring that the voltage setting results are traceable, repeatable, and engineering feasible, ultimately improving the reliability, safety margin, and production yield of the ATE testing strategy.

[0057] This application provides a test power supply adjustment method. By systematically compiling and processing the chip test program text information, test instruction sequence information and burst data block information can be automatically generated, thereby achieving systematic management of the target voltage reference value and voltage adjustment instructions for each BurstBlock. Based on this, by presetting a first-level voltage value, the slow-motion coarse-tuning calculation is advanced to the non-critical path, ensuring that the first-level voltage value meets the target reference voltage constraint while remaining within the maximum allowable range of the system, thus providing a stable and safe foundation for subsequent rapid fine-tuning. During the chip test execution phase, a closed-loop, fast, and accurate second-level voltage adjustment is achieved through second-level voltage fine-tuning based on the first-level voltage value and the target reference voltage value. The fine-tuning process is controlled by a second preset constraint condition, namely, the second-level voltage value is not greater than the first-level voltage value, and the deviation from the target reference voltage value is kept within a preset tolerance range, thus balancing voltage convergence speed and chip functional reliability. By combining the first-level voltage preset with rapid second-level voltage fine-tuning, this method significantly shortens the voltage adjustment time and avoids the low test efficiency problem caused by long convergence times or multiple iterations of the second-level voltage in traditional methods. Based on this, the method has the following characteristics: 1) It advances slow-motion calculations to the compilation stage, reducing the computational burden during pattern execution and improving the overall efficiency of the testing process; 2) The first-level voltage preset provides a stable coarse-tuning foundation, enabling the second-level voltage fine-tuning to converge in a very short time, achieving high-precision and fast-response voltage adjustment; 3) The second-level voltage fine-tuning process follows constraints, ensuring the safety and reliability of the chip during testing, while ensuring that the target voltage accuracy is within a controllable range; 4) This method makes full use of test instruction sequence information and burst data block information to achieve traceability, repeatability, and mass production capability of voltage adjustment, improving the stability and robustness of the automated testing system; 5) By comprehensively applying this method, the efficiency of ATE testing can be significantly improved while ensuring test accuracy and chip safety, especially suitable for chip testing scenarios of high-frequency, large-scale memory arrays.

[0058] Based on the test power supply adjustment method provided in the above embodiments, this application further provides a test power supply adjustment device. Please refer to... Figure 3 , Figure 3 This is a schematic diagram of the test power supply adjustment device. (For example...) Figure 3 As shown, the test power adjustment device 200 includes: a test program text information acquisition module 210, a test program compilation result file information acquisition module 220, a first-level voltage value acquisition module 230, and a second-level voltage value fine-tuning process execution module 240.

[0059] The test program text information acquisition module 210 is used to acquire the test program text information to be executed before chip testing; the test program compilation result file information acquisition module 220 is used to compile the test program text information to obtain the test program compilation result file information; wherein, the test program compilation result file information includes test instruction sequence information and burst data block information; the first-level voltage value acquisition module 230 is used to preset the first-level voltage value according to the burst data block information and the preset constraint strategy; the second-level voltage value fine-tuning process execution module 240 is used to execute the second-level voltage value fine-tuning process based on the burst data block information and the first-level voltage value when chip testing is performed according to the test instruction sequence information.

[0060] It should be noted that the above-mentioned test power supply adjustment device can execute the test power supply adjustment method provided in the embodiments of this application, and has the corresponding functional modules and beneficial effects of the method. Technical details not described in detail in the test power supply adjustment device embodiments can be found in the test power supply adjustment method provided in the embodiments of this application.

[0061] This application also provides an automated testing equipment 300 (ATE). Please refer to [link to relevant documentation]. Figure 4 This diagram illustrates the hardware structure of an automated testing device 300 capable of performing the methods described in the above embodiments. The automated testing device 300 includes: at least one processor 310; and a memory 320 communicatively connected to the at least one processor 310. Figure 4 Taking a processor 310 as an example, the memory 320 stores instructions executable by the at least one processor 310. These instructions, when executed by the at least one processor 310, enable the at least one processor 310 to perform the test power supply adjustment method described in the above embodiment. The processor 310 and the memory 320 can be connected via a bus or other means. Figure 4 Taking the example of a connection between China and Israel via a bus.

[0062] The memory 320, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as the program instructions / modules corresponding to the test power adjustment method in the embodiments of this application. The processor 310 executes various functional applications and data processing of the server by running the non-volatile software programs, instructions, and modules stored in the memory 320, thereby implementing the test power adjustment method described in the above embodiments.

[0063] The memory 320 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the computing device. Furthermore, the memory 320 may include high-speed random access memory and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, the memory 320 may optionally include memory remotely located relative to the processor 310, and these remote memories may be connected to the computing device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0064] The one or more modules are stored in the memory 320, and when executed by the one or more processors 310, the test power adjustment method described in the above embodiment is performed.

[0065] The above-described product can perform the methods provided in the embodiments of this application, and has the corresponding functional modules and beneficial effects for performing the methods. Technical details not described in detail in this embodiment can be found in the test power supply adjustment method described in the embodiments of this application.

[0066] This application provides a non-volatile computer-readable storage medium storing computer-executable instructions. These instructions are executed by one or more processors to enable the at least one processor to perform the test power adjustment method described in the above embodiments. For example, the non-volatile computer-readable storage medium may be a read-only memory (ROM), a random access memory (RAM), a compact disc read-only memory (CDROM), magnetic tape, floppy disk, or optical data storage device, etc.

[0067] This application provides a computer program product, which includes a computer program stored on a non-volatile computer-readable storage medium. The computer program includes program instructions, which, when executed by an automated test device, enable the automated test device to perform the test power adjustment method in any of the above method embodiments.

[0068] It should be noted that the device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0069] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0070] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them; under the concept of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of this application as described above, which are not provided in detail for the sake of brevity; although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A method for adjusting a test power supply, characterized in that, The method includes: Obtain the text information of the test program to be executed; The test program text information is compiled to obtain test program compilation result file information; wherein, the test program compilation result file information includes test instruction sequence information and burst data block information; Based on the burst data block information and the preset constraint strategy, a first-level voltage value is preset; When chip testing is performed according to the test instruction sequence information, a second-level voltage value fine-tuning process is executed based on the burst data block information and the first-level voltage value.

2. The test power supply adjustment method according to claim 1, characterized in that, The process of compiling the test program text information to obtain the test program compilation result file information includes: The test program text information is identified to obtain test instructions and voltage adjustment instructions; Generate the corresponding test instruction sequence information according to the test instructions; Generate the corresponding burst data block information according to the voltage adjustment command; Based on the test instruction sequence information and the burst data block information, the test program compilation result file information is obtained.

3. The test power supply adjustment method according to claim 1, characterized in that, The burst data block information includes the target reference voltage value for the secondary voltage. The step of presetting a first-level voltage value based on the burst data block information and the preset constraint strategy includes: The first-level voltage value is calculated based on the target reference voltage value and the preset threshold. Execute the preset procedure based on the first-level voltage value; The first-level voltage value satisfies a first preset constraint condition, which includes the first-level voltage value being greater than the target reference voltage value, the first-level voltage value not being greater than the target voltage upper limit, and the first-level voltage value not being greater than the preset maximum allowable output voltage.

4. The test power supply adjustment method according to claim 3, characterized in that, The step of executing a preset process based on the first-level voltage value includes: Based on the first-level voltage value, the register code corresponding to the first-level voltage value is obtained; The register code is written to a preset first-level voltage register.

5. The test power supply adjustment method according to claim 4, characterized in that, The test command sequence information includes secondary voltage fine-tuning commands. When performing chip testing according to the test instruction sequence information, the process of performing a second-level voltage value fine-tuning based on the burst data block information and the first-level voltage value includes: During the chip test, the burst data block information corresponding to the secondary voltage fine-tuning instruction is read according to the secondary voltage fine-tuning instruction; The secondary voltage value is adjusted based on the primary voltage value and the target reference voltage value in the burst data block information.

6. The test power supply adjustment method according to claim 1, characterized in that, The step of adjusting the secondary voltage value based on the primary voltage value and the target reference voltage value in the burst data block information includes: During the chip testing, the secondary voltage value is adjusted based on the second preset constraint, the primary voltage value, and the target reference voltage value. The second preset constraint condition includes that the secondary voltage value is not greater than the primary voltage value and that the deviation between the secondary voltage value and the target reference voltage value is within a preset tolerance range.

7. A test power supply adjustment device, characterized in that, The device includes: A test program text information acquisition module, which is used to acquire the text information of the test program to be executed; The test program compilation result file information acquisition module is used to compile the test program text information to obtain test program compilation result file information; wherein, the test program compilation result file information includes test instruction sequence information and burst data block information; A primary voltage value acquisition module is used to preset a primary voltage value based on the burst data block information and a preset constraint strategy. The secondary voltage value fine-tuning process execution module is used to execute the secondary voltage value fine-tuning process based on the burst data block information and the primary voltage value when performing chip testing according to the test instruction sequence information.

8. An automated testing device, characterized in that, include: At least one processor; as well as, A memory communicatively connected to the at least one processor; wherein, The memory stores instructions executable by the at least one processor, which, when executed by the at least one processor, enables the at least one processor to perform the method according to any one of claims 1-6.

9. A non-volatile computer-readable storage medium, characterized in that, The non-volatile computer-readable storage medium stores computer-executable instructions that, when executed by an automated testing device, cause the automated testing device to perform the method described in any one of claims 1-6.

10. A computer program product, characterized in that, The computer program product includes a computer program stored on a non-volatile computer-readable storage medium, the computer program including program instructions that, when executed by an automated testing device, cause the automated testing device to perform the method according to any one of claims 1-6.

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