A method and system for high-speed signal eye diagram testing based on automated testing equipment
By combining automated testing equipment with vector splitting and matching, virtual clock synchronization, and differential peak-valley segmentation to process high-speed signal eye diagrams, the problems of long testing time and human interference in traditional testing equipment are solved. This achieves automated high-speed signal eye diagram testing, improves testing efficiency, and ensures the accuracy and reliability of test results.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- XIAN MICROELECTRONICS TECH INST
- Filing Date
- 2025-08-19
- Publication Date
- 2026-06-30
AI Technical Summary
Traditional high-speed signal eye diagram testing relies on high-performance oscilloscopes and requires manual setup of the test platform, resulting in low testing efficiency and susceptibility to human error. Furthermore, traditional methods have long testing times.
High-speed signal eye diagram testing was performed using automated testing equipment. Through vector splitting and matching, virtual clock synchronization, and waveform capture, the two-dimensional array was processed using the differential peak-valley segmentation method. Characteristic parameters such as eye height, rise/fall time, and jitter were measured, and a virtual clock was constructed as the reference trigger signal for synchronization.
It achieves automated control and measurement, improves testing efficiency, reduces testing time, enhances testing accuracy and data processing convenience, avoids the influence of human factors, and ensures the clarity and reliability of test results.
Smart Images
Figure CN120993013B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of high-speed data testing technology, and relates to a high-speed signal eye diagram testing method and system based on automatic testing equipment. Background Technology
[0002] A high-speed signal eye diagram test based on automated testing equipment includes vector splitting and matching, virtual clock synchronization, and waveform capture calculation. Vector splitting and matching divides the high-speed signal configuration vector into configuration and action segments for matching. During vector execution, the first half of the configuration vector is run first, followed by the second half of the action vector. Subsequent eye diagram test calculations are based on the second half of the action vector. Virtual clock synchronization, in multi-clock domain vector configuration, constructs a separate virtual clock as a global reference trigger signal outside the vector signal. The high-speed signal under test is synchronized with the virtual clock, thereby improving waveform oscillation in the high-speed signal output and facilitating sampling and computation. Waveform capture calculation performs waveform capture processing on the high-speed signal's bitstream and uses a "differential peak-valley segmentation method" for waveform splitting calculation.
[0003] Traditional eye diagram testing uses an oscilloscope to accumulate and superimpose serial signals to obtain the result. However, testing eye diagrams with an oscilloscope requires additional instrument costs, and the test platform needs to be set up manually, which is inefficient for large-scale testing. Summary of the Invention
[0004] To address the shortcomings of existing technologies, the present invention aims to provide a high-speed signal eye diagram testing method and system based on automatic testing equipment.
[0005] To achieve the above objectives, the present invention adopts the following technical solution:
[0006] This invention provides a high-speed signal eye diagram testing method based on an automated testing device, comprising the following steps: dividing the high-speed signal configuration vector into a configuration segment and an action segment, wherein the configuration segment is used to quickly configure the test environment, and the action segment is used to control the test action; in the action segment, constructing a virtual clock as a reference trigger signal, and synchronizing the virtual clock with the high-speed signal under test to the same sequence group; capturing the waveform of the synchronized high-speed signal under test to generate a two-dimensional array consisting of sampling time and level value; performing differential peak-valley segmentation processing on the two-dimensional array, and measuring eye height, rise / fall time, and jitter based on the processing result.
[0007] Furthermore, the process of capturing the waveform of the synchronized high-speed signal under test and generating a two-dimensional array consisting of sampling time and level value includes: taking Bit Start as the starting point and resolution as the step UI, sampling successively, changing the VTH setting of the signal pin at each sampling point, scanning the critical point of PASS / FAIL as the level value of the sampling point, until BitStop ends, and mapping the time and level value of each sampling point to a two-dimensional array.
[0008] Furthermore, the differential peak-valley segmentation method includes: capturing the output waveforms of the SerDes interface P-end and N-end bitstreams; saving the captured waveforms at the P-end as an array pos_waveform and the captured waveforms at the N-end as an array neg_waveform; calculating diff_waveform based on the arrays pos_waveform and neg_waveform; identifying the minimum value min in diff_waveform and its corresponding horizontal coordinate minLocation; dividing the waveform into multiple segments based on minLocation; analyzing the waveform parameters of each segment, and measuring eye height, rise / fall time, and jitter.
[0009] Furthermore, the starting coordinates of the first waveform are... =minLocation%20, the starting coordinates of the second waveform are The starting coordinates of the nth waveform are .
[0010] Further, the parameters of each waveform segment are analyzed, and the eye height is measured by: determining whether each waveform is a rising edge; if it is a rising edge, recording the peak and trough of the waveform; if the peak is smaller than the peaks of other waveform segments, then the peak is the first temporary variable VtxDiffppHigh, and after the entire waveform segment is scanned, the first temporary variable VtxDiffppHigh is the minimum value of the peak of the entire waveform segment; if the trough is larger than the troughs of other waveform segments, then the trough is the second temporary variable VtxDiffppLow, and after the entire waveform segment is scanned, the second temporary variable VtxDiffppLow is the maximum value of the trough of the entire waveform segment; the eye height is obtained based on the difference between the first temporary variable VtxDiffppHigh and the second temporary variable VtxDiffppLow.
[0011] Furthermore, determining whether each waveform is a rising edge includes: if the voltage value at the beginning of the waveform is less than 0 and the voltage value at the end of the waveform is greater than 0, then the waveform is a rising edge.
[0012] Furthermore, the parameters of each waveform segment are analyzed, and the rise / fall time is measured, including: acquiring the output waveform, calculating the level values corresponding to the 20% and 80% maximum peak-to-peak voltage values based on the maximum peak-to-peak voltage value; acquiring the level transition points at 20% and 80% eye height; and calculating the difference between the two time points as the rise / fall time.
[0013] Furthermore, the analysis of each waveform parameter and the measurement of jitter include: setting the configuration device to output in pseudo-random binary sequence code mode; using time measurement unit test vectors to measure the time points when the rise and fall pass the threshold voltage; calculating the difference between each time point and the ideal expected time point; and subtracting the maximum and minimum values of the differences to obtain the jitter.
[0014] Furthermore, the capture of the output waveforms of the SerDes interface P-end and N-end includes a capture length of 40 bits, 20 sampling points per bit, and a voltage resolution of 5mV.
[0015] This invention also provides a high-speed signal eye diagram testing system based on an automated testing device, comprising: a partitioning module for dividing a high-speed signal configuration vector into a configuration segment and an action segment, wherein the configuration segment is used to quickly configure the test environment and the action segment is used to control the test action; a synchronization module for constructing a virtual clock as a global reference trigger signal in the action segment and synchronizing the virtual clock with the high-speed signal under test to the same sequence group; a capture module for capturing the waveform of the synchronized high-speed signal under test and generating a two-dimensional array consisting of sampling time and level value; and a measurement module for performing differential peak-valley segmentation processing on the two-dimensional array and measuring eye height, rise / fall time, and jitter based on the processing result.
[0016] Compared with the prior art, the present invention has the following beneficial technical effects:
[0017] This invention provides a high-speed signal eye diagram testing method based on automated testing equipment. Traditional eye diagram testing relies on high-performance oscilloscopes and requires manual setup of the test platform, resulting in low efficiency for large-scale testing. Furthermore, it necessitates manual measurement and recording. This application utilizes automated testing equipment to achieve automated control, measurement, and output of test data, facilitating data analysis and processing, improving testing efficiency, and avoiding interference from human factors.
[0018] This invention provides a high-speed signal eye diagram testing method based on an automatic testing device. Compared with the traditional Shmoo algorithm, the differential peak-valley segmentation method greatly reduces the testing time. The method processes a two-dimensional array to synthesize the waveform of the high-speed interface into a differential signal. The differential peak-valley segmentation method is used to segment the synthesized differential waveform to perform segmentation operations on the eye diagram characteristic parameters such as eye height, rise / fall time, and jitter, thereby improving accuracy.
[0019] This invention discloses a high-speed signal eye diagram testing method based on automated testing equipment. A virtual clock (Dummy clock) is constructed as the reference trigger signal. To synchronize with the high-speed signal output waveform, the period of the Dummy clock is set to an integer multiple of the complete cycle time of the high-speed signal output waveform. The high-speed signal port and the Dummy clock are set to the same Sequencing Group. During repeated vector operation, regardless of the operation status of other ports, ports within the same Sequencing Group can achieve timing synchronization at the start of operation. The globally stable reference phase of the Dummy clock enables the high-speed signal port to achieve a stable phase output, thus displaying a clear waveform in the Timing Diagram, facilitating waveform observation and capture sampling during subsequent testing. Attached Figure Description
[0020] Figure 1 This is a flowchart of a high-speed signal eye diagram testing method based on an automatic testing device according to the present invention;
[0021] Figure 2 This is a schematic diagram illustrating the eye diagram formation principle in an embodiment of the present invention;
[0022] Figure 3 This is a schematic diagram of the virtual clock synchronization technology in an embodiment of the present invention;
[0023] Figure 4 This is a schematic diagram of the waveform capture technology in an embodiment of the present invention;
[0024] Figure 5 This is a schematic diagram illustrating the principle of the differential peak-valley segmentation method in an embodiment of the present invention.
[0025] Figure 6 This is a diagram illustrating the actual effect of the virtual clock synchronization technology in an embodiment of the present invention.
[0026] Figure 7 This is a schematic diagram of the eye diagram feature parameters in an embodiment of the present invention;
[0027] Figure 8 This is a schematic diagram illustrating the eye height testing principle in an embodiment of the present invention.
[0028] Figure 9 This is a schematic diagram illustrating the rise / fall time test principle in an embodiment of the present invention.
[0029] Figure 10 This is a schematic diagram of the jitter principle test in an embodiment of the present invention. Detailed Implementation
[0030] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.
[0031] Example 1
[0032] This invention provides a high-speed signal eye diagram testing method based on automated testing equipment, such as... Figure 1 As shown, the process includes the following steps: dividing the high-speed signal configuration vector into a configuration segment and an action segment, wherein the configuration segment is used to quickly configure the test environment and the action segment is used to control the test action; in the action segment, a virtual clock is constructed as a reference trigger signal, and the virtual clock is synchronized with the high-speed signal under test to the same sequence group; the synchronized high-speed signal under test is subjected to waveform capture to generate a two-dimensional array consisting of sampling time and level value; the two-dimensional array is processed by differential peak-valley segmentation method, and eye height, rise / fall time and jitter are measured based on the processing result.
[0033] This invention is applicable to mass production testing of high-speed signal interfaces such as PCIe, RapidIO, and SerDes. The eye diagram is shown below. Figure 2 As shown, the high-speed signal is formed by collecting and superimposing high-speed signals at different locations according to clock intervals. The quality of the high-speed signal can be directly reflected by the degree of eye opening.
[0034] The high-speed signal configuration vector is split into two parts for matching: a configuration segment and an action segment. The first half of the configuration vector is run first, followed by the action vector. Eye diagram testing is based on the action vector. It should be noted that power loss and clock interruption are unavoidable during the configuration vector and action segment execution. This vector splitting effectively reduces test vector configuration time and improves testing efficiency.
[0035] To address the synchronization problem in high-speed signal configuration vectors constructed using a multi-clock domain model, a virtual clock synchronization technique is proposed. A separate virtual clock is constructed outside the vector signal, serving as a global clock reference trigger signal. The high-speed signal port to be measured is synchronized with the virtual clock as a sequence group, such as... Figure 3 As shown, a clear waveform can be observed, improving the oscillation phenomenon that occurs when the high-speed signal output waveform is not synchronized.
[0036] In this embodiment, a virtual clock (Dummy clk) is constructed as the reference trigger signal. To synchronize with the high-speed signal output waveform, the period of the Dummy clk needs to be set to an integer multiple of the complete cycle time of the high-speed signal output waveform. The high-speed signal port and the Dummy clk are set to the same Sequencing Group. This ensures that during repeated vector execution, regardless of the execution status of other ports, ports within the same Sequencing Group can achieve timing synchronization at the start of execution. This utilizes the globally stable reference phase of the Dummy clk to enable the high-speed signal port to achieve a stable phase output, resulting in a clear waveform displayed in the Timing Diagram, facilitating waveform observation and capture sampling during subsequent testing. Figure 6 As shown, virtual clock synchronization improves high-speed waveform output and reduces waveform oscillation.
[0037] Test programs are developed using test software on automated test equipment platforms. These programs configure devices to enter high-speed signal stream transmission and reception mode via test vectors. Waveform capture and processing methods are then used to capture waveforms, generate eye diagrams, and test eye diagram characteristic parameters. Figure 4 As shown. After the high-speed bitstream is stably output, parameters such as Bit Start, Bit Stop, and resolution are set to divide the sampling time period into several sampling segments. Sampling is performed sequentially, starting with Bit Start and using Resolution as the step size. At each sampling point, the VTH setting of the signal pin is changed, and the function is repeatedly run to scan for the critical point that causes the function to pass or fail; this is the level value at that point. The signal waveform level value is read at each sampling point until Bit Stop ends. The output waveform is reconstructed using the time and level value data of each sampling point. The sampling results are stored in a two-dimensional array, thus establishing a one-to-one correspondence between the sampling time and the waveform level value, converting the high-speed signal waveform into a two-dimensional array that can be used for computation.
[0038] A differential peak-valley segmentation method is applied to the two-dimensional array. Based on the processing results, eye height, rise / fall time, and jitter are measured. This differential peak-valley segmentation method significantly reduces testing time compared to the traditional Shmoo algorithm. By processing and calculating the captured two-dimensional array, the waveforms of the high-speed interface are synthesized into differential signals, such as... Figure 5 He Ru Figure 7 As shown, the differential peak-valley segmentation method is used to perform segmented calculations on the synthesized differential waveform, thereby enabling the testing of eye diagram characteristic parameters such as eye height, rise and fall time, and jitter.
[0039] Using automated testing equipment enables automated control and measurement, and the results are clearly reflected in the data, facilitating data analysis and processing, improving testing efficiency, and avoiding interference from human factors; while using an oscilloscope to measure eye diagrams requires manual observation, measurement, and recording.
[0040] Measuring eye height includes the following steps:
[0041] Digital waveform capture technology was used to simultaneously capture the output waveforms of the P-end and N-end of the SerDes serializer interface. The capture length was 40 bits, with 20 samples per bit and a voltage resolution of 5mV, for a total of 800 samples. High-precision voltage resolution and a reasonable number of samples ensured the accuracy and completeness of the waveform capture. The captured waveforms from the P-end were saved as an array `pos_waveform`, and those from the N-end as an array `neg_waveform`. The differential waveform was obtained by subtracting the P-end waveform from the N-end waveform and saved as an array `diff_waveform`. Combining the P-end and N-end waveforms into a differential waveform effectively improved the accuracy and efficiency of eye diagram parameter testing. Identifying the minimum value and its position in the differential waveform enabled precise waveform segmentation. The "peak-valley segmentation method" was used to find the minimum value in the `diff_waveform` array and its corresponding horizontal coordinate time `minLocation`, such as... Figure 8 As shown.
[0042] minLocation can only be the starting value of a certain rising edge. Therefore, the entire waveform can be divided into 40 equal rising and falling waveforms. The starting coordinate of the first waveform is... =minLocation%20, the starting coordinates of the second waveform are And so on, the starting coordinates of the nth waveform are By calculating the modulus between minLocation and the number of waveform sampling points, accurate waveform segmentation was achieved; the waveform was divided into multiple rising and falling waveform segments, which facilitates the subsequent measurement of segmentation parameters.
[0043] Analyze the parameters of each waveform segment: determine if each waveform is a rising edge; if so, record the peak and trough of the waveform. By identifying rising edge waveforms and recording peak and trough values, accurate measurement of eye height is achieved. If the peak is smaller than the peaks of other waveform segments, the peak is the first temporary variable VtxDiffppHigh. After scanning the entire waveform segment, the first temporary variable VtxDiffppHigh is the minimum peak value of the entire waveform segment. If the trough is larger than the troughs of other waveform segments, the trough is the second temporary variable VtxDiffppLow. After scanning the entire waveform segment, the second temporary variable VtxDiffppLow is the maximum trough value of the entire waveform segment. The eye height is obtained based on the difference between the first temporary variable VtxDiffppHigh and the second temporary variable VtxDiffppLow. By comparing the peak and trough values of each waveform segment, the minimum eye height is determined.
[0044] Determining whether each waveform is a rising edge involves: a voltage value less than 0 at the beginning of the waveform and a voltage value greater than 0 at the end; in this case, the waveform is considered a rising edge. Accurate identification of the rising edge is achieved by comparing the voltage values at the beginning and end of the waveform.
[0045] The rise / fall time test algorithm is as follows:
[0046] Rise time and fall time refer to the time required for the input terminal to receive a step voltage increase from 20% to 80% of its rated value and from 80% to 20% of its rated value, respectively. Figure 9 As shown, the waveform capture method is used to capture the output waveform of the vector operation. By matching the captured waveform with the time point, the rise / fall time can be obtained.
[0047] Measuring rise / fall time includes: acquiring the output waveform; calculating the voltage levels corresponding to 20% and 80% of the maximum peak-to-peak voltage based on the maximum peak-to-peak voltage value; acquiring the voltage level transition points at 20% and 80% eye height; and calculating the difference between the two points as the rise / fall time. The maximum peak-to-peak voltage value is a crucial parameter reflecting the signal amplitude variation range, and its accuracy directly affects the precision of subsequent voltage level calculations. The oscilloscope's automatic measurement function can be used to quickly read the maximum peak voltage and minimum valley voltage from the acquired output waveform.
[0048] The rise time is the time required for the signal to jump from 20% to 80% of its steady-state amplitude, and the fall time is the time required for it to drop from 80% to 20%.
[0049] Ideally, the edges of the serial data signal should perfectly match the reference signal, and each clock cycle should remain constant. However, in actual transmission, the clock cycle, data propagation delay, and signal transition time will always vary to varying degrees. This offset between the actual time and the ideal time is called jitter. Figure 10 As shown.
[0050] Analyze the parameters of each waveform segment and measure the jitter, including: setting the configuration device to output in pseudo-random binary sequence code mode; using time measurement units to measure the time points when the rise and fall of the test vector pass the threshold voltage; calculating the difference between each time point and the ideal expected time point; and subtracting the maximum and minimum values of the differences to obtain the jitter.
[0051] Specifically, the device is configured to enter the output PRBS pseudo-random binary sequence code mode, using the time measurement unit TMU test vector to measure the rise and fall of the threshold voltage VTH at the time points, for a total of 2000 sampling time points; the difference between each sampling time point and the ideal expected time point is calculated; the maximum and minimum values of the difference are calculated, and the maximum and minimum values are subtracted to obtain the jitter value pp_jitter. The jitter value is obtained by dividing pp_jitter by UI, and 1-pp_jitter / UI is the eye width, where UI is the interval time.
[0052] In summary, this invention provides a high-speed signal eye diagram testing method based on automated testing equipment. It employs vector splitting and matching technology and virtual clock synchronization technology, enabling devices to output clear and complete high-speed signal streams with only a short configuration time. Waveform capture calculation technology and the "differential peak-valley segmentation method" are used to capture high-speed signal waveforms and test eye diagram characteristic parameters. By testing the eye diagram characteristic parameters, the quality of high-speed signals can be reflected more accurately and clearly while ensuring sufficient testing time.
[0053] Example 2
[0054] A high-speed signal eye diagram testing system based on automatic testing equipment includes: a partitioning module, a synchronization module, a capture module, and a measurement module.
[0055] The system comprises the following modules: a partitioning module (for dividing the high-speed signal configuration vector into a configuration segment and an action segment, whereby the configuration segment is used to quickly configure the test environment and the action segment is used to control the test actions); a synchronization module (for constructing a virtual clock as a global reference trigger signal in the action segment and synchronizing the virtual clock with the high-speed signal under test to the same sequence group); a capture module (for capturing the waveform of the synchronized high-speed signal under test and generating a two-dimensional array consisting of sampling time and level value); and a measurement module (for performing differential peak-valley segmentation processing on the two-dimensional array and measuring eye height, rise / fall time, and jitter based on the processing results).
[0056] The high-speed signal eye diagram testing system based on automatic testing equipment provided by this invention can implement the same method steps as the above method, so it will not be described again.
[0057] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
Claims
1. A high-speed signal eye diagram testing method based on automatic testing equipment, characterized in that, Includes the following steps: The high-speed signal configuration vector is divided into a configuration segment and an action segment. The configuration segment is used to quickly configure the test environment, and the action segment is used to control the test actions. In the action segment, a virtual clock is constructed as a reference trigger signal, and the virtual clock is synchronized with the high-speed signal under test to the same sequence group; The waveform of the high-speed signal under test after synchronization is captured, and a two-dimensional array consisting of sampling time and level value is generated. The process includes: sampling successively with Bit Start as the starting point and resolution as the step UI, changing the VTH setting of the signal pin at each sampling point, scanning the PASS / FAIL threshold as the level value of the sampling point, until Bit Stop, and mapping the sampling time and level value of each sampling point into a two-dimensional array. The two-dimensional array is processed using a differential peak-valley segmentation method. Based on the processing results, eye height, rise / fall time, and jitter are measured. The differential peak-valley segmentation method includes: capturing the output waveforms of the SerDes interface P-end and N-end bitstreams; saving the captured waveforms at the P-end as an array pos_waveform and the captured waveforms at the N-end as an array neg_waveform; calculating diff_waveform based on the arrays pos_waveform and neg_waveform; identifying the minimum value min and its corresponding horizontal coordinate minLocation in diff_waveform; dividing the waveform into multiple segments based on minLocation; analyzing the waveform parameters of each segment, and measuring eye height, rise / fall time, and jitter. Analyzing the parameters of each waveform segment and measuring eye height includes: determining whether each waveform is a rising edge; if it is, recording the peak and trough of the waveform; if the peak is smaller than the peaks of other waveform segments, the peak is the first temporary variable VtxDiffppHigh, and after the entire waveform segment is scanned, the first temporary variable VtxDiffppHigh is the minimum value of the peak of the entire waveform segment; if the trough is larger than the troughs of other waveform segments, the trough is the second temporary variable VtxDiffppLow, and after the entire waveform segment is scanned, the second temporary variable VtxDiffppLow is the maximum value of the trough of the entire waveform segment; the eye height is obtained based on the difference between the first temporary variable VtxDiffppHigh and the second temporary variable VtxDiffppLow. Analyze the parameters of each waveform segment and measure the rise / fall time, including: acquiring the output waveform; calculating the level values corresponding to the 20% and 80% maximum peak-to-peak voltage values based on the maximum peak-to-peak voltage value; acquiring the level transition points at 20% and 80% eye height; and calculating the difference between the two time points as the rise / fall time. Analyze the parameters of each waveform segment and measure the jitter, including: setting the configuration device to output in pseudo-random binary sequence code mode; using time measurement units to measure the time points when the rise and fall of the test vector pass the threshold voltage; calculating the difference between each time point and the ideal expected time point; and subtracting the maximum and minimum values of the differences to obtain the jitter.
2. The high-speed signal eye diagram testing method based on automatic testing equipment according to claim 1, characterized in that, The waveform is divided into multiple segments based on minLocation, including: The starting coordinates of the first waveform are =minLocation%20, the starting coordinates of the second waveform are The starting coordinates of the nth waveform are .
3. The high-speed signal eye diagram testing method based on automatic testing equipment according to claim 1, characterized in that, The determination of whether each waveform is a rising edge includes: The waveform has a rising edge when the voltage at the beginning of the waveform is less than 0 and the voltage at the end of the waveform is greater than 0.
4. The high-speed signal eye diagram testing method based on automatic testing equipment according to claim 1, characterized in that: The capture of the waveform output from the P and N ends of the SerDes interface includes a capture length of 40 bits, 20 sampling points per bit, and a voltage resolution of 5mV.
5. A high-speed signal eye diagram testing system based on automatic testing equipment, characterized in that, include: The partitioning module is used to divide the high-speed signal configuration vector into a configuration segment and an action segment. The configuration segment is used to quickly configure the test environment, and the action segment is used to control the test actions. Synchronization module: Used in the action segment to construct a virtual clock as a global reference trigger signal and synchronize the virtual clock with the high-speed signal under test to the same sequence group; The capture module is used to capture the waveform of the high-speed signal under test after synchronization and generate a two-dimensional array consisting of sampling time and level value. It includes: taking Bit Start as the starting point and resolution as the step UI, sampling successively, changing the VTH setting of the signal pin at each sampling point, scanning the PASS / FAIL threshold as the level value of the sampling point, until BitStop ends, and mapping the time and level value of each sampling point to a two-dimensional array. Measurement module: Used to perform differential peak-valley segmentation processing on the two-dimensional array, and measure eye height, rise / fall time, and jitter based on the processing results; the differential peak-valley segmentation method includes: capturing the output waveforms of the SerDes interface P-end and N-end bitstreams; saving the captured waveforms at the P-end as an array pos_waveform, and the captured waveforms at the N-end as an array neg_waveform; calculating diff_waveform based on the arrays pos_waveform and neg_waveform; identifying the minimum value min in diff_waveform and its corresponding horizontal coordinate minLocation; dividing the waveform into multiple segments based on minLocation; analyzing the waveform parameters of each segment, and measuring eye height, rise / fall time, and jitter; Analyzing the parameters of each waveform segment and measuring eye height includes: determining whether each waveform is a rising edge; if it is, recording the peak and trough of the waveform; if the peak is smaller than the peaks of other waveform segments, the peak is the first temporary variable VtxDiffppHigh, and after the entire waveform segment is scanned, the first temporary variable VtxDiffppHigh is the minimum value of the peak of the entire waveform segment; if the trough is larger than the troughs of other waveform segments, the trough is the second temporary variable VtxDiffppLow, and after the entire waveform segment is scanned, the second temporary variable VtxDiffppLow is the maximum value of the trough of the entire waveform segment; the eye height is obtained based on the difference between the first temporary variable VtxDiffppHigh and the second temporary variable VtxDiffppLow. Analyze the parameters of each waveform segment and measure the rise / fall time, including: acquiring the output waveform; calculating the level values corresponding to the 20% and 80% maximum peak-to-peak voltage values based on the maximum peak-to-peak voltage value; acquiring the level transition points at 20% and 80% eye height; and calculating the difference between the two time points as the rise / fall time. Analyze the parameters of each waveform segment and measure the jitter, including: setting the configuration device to output in pseudo-random binary sequence code mode; using time measurement units to measure the time points when the rise and fall of the test vector pass the threshold voltage; calculating the difference between each time point and the ideal expected time point; and subtracting the maximum and minimum values of the differences to obtain the jitter.