A silicon optical CPO module based on a CPO-only brain architecture and a manufacturing method thereof

Abstract

The application relates to a silicon optical CPO module based on a CPO brain architecture, the CPO brain architecture is arranged in a through groove on the base of a PCB board and is electrically connected with the PCB board through elastic power-on needles, a cold plate is detachably connected with the base and presses the CPO brain architecture, and a plurality of multi-channel optical fiber arrays coupled with the CPO brain architecture are arranged on the upper surface of the base in each direction of the CPO brain architecture. A manufacturing method of a silicon optical CPO module based on a CPO brain architecture is provided, the base provided with the multi-channel optical fiber arrays is arranged on a PCB board; the CPO brain architecture is arranged in the through groove on the base, so that the CPO brain architecture is coupled with the multi-channel optical fiber arrays, the CPO brain architecture is electrically connected with the PCB board through the elastic power-on needles; and the cold plate is detachably connected with the base to press the CPO brain architecture. The beneficial effect is that the maintenance time of the CPO brain architecture which is easy to be damaged is less than 1 min, and a professional fiber arrangement engineer is not needed.

Description

Technical Field

[0001] This invention relates to the field of optical communication technology, specifically to a silicon photonics CPO module based on a swappable CPO brain architecture and its fabrication method. Background Technology

[0002] Traditional CPO modules include a PCB board, an ASIC chip, and multiple silicon photonic engines. The ASIC chip is centrally located on the upper surface of the PCB board. At least one silicon photonic engine is positioned in each direction of the ASIC chip on the upper surface of the PCB board, typically four silicon photonic engines in each of the four directions of the ASIC chip, resulting in 16 silicon photonic engines. Each silicon photonic engine is interconnected to the ASIC chip via the PCB board. In this type of CPO module, the silicon photonic engines are powered by an external light source module using an external ELSFP module. This ELSFP module employs a polarization-maintaining fiber array, which is very expensive, and the connection to the silicon photonic engines also requires a polarization-maintaining fiber array, leading to very high costs. Each silicon photonic engine contains 16 transmit fibers, 16 receive fibers, and 4 light source fibers; that is, one silicon photonic engine contains 36 fibers. The entire CPO module contains a total of... The current CPO system requires 16 x 36 = 576 optical fibers and 8 ELSFP pluggable light source modules, resulting in complex fiber routing. Furthermore, the current silicon photonics engine uses a pluggable electrical socket (power disconnected before plugging / unplugging). This socket (requiring high-speed signals) is large and has high high-frequency insertion loss, limiting the current system to 100G per wavelength. Therefore, 16 x 4 x 4 x 100G = 25600G, meaning the CPO system is 25.6T. We urgently need 51.2T. Increasing the number of channels would require 1152 optical fibers, which would be too large and difficult to route, failing to meet the requirements. Therefore, we can only use bonding and soldering of the silicon photonics engine to the ASIC chip for interconnection. However, this method is unmaintainable; if a silicon photonics engine or ASIC chip fails, the entire CPO needs to be scrapped and returned for repair, completely interrupting service. The routing and connection of the 576 optical fibers are extremely time-consuming and require specialized engineers. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a silicon photonics CPO module based on a CPO brain architecture and its fabrication method, so as to overcome the shortcomings of the prior art.

[0004] The technical solution of the present invention to solve the above-mentioned technical problems is as follows: A silicon photonics CPO module based on a replaceable CPO brain architecture includes: a PCB board and a CPO brain architecture. A base is provided on the upper surface of the PCB board, and a through slot is formed on the base through its upper and lower surfaces. The PCB board has elastic power-applying pins in the area enclosed by the through slot. The CPO brain architecture is located in the through slot and is electrically connected to the PCB board via the elastic power-applying pins. A cold plate is arranged above the CPO brain architecture. The cold plate is detachably connected to the base and presses down on the CPO brain architecture. Multiple multi-channel fiber arrays coupled to the CPO brain architecture are arranged on the upper surface of the base in each direction.

[0005] The beneficial effects of this invention are as follows: The CPO brain architecture (typically ASIC chips, silicon photonics chips, TIA chips, and driver chips are easily damaged) is a vulnerable component. When it is damaged, the cold plate is removed from the base, the CPO brain architecture located in the through slot is taken out, a new CPO brain architecture is replaced, and the cold plate is replaced again. After the cold plate is connected to the base, the cold plate presses down on the CPO brain architecture, and the elastic force of the elastic power-on pin keeps the CPO brain architecture electrically connected to the PCB board, thus completing the maintenance or repair. The entire solution takes less than 1 minute to maintain and does not require a professional fiber optic engineer. Other passive components, because they do not emit light, heat, or receive power, are basically not damaged during use.

[0006] Based on the above technical solution, the present invention can be further improved as follows.

[0007] Furthermore, a phase change soft thermal pad is placed between the CPO brain structure and the cold plate.

[0008] The further beneficial effects of adopting the above are as follows: the heat generated during the operation of the CPO brain architecture can be conducted to the cold plate through the phase change soft thermal conductive pad, and then the cold plate exchanges heat with the outside world to dissipate heat from the CPO brain architecture. The introduction of the phase change soft thermal conductive pad improves the heat dissipation efficiency.

[0009] Furthermore, the multi-channel fiber optic array is located below the area covered by the cold plate.

[0010] The further beneficial effect of adopting the above is that the cold plate can cover the multi-channel fiber array to protect it.

[0011] Furthermore, the CPO brain architecture includes: a circuit board, an ASIC chip eutecticly mounted on the upper surface of the circuit board in the middle region, at least one silicon photonic chip mounted on the upper surface of the circuit board in each direction of the ASIC chip, the silicon photonic chip being interconnected with the ASIC chip via a high-speed RF line within the circuit board, a TIA chip and a Driver chip electrically connected to the silicon photonic chip eutecticly mounted on the upper surface of the silicon photonic chip, a first lens array coupled to the waveguide side of the silicon photonic chip, and a second lens array coupled to the optical port side of the multi-channel fiber array, the first lens array and the second lens array being coupled together.

[0012] The further beneficial effects of adopting the above are as follows: Since the ASIC chip is mounted on the circuit board and the silicon photonics chip is mounted on the circuit board, and the silicon photonics chip is interconnected with the ASIC chip through the high-speed RF line in the circuit board, the interconnection distance between the ASIC chip and the silicon photonics chip is less than 5mm, the insertion loss is small, there is no electrical socket, and it can be used for single-wavelength 400G in the future.

[0013] Furthermore, the circuit board is made of glass, and each corner of the circuit board is provided with rounded chamfers. The ASIC chip is attached to the upper surface of the circuit board with gold-tin solder eutectic bonding, the silicon photonics chip is attached to the upper surface of the circuit board with tin-silver-copper solder, and the TIA chip and Driver chip are attached to the upper surface of the silicon photonics chip with gold-tin solder eutectic bonding, respectively.

[0014] The further beneficial effects of adopting the above are: rounded chamfers are provided at each corner of the circuit board, which increases the high-temperature stability of the circuit board and prevents cuts to the hands.

[0015] Furthermore, multiple third positioning holes are opened on the base around the through groove and in the area covered by the cold plate, penetrating its upper and lower surfaces. On the lower surface of the cold plate, there are positioning posts that enter each of the corresponding third positioning holes. The base is made of Invar alloy, and the cold plate is made of magnetic material. The cold plate and the base attract each other to achieve a detachable connection.

[0016] The further beneficial effects of the above are: the cold plate and the base attract each other to achieve a detachable connection, the magnetic cold plate and the Invar base generate attraction to press the elastic power-on needle, so that the elastic power-on needle is firmly in contact with the circuit board, so that the PCB board can supply power to the circuit board and provide control signals.

[0017] Furthermore, the lower half of the inner wall of the third positioning hole has internal threads. The PCB board has mounting holes that penetrate the upper and lower surfaces of each corresponding third positioning hole. Screws are arranged at the bottom of the PCB board. The shank of the screw enters the third positioning hole through the mounting hole and is threadedly connected to the third positioning hole to fix the base to the PCB board.

[0018] Furthermore, the inner wall of the channel has at least two support platforms below the CPO brain architecture for supporting the CPO brain architecture. The upper end of the elastic electrocautery needle is higher than the upper surface of the support platform. The support platforms inside the channel are provided with first positioning pins that penetrate their upper and lower surfaces. The CPO brain architecture has a first positioning hole at each corresponding first positioning pin. The PCB board has a second positioning hole at each corresponding first positioning pin. The upper and lower ends of each first positioning pin enter the first positioning hole and the second positioning hole, respectively.

[0019] The further beneficial effect of adopting the above is that optical performance can be guaranteed when replacing the CPO brain architecture.

[0020] Furthermore, the multi-channel fiber array is glued to the upper surface of the base. On the upper surface of the base, adhesive-resistant grooves are opened between two adjacent multi-channel fiber arrays in each direction of the CPO brain architecture; or, a second positioning pin is provided on the upper surface of the base at the corresponding multi-channel fiber array, and a magnet is provided on the lower surface of the multi-channel fiber array. A fourth positioning hole is opened on the lower surface of the magnet. The magnet attracts the base, and the second positioning pin enters the fourth positioning hole on the magnet.

[0021] The further beneficial effects of adopting the above are as follows: if there is too much adhesive used to bond the multi-channel fiber array, it can flow into the adhesive blocking groove, thereby preventing the adhesive from flowing to the adjacent multi-channel fiber array; in order to solve the maintenance problem after the multi-channel fiber array is damaged in a very low probability case, the magnet on the lower surface of the multi-channel fiber array is attracted to the base, and the second positioning pin on the upper surface of the base enters the fourth positioning hole on the magnet, which can facilitate on-site maintenance.

[0022] Based on the above technical solution, the present invention also provides a method for fabricating a silicon photonics CPO module based on a CPO brain-only architecture, for fabricating the aforementioned silicon photonics CPO module based on a CPO brain-only architecture, comprising the following steps: S1. Fix all multi-channel fiber optic arrays to the corresponding positions on the upper surface of the base; S2. Mount the base for the multi-channel fiber optic array onto the PCB board; S3. Insert the CPO brain architecture into the through slot on the base, couple the CPO brain architecture with the multi-channel fiber array, and electrically connect the CPO brain architecture to the PCB board via a flexible power pin. S4. Allow the cold plate to be detachably connected to the base, and press down the CPO brain architecture through the cold plate. Attached Figure Description

[0023] Figure 1 This is a structural diagram of the silicon photonics CPO module based on the CPO brain-only architecture in this invention; Figure 2 for Figure 1 A magnified view of a portion of the image; Figure 3 This is a structural diagram of the CPO brain architecture being installed in the through slot on the base in this invention; Figure 4 This is a structural diagram of the CPO brain architecture in this invention; Figure 5 This is a structural diagram of the base in this invention; Figure 6 This is a diagram showing the detachable connection between the multi-channel fiber array and the base in this invention; Figure 7 This is a structural diagram of the CPO unit in this invention; Figure 8 This is a flowchart illustrating the fabrication process of the silicon photonics CPO module based on the CPO brain architecture that only requires a CPO replacement in this invention. Figure 9 This is a flowchart illustrating the creation of the CPO brain architecture in this invention. Figure 10 This is a flowchart illustrating the maintenance process of the silicon photonics CPO module based on the CPO brain-only replacement architecture in this invention.

[0024] The attached diagram lists the components represented by each number as follows: 1. PCB board, 110. Flexible power pin, 120. Assembly hole, 130. Second positioning hole, 2. CPO brain architecture, 210. Circuit board, 211. Rounded chamfer, 212. First positioning hole, 220. ASIC chip, 230. Silicon photonics chip, 240. TIA chip, 250. Driver chip, 260. First lens array, 3. Base, 310. Through slot, 320. Third positioning hole, 330. Support, 340. First positioning pin, 350. Glue-resistant groove, 360. Second positioning pin, 4. Cold plate, 410. Positioning post, 5. Multi-channel fiber optic array, 510. Second lens array, 6. Phase change flexible thermal pad, 7. Screw, 8. Magnet, 810. Fourth positioning hole. Detailed Implementation

[0025] The principles and features of the present invention are described below with reference to the accompanying drawings. The examples given are only for explaining the present invention and are not intended to limit the scope of the present invention.

[0026] Example 1 like Figures 1-5As shown, a silicon photonics CPO module based on a replaceable CPO brain architecture includes: a PCB board 1, a CPO brain architecture 2, a base 3, a cold plate 4, and a multi-channel fiber array 5. The base 3 is located on the upper surface of the PCB board 1, and a through slot 310 is formed on the base 3, penetrating both the upper and lower surfaces of the base 3. The PCB board 1 has elastic power-applying pins 110 in the area enclosed by the through slot 310. The CPO brain architecture 2 is located within the through slot 310 and is electrically connected to the PCB board 1 via the elastic power-applying pins 110. The PCB board 1 can supply power and provide control signals to the circuit board 210 via the elastic power-applying pins 110. The length and width dimensions of the CPO brain architecture 2 match the length and width dimensions of the through slot 310. A cold plate 4 is positioned above the CPO brain architecture 2, and the cold plate 4 is detachably connected to the base 3. After the cold plate 4 is connected to the base 3, it presses down on the CPO brain. Architecture 2 utilizes the elastic force of the elastic electrode 110 to maintain an electrical connection between the CPO brain architecture 2 and the PCB board 1. The heat generated during the operation of the CPO brain architecture 2 can be exchanged with the outside environment through the cold plate 4, thereby dissipating heat from the CPO brain architecture 2. Using the cold plate 4 for heat dissipation allows the entire CPO unit to be fanless, effectively preventing dust from contaminating the end faces of the CPO brain architecture 2 and the multi-channel fiber array 5. In addition, the cold plate 4 can also protect the CPO brain architecture 2. On the upper surface of the base 3, multiple multi-channel fiber arrays 5 coupled to the CPO brain architecture 2 are arranged in each direction. The number of multi-channel fiber arrays 5 in each direction can be one, two, three, four, etc., preferably four. In this way, the number and layout of the multi-channel fiber arrays 5 remain consistent with the existing technology.

[0027] As a vulnerable component, the CPO brain architecture 2 (usually the ASIC chip 220, silicon photonics chip 230, TIA chip 240, and driver chip 250 are easily damaged) is damaged. When it is damaged, the cold plate 4 is removed from the base 3, and then the CPO brain architecture 2 located in the through slot 310 is taken out. A new CPO brain architecture 2 is then replaced, and the cold plate 4 is replaced. After the cold plate 4 is connected to the base 3, the cold plate 4 presses down on the CPO brain architecture 2. The elastic force of the elastic power-on pin 110 keeps the CPO brain architecture 2 electrically connected to the PCB board 1, thus completing the maintenance or repair. The entire maintenance solution takes less than 1 minute and does not require a professional fiber optic engineer. Other passive components, since they do not emit light, heat, or receive electricity, are basically not damaged during use.

[0028] Example 2 like Figure 1 , Figure 2 As shown, this embodiment is a further improvement on embodiment 1, as detailed below: A phase change flexible thermal pad 6 is placed between the CPO brain architecture 2 and the cold plate 4. The heat generated by the CPO brain architecture 2 during operation can be conducted to the cold plate 4 through the phase change flexible thermal pad 6, and then the cold plate 4 exchanges heat with the outside world to dissipate heat from the CPO brain architecture 2.

[0029] Example 3 like Figure 1 , Figure 2 As shown, this embodiment is a further improvement on embodiment 1 or 2, as detailed below: The multi-channel fiber optic array 5 is located below the area covered by the cold plate 4. The cold plate 4 can cover the multi-channel fiber optic array 5 to protect it.

[0030] Example 4 like Figures 1-4 As shown, this embodiment is a further improvement on embodiment 3, as detailed below: The CPO brain architecture 2 includes: a circuit board 210, an ASIC chip 220, a silicon photonics chip 230, a TIA chip 240, a driver chip 250, and a first lens array 260. The circuit board 210 is located in a through slot 310 and electrically connected to the PCB board 1 via an elastic power pin 110. The thickness tolerance of the circuit board 210 is ±10μm. An ASIC chip 220 is eutectic-mounted on the upper surface of the circuit board 210 in the middle region. At least one silicon photonics chip 230 is eutectic-mounted on the upper surface of the circuit board 210 in each direction of the ASIC chip 220. The number of silicon photonics chips 230 in each direction can be one, two, three, four, etc., preferably four in this embodiment. The silicon photonics chips 230 are interconnected with the ASIC chip 220 via high-speed RF lines within the circuit board 210. A TIA chip 240 electrically connected to the silicon photonics chip 230 is eutectic-mounted on the upper surface of the silicon photonics chip 230. A Driver chip 250 electrically connected to the silicon photonics chip 250 is eutectic-mounted on the upper surface of the silicon photonics chip 230. The circuit consists of silicon photonics chip 230 + TIA chip 240 + ... Driver chip 250 serves as a silicon photonics engine. Silicon photonics chip 230 has a first lens array 260 coupled to it on the waveguide side. The waveguide side of silicon photonics chip 230 has an input waveguide and an output waveguide. Multi-channel fiber array 5 has a second lens array 510 coupled to it on the optical port side. The first lens array 260 and the second lens array 510 are coupled together. Multi-channel fiber array 5 can be coupled to silicon photonics chip 230 after passing through the second lens array 510 and the first lens array 260. The fiber used to connect the ELSFP optical module in multi-channel fiber array 5 is a polarization-maintaining fiber. The polarization-maintaining fiber in multi-channel fiber array 5 is coupled to the input waveguide of silicon photonics chip 230 after passing through the second lens array 510 and the first lens array 260. The first lens array 260 and the second lens array 510 are located below the area covered by cold plate 4, which can effectively prevent dust from contaminating the end faces of the first lens array 260 and the second lens array 510. The second lens array 510 and the first lens array 260 are preferably made of quartz glass or other glass with a refractive index of 1.4 to 1.5. The second lens array 510 and the first lens array 260 are used to collimate the light. The tolerance of the second lens array 510 and the first lens array 260 is ±80μm, and the insertion loss within 80μm of misalignment is less than 0.3dB.

[0031] Since the ASIC chip 220 and the silicon photonics chip 230 are both surface-mounted on the circuit board 210, and the silicon photonics chip 230 is interconnected with the ASIC chip 220 via a high-speed RF line within the circuit board 210, the interconnection distance between the ASIC chip 220 and the silicon photonics chip 230 is less than 5mm. There is no electrical socket, which is suitable for future single-wavelength 400G applications. However, the electrical socket is too large to meet the requirement of an interconnection distance of less than 10mm between the ASIC chip 220 and the silicon photonics chip 230 (currently, the typical interconnection distance of a mainstream single-wavelength 100G detachable electrical socket is 15mm, resulting in high insertion loss). The TIA chip 240 and the Driver chip 250 are interconnected with the silicon photonics chip 230 via surface-mount.

[0032] The circuit board 210 is preferably made of glass, with a CTE (coefficient of thermal expansion) of approximately 3.3 ± 0.1 ppm / ℃. The silicon photonic chip 230 is made of silicon, with a CTE of 2.6 ppm / ℃ to 3 ppm / ℃. This means the CTE of the glass circuit board matches that of the silicon photonic chip 230, ensuring high temperature resistance and high precision. Each corner of the circuit board 210 has rounded chamfers 211. These rounded chamfers increase the high-temperature stability of the circuit board 210 and prevent cuts. The ASIC chip 220 is mounted on the circuit board using a gold-tin solder eutectic interface. On the upper surface of board 210, the ASIC chip 220 has a surface mount tolerance of ±10μm and the melting point of the gold-tin solder is 280℃; the silicon photonics chip 230 is mounted on the upper surface of board 210 using tin-silver-copper solder, with a surface mount tolerance of ±10μm and a melting point of tin-silver-copper solder of 217℃; the TIA chip 240 is eutectic mounted on the upper surface of silicon photonics chip 230 using gold-tin solder, with a melting point of 280℃; the Driver chip 250 is eutectic mounted on the upper surface of silicon photonics chip 230 using gold-tin solder, with a melting point of 280℃.

[0033] Example 5 like Figure 1 , Figure 2 As shown, this embodiment is a further improvement on embodiment 3, as detailed below: Multiple third positioning holes 320 are formed on the base 3 around the through groove 310 and in the area covered by the cold plate 4, penetrating its upper and lower surfaces. The base 3 can have four third positioning holes 320, which are located at the four corners of the base 3. The lower surface of the cold plate 4 has a positioning post 410 corresponding to each third positioning hole 320. The positioning post 410 on the lower surface of the cold plate 4 enters the third positioning hole 320 on the base 3. The base 3 is made of Invar alloy, which has a low CTE and is magnetic. Its CTE requirement is less than 3ppm / ℃. The cold plate 4 is made of magnetic material. The cold plate 4 and the base 3 are attracted to each other to achieve a detachable connection. The magnetic cold plate and the Invar base generate an attraction to press the elastic power-applying needle 110, so that the elastic power-applying needle 110 is firmly in contact with the circuit board 210, so that the PCB board 1 can supply power and provide control signals to the circuit board 210.

[0034] Furthermore, the lower half of the inner wall of the third positioning hole 320 has an internal thread. On the PCB board 1, mounting holes 120 are respectively opened at each of the third positioning holes 320, penetrating the upper and lower surfaces. Screws 7 are arranged at the bottom of the PCB board 1, and the shank end of the screw 7 enters the third positioning hole 320 through the mounting hole 120 and is threadedly connected to the third positioning hole 320, thereby fixing the base 3 to the PCB board 1.

[0035] Example 6 like Figure 1 , Figure 2 , Figure 3 , Figure 5 As shown, this embodiment is a further improvement on any one of embodiments 1 to 5, as detailed below: The inner wall of the through groove 310 has at least two support platforms 330 below the CPO brain architecture 2 for supporting the CPO brain architecture 2. The number of support platforms 330 can be two, three, four, etc. In this embodiment, the number of support platforms 330 is preferably four. The four support platforms 330 are respectively located at the four corners of the through groove 310. The upper end of the elastic electrocautery needle 110 is higher than the upper surface of the support platform 330. When the support platform 330 supports the circuit board 210, the elastic electrocautery needle 110 can firmly contact the circuit board 210. The support platforms 330 inside the through groove 310 are provided with first positioning pins 340 that penetrate their upper and lower surfaces. The CPO brain architecture 2 has corresponding first positioning pins. A first positioning hole 212 is made at each of the 340 locations. Specifically, the circuit board 210 of the CPO brain architecture 2 has a first positioning hole 212 made at each corresponding first positioning pin 340, and the PCB board 1 has a second positioning hole 130 made at each corresponding first positioning pin 340. The upper end of each first positioning pin 340 enters the first positioning hole 212, and the lower end of each first positioning pin 340 enters the second positioning hole 130. The tolerance of the first positioning hole 212 is ±10μm, the tolerance of the second positioning hole 130 is ±10μm, and the accuracy of the first positioning pin 340 is ±5μm. This ensures optical performance when the CPO brain architecture 2 is replaced.

[0036] Example 7 like Figure 3 , Figure 5 As shown, this embodiment is a further improvement on any one of embodiments 1 to 6, as detailed below: The multi-channel fiber array 5 is bonded to the upper surface of the base 3 with adhesive, which can be UV adhesive. On the upper surface of the base 3, in each direction of the CPO brain architecture 2, there are adhesive blocking grooves 350 between two adjacent multi-channel fiber arrays 5. If too much adhesive is used to bond the multi-channel fiber array 5, it can flow into the adhesive blocking grooves 350, thereby preventing the adhesive from flowing to the adjacent multi-channel fiber array 5.

[0037] Example 8 like Figure 6 As shown, this embodiment is a further improvement on any one of embodiments 1 to 7, as detailed below: A second positioning pin 360 is provided on the upper surface of the base 3 at the corresponding location of the multi-channel fiber array 5. A magnet 8 is provided on the lower surface of the multi-channel fiber array 5. A fourth positioning hole 810 is opened on the lower surface of the magnet 8. The magnet 8 attracts the base 3, making it very convenient to assemble and disassemble the multi-channel fiber array 5 and the base 3. The second positioning pin 360 enters the fourth positioning hole 810 on the magnet 8. The accuracy of the second positioning pin 360 is ±5μm, and the tolerance of the fourth positioning hole 810 is ±10μm. When replacing the multi-channel fiber array 5, the optical performance can be guaranteed, allowing the multi-channel fiber array 5 to be replaced and maintained on-site, thereby solving the maintenance problem of fiber array damage in extremely low probability cases.

[0038] Example 9 like Figure 8 As shown, a method for fabricating a silicon photonics CPO module based on a CPO brain-only architecture is characterized by the following steps for fabricating a silicon photonics CPO module based on the CPO brain-only architecture as described in any of Examples 1 to 8: S1. Fix all the multi-channel fiber arrays 5 at the corresponding positions on the upper surface of the base 3. For example, multiple multi-channel fiber arrays 5 are arranged on the upper surface of the base 3 in each direction of the through groove 310. Specifically, four multi-channel fiber arrays 5 can be arranged in each direction. S2. Mount the base 3 for mounting the multi-channel fiber array 5 on the PCB board 1. Specifically, the screw 7 can be installed by passing the mounting hole 120 on the PCB board 1 into the third positioning hole 320 on the base 3 and threadedly connecting it to the third positioning hole 320, thereby fixing the base 3 to the PCB board 1. S3. Assemble the CPO brain architecture 2 according to the corresponding assembly relationship, and install the CPO brain architecture 2 into the through slot 310 on the base 3, so that the CPO brain architecture 2 is coupled with the multi-channel fiber array 5, and the CPO brain architecture 2 is electrically connected to the PCB board 1 via the elastic power pin 110. S4. Make the cold plate 4 detachably connected to the base 3, and press down the CPO brain architecture 2 through the cold plate 4.

[0039] like Figure 9 As shown, the method for creating the CPO brain architecture 2 is as follows: The ASIC chip 220 is eutectic bonded to the upper surface of the circuit board 210 using gold-tin solder. The TIA chip 240 is attached to the upper surface of the silicon photonic chip 230 using gold-tin solder eutectic bonding, and the Driver chip 250 is attached to the upper surface of the silicon photonic chip 230 using gold-tin solder eutectic bonding. The first lens array 260 is then coupled and fixed to the side of the waveguide side of the silicon photonic chip 230 using UV adhesive. During coupling, the silicon photonic chip 230 is powered by a probe. At least one silicon photonic chip 230 is mounted on the upper surface of the circuit board 210 in each direction of the ASIC chip 220. The silicon photonic chip 230 can be mounted on the upper surface of the circuit board 210 using tin-silver-copper solder. When mounting the silicon photonic chip 230, a laser welding process is used to locally heat the solder joints to prevent the temperature of the first lens array 260 from becoming too high. The silicon photonic chip 230 is interconnected with the ASIC chip 220 via a high-speed RF line in the circuit board 210.

[0040] like Figure 10 As shown, the maintenance method for the silicon photonics CPO module based on the CPO brain architecture with only CPO replacement is as follows: When the CPO brain structure 2 is damaged, remove the cold plate 4 from the base 3, then take out the CPO brain structure 2 located in the through slot 310, replace it with a new CPO brain structure 2, and replace the cold plate 4. After the cold plate 4 is connected to the base 3, the cold plate 4 presses down on the CPO brain structure 2. The elastic force of the elastic power pin 110 keeps the CPO brain structure 2 electrically connected to the PCB board 1, thus completing the maintenance or repair.

[0041] For the damaged CPO brain architecture 2, if the silicon photonics engine is damaged, the damaged silicon photonics engine (silicon photonics chip 230 + TIA chip 240 + Driver chip 250) can be removed by local laser heating and a qualified silicon photonics engine can be reattached. If the ASIC chip 220 is damaged, the entire CPO brain architecture 2 is scrapped and only the qualified silicon photonics engine is recycled.

[0042] Example 10 like Figure 7 As shown, the CPO complete unit includes: a silicon photonics CPO module based on a CPO brain-only architecture, a fiber optic distribution frame, and an ELSFP pluggable light source module. The polarization-maintaining fiber of the multi-channel fiber array 5 in the silicon photonics CPO module based on the CPO brain-only architecture is externally connected to the ELSFP pluggable light source module via the fiber optic distribution frame. The other fibers of the multi-channel fiber array 5 in the silicon photonics CPO module based on the CPO brain-only architecture are externally connected to the fiber optic distribution frame.

[0043] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A silicon photonics CPO module based on a CPO-only brain architecture, characterized in that, include: A PCB board (1) and a CPO brain architecture (2) are provided. A base (3) is provided on the upper surface of the PCB board (1). A through slot (310) is provided on the base (3) through its upper and lower surfaces. An elastic power-applying pin (110) is provided on the PCB board (1) in the area enclosed by the through slot (310). The CPO brain architecture (2) is located in the through slot (310) and is electrically connected to the PCB board (1) through the elastic power-applying pin (110). A cold plate (4) is arranged on the top of the CPO brain architecture (2). The cold plate (4) is detachably connected to the base (3) and is used to press down on the CPO brain architecture (2). Multiple multi-channel fiber arrays (5) coupled to the CPO brain architecture (2) are arranged on the upper surface of the base (3) in each direction.

2. A silicon photonics CPO module based on a CPO-only brain architecture according to claim 1, characterized in that, A phase change soft thermal pad (6) is arranged between the CPO brain architecture (2) and the cold plate (4).

3. A silicon photonics CPO module based on a CPO-only brain architecture according to claim 1, characterized in that, The multi-channel fiber array (5) is located below the area covered by the cold plate (4).

4. A silicon photonics CPO module based on a CPO-only brain architecture according to claim 1, 2, or 3, characterized in that, The CPO brain architecture (2) includes: a circuit board (210), on the upper surface of the circuit board (210) in the middle region, an ASIC chip (220) is eutectic-mounted, and at least one silicon photonic chip (230) is eutectic-mounted on the upper surface of the circuit board (210) in each direction of the ASIC chip (220). The silicon photonic chip (230) is interconnected with the ASIC chip (220) via a high-speed RF line in the circuit board (210). The upper surface of the silicon photonic chip (230) is eutectic-mounted with a TIA chip (240) and a Driver chip (250) electrically connected thereto. The side of the silicon photonic chip (230) on the waveguide side has a first lens array (260) coupled thereto, and the side of the multi-channel fiber array (5) on the optical port side has a second lens array (510) coupled thereto. The first lens array (260) and the second lens array (510) are coupled together.

5. A silicon photonics CPO module based on a CPO-only brain architecture according to claim 4, characterized in that, The circuit board (210) is a glass circuit board, and each corner of the circuit board (210) is provided with a rounded chamfer (211). The ASIC chip (220) is attached to the upper surface of the circuit board (210) with gold-tin solder eutectic bonding. The silicon photonic chip (230) is attached to the upper surface of the circuit board (210) with tin-silver-copper solder. The TIA chip (240) and the Driver chip (250) are attached to the upper surface of the silicon photonic chip (230) with gold-tin solder eutectic bonding, respectively.

6. A silicon photonics CPO module based on a CPO-only brain architecture according to claim 3, characterized in that, The base (3) has multiple third positioning holes (320) around the through groove (310) and in the covered area of ​​the cold plate (4), which penetrate the upper and lower surfaces. The lower surface of the cold plate (4) has a positioning post (410) that enters each of the third positioning holes (320). The base (3) is made of Invar alloy, and the cold plate (4) is made of magnetic material. The cold plate (4) and the base (3) are attracted to each other to achieve a detachable connection.

7. A silicon photonics CPO module based on a CPO-only brain architecture according to claim 6, characterized in that, The lower half of the inner wall of the third positioning hole (320) has an internal thread. The PCB board (1) has an assembly hole (120) that passes through the upper and lower surfaces of each third positioning hole (320). Screws (7) are arranged on the lower part of the PCB board (1). The shank end of the screw (7) enters the third positioning hole (320) through the assembly hole (120) and is threadedly connected to the third positioning hole (320) to fix the base (3) to the PCB board (1).

8. A silicon photonics CPO module based on a CPO-only brain architecture according to any one of claims 1 to 7, characterized in that, The inner wall of the through groove (310) has at least two support platforms (330) for supporting the CPO brain architecture (2) below. The upper end of the elastic electrocautery needle (110) is higher than the upper surface of the support platform (330). The support platform (330) inside the through groove (310) is provided with a first positioning pin (340) that penetrates its upper and lower surfaces. The CPO brain architecture (2) is provided with a first positioning hole (212) at each first positioning pin (340). The PCB board (1) is provided with a second positioning hole (130) at each first positioning pin (340). The upper and lower ends of each first positioning pin (340) enter the first positioning hole (212) and the second positioning hole (130) respectively.

9. A silicon photonics CPO module based on a CPO-only brain architecture according to claim 1, characterized in that, The multi-channel fiber array (5) is glued to the upper surface of the base (3). On the upper surface of the base (3), a resist groove (350) is opened between two adjacent multi-channel fiber arrays (5) in each direction of the CPO brain architecture (2); or, a second positioning pin (360) is provided on the upper surface of the base (3) at the corresponding multi-channel fiber array (5), and a magnet (8) is provided on the lower surface of the multi-channel fiber array (5). A fourth positioning hole (810) is opened on the lower surface of the magnet (8). The magnet (8) attracts the base (3), and the second positioning pin (360) enters the fourth positioning hole (810) on the magnet (8).

10. A method for fabricating a silicon photonics CPO module based on a CPO brain-only architecture, characterized in that, To fabricate a silicon photonics CPO module based on the CPO brain-only architecture as described in any one of claims 1 to 9, the following steps are included: S1. Fix all the multi-channel fiber arrays (5) to the corresponding positions on the upper surface of the base (3); S2. Mount the base (3) for the multi-channel fiber array (5) onto the PCB board (1); S3. Insert the CPO brain architecture (2) into the through slot (310) on the base (3) to couple the CPO brain architecture (2) with the multi-channel fiber array (5) and to electrically connect the CPO brain architecture (2) to the PCB board (1) via the elastic power pin (110). S4. Make the cold plate (4) detachably connected to the base (3) and press down the CPO brain architecture (2) through the cold plate (4).

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