Polishing-free low-loss coupling optical fiber array adaptive to deep silicon etching photon chip, deep silicon etching photon chip coupling assembly and method

Abstract

The invention discloses a non-polishing low-loss coupling optical fiber array adaptive to a deep silicon etching photon chip, a deep silicon etching photon chip coupling assembly and a method, and belongs to the technical field of silicon photon integration. The device comprises an optical fiber array main body, a V-shaped groove substrate and a special-shaped cover plate, the special-shaped cover plate is attached to the upper surface of the V-shaped groove substrate, an avoiding groove is formed in the position, corresponding to a deep silicon etching area of the end face of the chip, of the special-shaped cover plate, and the depth of the avoiding groove is not smaller than the total height of a residual step on the end face of the chip and a deep groove protruding structure so as to eliminate mechanical interference. The tail end of the optical fiber is positioned in the V-shaped groove, and the light-emitting end face is parallel and tightly butted with the end face of the chip. The customized avoiding groove is integrated in the cover plate, direct, lossless and low-loss coupling of the optical fiber array and the deep silicon etching silicon optical chip with the composite three-dimensional morphology end face can be achieved without extending the optical fiber, removing a bottom cover or polishing the end face of the chip, the integrity of the end face of the chip is effectively protected, and the coupling precision and the device yield are improved.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of coupling packaging of integrated photon chips and fiber arrays, and particularly relates to a low-loss coupling fiber array without polishing for adapting to deep silicon etching photon chips, a deep silicon etching photon chip coupling assembly and a method. BACKGROUND

[0002] Deep silicon etching (DRIE) is a key process for manufacturing high-performance silicon photon chips, and can form high-aspect-ratio functional grooves with a depth of 100-250 μm. However, this process introduces two major coupling obstacles at the chip end face: first, after wafer cutting, a residual step with a height of 50-200 μm is formed at the junction of the etched area and the non-etched area; second, to achieve edge coupling, a protruding deep groove structure needs to be reserved at the chip end face, and the protruding height is 10-30 μm.

[0003] The existing flat plate type cover plate of the fiber array (FA) cannot avoid the above-mentioned complex topography, resulting in mechanical interference and unable to directly fit the chip end face. To solve this problem, the industry adopts three remedial schemes, but all have serious defects: Extending the fiber out of the groove: the fiber end is stretched out of the V-shaped groove to cross the obstacle, but the stretched section lacks support and is prone to breakage, and the end face polishing yield is low; Removing the FA cover plate: removing the cover plate to shorten the coupling distance, but sacrificing the positioning accuracy and structural stability of the fiber; End face polishing: removing the step and protruding structure by mechanical polishing, but this process is extremely easy to cause the silicon end face to crack (high scrap rate) and damage the high-quality end face formed by etching (roughness ≤1 nm), introducing additional scattering loss.

[0004] Therefore, the existing technology cannot realize interference-free and low-loss fiber-chip coupling while preserving the high-quality end face of deep silicon etching, which is a key bottleneck restricting the performance and production yield of silicon photon devices. SUMMARY

[0005] The technical problem to be solved by the present application is to provide a low-loss coupling fiber array without polishing for adapting to deep silicon etching photon chips, a deep silicon etching photon chip coupling assembly and a method, which integrates a customized avoidance groove on the cover plate, without the need to extend the fiber, remove the bottom cover or polish the chip end face, to realize direct, lossless and low-loss coupling of the fiber array and the deep silicon etching silicon optical chip with a complex three-dimensional topography end face, effectively protect the integrity of the chip end face, and improve the coupling accuracy and device yield.

[0006] To solve the above technical problems, the technical solution adopted by the present application is: A low-loss coupling fiber array without polishing for adapting to deep silicon etching photon chips: comprising a V-shaped groove bottom plate, an array fiber and an upper cover plate; The V-shaped groove bottom plate is provided with a complete V-shaped groove group, the array optical fiber is embedded in the V-shaped groove group, and the optical fiber end is flush with the end face of the V-shaped groove bottom plate without the need to extend out of the groove; The upper cover plate is provided with a structured deformation part near the chip coupling end, and the structured deformation part is one or a combination of a slope structure, a step structure or a misalignment structure; The total avoidance depth of the structured deformation part is not less than the sum of the residual step height and the deep trench protrusion height of the deep silicon etching photonic chip, and the total avoidance width is not less than the sum of the residual step width and the deep trench protrusion width, so that the coupling gap between the optical fiber core and the edge coupler of the deep silicon etching photonic chip is ≤5μm.

[0007] As a preferred scheme, the surface roughness of the slope structure is ≤0.1μm; the step structure includes 1-3 sub-steps, the height of a single sub-step is equal to 1.1 times the height of the corresponding area step plus 2μm, and the width of a single sub-step is equal to 1.1 times the width of the corresponding area step plus 2μm.

[0008] As a preferred scheme, the misalignment structure has an offset of 15-60μm, and the offset direction is opposite to the protruding direction of the deep silicon etching chip step and the deep trench protrusion.

[0009] As a preferred scheme, the end face of the array optical fiber is polished by grinding, and the roughness is ≤0.05μm.

[0010] As a preferred scheme, the V-shaped groove spacing of the V-shaped groove bottom plate is 125μm or 250μm, and the size of the V-shaped groove ensures that after embedding the optical fiber, the vertical distance between the optical fiber core and the upper surface of the bottom plate is accurately matched with the height of the edge coupler of the deep silicon etching photonic chip.

[0011] A deep silicon etching photonic chip coupling assembly includes a deep silicon etching photonic chip and a non-interference low-loss coupling optical fiber array adapted to the deep silicon etching photonic chip; The deep silicon etching photonic chip includes a silicon substrate, a silicon oxide layer and an edge coupler, the silicon substrate is formed with a functional groove with a depth of 100-250μm by reactive ion etching, the groove end face roughness is ≤1nm, the end face of the chip after cutting forms a residual step and a deep trench protrusion, and the end face of the chip is not polished, and the end face with a roughness of ≤1nm formed by etching is directly used as a coupling interface; The structured deformation part of the non-interference low-loss coupling optical fiber array adapted to the deep silicon etching photonic chip forms a spatial avoidance with the residual step and the deep trench protrusion.

[0012] Preferably, the residual step height of the deep silicon etching photonic chip is 50-200 μm, and the width is 10-50 μm; the protruding height of the deep groove is 10-30 μm, and the width is 15-40 μm.

[0013] Preferably, the V-shaped groove bottom plate is bonded to the end face of the deep silicon etching photonic chip through optical coupling glue.

[0014] A preparation method of a deep silicon etching photonic chip coupling assembly, comprising the following steps: a) preparing a deep silicon etching photonic chip: etching a functional groove with a depth of 100-250 μm at the coupling end face position of the photonic chip, and controlling the etching parameters so that the roughness of the groove end face is ≤1 nm; cutting the wafer into chip monomers, and not polishing the end face of the chip to reserve the etching end face as the coupling interface; b) processing a structured cover plate: laser processing or bevel polishing the cover plate blank to form the structured deformation part; c) assembling a non-interference low-loss coupling fiber array adapted to the deep silicon etching photonic chip: embedding the optical fiber into the V-shaped groove bottom plate, calibrating the shaft with the visual alignment system, covering the structured cover plate, and curing the UV glue to ensure that the end of the optical fiber is basically flush with the end of the bottom plate; polishing the end face of the V-shaped groove of the optical fiber array, and the roughness is ≤0.05 μm; d) coupling alignment: adjusting the relative position of the non-interference low-loss coupling fiber array adapted to the deep silicon etching photonic chip and the deep silicon etching photonic chip with the visual alignment system and the optical power detection system, so that the coupling gap is ≤10 μm, and the optical coupling loss is ≤1 dB, and then point optical coupling glue is cured.

[0015] Preferably, in step d), the position resolution of the visual alignment system is not greater than 0.1 μm, and the angle resolution is not greater than 0.1°, which are used to simultaneously identify the step and protruding structure of the chip and the structured deformation part of the non-interference low-loss coupling fiber array adapted to the deep silicon etching photonic chip. The detection accuracy of the optical power detection system is ≥0.01 mW, which is used to monitor the change of optical coupling loss in the alignment process, and assist the visual alignment system to adjust in X / Y / Z / θX / θY / θZ six degrees of freedom, so as to realize the minimum optical coupling loss.

[0016] The present application can achieve the following beneficial effects: 1. Significant advantages in end-face quality and substantial reduction in loss: The roughness of the coupling end face directly formed by deep silicon etching is ≤1nm, which is 80%-90% lower than the 5-10nm of traditional polishing. The scattering loss is reduced from 0.2-0.5dB to 0.1-0.2dB. Moreover, the etched end face is free of cracks (the crack rate is reduced from 30% to 0), the waveguide structure is intact, and with a small gap within 5μm, the total coupling loss is ≤1dB, which is more than 40% lower than the traditional polishing solution. 2. Simultaneously solve interference and gap problems: The composite deformation part of the cover plate achieves dual avoidance of "step + protruding structure", which, together with the precise positioning of the V-groove bottom plate, reduces the coupling gap from 20-50μm to ≤5μm, further amplifying the low loss advantage of the high-quality end face; 3. Completely eliminate defective processes: The optical fiber does not need to be extended to form a V-groove, and the fiber end face breakage rate is reduced from 15% to 0; the base plate and cover plate are completely retained without removal, and the fiber positioning accuracy is maintained at ±0.5μm, which is 6 times better than the solution of removing the cover plate. 4. Advantages of eliminating polishing process: After chip cutting, the etched end face is directly assembled, avoiding 30% of the risk of breakage and scrap, eliminating the investment in polishing equipment (reducing fixed asset costs by 300,000 yuan), shortening the process cycle by 2-3 days, and reducing the single chip packaging cost by 30%; 5. High mass production stability: The quality consistency of the etched end face is better than that of polishing (roughness fluctuation ±0.2nm vs ±2nm). Combined with the CTE-matched packaging structure, the loss drift is ≤0.2dB after 1000 temperature cycles from -40℃ to 85℃, meeting the industrial-grade reliability requirements. Attached Figure Description

[0017] The present invention will be further described below with reference to the accompanying drawings and embodiments: Figure 1 The diagram shows a cross-sectional schematic of a low-loss, non-polishing coupled fiber array (sloping structure) adapted to a deep silicon etched photonic chip and a deep silicon etched end face optical chip coupling component provided by an embodiment of the present invention. Figure 2 The diagram shows a cross-sectional schematic of a low-loss, non-polishing coupled fiber array (stepped structure) adapted to a deep silicon etched photonic chip and a deep silicon etched end face optical chip coupling component provided by an embodiment of the present invention. Figure 3 The diagram shows a cross-sectional schematic of a low-loss, non-polishing coupled fiber array (misaligned structure) adapted to a deep silicon etched photonic chip and a deep silicon etched end face optical chip coupling component provided by an embodiment of the present invention. Figure 4 The diagram shows a cross-sectional schematic of a conventional FA coupled with a deep silicon etched end face optical chip assembly. Figure 5The diagram shows a cross-sectional schematic of the existing extended fiber optic FA with V-groove and deep silicon etched end face optical chip coupling assembly. Detailed Implementation

[0018] Preferred solutions include Figures 1 to 5 As shown, this invention discloses a low-loss coupled fiber array without polishing, a coupling component for deep silicon etched photonic chips, and a method for adapting to deep silicon etched photonic chips. The invention aims to simultaneously address the following five major technical challenges: 1) the low efficiency and high end-face roughness, chipping damage, and waveguide destruction inherent in traditional polishing methods; 2) the coupling interference problem between residual steps after deep silicon etched chip cutting and the fiber optic array (FA); 3) the high power loss problem caused by a 20-50μm gap formed by deep trench protrusions in edge coupling; 4) the end-face fragility and low yield caused by extending the fiber to the V-groove; and 5) the problems of loose positioning, high cost, and poor stability caused by removing the FA cover plate. Ultimately, the invention achieves the mass production goal of "deep silicon etched chip without polishing (directly utilizing high-quality etched end-faces) → FA interference-free assembly → coupling gap ≤10μm → loss ≤1dB".

[0019] An interference-free, low-loss coupled fiber optic array adapted for deep silicon etched chips The fiber optic array includes a V-groove base plate, array fibers, and a top cover plate. Its core innovation lies in the collaborative design of "precise base plate positioning + cover plate deformation avoidance + high-quality end-face adaptation through deep silicon etching," with the specific structure as follows: V-groove base plate: The surface of the V-groove base plate is formed with V-groove groups through mechanical processing or etching, with a groove spacing of 125μm / 250μm (adapted to standard arrays). The V-groove size ensures that the vertical distance between the fiber core and the upper surface of the base plate after the fiber is embedded is precisely matched with the height of the edge coupler of the deep silicon etched chip, and achieves micron-level gap coupling with the high-quality end face of the chip; the V-groove base plate retains the complete structure without the need for local removal, ensuring the stability of fiber positioning. Array fiber: Single-mode or multi-mode fiber is used. The fiber end face is ground and polished (roughness ≤0.05μm). The fiber end is flush with the end of the V-groove bottom plate, eliminating the need for extension out of the groove and avoiding the risk of end face damage. Cover plate: The overall thickness of the upper cover plate is 250±10μm. A composite structured deformation part is provided in a local area near the chip coupling end. This deformation part is one or a combination of inclined plane, step, and misalignment structure. The size is precisely adapted to the dual characteristics of "residual step + deep trench protrusion" of the deep silicon etched chip. 1) Inclined structure: Inclined angle 30°-60° (45° when step height is 100μm), the starting position of the inclination is 80-120μm from the coupling end face of the cover plate, the clearance depth between the lowest point of the inclination and the lower surface of the cover plate is ≥ step height H + deep groove protrusion height h (total clearance depth ≥ H + h + 5μm assembly tolerance), the clearance width of the inclination along the fiber extension direction is ≥ step width W + deep groove protrusion width w (total clearance width ≥ W + w + 5μm), the surface of the inclination is polished (roughness ≤ 0.1μm) to avoid scattering loss; 2) Step structure: Set 1-3 levels of sub-steps (adapt to multi-level etching structures). The height of a single sub-step = the height of the corresponding area step × 1.1 + 2μm, and the width = the width of the corresponding area step × 1.1 + 2μm. For example, if the chip step H = 100μm and the deep trench protrusion h = 20μm, then the sub-step height = 122μm, ensuring complete avoidance of the dual structure. 3) Misaligned structure: The coupling end of the cover plate is offset by 15-60μm along the optical fiber axis. The offset direction is opposite to the direction of the step / protrusion. The offset amount = protrusion size × 1.1 + 3μm, so as to achieve no interference in the lateral direction.

[0020] The cover plate and the base plate are bonded together with UV-cured adhesive.

[0021] A deep silicon etched photonic chip coupling component The component includes a deep silicon etched photonic chip and the aforementioned fiber array. Its core feature lies in achieving coupling directly using the high-quality end face formed by deep silicon etching, as detailed below: Deep silicon etched photonic chip: includes at least a silicon substrate and a waveguide layer; the silicon substrate is formed with functional trenches 100-250μm deep by reactive ion etching (RIE), so that the trench end face (i.e. the coupling end face) directly forms a mirror quality with a roughness ≤1nm, without cracks or jagged edges; after chip cutting (cutting accuracy ±5μm), residual steps (H=50-200μm, W=10-50μm) are formed, and the deep trench protrusions (h=10-30μm, w=15-40μm) are formed. The chip end face does not undergo any polishing treatment, and the high-quality end face formed by etching is directly used as the coupling interface. Coupling and Adaptation Relationship: The composite structured deformation part of the FA and the chip's "residual steps + deep trench protrusion" form a 360° spatial avoidance (no mechanical contact); after calibration by a visual alignment system (position resolution no greater than 0.1μm, angular resolution no greater than 0.1°) and an optical power detection system (detection accuracy ≥0.01mW), the coupling gap between the fiber core and the edge coupler is ≤10μm, and the high-quality end face of the fiber and the high-quality end face of the chip form a "double high-quality interface" match to maximize the reduction of scattering loss; the V-groove base plate is bonded to the chip end face by optical coupling adhesive.

[0022] Method for fabricating coupling components The steps are as follows, with the core emphasis on the connection between "high-quality end-face preparation by etching" and "coupling without polishing": Deep silicon etching high-quality end-face chip fabrication: Deep trenches are prepared on silicon substrates using deep silicon etching technology, so that the roughness of the trench end face is ≤1nm; the wafer is then cut into individual chips using a wafer dicing machine, and the end face is not polished, directly retaining the etched mirror quality, resulting in a chip with "residual steps + deep trench protrusion + high-quality coupling end face". Structured cover plate processing: The cover plate blank is processed by laser (accuracy ±1μm) to composite deformation parts, and the stepped structure is processed in steps (each step depth accuracy ±0.5μm). Fiber optic array assembly: The fiber is embedded into the V-groove base plate. After alignment using a vision system, the structured cover plate is fitted. The coupling end of the misaligned FA cover plate is offset by 15-60 μm along the fiber axis, with the offset direction opposite to the step / protrusion direction. The offset amount = protrusion size × 1.1 + 3 μm. Adhesive is then applied and cured. The end faces of the V-groove of the fiber optic array are ground and polished (roughness ≤ 0.05 μm) to form the finished FA product (yield ≥ 95%). High-quality end-face non-polishing coupling alignment: The chip is fixed on a vacuum adsorption platform, the FA is fixed on a six-dimensional adjustment frame, a high-magnification CCD vision system simultaneously identifies chip steps, protruding structures and FA deformation parts, an optical power detection system monitors optical coupling loss, and the X / Y / Z / θX / θY / θZ directions are adjusted to make the coupling gap ≤10μm and the optical coupling loss ≤1dB. The optical coupling adhesive is applied and cured to complete the "double high-quality end-face" coupling assembly.

[0023] Example 1: sloping structure FA adapted for deep silicon etched photonic chips 1. Fabrication of high-quality end-face chips by deep silicon etching Deep trenches were fabricated on a silicon substrate using reactive ion etching (RIE) with an etching depth of 150 μm. Parameters such as etching power and gas flow rate were controlled to achieve a trench end-face roughness of 0.8 nm without any chipping. The wafer was then diced into individual chips using laser dicing with a dicing precision controlled within ±5 μm. After dicing, residual steps (H=100 μm, W=30 μm) and protruding deep trench portions (h=20 μm, w=15 μm) were formed on the chip end-face. The chip edge coupler mode field diameter was 9 μm. No polishing was performed on the end-face; the high-quality end-face formed by etching was used directly as the coupling interface.

[0024] 2. Structured cover plate processing A cover plate blank with a thickness of 250μm was selected, and the inclined deformation part was made by laser processing. The inclined angle was set to 45°, and the starting position of the inclination was 100μm away from the coupling end face of the cover plate. Based on the chip residual step and deep trench protrusion size, the total avoidance depth was calculated to be ≥100μm+20μm+5μm=125μm, and the total avoidance width was ≥30μm+15μm+5μm=50μm. After processing, the inclined surface was polished to ensure that the inclined surface roughness was ≤0.1μm.

[0025] 3. Fiber Array Assembly V-groove base plate: The V-groove group is manufactured using mechanical processing technology. The groove spacing is set to 127μm, and the distance from the bottom of the groove to the upper surface is 63μm. This ensures that the vertical distance between the fiber core and the upper surface of the base plate after the fiber is embedded is precisely matched with the height of the chip edge coupler.

[0026] Array fiber: Single-mode fiber is selected, and the fiber end face is ground and polished to achieve a roughness of 0.05μm. The fiber is embedded into the V-groove base plate, and after being aligned and oriented by a vision alignment system, the structured cover plate is closed. UV adhesive is then used for curing to ensure that the fiber end is flush with the end of the base plate, with no extension out of the groove. The end face of the V-groove in the fiber array is ground and polished (roughness ≤0.05μm).

[0027] 4. High-quality end face without polishing and grinding coupling alignment The prepared deep silicon etched photonic chip was fixed on a vacuum adsorption platform, and the fiber array was fixed on a six-dimensional adjustment frame. A high-magnification CCD vision alignment system (position resolution no greater than 0.1 μm, angular resolution no greater than 0.1°) was used to simultaneously identify chip steps, protruding structures and FA inclined deformation parts. The positions in the six directions of X / Y / Z / θX / θY / θZ were adjusted to make the coupling gap between the fiber core and the chip edge coupler reach 3 μm. The coupling assembly was completed by dispensing and curing.

[0028] The chip is fixed to a vacuum adsorption platform, and the FA is fixed to a six-dimensional adjustment frame. A high-magnification CCD vision system simultaneously identifies chip steps, protruding structures, and deformed parts of the FA. An optical power detection system monitors changes in optical coupling loss, and the X / Y / Z / θX / θY / θZ directions are adjusted to achieve a coupling gap of 5μm. After adhesive dispensing and curing, the "double high-quality end face" coupling assembly is completed.

[0029] 5. Performance Testing and Verification The performance of the assembled coupling components was tested, and the results are as follows: the coupling loss is 0.7dB at room temperature; after 1000 cycles of testing within a temperature range of -40℃ to 85℃, the loss drift is 0.15dB; compared with chips of the same structure using polished end faces (end face roughness 8nm), the loss is reduced by 0.9dB; the fiber array assembly yield reaches 96%, which is 26 percentage points higher than the existing extended fiber solution; and the single-chip packaging cost is reduced by 35% compared with the traditional polishing solution.

[0030] Example 2: Stepped structure FA adapted to deep silicon etched photonic chip 1. Fabrication of high-quality end-face chips by deep silicon etching Deep trenches were fabricated on a silicon substrate using a two-stage deep silicon etching process. The first stage had an etching depth of 120 μm, and the second stage had an etching depth of 80 μm. The etching parameters were controlled to achieve a trench end-face roughness of 0.9 nm. The trenches were then diced into individual chips using a wafer dicing machine with a dicing accuracy of ±5 μm. After dicing, two residual steps were formed (H1=120 μm / W1=40 μm, H2=80 μm / W2=25 μm) and a protruding portion of the deep trench (h=30 μm / w=20 μm). The chip end-faces were not polished.

[0031] 2. Structured cover plate processing A polyimide cover plate blank with a thickness of 280μm was selected. A two-stage sub-step deformation section was fabricated using a step-by-step laser processing technology: the first stage sub-step has a height of 120μm × 1.1 + 3μm = 135μm and a width of 40μm × 1.1 + 2μm = 46μm; the second stage sub-step has a height of 80μm × 1.1 + 3μm = 91μm and a width of 25μm × 1.1 + 2μm = 29.5μm. The depth accuracy of each step during processing was controlled within ±0.5μm.

[0032] 3. Fiber Array Assembly The V-groove base plate has a groove spacing of 250 μm, and the distance from the groove bottom to the upper surface is calibrated according to the height of the chip edge coupler. Multimode optical fiber is selected, and the end face is ground and polished (roughness 0.04 μm). The optical fiber is embedded in the V-groove base plate, and after calibration, the stepped cover plate is closed. After UV adhesive curing, it is ensured that the end of the optical fiber is flush with the base plate. The end face of the V-groove of the fiber array is ground and polished (roughness ≤0.05 μm).

[0033] 4. High-quality end face without polishing and grinding coupling alignment Using the same coupling alignment equipment and method as in Example 1, the coupling gap was adjusted to 6 μm, and the assembly was completed by dispensing and curing.

[0034] 5. Performance Testing and Verification Test results show that the coupling component has a loss of 0.8dB at room temperature, which is 0.9dB lower than that of a chip with the same structure using polished end face (loss of 1.7dB); after 1000 cycles at temperatures ranging from -40℃ to 85℃, the loss drift is 0.2dB, which is 67% better than the existing bottom cover removal solution (loss drift of 0.6dB); and the single-chip packaging cost is reduced by more than 40% compared to the bottom cover removal solution.

[0035] 5.3 Example 3: Misaligned FA structure adapted to deep silicon etched photonic chip 1. Fabrication of high-quality end-face chips by deep silicon etching Deep trenches were fabricated on a silicon substrate using a deep silicon etching process with an etching depth of 120 μm. The etching parameters were controlled to achieve a trench end-face roughness of 0.7 nm. After dicing, residual steps (H=80 μm / W=20 μm) were formed on the chip end-face, and the protruding part of the deep trench bulged outward (h=25 μm / w=15 μm). The chip end-face was not polished.

[0036] 2. Structured cover plate processing A cover plate blank with a thickness of 250μm is selected. The offset is calculated based on the chip bump size: (25μm+15μm)×1.1+2μm=42μm. Laser processing is used to offset the coupling end of the cover plate inward by 42μm to form a misaligned structural deformation part.

[0037] 3. Fiber Array Assembly The V-groove base plate has a groove spacing of 125μm, and the distance from the bottom of the groove to the upper surface is precisely matched to the height of the chip edge coupler. Single-mode optical fiber with an end-face roughness of 0.03μm is selected. After being embedded in the V-groove base plate, it is assembled and cured with the structured cover plate, and the end of the optical fiber is flush with the base plate. The end face of the V-groove of the fiber array is ground and polished (roughness ≤0.05μm).

[0038] 4. High-quality end face without polishing and grinding coupling alignment The coupling gap was adjusted to 2μm using a vision alignment system, and the assembly was completed by dispensing and curing.

[0039] 5. Performance Testing and Verification Test results show that the coupling component has a loss of 0.6dB at room temperature, which is 1.2dB lower than the traditional polishing solution (loss of 1.8dB); the assembly efficiency reaches 1200 pieces / day, which is 50% higher than the traditional polishing solution (800 pieces / day); after 1000 cycles at temperatures ranging from -40℃ to 85℃, the loss drift is ≤0.18dB, meeting the industrial-grade reliability requirements.

[0040] The above embodiments are merely preferred technical solutions of the present invention and should not be considered as limitations on the present invention. The scope of protection of the present invention should be limited to the technical solutions described in the claims, including equivalent substitutions of the technical features described in the claims. That is, equivalent substitutions and improvements within this scope are also within the scope of protection of the present invention.

Claims

1. A non-interference, low-loss coupled fiber array adapted to deep silicon etched photonic chips, characterized in that, Includes a V-groove base plate, an array of optical fibers, and a top cover plate; The V-groove bottom plate is provided with a complete V-groove group, and the array optical fiber is embedded in the V-groove group with the end of the optical fiber flush with the end surface of the V-groove bottom plate, without the need for extension out of the groove; The upper cover plate has a structured deformation part near the chip coupling end, and the structured deformation part is one or a combination of inclined surface structure, stepped structure or misaligned structure; The total clearance depth of the structured deformation portion is not less than the sum of the residual step height and the deep trench protrusion height of the deep silicon etched photonic chip, and the total clearance width is not less than the sum of the residual step width and the deep trench protrusion width, so that the coupling gap between the fiber core and the edge coupler of the deep silicon etched photonic chip is ≤5μm.

2. The interference-free, low-loss coupled fiber array adapted to deep silicon etched photonic chips according to claim 1, characterized in that: The surface roughness of the inclined structure is ≤0.1μm; the step structure includes 1-3 sub-steps, the height of a single sub-step is equal to 1.1 times the height of the corresponding area step plus 2μm, and the width of a single sub-step is equal to 1.1 times the width of the corresponding area step plus 2μm.

3. The interference-free, low-loss coupled fiber array adapted to deep silicon etched photonic chips according to claim 1, characterized in that: The offset of the misaligned structure is 15-60μm, and the offset direction is opposite to the direction of the protrusions of the deep silicon etched chip steps and deep trenches.

4. The interference-free, low-loss coupled fiber array adapted to deep silicon etched photonic chips according to claim 1, characterized in that: The end face of the array fiber is ground and polished, with a roughness ≤0.05μm.

5. The interference-free, low-loss coupled fiber array adapted to deep silicon etched photonic chips according to claim 1, characterized in that: The V-groove spacing of the V-groove base plate is 125μm or 250μm. The size of the V-groove ensures that after the optical fiber is embedded, the vertical distance between the optical fiber core and the upper surface of the base plate is precisely matched with the height of the edge coupler of the deep silicon etched photonic chip.

6. A deep silicon etched photonic chip coupling component, characterized in that, Including a deep silicon etched photonic chip and an interference-free, low-loss coupled fiber array adapted to a deep silicon etched photonic chip as described in any one of claims 1 to 5; The deep silicon etched photonic chip includes a silicon substrate, a silicon oxide layer, and an edge coupler. The silicon substrate is formed with functional trenches of 100-250 μm depth by reactive ion etching. The roughness of the trench end face is ≤1 nm. After the chip is cut, residual steps and deep trench protrusions are formed on the end face. The chip end face is not polished and is directly used as the coupling interface with the end face with a roughness of ≤1 nm formed by etching. The structured deformable portion of the non-interference low-loss coupled fiber array adapted to the deep silicon etched photonic chip forms a spatial avoidance with the residual steps and deep trench protrusions.

7. The deep silicon etched photonic chip coupling component according to claim 6, characterized in that: The residual step height of the deep silicon etched photonic chip is 50-200μm, and the width is 10-50μm; the protrusion height of the deep trench is 10-30μm, and the width is 15-40μm.

8. The deep silicon etched photonic chip coupling component according to claim 6, characterized in that: The V-groove base plate is bonded to the end face of the deep silicon etched photonic chip using optical coupling adhesive.

9. A method for fabricating a deep silicon etched photonic chip coupling component as described in any one of claims 6 to 8, characterized in that, Includes the following steps: a) Fabrication of deep silicon etched photonic chips: functional trenches with a depth of 100-250μm are etched at the coupling end face of the photonic chip, and the etching parameters are controlled to make the roughness of the trench end face ≤1nm; the wafer is cut into chip units, and the chip end face is not polished, but the etched end face is retained as the coupling interface. b) Processing the structured cover plate: Laser processing or bevel polishing is performed on the cover plate blank to form the structured deformed part; c) Assemble an interference-free, low-loss coupled fiber array adapted to deep silicon etched photonic chips: embed the fiber into the V-groove base plate, calibrate the axis using a vision alignment system, cover it with the structured cover plate and cure it with UV adhesive to ensure that the fiber end is basically flush with the end of the base plate. The end face of the V-groove of the fiber array is ground and polished to a roughness of ≤0.05μm; d) Coupling alignment: The relative position of the interference-free low-loss coupling fiber array adapted to the deep silicon etched photonic chip and the deep silicon etched photonic chip is adjusted using a vision alignment system and an optical power detection system to make the coupling gap ≤10μm and the optical coupling loss ≤1dB. Then, optical coupling adhesive is applied and cured.

10. The method for fabricating a deep silicon etched photonic chip coupling component according to claim 9, characterized in that: In step d), the position resolution of the visual alignment system is no greater than 0.1 μm and the angle resolution is no greater than 0.1°. It is used to simultaneously identify the steps and protruding structures of the chip and the structured deformation parts of the non-interference low-loss coupled fiber array of the adapted deep silicon etched photonic chip. The detection accuracy of the optical power detection system is ≥0.01 mW. It is used to monitor the change in optical coupling loss during alignment and assist the visual alignment system in adjusting in six degrees of freedom (X / Y / Z / θX / θY / θZ) to achieve minimum optical coupling loss.

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