A hardware control driving system based on a reconfigurable intelligent metasurface phased array with extremely low cost

Abstract

The application discloses a kind of hardware control driving systems based on extremely low cost reconfigurable intelligent metasurface phased array, it is related to intelligent metasurface driving technical field, including FPGA master module, power amplifier module, radio frequency diode array and resistance;Radio frequency diode array is made of multiple groups of reverse parallel diodes, one end is connected with power amplifier module 1.65V output end, the other end is independently connected with each IO port of FPGA through resistance;Power amplifier module is complementary push-pull structure, only contains pull-up, pull-down transistor, provides bidirectional current;FPGA outputs 0V / 3.3V level, through 1.65V voltage difference control diode on-off, compatible Sub-6GHz and millimeter wave radio frequency diode.The application omits negative voltage circuit and special driving chip, architecture is extremely simple, cost is extremely low, power consumption is small, supports large-scale array expansion, provides reliable driving scheme for commercial application of intelligent metasurface.

Description

Technical Field

[0001] This invention relates to the field of intelligent metasurface driving technology, and more specifically to a hardware control and driving system based on an extremely low-cost reconfigurable intelligent metasurface phased array. Background Technology

[0002] Intelligent metasurfaces (RIS / IRS) are two-dimensional artificial electromagnetic structures composed of a large number of subwavelength electromagnetic units arranged periodically or aperiodically. Each unit integrates tunable devices (such as PIN diodes, varactor diodes, MEMS, phase change materials, etc.). By independently or in groups adjusting the electrical bias state of each unit through a drive control system, the equivalent impedance and reflection / transmission coefficient of the unit can be dynamically changed. This allows for precise programmable control of the phase, amplitude, polarization, and propagation direction of the incident electromagnetic wave, enabling functions such as beamforming, beam scanning, interference suppression, signal enhancement, and channel reconstruction.

[0003] Compared to traditional phased arrays, smart metasurfaces do not require high-cost T / R components, RF links, high-power amplifiers, or high-speed ADCs / DACs. Theoretically, they have inherent advantages such as low power consumption, low cost, planarity, easy conformal design, and easy large-scale deployment, and are recognized as a core key technology for 6G and next-generation wireless communication.

[0004] However, common RIS-driven control schemes mainly include the following: Discrete MOSFET array solution: Each unit is equipped with an independent MOSFET switch and resistor network, and is directly driven by an external control signal. This solution is intuitive, but as the array size increases, the number of components becomes huge (each unit requires 2-4 MOSFETs and several resistors and capacitors), the PCB layout becomes crowded, the cost per board increases sharply, and the static power consumption is high, making it difficult to meet the needs of portable or low-power applications.

[0005] Dedicated multi-channel driver chip solution: This solution uses a multi-channel digital analog single-pole double-throw switch to simultaneously control several channels to output preset positive and negative voltages. Although it offers high integration and performance, commercial chips are typically expensive. A single TI single-pole double-throw switch chip with four channels costs 24 yuan, and the price continues to rise. This is equivalent to a control unit costing around 6 yuan. Antennas generally use 256-channel units, and the cost of the driver unit alone reaches over 1500 yuan, further increasing system cost and power consumption.

[0006] The power supply and bias networks are complex, resulting in high power consumption and cost. Each unit requires independent, stable, and low-noise DC bias voltage and current, necessitating multiple high-precision power supplies, LDOs, DC-DC converters, filtering, and voltage regulation circuits. In particular, a high-current negative voltage network is required, necessitating complex power management and heat dissipation designs, significantly increasing system cost and size.

[0007] Therefore, how to provide a drive control solution with a minimal hardware architecture, high integration, few components, mass production capability, and extremely low cost is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0008] In view of this, the present invention provides a hardware control and drive system based on an extremely low-cost reconfigurable intelligent metasurface phased array. Addressing the core pain points of existing intelligent metasurface phased array drive and control systems, which suffer from high cost and complex architecture, this invention proposes a drive and control scheme with a minimally simplistic hardware architecture, high integration, fewer components, mass production capability, and extremely low cost. While ensuring basic phase modulation accuracy and response speed, it significantly reduces the number of main control chips, drive circuits, and wiring, providing low-cost, highly reliable, and easily deployable technical support for the large-scale commercial application of intelligent metasurfaces.

[0009] To achieve the above objectives, the present invention adopts the following technical solution: A hardware control and drive system based on an extremely low-cost reconfigurable intelligent metasurface phased array includes: an FPGA main control module, a power amplifier module, an RF diode array, and resistors; the RF diode array consists of multiple sets of anti-parallel RF diodes, with the common terminal of each set of RF diodes uniformly connected to the output terminal of the power amplifier module, and the other end of each set of RF diodes independently connected to one I / O port of the FPGA main control module via a resistor; the power amplifier module is a voltage follower structure, with its non-inverting input terminal electrically connected to a fixed 1.65V DC level, and its output terminal directly connected to its own inverting input terminal to form a negative feedback closed loop; the power supply terminal of the power amplifier module is electrically connected to a 5V positive power supply, and its ground terminal is grounded.

[0010] Preferably, the RF diode is a Sub-6GHz band RF diode or a millimeter-wave band RF diode, wherein the on-state voltage drop of the Sub-6GHz band RF diode is 0.85V, and the on-state voltage drop of the millimeter-wave band RF diode is ≤1.33V.

[0011] Preferably, the power amplifier module adopts a complementary push-pull structure, which integrates a pull-up transistor and a pull-down transistor internally; the input terminal of the pull-up transistor is electrically connected to a 5V positive power supply, the input terminal of the pull-down transistor is electrically grounded, and the output terminals of the pull-up transistor and the pull-down transistor are jointly electrically connected to the output terminal of the power amplifier module.

[0012] Preferably, the hardware drive system supplies power to the power amplifier module via a 5V positive power supply.

[0013] As can be seen from the above technical solution, compared with the prior art, the present invention discloses a hardware control and driving system based on an extremely low-cost reconfigurable intelligent metasurface phased array. It employs a simplified architecture that uses a power amplifier module to provide a fixed 1.65V reference level and an FPGA to output 0V / 3.3V levels to control the on / off switching of reverse parallel RF diodes. This eliminates the need for negative voltage power supply chips, dedicated driver chips, and numerous MOSFETs required in traditional solutions, significantly reducing the number of components, simplifying circuit design and PCB routing, and substantially lowering hardware costs. The power amplifier module adopts a complementary push-pull structure containing only pull-up and pull-down transistors, possessing both current-pull and current-sinking capabilities. It can drive multiple RF diodes independently and in parallel, adapting to arbitrary code table changes and being compatible with both Sub-6GHz and millimeter-wave RF diodes, demonstrating strong versatility. The system requires only a single 5V power supply, has no negative voltage-related circuits, and features low power consumption and small size, facilitating the miniaturization design and large-scale array expansion deployment of RIS phased arrays. This provides a low-cost, highly reliable core driving solution for the commercialization of intelligent metasurfaces. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0015] Figure 1 This is a schematic diagram of a traditional MOS transistor driving scheme provided by the present invention; Figure 2 This is a schematic diagram of a conventional MOS transistor antenna array driver provided by the present invention; Figure 3 This is a schematic diagram of a conventional single-pole double-throw switch controlling an antenna array, provided by the present invention. Figure 4 A schematic diagram of the driving circuit using a 1.65V level as a reference point provided by the present invention; Figure 5 This is a schematic diagram of the power amplifier principle provided by the present invention; Figure 6 A schematic diagram of the low-cost driving core circuit provided by the present invention. Detailed Implementation

[0016] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0017] This invention discloses a hardware control and drive system based on an extremely low-cost reconfigurable intelligent metasurface phased array, comprising: an FPGA main control module, a power amplifier module, an RF diode array, and resistors; the RF diode array consists of multiple sets of anti-parallel RF diodes, with the common terminal of each set of RF diodes uniformly connected to the output terminal of the power amplifier module, and the other end of each set of RF diodes independently connected to one I / O port of the FPGA main control module via a resistor; the power amplifier module is a voltage follower structure, with its non-inverting input terminal electrically connected to a fixed 1.65V DC level, and its output terminal directly connected to its own inverting input terminal to form a negative feedback closed loop; the power supply terminal of the power amplifier module is electrically connected to a 5V positive power supply, and its ground terminal is grounded.

[0018] The RF diode switch of the RIS phased array is characterized by its relative voltage magnitude and conduction capability. It uses the midpoint of the voltage level at one end of the diode as a constant reference point, and changes in the voltage at the other end to enable the diode switch to conduct. The control chip has both current sinking and current sourcing capabilities, which can meet the requirements of arbitrary code table changes.

[0019] In one specific embodiment, the RF diode is either a Sub-6GHz band RF diode or a millimeter-wave band RF diode. The forward voltage drop of the Sub-6GHz band RF diode is 0.85V, and the forward voltage drop of the millimeter-wave band RF diode is ≤1.33V. The core component of the RIS intelligent metasurface phased array is the RF diode of the antenna array. The voltage across the diode varies depending on the frequency band. Currently, the forward voltage drop of the RF diode in the Sub-6GHz band is 0.85V, and the forward voltage drop of the diode in the millimeter-wave band is below 1.33V. Therefore, as long as the voltage difference across the diode exceeds 1.33V, it can conduct, meeting the operational requirements.

[0020] In one specific embodiment, the power amplifier module adopts a complementary push-pull structure, which integrates a pull-up transistor and a pull-down transistor internally; the input terminal of the pull-up transistor is electrically connected to a 5V positive power supply, the input terminal of the pull-down transistor is electrically grounded, and the output terminals of the pull-up transistor and the pull-down transistor are electrically connected to the output terminal of the power amplifier module.

[0021] In one specific embodiment, the hardware driver system supplies power to the power amplifier module via a 5V positive power supply.

[0022] like Figure 1As shown, when the FPGA outputs a high or low level, the upper and lower MOSFETs are respectively turned on. When the FPGA outputs a high level, Q1 turns on, outputting +VCC, and D1 turns on. When the FPGA outputs a low level, Q2 turns on, outputting -VCC, and D2 turns on, thus achieving the switching of positive and negative voltages in the array unit. The current value depends on the actual resistance values ​​of resistors R1 and R2 on the series diodes. A VCC greater than 1.33V is sufficient for most requirements. Figure 1 Only the components required for one element are listed. For example, if the antenna has 256 elements, then... Figure 2 .

[0023] As shown in the diagram, the driving circuit of a phased array antenna requires many external components, resulting in high costs. Even if a single-pole double-throw switch were used instead, a chip would still be needed to switch between positive and negative voltages; the only difference would be replacing the MOSFETs corresponding to Q1 and Q2 with numerous digital switches, such as... Figure 3 .

[0024] from Figure 3 This can be seen as a switch chip driver. When the FPGA's I / O output is high, SA is connected to D, meaning +VCC is output to D. When the FPGA's I / O output is low, SB is connected to D, meaning -VCC is output to D, thus achieving the switching of positive and negative voltages in the array cells. Figure 3 Taking four units as an example, a chip has four switches, which increases the cost. These are the traditional driving methods of RIS phased arrays.

[0025] If the drive control method of this invention is adopted, the control of RIS phased arrays will be revolutionary. The specific principle is as follows: Figure 4 As shown.

[0026] Two diodes, D1 and D2, are connected in reverse parallel. One end is connected to a fixed voltage of 1.65V. The RIS phased array RF diodes have two main conduction voltages: 0.85V and 1.33V. Therefore, the voltage difference of 1.65V is sufficient to enable the diodes to conduct. The other end is connected in parallel to the output IO of the FPGA. The IO output has two levels.

[0027] When the FPGA outputs a high level (3.3V), D2 is cut off, and the voltage drop across D1 is 3.3V - 1.65V = 1.65V, which is greater than 0.85V or 1.33V. Therefore, D1 is forward-biased, and current flows from the FPGA's I / O to the 1.65V power supply.

[0028] When the FPGA outputs a low level (0V), D1 is cut off, and the voltage drop across D2 is 1.65V - 0V = 1.65V, which is greater than 0.85V or 1.33V. Therefore, D2 is forward-biased, and current flows from the 1.65V power supply to the FPGA's I / O terminal.

[0029] Figure 4 The principle is based on the relative voltage difference of diodes for conduction. For D1 and D2 to conduct relative to each other, two conditions must be met: FPGA I / O must have the ability to pull current or sink current.

[0030] A 1.65V power supply must have the ability to draw or sink current.

[0031] Both are indispensable. FPGA chips inherently possess the ability to source or sink current in their I / O functions. However, typical 1.65V power supply chips can only provide current, not sink it. One of the core aspects of this invention is to solve the current source / sink problem at 1.65V. The specific implementation principle is as follows: Figure 5 As shown.

[0032] Figure 5 This is a power amplifier, not a power supply. The chip's positive terminal supplies 5V, and its negative terminal supplies 0V, eliminating the need for a separate negative voltage supply chip. The non-inverting input (+IN) is connected to a 1.65V power supply, and the output (V-OUT) is fed back to the inverting input (-IN), forming a voltage follower that is always equal to +IN. This ensures that the power amplifier's output voltage (V-OUT) is always 1.65V. The following is an analysis of its working principle. Figure 6 As shown.

[0033] Analysis 1: When FPGA control 1 outputs a high level, the voltage at the left end of the two resistors is 3.3V, corresponding to a stable voltage at the right end of D1 and D2 of 1.65V. Therefore, diode D1 is forward biased at 1.65V, which is greater than 0.85V or 1.33V, and conducts in the forward direction, while D2 is reverse cut off. The current flows through control 1 into D1, then into V-OUT (V-OUT=1.65V), and finally into the lower NPN transistor inside the U1 chip, which is connected to GND. This demonstrates the current sinking capability of the power amplifier U1 chip.

[0034] When FPGA control 1 outputs a low level, the voltage at the left end of the two resistors is 0V, corresponding to a stable voltage at the right end of D1 and D2 at 1.65V. Therefore, diode D2 is forward biased at 1.65V, which is greater than 0.85V or 1.33V, and conducts in the forward direction. Meanwhile, D1 is reverse-biased and cut off. Current flows from the V-OUT (1.65V) output of chip U1, through the positive terminal of diode D2, through the series resistor, into FPGA control 1, and finally into the FPGA's GND. This demonstrates that the power amplifier U1 chip has the ability to pull current. The above is a complete analysis based on one channel with different control states.

[0035] Analysis 2: When controlling one output to a high level while simultaneously controlling two outputs to a low level, how does chip U1 work? As analyzed in the single-channel analysis, for the high-level output, chip U1's sinking transistor D1 conducts, and for the low-level output, chip U1's pulling transistor D2 conducts. Because each I / O pin of an FPGA can only either source or sink current, it cannot simultaneously satisfy both. Therefore, the voltage level of each FPGA pin is fixed—either 1 or 0. However, the output V-OUT (1.65V) of the power amplifier chip U1 can simultaneously satisfy both source and sink current. The internal structure of the power amplifier is a complementary push-pull structure, containing one pull-up transistor for source current and one pull-down transistor for sink current. These two transistors work alternately or collaboratively under the control of the input signal, thus achieving bidirectional current capability.

[0036] Therefore, one end of the N anti-parallel diodes is connected to the N control I / O pins of the FPGA, which can independently and arbitrarily control 0 or 1 to control the forward and reverse bias of different units. The other end of the N anti-parallel diodes is all connected to the V-OUT output (1.65V) of U1. These N FPGA control I / O pins can arbitrarily change between 0 and 1 states. The current flow into and out of the V-OUT pin of the U1 chip is completely parallel and independent. At the same time, the V-OUT pin is connected to the op-amp -IN to form a negative feedback voltage follower, which always keeps the calibration voltage equal to the +IN input voltage of 1.65V. No matter how the 0 and 1 of the FPGA control pins are arranged, V-OUT always maintains the same voltage of 1.65V as +IN, automatically achieving balance. This is the core point of this invention. At the same time, only one positive voltage of 1.65V is needed, eliminating the need for negative voltage chips and external circuits required by traditional control.

[0037] Compared to traditional RIS phased array drivers, this invention saves a significant amount of peripheral driving circuitry. Taking a 256-unit array as an example, compared to… Figure 2 Each circuit typically requires at least 2-4 MOSFETs or a single-pole double-throw switch. The cost of a single MOSFET is around 3 yuan, and the cost of a single-pole double-throw switch is around 6 yuan. Therefore, the cost of 256 MOSFETs would be 768 yuan, and the cost of 256 switches would be 1536 yuan, not including the required negative power supply design. This patented design saves on these costs and also saves on PCB layout area, enabling the miniaturization of the RIS phased array control board. 256 units is only the size of a standard phased array board. In reality, many such boards need to be assembled. For example, a 5x5 phased array antenna requires 25 antennas with 256 units each. Taking the chip as an example, the cost savings are 38,400 yuan. Therefore, the cost savings of this patent in the field of RIS phased array control are enormous.

[0038] In summary, in RIS metasurface reconfigurable phased array antennas, any scheme that uses operational amplifiers or power supply chips to drive the antenna RF diodes, and utilizes the intermediate level of the control chip as the output reference point of the operational amplifier or power supply, falls within the scope of this patent.

[0039] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. The methods disclosed in the embodiments are described simply because they correspond to the methods disclosed in the embodiments; relevant parts can be found in the method section.

[0040] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A hardware control and drive system based on an extremely low-cost reconfigurable intelligent metasurface phased array, characterized in that, include: The system comprises an FPGA main control module, a power amplifier module, an RF diode array, and resistors. The RF diode array consists of multiple sets of anti-parallel RF diodes. The common terminal of each set of RF diodes is electrically connected to the output terminal of the power amplifier module, and the other end of each set of RF diodes is independently electrically connected to one I / O port of the FPGA main control module via a resistor. The power amplifier module is a voltage follower structure. Its non-inverting input terminal is electrically connected to a fixed DC level of 1.65V, and its output terminal is directly electrically connected to its own inverting input terminal to form a negative feedback closed loop. The power supply terminal of the power amplifier module is electrically connected to a 5V positive power supply, and its ground terminal is electrically grounded.

2. The hardware control and drive system based on an extremely low-cost reconfigurable intelligent metasurface phased array according to claim 1, characterized in that, The radio frequency diode is either a Sub-6GHz band radio frequency diode or a millimeter-wave band radio frequency diode. The forward voltage drop of the Sub-6GHz band radio frequency diode is 0.85V, and the forward voltage drop of the millimeter-wave band radio frequency diode is ≤1.33V.

3. The hardware control and drive system based on an extremely low-cost reconfigurable intelligent metasurface phased array according to claim 1, characterized in that, The power amplifier module adopts a complementary push-pull structure, which integrates pull-up transistors and pull-down transistors. The input terminal of the pull-up transistor is electrically connected to a 5V positive power supply, and the input terminal of the pull-down transistor is electrically grounded. The output terminals of the pull-up transistor and the pull-down transistor are both electrically connected to the output terminal of the power amplifier module.

4. The hardware control and drive system based on an extremely low-cost reconfigurable intelligent metasurface phased array according to claim 1, characterized in that, The hardware driver system supplies power to the power amplifier module via a 5V positive power supply.

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