Voltage drop control circuit for low power ldo regulator

Abstract

The present disclosure relates to voltage drop control circuitry for low power LDO regulators. A voltage regulator provides a regulated voltage from a power supply voltage input to digital circuitry, including an amplifier that compares a reference voltage to the regulated voltage to control the source-gate voltage of an output transistor. A source-gate boost circuit improves the response of the regulator to operations with high current demand. The boost circuit includes a capacitor switchably connected between the power supply voltage and a bias current source or the gate of the output transistor. A phase generator controls two switches with non-overlapping control signals to implement an integrating phase that charges the capacitor voltage above the source-gate voltage of the output transistor and a sharing phase that connects the charged capacitor to the gate of the transistor to boost the source-gate voltage to increase the current sourcing capability during high frequency digital circuit operations. A clock gating circuit enables the phase generator in response to a clock activation to synchronize the boost operation with periods of increased current demand.

Description

Technical Field

[0001] This disclosure relates to a voltage drop control circuit for a low-power low-dropout (LDO) regulator that operates at low supply voltages. Background Technology

[0002] The market for MEMS (Micro-electromechanical System) sensors increasingly demands devices with specific power consumption specifications and wide operating voltage ranges, while maintaining compatibility with standard digital communication protocols at high operating frequencies. This requirement presents challenges for power management design, particularly in voltage regulation.

[0003] Typically, some current MEMS sensors operate with a minimum supply voltage (VDD) of 1.62V and employ standard voltage regulator circuit designs. These designs rely on using high on-chip decoupling capacitors and predetermined bias currents to maintain normal regulator operation. As an example, these methods aim to ensure a total output voltage error of 200mV relative to a typical value of 1.2V (minimum 1V).

[0004] However, these designs become inactive when trying to meet the requirements of newer designs that operate with VDD as low as 1.2V while powering digital logic at a typical voltage of 1.1V (minimum 1V). Under these conditions, much higher bias current is required to maintain the total output voltage error within 100mV. The problem with existing designs becomes apparent when VDD approaches 1.2V, as digital components are at risk of abnormal power supply voltages due to significant voltage drops during digital communication. Compensating for this limitation requires very high bias current, which conflicts with the goal of minimizing power consumption.

[0005] Therefore, further development is needed. Summary of the Invention

[0006] An apparatus includes a voltage regulator having an input coupled to receive a power supply voltage and an output configured to provide a regulated voltage to digital circuitry. The voltage regulator includes: an amplifier having a first input coupled to receive a reference voltage and a second input coupled to an output; a transistor having a first conductive terminal coupled to the power supply voltage, a second conductive terminal coupled to the output, and a control terminal coupled to the output of the amplifier; a capacitor coupled between the power supply voltage and a first node; a first switch coupled between the first node and a bias current source; a second switch coupled between the first node and the control terminal of the transistor; and a non-overlapping phase generator configured to generate non-overlapping first and second control signals to control the first and second switches, respectively. During an integration phase controlled by the first control signal, the first switch closes to charge the capacitor using a voltage higher than the voltage from the conductive terminal to the control terminal of the transistor. During the sharing phase, controlled by the second control signal, the second switch closes to couple the charged capacitor to the control terminal of the transistor to boost the voltage between its conduction terminal and the control terminal, thereby improving the current sourcing capability during high-frequency operation of the digital circuit. The duration of the integrating phase is independent of the operating frequency of the digital interface clock signal. The device also features a clock gating circuit configured to enable the non-overlapping phase generator and synchronize the integrating and sharing phases with the current demand from the digital circuit. The clock gating circuit can enable the non-overlapping phase generator in response to activation of the digital interface clock signal or when the application clock causes a large current demand.

[0007] The device may include: a boost stop circuit configured to monitor a regulated voltage and disable the clock gating circuit when the regulated voltage exceeds the maximum operating voltage of the digital circuit. The boost stop circuit may include: a voltage divider coupled to the output to generate a divided voltage; a comparator configured to compare the divided voltage with a reference voltage representing the maximum operating voltage; and logic circuitry coupled to the output of the comparator to generate a boost stop signal for disabling the clock gating circuit.

[0008] The device may include: a counter, clocked by a digital interface clock signal; and detection logic coupled to the output of the counter to generate a timing control signal. The counter may be implemented as a Gray code counter, configured to minimize switching noise during counting transitions by ensuring that only one bit changes at a time during the counting transition. The detection logic may include: a first parallel detection path and a second parallel detection path monitoring the output of the Gray code counter, each detection path including an AND gate and a flip-flop to generate a corresponding step signal; and a combination gate configured to combine the step signal with a boost stop signal to generate an enable signal for the clock gating circuitry.

[0009] A method for regulating a voltage supplied to a digital circuit includes: receiving a power supply voltage at an input of a voltage regulator; comparing a reference voltage with an output voltage of the voltage regulator using an amplifier; controlling a transistor coupled between the power supply voltage and the output based on the comparison; closing a first switch during an integral phase based on a first control signal to charge a capacitor with a voltage higher than the conduction-to-control-terminal voltage of the transistor, and closing a second switch during a shared phase based on a second control signal to couple the charged capacitor to the control terminal of the transistor to boost its conduction-to-control-terminal voltage, wherein the first and second control signals are non-overlapping signals generated by a non-overlapping phase generator and maintained for a given dead time between their active periods; and enabling the non-overlapping phase generator using a clock gating circuit. The non-overlapping phase generator can be enabled based on activation of a digital interface clock signal.

[0010] The method may include: comparing an regulated voltage with the maximum operating voltage of the digital circuit; and disabling the clock gating circuit when the regulated voltage exceeds the maximum operating voltage. The method may include: monitoring the counter output of a counter clocked from a digital interface clock signal; generating a first step signal and a second step signal based on the counter output using a parallel detection path; and combining the first step signal and the second step signal with a boost stop signal to generate an enable signal for the clock gating circuit. The counter may be implemented as a Gray code counter configured to minimize switching noise during counting transitions by ensuring that only one bit changes at a time during counting transitions. The method includes: maintaining the conduction-to-control terminal voltage of the transistor at a static value during static operation; and adjusting the conduction-to-control terminal voltage towards a target value corresponding to the increased load current during the shared phase during high-frequency operation of the digital circuit. The method also includes synchronizing the integrating phase and the shared phase with current demands from the digital circuit. Attached Figure Description

[0011] Figure 1AThis is a block diagram showing a MEMS sensor system with voltage regulators that supply power to analog and digital circuit sections.

[0012] Figure 1B This is a schematic diagram illustrating the detailed structure of a voltage regulator with gate boost capability and timing signal, which can be used to drive... Figure 1A The digital circuit section of the MEMS sensor system.

[0013] Figure 2 It is in operation Figures 1A to 1B Timing diagrams of various signals from a MEMS sensor system.

[0014] Figure 3 It shows the prevention Figures 1A to 1B A schematic diagram of a boost stop signal generator circuit where the regulator output voltage exceeds the maximum operating voltage.

[0015] Figure 4 This describes the use of Gray code counters to implement [something] during SPI (Serial Peripheral Interface) communication. Figures 1A to 1B A schematic diagram of the timing control circuit for a voltage regulator. Detailed Implementation

[0016] The following disclosure enables those skilled in the art to make and use the subject matter described herein. The general principles outlined in this disclosure can be applied to embodiments and applications other than those detailed above without departing from the spirit and scope of this disclosure. This disclosure is not intended to be limited to the embodiments shown, but rather to have the widest scope consistent with the principles and features disclosed or suggested herein.

[0017] Note that in the following description, unless otherwise stated, any resistor or resistor mentioned is a discrete device and not merely an electrical lead between two points. Therefore, any resistor or resistor connected between two points has a higher resistance than a lead between those two points, and such a resistor or resistor cannot be interpreted as a lead. Similarly, unless otherwise stated, any capacitor or capacitor mentioned is a discrete device and not a parasitic element.

[0018] Now for reference Figure 1A The MEMS sensor system 10 includes a bandgap reference circuit 20 that provides a reference voltage Vbg to voltage regulators 30 and 50. Voltage regulator 30 supplies power to analog circuit section 40, while voltage regulator 50 supplies power to digital circuit section 60. Voltage regulator 50 is biased by a bias current Ibias and has a decoupling capacitor Cdec connected between its output and ground.

[0019] When digital circuit section 60 operates at high frequencies, it requires a large current. While the decoupling capacitor Cdec helps stabilize the output voltage during rapid load current changes, and the bias current Ibias establishes a stable operating point to prevent problems when operating with reduced voltage headroom (such as when the supply voltage VDD is 1.2V and the regulator 50 is to provide a regulated output of 1.1V to digital circuit section 60), the voltage regulator 50 disclosed herein has been developed.

[0020] Specifically, such as Figure 1B As shown in the circuit diagram, voltage regulator 50 includes a first-stage amplifier 51, which is powered between VDD and ground and biased by a bias current IB1. The inverting input terminal of amplifier 51 is coupled to receive a bandgap voltage Vbg from bandgap reference circuit 20, and the non-inverting input terminal of amplifier 51 is fed back to the output node OUT_VREG. The source of p-channel transistor MP1 is coupled to VDD, its drain is connected to the output node OUT_VREG, and its gate is connected to receive the gate drive voltage GATEP generated at the output of amplifier 51. The drain of n-channel transistor MN2 is connected to the output node OUT_VREG, its source is coupled to ground, and its gate is connected to the gate of n-channel transistor MN1 to receive the gate drive voltage GATEN generated thereon. The drain and gate of n-channel transistor MN1 are connected, its drain receives a bias current IB2, and its source is coupled to ground. MN1 and MN2 form a current mirror, which is configured to apply a fixed sink current equal to IB2 to the output node OUT_VREG.

[0021] The drain of n-channel transistor MN3 receives bias current IB3 and is connected to its gate, while its source is coupled to ground. The drain of n-channel transistor MN4 is connected to the first terminal of switch S1, its source is coupled to ground, and its gate is connected to the gate of n-channel transistor MN3. MN3 and MN4 form a current mirror that mirrors current IB3 when switch S1 is high, causing it to sink from node Ncap.

[0022] The second terminal of switch S1 is connected to node Ncap. Capacitor C is connected between VDD and node Ncap, and the second switch S2 is connected between node Ncap and the gate of p-channel transistor MP1. Switch S1 is controlled by a signal. Controlled by int, switch S2 is controlled by a signal. sh control. Miller capacitor Cm is connected between the gate of p-channel transistor MP1 and node OUT_VREG. Decoupling capacitor Cdec is connected between node OUT_VREG and ground. Load current Iload drawn by digital circuit segment 60 is drawn from node OUT_VREG.

[0023] The clock gating circuit 55 has: a clock input, coupled to receive the clock signal CLK (also referred to herein as SPC); an enable input, coupled to receive the enable signal EN; and an output, connected to the input of inverter 56. The output of inverter 56 generates a signal. ,Signal The signal is connected to the input of the non-overlapping phase generator 57, which outputs a non-overlapping signal. sh and signal int.

[0024] The operation of voltage regulator 50 will now be described. During normal operation, when digital circuit segment 60 is not actively communicating via its interface (e.g., SPI communication), the load current Iload is relatively small. Amplifier 51 maintains the output voltage at the desired regulation level by comparing the output voltage at node OUT_VREG with the bandgap reference voltage Vbg and adjusting the gate voltage of p-channel transistor MP1 accordingly.

[0025] When digital circuit segment 60 initiates interface communication (such as SPI data transmission at high frequencies, e.g., 10MHz), the load current Iload increases significantly. This sudden increase in current demand may cause a voltage drop at node OUT_VREG due to the limited bandwidth of regulator 50, which is proportional to the ratio of bias current IB1 to Miller capacitor Cm when the input-pair transistor of 51 is operating in the subthreshold region.

[0026] The source-gate voltage VSG of MP1 is directly dependent on the requested output current, where ILOAD_TARGET corresponds to VSG_TARGET. During static operation, when digital circuitry segment 60 does not require current (e.g., Iload = 0), VSG is maintained at the value VSG_QUIESCENT. However, when the SPI clock is active, digital circuitry segment 60 requires ILOAD_TARGET, therefore VSG must be adjusted to VSG_TARGET.

[0027] To compensate for this voltage drop without increasing the bias current IB1 and the capacitance of the decoupling capacitor Cdec, the voltage regulator 50 implements a source-gate boost circuit. This boost circuit includes a capacitor C, switches S1 and S2, current mirrors MN3-MN4, and a signal... sh and int is used to control the non-overlapping phase generator 57 of these switches.

[0028] When enabled, clock gating circuit 55 provides a gated clock signal to non-overlapping phase generator 57 via inverter 56. Non-overlapping phase generator 57 generates two non-overlapping phase signals. sh and int.

[0029] When the SPI clock is off, capacitor C operates in parallel with capacitor Cgs of MP1 (where... (sh is kept high) to store VSG_QUIESCENT. When the SPI clock is on, the circuit operates in two phases (i.e., the integrating phase and the shared phase).

[0030] During the integral phase, when int activity (logical high) and When sh is inactive (logic low), switch S1 is closed and switch S2 is open.

[0031] During the integral phase, the voltage VCAP at node Ncap follows equation VCAP. i = VSG i-1 + (IB3 / C)×ΔT (i>0) (for i = 0, VCAP0= VSG0= VSG_QUIESCENT), where:

[0032] VSG is the source-gate voltage of MP1, IB3 is the bias current through transistors MN3 / MN4, C is the value of the boost capacitor, and ΔT is a fixed integral time period controlled by the non-overlapping phase generator (ΔT is...). (int remains high for a duration during each clock cycle).

[0033] When the digital circuit segment is active, this integration occurs periodically in each clock cycle, thereby ensuring that VCAP remains at an appropriate voltage level above VSG to compensate for the increased current demand.

[0034] In the following During the sh sharing period, sh becomes active. int becomes inactive. Switch S1 opens and switch S2 closes, thus connecting capacitor C in parallel with the capacitance Cgs of MP1. This connection allows the VSG MOS driver to rapidly adjust towards VSG_TARGET, temporarily increasing the current source capability of MP1 to respond more quickly to increased load current demands, even with potential bandwidth limitations of regulator 50. The alternating operation of S1 and S2 creates a charge pump effect, continuously refreshing the boosted source-gate voltage to accelerate the regulator's response during high-load periods requiring enhanced current source capability.

[0035] The duration ΔT of the integral phase is independent of the digital interface operating frequency, thus allowing consistent compensation regardless of the interface clock speed.

[0036] By implementing this source-gate boost technique, the voltage regulator 50 can maintain its output voltage during high-frequency digital interface operation while maintaining low quiescent current operation with relatively small bias currents Ib1, Ib2, and Ib3.

[0037] The non-overlapping phase generator 57 ensures the signal int and The phase signals do not overlap, thus preventing a direct connection between the integral phase operation and the shared phase operation. During operation, when EN is active, the clock gating circuit 55 passes the clock signal to the inverter 56, which provides the edge for the non-overlapping phase generator 57. The non-overlapping phase generator 57 then generates two phase signals. int and sh, with a guaranteed dead time between their active periods. Non-overlapping phases ensure that capacitor C is never simultaneously connected to both MP1 (via S2) and MN4 (via S1), because S1 and S2 operate in a mutually exclusive manner. During the int period, C is connected to MN4 for charging, while During sh, C is connected to the gate of MP1 for boosting, with a guaranteed dead time between these connections.

[0038] The switching system implements a precise timing relationship between the interface operating frequency (e.g., the SPI clock frequency) and the capacitor refresh cycle, thereby enabling the voltage adjustment on the gate of MP1 to be synchronized with the current demand from the digital circuit segment 60.

[0039] Figure 2The timing diagram illustrates the relationship between these signals during an example SPI read operation. When CS goes active (goes low) to initiate a digital interface operation, this triggers several responses in the system. The boost operation is inherently synchronized with the current demand of the digital interface because the clock gating circuit 55 receives the same clock signal (SPC) that drives the digital interface operation. This ensures that the boost directly responds to and is synchronized with the active period of the interface and its corresponding current demand. The EN signal, derived from the chip select (CS) signal of the interface, ensures that the boost operation only occurs when the interface is actually requesting current. When these conditions are met, SDI begins receiving serial data (from MSB IN (most significant bit input) to LSB OUT (least significant bit output)), and then SDO sends serial data synchronized with the SPC clock (from MSB OUT (most significant bit output) to LSB OUT). The EN signal is activated in response to CS going low, which allows the clock gating circuit 55 to begin transmitting the SPC clock.

[0040] The PHI from inverter 56 drives non-overlapping phase generator 57, which generates... int and sh. The non-overlapping phase generator 57 generates a pulse width ΔT independent of the SPC clock frequency. This ensures consistent charging of capacitor C regardless of the digital interface operating speed. These are non-overlapping phase control switches S1 and S2.

[0041] The Gray code counter states shown in the timing diagram coordinate these operations. During communication, the VCAP voltage transitions from its initial VSG_QUIESCENT level through multiple boost operations. Each boost cycle increases VCAP during the integration phase and then stabilizes towards VSG_TARGET during the shared phase. Once communication ends, VCAP returns to the VSG_QUIESCENT level.

[0042] exist After the int returns to low and the dead time has elapsed to prevent shoot-through current paths, sh becomes active to connect the charged capacitor to the gate of MP1. int transformation and The dead time between sh transitions is crucial to preventing any direct path between the charging circuit and the PMOS gate node, which could otherwise lead to voltage spikes or operational instability.

[0043] The non-overlapping phase generator 57 can be implemented using conventional logic gates and delay elements to ensure int and The correct timing relationship between sh. For example, cross-coupled NAND gates with delay chains can be used to generate non-overlapping characteristics, while single-trigger circuits can be used for... int establishes a fixed ΔT pulse width.

[0044] This implementation enables the boost circuit to operate robustly while maintaining low power consumption through careful timing control of the charge transfer process.

[0045] Now for reference Figure 3 The voltage regulator 50 may also include a BOOST_STOP signal generator circuit 60, which is used to prevent the regulator output voltage from exceeding the maximum operating voltage of the digital logic, which is of particular interest during multiple communication burst scenarios. Circuit 60 includes a comparator 61 powered between VDD and ground, followed by two inverters 62 and 63 at its output.

[0046] Comparator 61 monitors OUT_VREG via a voltage divider network formed by resistors R1 and R2. The voltage divider generates a scaled version of OUT_VREG according to the following equation: VSENSE = R2 / (R1+R2) × OUT_VREG

[0047] When OUT_VREG exceeds OUT_VREG_MAX, the comparator output changes, and after passing through inverters 62 and 63, a logic high BOOST_STOP signal is generated. This BOOST_STOP signal is provided to the clock gating circuit 55 (e.g., when asserted) Figure 1B As shown, this disables the clock signal to the non-overlapping phase generator 57, effectively stopping the boost capacitor switching operation. By interrupting the boost capacitor charging and shared phase, the BOOST_STOP signal here (when asserted) is used to prevent further voltage increases at the regulator output.

[0048] Now for reference Figure 4The diagram illustrates a control circuit 70, which can be used to implement timing control of a voltage regulator during SPI communication. The control circuit 70 utilizes a Gray code counter 73 instead of a conventional binary counter to minimize switching noise and glitches during counting transitions, as Gray code ensures that only one bit changes at a time with each count increment. This is particularly important in sensitive analog circuits where switching noise can affect the regulated output voltage. The Gray code counter and its outputs QA-QD and their inverted versions QAN-QDN can provide a series of states to achieve precise timing control of boost operation. While a Gray code counter is utilized in this embodiment due to its advantages in minimizing switching noise, other suitable counting schemes can be implemented with appropriate consideration for noise management and glitch prevention in sensitive analog circuit environments.

[0049] The counter is clocked by the CLK signal and has a clear input controlled by the CLEAR_DATA signal, which is generated by combining the power-on reset signal and the chip select signal (in the case of SPI communication) via inverter 71 and AND gate 72.

[0050] Two parallel detection paths monitor the counter output to generate control signals STEP1 and STEP2. The first path includes an AND gate 78 that receives QAN, QBN, QCN, and QD as inputs and provides the output via an OR gate 79 and a flip-flop 80. Similarly, the second path uses an AND gate 81 that receives QA, QBN, QCN, and QDN as inputs and provides the output via an OR gate 82 and a flip-flop 83. Both flip-flops 80 and 83 are clocked by CLKN (e.g., an inverted version of CLK) and can be reset by the CLEAR_DATA signal.

[0051] The STEP1 and STEP2 signals, along with the BOOST_STOP signal, are received by AND gate 84 to generate an enable signal EN for clock gating circuit 55. Then, as described above, clock gating circuit 55 generates phi via inverter 56. Signal.

[0052] Specifically, this implementation is designed for SPI interface operation, although the design is also suitable for other serial interfaces (such as I2C or I3C) and any other application requiring the management of high current demands (such as an onboard microprocessor). Gray code counter 73 and detection logic enable proper timing of boost operation synchronized with clock CLK, while maintaining the ability to disable boost functionality via the BOOST_STOP signal as described above.

[0053] Finally, it is obvious that modifications and changes can be made to the content described and explained herein without departing from the scope of this disclosure.

[0054] Although this disclosure has been described using a limited number of embodiments, those skilled in the art who benefit from it will envision other embodiments without departing from the scope of the disclosure. Furthermore, those skilled in the art will envision embodiments that represent various combinations of the embodiments disclosed herein in various ways.

Claims

1. A device including a voltage regulator having an input coupled to receive a power supply voltage and an output configured to provide a regulated voltage to digital circuitry, the voltage regulator comprising: An amplifier having a first input terminal coupled to receive a reference voltage and a second input terminal coupled to the output terminal; A transistor having a first conductive terminal coupled to the power supply voltage, a second conductive terminal coupled to the output terminal, and a control terminal coupled to the output terminal of the amplifier; A capacitor is coupled between the power supply voltage and the first node; The first switch is coupled between the first node and the bias current source; A second switch is coupled between the first node and the control terminal of the transistor; A non-overlapping phase generator is configured to generate a first non-overlapping control signal and a second non-overlapping control signal to control the first switch and the second switch, respectively, wherein: During the integral phase controlled by the first control signal, the first switch closes to charge the capacitor using a voltage higher than the voltage from the conduction terminal to the control terminal of the transistor, and During the shared phase controlled by the second control signal, the second switch closes to couple the charged capacitor to the control terminal of the transistor to adjust its control terminal voltage, thereby improving the current source capability during high-frequency operation of the digital circuit. as well as A clock-gated circuit is configured to enable the non-overlapping phase generator.

2. The device of claim 1, wherein during the shared phase, the charged capacitor is coupled to the control terminal of the transistor to boost the source-gate voltage of the transistor to a value higher than its static value.

3. The device of claim 1, wherein the clock gating circuit enables the non-overlapping phase generator in response to activation of the digital interface clock signal.

4. The device of claim 1, wherein the clock gating circuit enables the non-overlapping phase generator when the application clock causes a large current demand.

5. The device according to claim 1, further comprising: A boost stop circuit is configured to monitor the regulated voltage and disable the clock gating circuit when the regulated voltage exceeds the maximum operating voltage of the digital circuit.

6. The device according to claim 5, wherein the boost stop circuit comprises: A voltage divider is coupled to the output terminal to generate a voltage divider. A comparator is configured to compare the divided voltage with a reference voltage representing the maximum operating voltage; as well as A logic circuit device is coupled to the output of the comparator to generate a boost stop signal for disabling the clock gating circuit.

7. The device according to claim 1, further comprising: The code counter is clocked by a digital interface clock signal. as well as The detection logic is coupled to the output of the counter to generate a timing control signal; The counter is configured to minimize switching noise during count transitions.

8. The device of claim 7, wherein the counter is a Gray code counter configured to minimize switching noise during a counting transition by ensuring that only one bit changes at a time during the counting transition.

9. The device according to claim 8, wherein the detection logic includes: A first parallel detection path and a second parallel detection path monitor the output of the Gray code counter. Each detection path includes an AND gate and a flip-flop to generate a corresponding step signal. as well as A combination gate is configured to combine the step signal with the boost stop signal to generate an enable signal for the clock gating circuit.

10. The device of claim 1, wherein the transistor is a p-channel transistor, the first conductive terminal of the transistor is the source, the second conductive terminal of the transistor is the drain, and the control terminal of the transistor is the gate, the voltage from the conductive terminal to the control terminal is the source-gate voltage of the p-channel transistor, and the control terminal voltage is the gate voltage.

11. The device according to claim 10, wherein: During static operation, when the digital circuit does not require current, the voltage from the conduction terminal to the control terminal of the transistor is maintained at a static value. and During high-frequency operation of the digital circuit, the shared phase provides a rapid adjustment of the voltage from the conduction terminal to the control terminal toward a target value corresponding to the increased load current.

12. The device according to claim 1, wherein: The digital interface clock signal is the Serial Peripheral Interface (SPI) clock signal; and The non-overlapping phase generator is configured to generate the first control signal and the second control signal, with a guaranteed dead time between the active periods of the first control signal and the second control signal to prevent direct connection between the integral phase and the shared phase.

13. The device according to claim 1, wherein: The duration of the integral phase is independent of the operating frequency of the digital interface clock signal; and The clock gating circuit is configured to synchronize the integrating phase and the shared phase with the current demand from the digital circuit.

14. A method for regulating the voltage supplied to a digital circuit, comprising: Receives the power supply voltage at the input terminal of the voltage regulator; An amplifier is used to compare the reference voltage with the output voltage of the voltage regulator. The transistor coupled between the power supply voltage and the output terminal is controlled based on the comparison. During the integral phase based on the first control signal, the first switch is closed to charge the capacitor using a voltage higher than the voltage from the conduction terminal to the control terminal of the transistor. During the shared phase based on the second control signal, the second switch is closed to couple the charged capacitor to the control terminal of the transistor to adjust its control terminal voltage, wherein the first control signal and the second control signal are non-overlapping signals generated by the non-overlapping phase generator; and The non-overlapping phase generator is enabled using a clock-gated circuit.

15. The method of claim 14, wherein during the shared phase, the charged capacitor is coupled to a control terminal of the transistor to boost the source-gate voltage of the transistor to a value higher than its static value.

16. The method of claim 14, wherein enabling the non-overlapping phase generator comprises enabling the non-overlapping phase generator based on activation of a digital interface clock signal.

17. The method of claim 14, further comprising: The adjusted voltage is compared with the maximum operating voltage of the digital circuit; as well as The clock gating circuit is disabled when the regulated voltage exceeds the maximum operating voltage.

18. The method of claim 14, further comprising: The counter output of the counter that monitors the clock signal from the digital interface for clock control; The first step signal and the second step signal are generated based on the output of the counter using a parallel detection path. as well as The first step signal and the second step signal are combined with the boost stop signal to generate an enable signal for the clock gating circuit.

19. The method of claim 18, wherein the counter is a Gray code counter configured to minimize switching noise during a counting transition by ensuring that only one bit changes at a time during the counting transition.

20. The method of claim 14, wherein: During static operation, the voltage between the conduction terminals and control terminals of the transistor is maintained at a static value; and During high-frequency operation of the digital circuit, during the shared phase, the voltage from the conduction terminal to the control terminal is adjusted toward a target value corresponding to the increased load current.

21. The method of claim 14, further comprising: A given dead time is maintained between the active period of the first control signal and the active period of the second control signal; as well as The integral phase and the shared phase are synchronized with the current demand from the digital circuit.

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