Reference clock transceiver and multi-die package system

Abstract

The application relates to the technical field of integrated circuits, and provides a reference clock transceiver and a multi-die package system. The reference clock transceiver comprises a multiplexer for gating a reference clock signal in CML logic received outside a multi-die package chip or from other dies; an AC coupling circuit for AC shaping and common-mode voltage shifting; a preamplifier for amplitude amplification and output of a third differential clock signal; a hysteresis comparator for converting the third differential clock signal from CML logic to CMOS logic and outputting to an internal circuit of the die; and a CML buffer for driving capability amplification of the third differential clock signal and output to the next die in cascade. The application can receive an off-chip reference clock and transmit a clock signal in the chip; the differential CML logic transmission has strong anti-interference capability; the integrated CML buffer realizes efficient cascade distribution of clock signals between multiple dies, and packaging pin resources are saved.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to reference clock transceivers and multi-die packaging systems. Background Technology

[0002] With the increasing demands of artificial intelligence for high-bandwidth transmission and large-scale data processing, coupled with the constraints of Moore's Law in semiconductors, traditional monolithic chip design is transitioning to multi-die packaging design. As the core driver of large-scale monolithic system-on-a-chip (SoC), the clock circuit's signal quality directly affects the timing accuracy of various functional modules and the overall performance of the chip. Therefore, in multi-die architectures, how to efficiently and stably transmit clock signals is a key issue that requires careful attention.

[0003] Currently, the commonly used clocking scheme for large-scale monolithic systems is to introduce a high-quality external reference clock through a reference clock receiver, and then synthesize the desired target frequency through a frequency synthesizer. However, when this scheme is directly applied to multi-die systems, it has the following shortcomings: 1. Increased pin usage and cost: If each die is equipped with an independent external crystal oscillator and internal circuitry, it will occupy more pin resources and increase hardware costs.

[0004] 2. High power consumption and susceptibility to interference in long-distance transmission: When using single-ended CMOS (Complementary Metal-Oxide-Semiconductor) level for long-distance transmission, the power consumption is relatively high and the anti-interference ability is weak, making it difficult to ensure signal integrity.

[0005] 3. Insufficient flexibility: Traditional solutions can usually only transmit a reference clock at a fixed frequency, making it difficult to adapt to the diverse clock requirements of multi-die systems. Summary of the Invention

[0006] This application provides a reference clock transceiver and a multi-die package system, which enables high-quality, high-interference-resistant clock signal distribution and transmission across dies with fewer package pin resources in the multi-die package system.

[0007] This application provides a reference clock transceiver disposed within a die in a multi-die package system. The reference clock transceiver includes: a multiplexer, with a first input terminal for receiving a first reference clock signal from outside the multi-die package chip, and a second input terminal for receiving second reference clock signals from other dies in the multi-die package system; the multiplexer outputs a first differential clock signal; wherein the first and second reference clock signals employ CML logic; an AC coupling circuit connected to the output terminal of the multiplexer for AC shaping and common-mode voltage shifting of the first differential clock signal to output a second differential clock signal; a preamplifier connected to the output terminal of the AC coupling circuit for amplifying the amplitude of the second differential clock signal to output an amplified third differential clock signal; a hysteresis comparator connected to the output terminal of the preamplifier for converting the third differential clock signal from CML logic to CMOS logic and outputting a first output clock signal after conversion logic to the internal circuitry of the die; and a CML buffer connected to the output terminal of the preamplifier for amplifying the drive capability of the third differential clock signal to obtain a second output clock signal for transmission to the next cascaded die.

[0008] According to the reference clock transceiver provided in this application, it further includes: an electrostatic discharge protection circuit, disposed at the input front end of the multiplexer, for providing an electrostatic current discharge path for the input reference clock signal.

[0009] According to the reference clock transceiver provided in this application, the electrostatic discharge protection circuit includes a two-stage electrostatic discharge network. The first-stage electrostatic discharge network is a diode discharge circuit, and the second-stage electrostatic discharge network is a discharge circuit combining a resistor and a diode.

[0010] According to the reference clock transceiver provided in this application, the multiplexer is composed of multiple transmission gate devices coupled in parallel; the transmission gate devices are composed of N-type field-effect transistors and P-type field-effect transistors connected in parallel, and the width-to-length ratio of the N-type field-effect transistors and P-type field-effect transistors is greater than a preset threshold, so as to reduce the on-resistance and suppress the transmission loss of the clock signal.

[0011] According to a reference clock transceiver provided in this application, the AC coupling circuit outputs a second differential clock signal at a preset static operating point; the preamplifier includes a load resistor; the peak-to-peak amplitude of the third differential clock signal is the product of the resistance value of the load resistor and the current value corresponding to the preset static operating point.

[0012] This application also provides a multi-die packaging system, including a packaging substrate, a silicon dielectric interlayer, and a plurality of dies disposed on the silicon dielectric interlayer; the plurality of dies communicate with each other through metal traces inside the silicon dielectric interlayer; at least one of the plurality of dies is provided with the aforementioned reference clock transceiver.

[0013] According to the multi-die packaging system provided in this application, the multi-die packaging system adopts a serial single clock source architecture; the multi-die packaging system receives a single external clock source signal through two external pins as the first reference clock signal of the first die; the second output clock signal output by the CML buffer of the first die is transmitted to the multiplexer of the next die as the second reference clock signal through metal traces, and is sequentially transmitted in series to multiple dies in the multi-die packaging system.

[0014] According to the present application, a multi-die packaging system is provided, which adopts a serial multi-clock source architecture. The multi-die packaging system receives multiple external clock source signals through multiple sets of external pins. The first set of cascaded dies shares the first external clock source signal, and the second set of cascaded dies shares the second external clock source signal, so as to provide different reference clocks for dies with different application requirements in the multi-die packaging system.

[0015] According to the present application, a multi-die packaging system is provided, which adopts a parallel single clock source architecture. The multi-die packaging system receives a single external clock source signal through two external pins as the first reference clock signal for multiple dies. The multiple dies in the multi-die packaging system are connected in parallel based on the first reference clock signal.

[0016] According to the present application, a multi-die packaging system is provided, which adopts a parallel multi-clock source architecture. The multi-die packaging system receives multiple external clock source signals through multiple sets of external pins. The first set of dies is connected in parallel based on the first external clock source signal, and the second set of dies is connected in parallel based on the second external clock source signal, so as to provide different reference clocks for dies with different application requirements in the multi-die packaging system.

[0017] The reference clock transceiver and multi-die package system provided in this application include: a multiplexer for selecting and receiving a first reference clock signal from outside the multi-die package chip or a second reference clock signal from other dies, and outputting a first differential clock signal, wherein both the first and second reference clock signals adopt CML logic; an AC coupling circuit for AC shaping and common-mode voltage shifting of the first differential clock signal, and outputting a second differential clock signal; a preamplifier for amplifying the amplitude of the second differential clock signal, and outputting a third differential clock signal; a hysteresis comparator for converting the third differential clock signal from CML logic to CMOS logic, and outputting a first output clock signal to the internal circuitry of the die; and a CML buffer for amplifying the drive capability of the third differential clock signal to obtain a second output clock signal for transmission to the next cascaded die. Through the above methods, this application can receive external reference clocks and transmit clock signals on-chip; it adopts differential CML logic transmission, which has strong anti-interference ability, and achieves efficient cascading distribution of clock signals between multiple bare dies by integrating CML buffers, saving package pin resources. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of an on-chip integrated oscillation circuit provided by related technologies.

[0020] Figure 2 This is a schematic diagram of a clock signal with a stable amplitude output using an on-chip integrated oscillation circuit in related technologies.

[0021] Figure 3 This is one of the structural schematic diagrams of the reference clock transceiver provided in the embodiments of this application.

[0022] Figure 4 This is the second schematic diagram of the reference clock transceiver provided in the embodiments of this application.

[0023] Figure 5 This is a schematic diagram of the electrostatic discharge protection circuit provided in the embodiments of this application.

[0024] Figure 6 This is a schematic diagram of the structure of the multiplexer provided in the embodiments of this application.

[0025] Figure 7This is a schematic diagram of the structure of the AC coupling circuit provided in the embodiment of this application.

[0026] Figure 8 This is a schematic diagram of the signal processing of the AC coupling circuit provided in the embodiments of this application.

[0027] Figure 9 This is a schematic diagram of the preamplifier provided in the embodiments of this application.

[0028] Figure 10 This is a schematic diagram of preamplifier signal processing provided in an embodiment of this application.

[0029] Figure 11 This is a schematic diagram of the hysteresis comparator provided in the embodiments of this application.

[0030] Figure 12 This is a schematic diagram of the structure of the CML buffer provided in the embodiments of this application.

[0031] Figure 13 This is a schematic diagram of the structure of a multi-die packaging system provided by related technologies.

[0032] Figure 14 This is one of the structural schematic diagrams of the multi-die packaging system provided in the embodiments of this application.

[0033] Figure 15 This is the second schematic diagram of the structure of the multi-die packaging system provided in the embodiments of this application.

[0034] Figure 16 This is the third schematic diagram of the structure of the multi-die packaging system provided in the embodiments of this application.

[0035] Figure 17 This is a schematic diagram of the serial single-clock source architecture provided in the embodiments of this application.

[0036] Figure 18 This is a schematic diagram of the serial multi-clock source architecture provided in the embodiments of this application.

[0037] Figure 19 This is a schematic diagram of the parallel single clock source architecture provided in the embodiments of this application.

[0038] Figure 20 This is a schematic diagram of the parallel multi-clock source architecture provided in the embodiments of this application. Detailed Implementation

[0039] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0040] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the embodiments of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0041] In relevant single-die package solutions, a reference clock is typically provided using an off-chip quartz crystal oscillator (i.e., a quartz crystal) in conjunction with an on-chip oscillation circuit. Please refer to [link to relevant documentation]. Figures 1-2 , Figure 1 This is a schematic diagram of an on-chip integrated oscillation circuit provided by related technologies. Figure 2 This is a schematic diagram of a clock signal with a stable amplitude output using an on-chip integrated oscillation circuit in related technologies.

[0042] like Figure 1 As shown, the on-chip oscillation circuit consists of an inverting amplifier and a feedback resistor. Its main function is to amplify its own noise signal, continuously increasing the amplitude of this signal with each positive cycle until a stable clock signal is output. Figure 2 As shown, the clock signal includes an oscillation phase and a stabilization phase.

[0043] However, the above solution has the following problems when applied to multi-die packaging systems: 1. In the above crystal oscillator scheme, each die needs to be independently configured with an external quartz crystal oscillator and an internal oscillation circuit, and occupies two package pins for connecting the crystal oscillator (e.g., Figure 1 (osc_in and osc_out in the code). In a package system containing N dies, a total of N quartz crystal oscillators, N sets of oscillation circuits, and 2N package pins are required, which is unacceptable in advanced packages where package area and cost are limited.

[0044] 2. The reference clock signal for single-ended CMOS level logic transmission has relatively high power consumption and poor anti-interference capability in long-distance channel transmission.

[0045] 3. The reference clock frequency is determined by the inherent resonant frequency of the external quartz crystal oscillator, and each die can only obtain a reference clock of a fixed frequency. It can only transmit a reference clock of a fixed frequency, resulting in relatively poor flexibility.

[0046] To address the aforementioned issues, this application proposes a reference clock transceiver, which is located within each die. This transceiver not only receives external clock signals or clock signals transmitted from other dies, but also forwards clock signals to the next cascaded die. This application enables flexible cascaded transmission of reference clock signals among multiple dies, reduces the number of external pins, and supports various clock distribution topologies such as series and parallel connections.

[0047] To facilitate understanding of the various embodiments of this application, several terms involved in this application will be explained first.

[0048] A multi-die package system refers to a system architecture that integrates multiple semiconductor dies within a single package. The dies communicate electrically with each other via a silicon interposer, package substrate, or other interconnection methods. This packaging approach allows for the integration of more functional modules within a limited package area, thereby improving system performance and integration density.

[0049] A die is an independent functional unit cut from a semiconductor wafer. In a multi-die packaging system, each die can perform different functions, such as a processor core, memory controller, or input / output interface.

[0050] Current-mode logic (CML) is a high-speed differential signal transmission standard. CML signals are transmitted differentially, featuring low voltage swing (typically 400mV to 800mV peak-to-peak) and low noise, making them suitable for transmitting high-frequency reference clock signals. CML signals typically swing differentially around a common common-mode voltage.

[0051] Complementary Metal-Oxide-Semiconductor (CMOS) logic is the logic standard used in on-die digital circuits, and its signal swing is typically the full swing of the power supply voltage (e.g., 0V to 0.8V).

[0052] A multiplexer is a selector circuit that selects one output from multiple input signals based on a control signal. In this application, the multiplexer is used to select a reference clock signal from an external die or another die.

[0053] An AC coupling circuit is a signal processing circuit that utilizes the DC-blocking and AC-passing characteristics of a capacitor to remove the DC bias component of the input signal, retaining only the AC signal component, and shifting the AC signal to the desired common-mode voltage. AC coupling circuits can eliminate common-mode voltage mismatch problems caused by process variations or power supply voltage differences between different dies.

[0054] A preamplifier is a small-signal amplifier circuit used to initially amplify differential signals with small amplitudes after AC coupling, so that they reach the level range that subsequent circuits (such as hysteresis comparators) can correctly distinguish.

[0055] A hysteresis comparator is a comparator circuit with positive feedback, exhibiting a hysteresis loop in its input-output characteristics. Compared to ordinary comparators, hysteresis comparators have stronger noise immunity to input signals, preventing multiple output signal jumps caused by noise near the zero-crossing point of the input signal, thus producing a clean CMOS logic level output.

[0056] A CML buffer is a signal drive enhancement circuit used to enhance the driving capability of a signal, enabling it to drive longer transmission lines or larger load capacitances. In this application, the CML buffer is used to enhance the CML differential clock signal before transmitting it to the next cascaded die.

[0057] An electrostatic discharge (ESD) protection circuit is a protective circuit installed at the input of a circuit. It provides a low-impedance current discharge path when an ESD event occurs, directing the transient large current to the power supply or ground, thereby protecting the subsequent internal circuits from ESD breakdown damage.

[0058] A silicon dielectric interlayer is an intermediate interconnect layer based on silicon material. It contains high-density metal traces and silicon vias to enable high-speed signal interconnection between multiple dies and between dies and the package substrate.

[0059] A differential clock signal is a clock signal composed of a pair of complementary signal lines, where the voltage waveforms on the two signal lines have equal amplitudes but opposite polarities. Differential transmission has advantages such as strong immunity to common-mode noise and low electromagnetic interference, making it suitable for transmitting high-quality clock signals.

[0060] Please see Figure 3 , Figure 3 This is one of the structural schematic diagrams of a reference clock transceiver provided in an embodiment of this application. The reference clock transceiver can be disposed within a die in a multi-die package system.

[0061] The reference clock transceiver may include a multiplexer 310, an AC coupling circuit 320, a preamplifier 330, a hysteresis comparator 340, and a CML buffer 350.

[0062] The multiplexer 310 has a first input terminal for receiving a first reference clock signal from outside the multi-die package chip, and a second input terminal for receiving a second reference clock signal from other dies in the multi-die package system; the multiplexer 310 is used to output a first differential clock signal; wherein the first reference clock signal and the second reference clock signal adopt CML logic.

[0063] The AC coupling circuit 320 is connected to the output of the multiplexer 310 and is used to perform AC shaping and common-mode voltage shifting on the first differential clock signal to output the second differential clock signal.

[0064] The preamplifier 330 is connected to the output of the AC coupling circuit 320 and is used to amplify the amplitude of the second differential clock signal and output the amplified third differential clock signal.

[0065] Hysteresis comparator 340 is connected to the output of preamplifier 330 and is used to convert the third differential clock signal from CML logic to CMOS logic and output the first output clock signal after conversion logic to the internal circuitry of the die.

[0066] CML buffer 350 is connected to the output of preamplifier 330 to amplify the driving capability of the third differential clock signal to obtain a second output clock signal for transmission to the next cascaded die.

[0067] In this embodiment, both the first and second reference clock signals are transmitted using CML logic. Using CML to transmit the reference clock signals reduces signal reflection and electromagnetic interference on the transmission line due to the low voltage swing of the CML signal, which helps maintain signal integrity during high-frequency transmission.

[0068] The multiplexer 310 has two input terminals and one output terminal. The first input terminal is used to receive a first reference clock signal from outside the multi-die package chip, and the second input terminal is used to receive a second reference clock signal from other dies in the multi-die package system. That is, the multiplexer 310 selects to receive either the first reference clock signal from outside the multi-die package chip or the second reference clock signal from other dies, and outputs a first differential clock signal.

[0069] It should be noted that the multiplexer in this application is not a dynamically switching switch, but rather resembles a static signal channel with alternative paths. In multi-die package systems, system designers select the global reference clock source through fixed configuration signals during chip manufacturing or system initialization. This configuration directly determines the physical or logical connection between the valid clock source and the input pin, and the control logic inside the multiplexer is also fixed to continuously conduct the valid input.

[0070] With this fixed multiplexer with alternative paths, the same die can be adapted to different physical traces simply by changing the connection method of the configuration pins during packaging or system initialization. This improves design flexibility and reduces mask and R&D costs.

[0071] Specifically, the AC coupling circuit 320 uses a coupling capacitor to remove the DC bias component in the first differential clock signal, retaining only the AC clock signal component. Simultaneously, the AC coupling circuit 320 uses an internal bias network to shift the common-mode voltage of the AC clock signal to a preset static operating point.

[0072] Since the common-mode voltage of the first differential clock signal may deviate from the optimal operating point required by the subsequent circuit due to the influence of the preceding circuit and the signal transmission path, the common-mode voltage shifting of the AC coupling circuit 320 can ensure that the subsequent preamplifier 330 operates within its optimal operating region.

[0073] The amplitude of the second differential clock signal may be small after passing through the AC coupling circuit 320. The preamplifier 330 amplifies the amplitude of the second differential clock signal to a level sufficient to drive the subsequent hysteresis comparator 340 and CML buffer 350 to operate normally through its internal gain stage.

[0074] Optionally, the gain of the preamplifier 330 can be set by adjusting its internal load resistor and bias current.

[0075] The hysteresis comparator 340 is used to convert the third differential clock signal from CML logic to CMOS logic, and outputs the first output clock signal after the conversion logic to the internal circuitry of the die.

[0076] Specifically, the hysteresis comparator 340 compares the positive and negative terminals of the third differential clock signal. When the voltage at the positive terminal is higher than the voltage at the negative terminal by more than an upper threshold, the output of the hysteresis comparator 340 flips to a high level (CMOS logic power supply voltage, e.g., 0.8V); when the voltage at the positive terminal is lower than the voltage at the negative terminal by more than a lower threshold, the output of the hysteresis comparator 340 flips to a low level (CMOS logic ground voltage, e.g., 0V). The difference between the upper and lower thresholds is the hysteresis.

[0077] This embodiment uses a hysteresis comparator 340 for CML to CMOS logic conversion because the hysteresis effectively suppresses output jitter caused by noise superimposed on the input signal. Near the zero-crossing point of the clock signal, the input signal is easily affected by noise, causing slight fluctuations. Ordinary comparators may trigger multiple false triggers at this point, resulting in glitches in the output clock signal. However, due to the difference between its upper and lower thresholds, the hysteresis comparator 340 only triggers the output toggles when the change in the input signal exceeds the hysteresis, thus effectively eliminating noise sensitivity near the zero-crossing point and producing a clean and stable CMOS logic clock output.

[0078] Furthermore, the first output clock signal can be a full-amplitude CMOS logic signal, which can be directly provided to the phase-locked loop, delay-locked loop or other internal circuits that require a reference clock inside the die.

[0079] CML buffer 350 is connected to the output of preamplifier 330. CML buffer 350 receives the third differential clock signal, amplifies the driving capability of the third differential clock signal, and obtains the second output clock signal.

[0080] The second output clock signal remains in the form of a CML differential signal and can be used to transmit the signal through the metal traces in the silicon dielectric interlayer of the multi-die package system to the second input of the multiplexer of the reference clock transceiver in the next cascaded die.

[0081] It should be noted that the hysteresis comparator 340 and the CML buffer 350 are connected in parallel to the output of the preamplifier 330. That is, the third differential clock signal can be fed into the hysteresis comparator 340 and the CML buffer 350 together.

[0082] The hysteresis comparator 340 generates a CMOS logic clock signal (first output clock signal) for use within the current die, while the CML buffer 350 generates a CML differential clock signal (second output clock signal) for cascading transmission to the next die. This architecture enables each die to be both a receiver and a relayer of clock signals, achieving chained transmission of clock signals between multiple dies.

[0083] In summary, the reference clock transceiver provided in this application embodiment can achieve the following technical effects: First, by using a multiplexer to flexibly select an external clock or a clock transmitted from another die, the reference clock transceiver can adapt to various clock allocation topologies; Second, by using an AC coupling circuit to eliminate common-mode voltage differences between signals from different sources, the adaptability and robustness of the circuit are improved; Third, by using a hysteresis comparator to achieve high-quality logic conversion from CML to CMOS, the jitter of the output clock is reduced; Fourth, by using a CML buffer to achieve cascaded forwarding of clock signals, the number of external clock pins required by the system is reduced.

[0084] The reference clock transceiver described in this application has at least the following advantages compared to related technologies: 1. Reduced pin count and hardware cost. Through multiplexer design, the die can receive both external clock signals and internally cascaded clock signals. This allows multiple dies to share a single external clock source, eliminating the need for a separate oscillator and start-up circuit for each die, thus reducing the number of external pins and lowering hardware costs.

[0085] 2. Good anti-interference capability. Differential CML logic is used to transmit clock signals between dies. Compared with traditional single-ended logic, this method can better suppress noise, which helps to maintain signal integrity and control transmission loss and power consumption in long traces of multi-die packages.

[0086] 3. Facilitates clock cascading distribution. The transceiver internally incorporates a hysteresis comparator and a CML buffer. The hysteresis comparator converts the signal for use on its own die, while the CML buffer amplifies the signal before passing it to the next die. This allows each die to receive, use, and forward clock signals without requiring additional external drive circuitry.

[0087] 4. Improve the output clock waveform. By using a hysteresis comparator during signal conversion, the inherent hysteresis characteristic can be utilized to reduce noise glitches near the differential signal crossover point, making the clock waveform output to the die more stable.

[0088] 5. Compatible with voltage differences across dies. By adding AC coupling circuitry to process the signal, the transceiver can adapt to potential DC level differences between different dies, ensuring that subsequent circuits maintain normal operation and improving the reliability of inter-die interconnection.

[0089] 6. Supports multiple clock routing structures. Based on the transceiver's signal input and forwarding capabilities, the system can be configured with serial, parallel fan-out, or multiple clock source routing structures according to actual needs, adapting to the different clock signal requirements of different dies.

[0090] In some embodiments, the reference clock transceiver further includes an electrostatic discharge (ESD) protection circuit. The ESD protection circuit is located at the input front end of the multiplexer and provides an ESD current discharge path for the input reference clock signal.

[0091] Specifically, when an electrostatic discharge (ESD) event occurs, such as during packaging assembly or system testing, a human body or device may apply a high-voltage electrostatic pulse to external pins. If this high-voltage electrostatic pulse directly enters the multiplexer, it may break down the gate oxide layer of the field-effect transistors inside the multiplexer, causing permanent damage to the circuit.

[0092] The electrostatic discharge (ESD) protection circuit quickly turns on when an ESD event occurs, allowing the transient large current to be discharged through a low-impedance path to the power rail or ground rail, thereby clamping the voltage at the input of the multiplexer within a safe range.

[0093] Furthermore, the electrostatic discharge (ESD) protection circuit includes a two-stage ESD discharge network. The first-stage ESD discharge network is a diode discharge circuit, and the second-stage ESD discharge network is a discharge circuit combining a resistor and a diode. By employing a multi-stage discharge network structure, this embodiment can provide sufficient ESD protection while minimizing parasitic effects on the signal path.

[0094] Please see Figure 4 , Figure 4 This is the second schematic diagram of the reference clock transceiver provided in the embodiments of this application.

[0095] This embodiment applies to a reference clock transceiver for multi-die packaged chips. The reference clock transceiver includes an electrostatic discharge protection circuit, a 2-to-1 multiplexer, an AC coupler, a (CML) preamplifier, a hysteresis comparator, and a CML buffer.

[0096] The reference clock transceiver receives two differential clock sources: the on-chip clock input is directly connected to the in0 pin of the 2-to-1 multiplexer, while the off-chip clock input must first pass through an ESD protection circuit before connecting to the in1 pin of the 2-to-1 multiplexer. The signal output from the 2-to-1 multiplexer enters an AC coupler, where it undergoes AC shaping and common-mode voltage shifting based on the reference voltage, followed by amplitude amplification by a preamplifier. The amplified signal is then split into two paths: one path is sent to a hysteresis comparator to convert the signal into CMOS logic, serving as the internal clock for the die's logic; the other path is sent to a CML buffer to enhance the drive capability, serving as the on-chip clock output for the CML logic and passed to the next die.

[0097] In this embodiment, the reference clock transceiver receives and transmits CML logic clock signals outside the die, while outputting CMOS logic clock signals inside the die to drive other circuits within the die. The transceiver's input can receive clock signals from outside the chip and from other dies outside the die, and its output, a CML clock signal, can be sent to the CML input of the next die.

[0098] Please see Figure 5 , Figure 5 This is a schematic diagram of the electrostatic discharge protection circuit provided in the embodiments of this application.

[0099] The electrostatic discharge protection circuit consists of two-stage electrostatic discharge networks. The first-stage electrostatic discharge network (1 st ESD) is a diode discharge circuit, and the second-stage electrostatic discharge network (2) nd The ESD protection circuit is a combination of resistors and diodes. This two-stage electrostatic discharge protection circuit effectively provides an ESD current path to prevent current from flowing into the internal circuitry of the IC and causing damage during ESD discharge.

[0100] The primary function of the first-stage electrostatic discharge network is to provide a coarse discharge, quickly diverting most of the ESD current. The primary function of the second-stage electrostatic discharge network is to provide a fine discharge, ensuring that the voltage reaching the input of the multiplexer is within the device's safe operating voltage range.

[0101] like Figure 5 As shown, the electrostatic discharge protection circuit uses the same two-stage protection series connection method for the two input signals inn and inp.

[0102] After the signal is input, it first passes through the first-stage electrostatic discharge network. Each signal line is connected to the middle node of two reverse-biased diodes (d1 and d2, d3 and d4). The two ends of these two diodes are connected to the power supply and ground, respectively, for initial electrostatic discharge.

[0103] Subsequently, the signal enters the second-stage electrostatic discharge network. After a resistor (R) is connected in series with the signal line, similar to the first-stage network, the signal line is again connected to the midpoint of two reverse-biased diodes (d5 and d6, d7 and d8). The diodes are also connected to power and ground to further absorb residual electrostatic energy. After passing through these two stages of protection networks composed of diodes and resistors, the signal is finally output from the outn and outp terminals.

[0104] In some embodiments, the multiplexer is composed of multiple transmission gate devices coupled in parallel. The transmission gate devices are composed of N-type field-effect transistors (such as NMOS transistors) and P-type field-effect transistors (such as PMOS transistors) connected in parallel, and the width-to-length ratio of the N-type field-effect transistors and P-type field-effect transistors is greater than a preset threshold in order to reduce the on-resistance and suppress the transmission loss of the clock signal. That is, the width-to-length ratio of NMOS and PMOS should be selected to a relatively large value to ensure a relatively small on-resistance and avoid signal transmission loss.

[0105] In this embodiment, the transmission gate is a bidirectional analog switch circuit consisting of an N-type field-effect transistor (NMOS) and a P-type field-effect transistor (PMOS) connected in parallel. When the transmission gate is on, the signal can pass through bidirectionally; when the transmission gate is off, the signal is isolated. The on-resistance of the transmission gate is related to the width-to-length ratio of the field-effect transistors.

[0106] Please see Figure 6 , Figure 6 This is a schematic diagram of the structure of the multiplexer provided in the embodiments of this application.

[0107] The multiplexer employs a symmetrical two-way selection structure for differential clock signals. In the first clock path, the on-chip clock signal Ckn_in and the off-chip clock signal Ckn_ex are respectively connected to the input terminals of their independent transmission gates. Subsequently, the output terminals of these two transmission gates are coupled together in parallel and connected to the output node Ckn_out.

[0108] The connection method of the second clock path is exactly the same. The on-chip signal Ckp_in and the off-chip signal Ckp_ex pass through independent transmission gates, and their outputs are also combined and connected to the same output node Ckp_out.

[0109] In terms of specific device-level connections, each transmission gate is composed of an NMOS transistor (M0) and a PMOS transistor (M1) connected in parallel, with the source and drain of the two transistors shorted respectively. The entire circuit can achieve a two-to-one selection output of the on-chip or off-chip clock signal by controlling the on / off state of the corresponding transmission gates.

[0110] In some embodiments, the AC coupling circuit outputs a second differential clock signal at a preset static operating point; the preamplifier includes a load resistor; the peak-to-peak amplitude of the third differential clock signal is the product of the resistance value of the load resistor and the current value corresponding to the preset static operating point.

[0111] Please see Figures 7-8 , Figure 7 This is a schematic diagram of the structure of the AC coupling circuit provided in the embodiment of this application. Figure 8 This is a schematic diagram of the signal processing of the AC coupling circuit provided in the embodiments of this application.

[0112] The main function of the AC coupler circuit is to perform AC shaping on the waveform of the input clock signal, shift the common-mode voltage of the differential clock signal, and transform the differential signal waveform into an oscillation at a fixed DC voltage static point. This DC static operating point provides a suitable common-mode voltage operating point for the subsequent pre-amplifier circuit to meet the driving requirements of the input stage of the subsequent pre-amplifier.

[0113] like Figure 7 As shown, the differential input terminals inn and inp are connected in series with capacitors C1 and C2, respectively, and then connected to the differential output terminals outn and outp. This structure only allows AC signals to pass through. Meanwhile, to provide a suitable DC operating point for the subsequent stage, a reference voltage is introduced into the circuit. This reference voltage is connected to the common terminal of resistors R1 and R2, while the other ends of R1 and R2 are connected in parallel to the output terminals outn and outp of the capacitor stage, respectively. This fixes the common-mode voltage bias of the differential output signal at the set reference voltage level.

[0114] like Figure 8 As shown, V0 is the first differential clock signal and V1 is the second differential clock signal.

[0115] This application uses a load resistor to set the output amplitude. The resistance value and bias current of the load resistor are both designable parameters. Designers can adjust these two parameters to flexibly set the amplitude of the third differential clock signal to meet the input requirements of different subsequent circuits.

[0116] Please see Figures 9-10 , Figure 9 This is a schematic diagram of the preamplifier provided in an embodiment of this application. Figure 10 This is a schematic diagram of preamplifier signal processing provided in an embodiment of this application.

[0117] The core of the preamplifier is a differential input pair consisting of transistors MN1 and MN2. The sources of the two transistors are connected to each other and are connected to the drain of transistor MN3 below, which provides bias current. The source of MN3 is grounded and its gate is connected to the bias voltage Vbias.

[0118] On the signal input side, the gates of MN1 and MN2 are connected to the first input signal Vinp and the second input signal Vinn, respectively. On the signal output side, the drains of MN1 and MN2 are connected in series with a load resistor R, and the other ends of these two resistors are connected to the top power supply terminal. Simultaneously, the drain nodes of MN1 and MN2 connected to the resistors serve as the first output signal Voutn and the second output signal Voutp, respectively.

[0119] The preamplifier can amplify the amplitude of weak clock signals. Optionally, the amplified peak-to-peak amplitude Vpp is equal to the product of the load resistor value RL and the current value I corresponding to the preset static operating point, i.e., Vpp=RL×I, to meet the driving requirements of the subsequent comparator and CML buffer.

[0120] Schematic, in one specific embodiment, if the load resistor RL is 500Ω and the bias current I of the preamplifier at the preset quiescent operating point is 0.8mA, then the peak-to-peak amplitude Vpp of the third differential clock signal is 500Ω × 0.8mA = 400mV. This amplitude is sufficient to drive the subsequent hysteresis comparator to perform a reliable CML to CMOS logic conversion.

[0121] like Figure 10 As shown, V1 is the second differential clock signal, and V2 is the third differential clock signal.

[0122] Please see Figure 11 , Figure 11 This is a schematic diagram of the hysteresis comparator provided in the embodiments of this application.

[0123] The hysteresis comparator can convert the clock signal of the preceding CML logic into a CMOS logic clock signal, and can effectively avoid glitch glitches caused by noise in the output clock signal. The conversion to CMOS logic levels is suitable for driving various on-chip circuits.

[0124] like Figure 11 As shown, a hysteresis comparator can be divided into the following main parts: ① Input and differential amplifier stage: The core is a differential amplifier consisting of differential input pairs (MN1 and MN2). Their gates receive the positive and negative input signals Vinp and Vinn, respectively. The sources of MN1 and MN2 are connected together and jointly connected to the drain of the bottom transistor MN3 to obtain the bias current. The drains of MN1 and MN2 are connected upwards to internal nodes a1 and b1, respectively.

[0125] ②Hysteresis load network: Between nodes a1 and b1 and the top power supply, an active load providing hysteresis characteristics is connected. This load consists of two pairs of transistors: the outer pairs are transistors configured as diodes (MN5 and MN6, i.e., gate and drain shorted), and the inner pairs are cross-coupled transistors (MN3 and MN4, i.e., the gate of MN3 is connected to the drain of MN4, b1, and the gate of MN4 is connected to the drain of MN3, a1). This cross-coupled structure introduces positive feedback, which is key to achieving the hysteresis characteristics.

[0126] ③ Differential to single-ended converter and output stage: The differential signals at nodes a1 and b1 need to be converted from differential to single-ended. a1 is connected to the gate of transistor MN7, and b1 is connected to the gate of MN8. MN7 and MN8, along with their bottom loads (MN9 and MN10, where MN9 is a diode connection), converge at node c1 to output a single-ended signal. Two inverters are connected in series after node c1 for further shaping and amplification of the signal, ultimately outputting a CMOS logic level clock signal Vout. The intermediate node between the two inverters is labeled c2.

[0127] ④ Feedback and bias adjustment network: The bias voltage Vbias is connected to the gates of two adjustable devices (MN11, MN12). The final output signal Vout is fed back to the gate of transistor MN13, while the intermediate inverted signal c2 is fed back to the gate of transistor MN14. MN13 and MN14 are connected to the input nodes Vinp and Vinn, respectively, and the characteristics of the input terminals are dynamically adjusted by the high and low states of the output level to assist in hysteresis control.

[0128] Please see Figure 12 , Figure 12 This is a schematic diagram of the structure of the CML buffer provided in the embodiments of this application.

[0129] The main function of a CML buffer is to increase the driving capability and convert the input signal into a clock signal of a specific amplitude for long-distance transmission. This embodiment uses a CML buffer constructed from two cascaded differential circuits.

[0130] The first stage circuit serves as the input stage, consisting of a differential pair of transistors MN1 and MN2. The differential input signals Vinp and Vinn are connected to the gates of MN1 and MN2, respectively; their drains are connected upwards to the power supply through load resistors of resistance R. The sources of MN1 and MN2 are connected together and then to the drain of transistor MN0. The gate of MN0 is connected to a bias voltage Vbias, and its source is grounded, providing a bias current of magnitude I for the first stage.

[0131] The second stage circuit, serving as the output stage, consists of a differential pair of transistors MN4 and MN5. The two stages are directly coupled: the drain of MN2 is connected to the gate of MN4, and the drain of MN1 is connected to the gate of MN5. The drains of MN4 and MN5 are connected upwards to the power supply through load resistors with a resistance of R / n, and the final buffered output signals Voutn and Voutp are led out from these two drain nodes, respectively. The sources of MN4 and MN5 are connected to the drain of transistor MN3. The gate of MN3 is also connected to Vbias, and its source is grounded, providing a voltage of n. By adjusting the bias current of I and proportionally reducing the load resistance, signal driving capability and current amplification can be achieved.

[0132] Multi-die packaging systems generally come in several forms, the first of which is the traditional standard package.

[0133] Please see Figure 13 , Figure 13 This is a schematic diagram of a multi-die packaging system provided by related technologies. Multiple dies, Die0, Die1, and Die2, are disposed on the packaging substrate 100. All dies share a single packaging substrate 100, and the multiple dies, Die0, Die1, and Die2 on the packaging substrate 100 are connected by metal wires.

[0134] In contrast, the multi-die packaging system provided in this application can integrate multiple high-performance dies and can adopt advanced packaging forms. The reference clock signal is transmitted through the intermediate silicon dielectric metal trace in the multi-die package.

[0135] Please see Figures 14-16 , Figure 14 This is one of the structural schematic diagrams of the multi-die packaging system provided in the embodiments of this application. Figure 15 This is the second schematic diagram of the multi-die packaging system provided in the embodiments of this application. Figure 16 This is the third schematic diagram of the structure of the multi-die packaging system provided in the embodiments of this application.

[0136] In this embodiment, the multi-die packaging system includes a packaging substrate 100, a silicon dielectric interlayer 200, and a plurality of die dies Die0, Die1, and Die2 disposed on the silicon dielectric interlayer 200; the plurality of die dies Die0, Die1, and Die2 communicate with each other through metal traces inside the silicon dielectric interlayer 200; at least one of the plurality of die dies Die0, Die1, and Die2 has the aforementioned reference clock transceiver disposed inside it.

[0137] It should be noted that in high-performance multi-die packages, due to the large spacing between different dies, signal transmission is prone to loss and is susceptible to interference from the surrounding environment, which may affect the normal operation of the internal circuitry of the dies. Therefore, this embodiment uses differential CML level transmission of the clock signal to improve signal integrity and anti-interference capability.

[0138] The packaging substrate 100 is the underlying carrier of the multi-die packaging system, on which a ball grid array (BGA) or other interconnect structure for connection with an external circuit board is disposed. The packaging substrate 100 may also include multiple layers of metal wiring layers for introducing external signals (including reference clock signals, power signals, data signals, etc.) from outside the package to the silicon dielectric interlayer 200.

[0139] Optionally, the silicon dielectric interlayer 200 may include high-density metal traces for high-speed signal interconnection between multiple dies.

[0140] Optionally, the silicon dielectric interlayer 200 can be in the form of a silicon bridge.

[0141] Alternatively, the multi-die packaging system can take the form of CoWoS.

[0142] At least one of the multiple die types Die0, Die1, and Die2 has a reference clock transceiver internally configured as described in the above embodiments. In one embodiment, each die in the multi-die packaging system has a built-in reference clock transceiver, enabling each die to receive and forward reference clock signals.

[0143] In summary, by incorporating a reference clock transceiver within the die in a multi-die package system, flexible allocation and transmission of the reference clock signal among multiple dies can be achieved. Compared to schemes where each die independently receives the reference clock from an external source, the multi-die package system of this embodiment can reduce the number of external clock pins, lower packaging costs and complexity, while supporting various flexible clock allocation architectures.

[0144] Reference clock schemes for multi-die package systems are flexible and varied. Here are some application examples: In some embodiments, a multi-die package system may employ a serial single-clock source architecture.

[0145] Please see Figure 17 , Figure 17 This is a schematic diagram of the serial single-clock source architecture provided in the embodiments of this application.

[0146] The multi-die package system receives a single external clock source signal as the first reference clock signal for the first die through two external pins (corresponding to the positive and negative terminals of the differential signal, respectively); the second output clock signal output by the CML buffer of the first die is transmitted to the multiplexer of the next die as the second reference clock signal through metal traces, and is transmitted in series to multiple dies in the multi-die package system.

[0147] The entire multi-die package system requires only two external pins to provide a reference clock signal for all dies, maximizing the conservation of package pin resources. Furthermore, since all dies share the same clock source, they naturally share the same frequency, which is beneficial for system-level clock synchronization.

[0148] like Figure 17As shown, the multi-die packaging system includes a packaging substrate 100, a silicon dielectric interlayer 200, and multiple dies Die0, Die1, and Die2 disposed on the silicon dielectric interlayer 200. Each die is provided with an on-chip clock input pin (ckinp_in and kkinn_in), an off-chip clock input pin (ckinp_ex and kkinn_ex), and an on-chip clock output pin (ckoutp_in and koutn_in).

[0149] The external clock input pins of die 0 are connected to external clock signals (CLKP and CLKN). The internal clock output pins of die 0 are connected to the internal clock input pins of die 1. The internal clock output pins of die 1 are connected to the internal clock input pins of die 2. The internal clock input pins of die 0, the external clock input pins of die 1, the external clock input pins of die 2, and the internal clock output pins of die 2 are all left unconnected.

[0150] In this embodiment, multiple dies share a single external clock source. The multiple dies are connected in series, utilizing only two external pins, resulting in strong driving capability and suitability for long-distance transmission multi-die packaging.

[0151] In some embodiments, the multi-die package system employs a cascaded multi-clock source architecture. See also... Figure 18 , Figure 18 This is a schematic diagram of the serial multi-clock source architecture provided in the embodiments of this application.

[0152] The multi-die package system receives multiple external clock source signals through multiple sets of external pins; the first set of cascaded dies shares the first external clock source signal, and the second set of cascaded dies shares the second external clock source signal, so as to provide different reference clocks for dies with different application requirements within the multi-die package system.

[0153] The first external clock source signal and the second external clock source signal can be the same or different.

[0154] A cascaded multi-clock source architecture can provide different reference clocks for dies with different application requirements in a multi-die package system. For example, the first set of cascaded dies might be a high-performance processor core requiring a 100MHz reference clock; the second set of cascaded dies might be a high-speed serial interface module requiring a 156.25MHz reference clock. With this cascaded multi-clock source architecture, die groups with different frequency requirements can use different frequency clock sources without requiring additional frequency conversion within the die itself.

[0155] like Figure 18As shown, the multi-die packaging system includes a packaging substrate 100, a silicon dielectric interlayer 200, and multiple dies Die0, Die1, and Die2 disposed on the silicon dielectric interlayer 200. Each die is provided with an on-chip clock input pin (ckinp_in and kkinn_in), an off-chip clock input pin (ckinp_ex and kkinn_ex), and an on-chip clock output pin (ckoutp_in and koutn_in).

[0156] The external clock input pin of die 0 is connected to the first external clock signal (CLKP0 and CLKN0). The internal clock output pin of die 0 is connected to the internal clock input pin of die 1. The external clock input pin of die 2 is connected to the second external clock signal (CLKP1 and CLKN1). The internal clock input pin of die 0, the external clock input pin of die 1, the internal clock output pin of die 1, the internal clock input pin of die 2, and the internal clock output pin of die 2 are all left unconnected.

[0157] In this embodiment, some dies share a single external clock source, while the remaining dies use a different clock source. Different frequency clock signals can be transmitted to the dies for different applications. Only four external pins are used, but two reference clocks are available for flexible internal use.

[0158] In some embodiments, the multi-die package system employs a parallel single-clock source architecture. See also... Figure 19 , Figure 19 This is a schematic diagram of the parallel single clock source architecture provided in the embodiments of this application.

[0159] The multi-die package system receives a single external clock source signal through two external pins as the first reference clock signal for multiple dies. The multiple dies in the multi-die package system are connected in parallel based on the first reference clock signal. That is, the multiplexer of the reference clock transceiver in each die is configured to select the first input terminal and directly receive the first reference clock signal from the outside.

[0160] Optionally, in a parallel single-clock source architecture, the CML buffer of the reference clock transceiver of each die can be left unused (i.e., the second output clock signal is not transmitted to other dies), or the CML buffer can be disabled to reduce power consumption.

[0161] like Figure 19As shown, the multi-die packaging system includes a packaging substrate 100, a silicon dielectric interlayer 200, and multiple dies Die0 and Die1 disposed on the silicon dielectric interlayer 200. Each die is provided with an on-chip clock input pin (ckinp_in and kkinn_in), an off-chip clock input pin (ckinp_ex and kkinn_ex), and an on-chip clock output pin (ckoutp_in and koutn_in).

[0162] The external clock input pins of die 0 are connected to external clock signals (CLKP and CLKN), and the external clock input pins of die 1 are also connected to external clock signals (CLKP and CLKN). The internal clock input pins of die 0, the internal clock output pins of die 0, the internal clock input pins of die 1, and the internal clock output pins of die 1 are all left unconnected.

[0163] Employing a parallel single-clock source architecture, all dies directly obtain their reference clock from the same external clock source, avoiding the accumulated delay and phase noise degradation issues caused by cascading. Furthermore, this architecture requires only two external pins.

[0164] In this embodiment, multiple dies share a single external clock source. The multiple dies are connected in parallel, utilizing only two external pins, but this requires high input drive capability and is more suitable for multi-die packages where the dies are relatively close together.

[0165] In some embodiments, the multi-die package system employs a parallel multi-clock source architecture. See also... Figure 20 , Figure 20 This is a schematic diagram of the parallel multi-clock source architecture provided in the embodiments of this application.

[0166] The multi-die package system receives multiple external clock source signals through multiple sets of external pins; the first set of dies is connected in parallel based on the first external clock source signal, and the second set of dies is connected in parallel based on the second external clock source signal, so as to provide different reference clocks for dies with different application requirements in the multi-die package system.

[0167] The parallel multi-clock source architecture provides different reference clock frequencies for dies with varying application requirements, while avoiding the cumulative latency and phase noise degradation caused by cascading within the same group of dies. This architecture is particularly suitable for large-scale multi-die package systems with a large number of dies and diverse functions. For example, the first group of dies might be a CPU core using a 100MHz reference clock; the second group might be a high-speed Ethernet interface using a 156.25MHz reference clock.

[0168] like Figure 20As shown, the multi-die packaging system includes a packaging substrate 100, a silicon dielectric interlayer 200, and multiple dies Die0 and Die1 disposed on the silicon dielectric interlayer 200. Each die is provided with an on-chip clock input pin (ckinp_in and kkinn_in), an off-chip clock input pin (ckinp_ex and kkinn_ex), and an on-chip clock output pin (ckoutp_in and koutn_in).

[0169] The external clock input pins of die 0 are connected to the first external clock signal (CLKP0 and CLKN0), and the external clock input pins of die 1 are connected to the second external clock signal (CLKP1 and CLKN1). The internal clock input pins of die 0, the internal clock output pins of die 0, the internal clock input pins of die 1, and the internal clock output pins of die 1 are all left unconnected.

[0170] In this embodiment, a common external clock source or a multi-clock source scheme is used. Four pins are brought out externally, which can be connected in parallel to share a single clock source, or different clock sources can be used separately. When connected in parallel, an external driver circuit can be integrated to provide a reliable clock for the chip's internal circuitry. Using different clock sources allows for flexible application handling.

[0171] It should be noted that, compared to a series single-clock-source architecture, a parallel multi-clock-source architecture requires more external pins to introduce multiple clock source signals. Designers need to weigh the number of pins against the flexibility of clock distribution and choose the most suitable architecture based on specific system requirements.

[0172] The following is a comparison and summary of the four clock distribution architectures mentioned above: ① Serial Single Clock Source Architecture: This architecture uses a minimum number of external pins (two), with all dies sharing a single clock source. Clock signals are transmitted sequentially through cascading. It is suitable for scenarios with a moderate number of dies and consistent clock frequency requirements.

[0173] ② Serial multi-clock source architecture: Utilizes multiple sets of external pins, with different sets of cascaded dies using different clock sources. Suitable for scenarios with a large number of dies and different functional modules requiring different frequency reference clocks.

[0174] ③ Parallel Single Clock Source Architecture: Using two external pins, all dies obtain their reference clock directly from the same external clock source in parallel. This is suitable for scenarios with high requirements for clock skew and phase noise, and a small number of dies.

[0175] ④ Parallel Multi-Clock Source Architecture: This architecture uses multiple sets of external pins, with different sets of dies connected in parallel to obtain different clock source signals. It is suitable for large-scale systems with a large number of dies, diverse functions, and high clock quality requirements.

[0176] It should be noted that in practical applications, the above four architectures can be used in combination. For example, some dies may use a serial architecture for cascaded transmission, while other dies may use a parallel architecture to directly receive an external clock.

[0177] In summary, the reference clock transceiver and multi-die package system provided in this application adopt differentiated signal processing methods for internal and external circuits. The dies uniformly transmit and receive CML logic clock signals externally, and internally convert them into CMOS logic clock signals to drive internal circuits. Its signal transmission is highly flexible; it can not only receive clocks from external chips or other dies, but also pass them as CML signals to the next die. Because CML levels have strong anti-interference capabilities, they are suitable for long-distance transmission. Combined with a built-in CML buffer, the stability of transmission between multiple dies is ensured. Furthermore, the system is internally equipped with a hysteresis comparator, which not only accurately converts the CML level to the CMOS level required by the internal PLL (Phase-Locked Loop), but also effectively suppresses clock noise, ensuring signal purity.

[0178] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0179] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0180] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A reference clock transceiver, characterized in that, The reference clock transceiver, located within a die in a multi-die packaging system, includes: A multiplexer has a first input terminal for receiving a first reference clock signal from outside the multi-die packaged chip, and a second input terminal for receiving second reference clock signals from other dies in the multi-die packaged system; the multiplexer is used to output a first differential clock signal; wherein the first reference clock signal and the second reference clock signal adopt CML logic; An AC coupling circuit, connected to the output of the multiplexer, is used to perform AC shaping and common-mode voltage shifting on the first differential clock signal and output a second differential clock signal. A preamplifier, connected to the output of the AC coupling circuit, is used to amplify the amplitude of the second differential clock signal and output the amplified third differential clock signal. A hysteresis comparator, connected to the output of the preamplifier, is used to convert the third differential clock signal from CML logic to CMOS logic and output the first output clock signal after conversion logic to the internal circuit of the die. The CML buffer, connected to the output of the preamplifier, is used to amplify the driving capability of the third differential clock signal to obtain a second output clock signal for transmission to the next cascaded die.

2. The reference clock transceiver according to claim 1, characterized in that, Also includes: An electrostatic discharge (ESD) protection circuit is located at the input front end of the multiplexer to provide an ESD discharge path for the input reference clock signal.

3. The reference clock transceiver according to claim 2, characterized in that, The electrostatic discharge protection circuit includes a two-stage electrostatic discharge network. The first-stage electrostatic discharge network is a diode discharge circuit, and the second-stage electrostatic discharge network is a discharge circuit combining a resistor and a diode.

4. The reference clock transceiver according to any one of claims 1 to 3, characterized in that, The multiplexer is composed of multiple transmission gate devices coupled in parallel; The transmission gate device is composed of N-type field-effect transistors and P-type field-effect transistors connected in parallel, and the width-to-length ratio of the N-type field-effect transistors and the P-type field-effect transistors is greater than a preset threshold, so as to reduce the on-resistance and suppress the transmission loss of the clock signal.

5. The reference clock transceiver according to any one of claims 1 to 3, characterized in that, The AC coupling circuit outputs a second differential clock signal at a preset static operating point; the preamplifier includes a load resistor; The peak-to-peak amplitude of the third differential clock signal is the product of the resistance value of the load resistor and the current value corresponding to the preset static operating point.

6. A multi-die packaging system, characterized in that, It includes a packaging substrate, a silicon dielectric interlayer, and a plurality of bare dies disposed on the silicon dielectric interlayer; The multiple dies communicate with each other through metal traces inside the silicon dielectric interlayer; At least one of the plurality of dies is provided with a reference clock transceiver as described in any one of claims 1 to 5.

7. The multi-die packaging system according to claim 6, characterized in that, The multi-die packaging system adopts a serial single-clock source architecture; The multi-die packaging system receives a single external clock source signal as the first reference clock signal for the first die through two external pins. The second output clock signal output by the CML buffer of the first die is transmitted through the cascaded metal traces to the multiplexer of the next die as the second reference clock signal, and then transmitted in series to multiple dies in the multi-die packaging system.

8. The multi-die packaging system according to claim 6, characterized in that, The multi-die packaging system adopts a serial multi-clock source architecture; The multi-die package system receives multiple external clock source signals through multiple sets of external pins; wherein, the first set of cascaded dies shares the first external clock source signal, and the second set of cascaded dies shares the second external clock source signal, so as to provide different reference clocks for dies with different application requirements within the multi-die package system.

9. The multi-die packaging system according to claim 6, characterized in that, The multi-die packaging system adopts a parallel single clock source architecture; The multi-die packaging system receives a single external clock source signal via two external pins as the first reference clock signal for multiple dies; the multiple dies in the multi-die packaging system are connected in parallel based on the first reference clock signal.

10. The multi-die packaging system according to claim 6, characterized in that, The multi-die packaging system adopts a parallel multi-clock source architecture; The multi-die package system receives multiple external clock source signals through multiple sets of external pins; wherein, the first set of dies is connected in parallel based on the first external clock source signal, and the second set of dies is connected in parallel based on the second external clock source signal, so as to provide different reference clocks for dies with different application requirements in the multi-die package system.

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