Power equipment remote upgrading method and system based on ARM and FPGA

Abstract

The present application relates to the technical field of power equipment, and provides a power equipment remote upgrading method and system based on ARM and FPGA to solve the problem of poor adaptability of existing solutions that only support fixed frame length transmission. The power equipment remote upgrading method based on ARM and FPGA includes receiving and analyzing a remote upgrading instruction frame by a power monitoring terminal. After receiving each subpackaged upgrading file, the power monitoring terminal performs CRC checking on each subpackaged upgrading file according to subpackaging parameters and records total package data CRC checksum I. After checking, the corresponding upgrading file is integrated and stored in an external Flash storage module. The power monitoring terminal determines that the upgrading object is ARM / FPGA, responds to the corresponding upgrading start instruction and starts the ARM / FPGA upgrading process, realizes independent and accurate automatic upgrading of ARM / FPGA, and guarantees the upgrading stability and the compatibility of the main station.

Description

Technical Field

[0001] This invention relates to the field of power equipment technology, and in particular to a method and system for remote upgrading power equipment based on ARM and FPGA. Background Technology

[0002] The statements in this section are merely background information related to the present invention and do not necessarily constitute prior art.

[0003] Power monitoring equipment is typically deployed directly along high-voltage lines for real-time monitoring of transmission line operation, accurate fault diagnosis, and early warning. Updating and updating the software of power monitoring equipment is a necessary measure to ensure its continuous and stable operation and adapt to the evolving needs of power grid operation and maintenance.

[0004] Power monitoring equipment using an "ARM+FPGA" collaborative architecture differs in the hardware characteristics and transmission signal frame lengths of FPGA and ARM processors. Their functions also differ: the FPGA is responsible for real-time acquisition, buffering, and preprocessing of traveling wave signals from transmission lines, ensuring the timeliness and accuracy of signal capture; the ARM, as the main control unit, handles fault location algorithm calculations, peripheral control, early warning information generation, and data interaction with maintenance terminals, adapting to diverse maintenance needs through software flexibility. However, existing upgrade solutions for power monitoring equipment are all generalized automatic upgrade schemes, still employing an "overall automatic upgrade" logic that only supports fixed frame length transmission, resulting in poor performance for power monitoring equipment with an "ARM+FPGA" architecture. Summary of the Invention

[0005] To address the aforementioned technical issues, this invention provides a method and system for remotely upgrading power equipment based on ARM and FPGA. This system enables independent, precise, and automatic upgrades of ARM / FPGA, reduces device upgrade coupling, optimizes the upgrade process, and incorporates multiple verification mechanisms and a variable frame length mechanism to ensure upgrade stability and master station compatibility.

[0006] To achieve the above objectives, the present invention adopts the following technical solution: The first aspect of the present invention provides a method for remotely upgrading power equipment based on ARM and FPGA.

[0007] In one or more embodiments, a method for remotely upgrading power equipment based on ARM and FPGA is provided, including: The system master station receives the program to be upgraded and completes the communication parameter configuration, and sends a remote upgrade instruction frame and various sub-package upgrade files to the power monitoring terminal with ARM+FPGA architecture; the remote upgrade instruction frame includes an upgrade start instruction, an upgrade file identifier and sub-package parameters, and the upgrade file is an ARM program upgrade file and / or an FPGA program upgrade file; The power monitoring terminal receives the remote upgrade command frame, parses the remote upgrade command frame, returns a response signal to the system master station, and enters the upgrade ready state. After the system master station confirms receipt of the response signal, it sends each sub-package upgrade file to the power monitoring terminal in sequence. After receiving each sub-package upgrade file, the power monitoring terminal performs CRC (Cyclic Redundancy Check) verification on each sub-package upgrade file according to the parsed sub-package parameters and records the CRC checksum of the total package data. After the verification is correct, the corresponding upgrade files are integrated and stored in the external Flash storage module. Based on the parsed upgrade file identifier, the power monitoring terminal determines that the upgrade target is ARM / FPGA, responds to the corresponding upgrade start command, and initiates the corresponding ARM / FPGA upgrade process. The ARM / FPGA upgrade process is as follows: the ARM / FPGA controller performs a packet CRC read check on the upgrade file in the external Flash storage module, calculates the total packet data CRC checksum II and compares it with the total packet data CRC checksum I. If they match, the ARM / FPGA program storage area is erased, written, and the new program is loaded.

[0008] In one implementation, the upgrade file is identified by a preset character code; wherein, the ARM program upgrade file corresponds to the first character code, the FPGA program upgrade file corresponds to the second character code, and the power monitoring terminal determines the upgrade target by recognizing the preset character code.

[0009] As one implementation method, during the program erasure, data writing and new program loading process, the ARM / FPGA controller monitors the upgrade status in real time; if an abnormal interruption occurs, the upgrade operation is stopped immediately, the program version before the upgrade is restored, and the abnormal information is reported to the system master station.

[0010] As one implementation method, after the power monitoring terminal identifies the upgrade target, but before responding to the corresponding upgrade initiation command, it also includes: The power monitoring terminal loads corresponding exclusive parsing rules according to the hardware upgrade requirements of ARM / FPGA, performs hierarchical and targeted parsing of the parameter fields of the remote upgrade command frame, extracts the exclusive parameters of the target device ARM / FPGA, and filters out parameters irrelevant to the target device.

[0011] As one implementation method, if the CRC check of a certain sub-package upgrade file fails, the power monitoring terminal sends a retransmission request to the system master station; the system master station re-issues the corresponding sub-package upgrade file until the check succeeds or the preset number of retransmissions is reached.

[0012] As one implementation method, if the verification still fails after reaching the preset number of retransmissions, the upgrade will be terminated and the upgrade failure information will be reported to the system master station.

[0013] As one implementation method, before the system master station issues the upgrade file, a frame length negotiation instruction frame is first sent to the power monitoring terminal. The frame length negotiation instruction frame contains the frame length configuration parameters that the system master station intends to use. The ARM controller parses the frame length negotiation instruction frame and verifies the validity of the frame length. If it is valid, it sends a frame length adaptation success response and automatically loads the parsing rules for the corresponding frame length.

[0014] As one implementation method, when the ARM controller performs the upgrade operation, the basic monitoring function module of the power monitoring terminal is kept running normally. The basic monitoring function module is used to collect and temporarily store the basic voltage and current parameters of the power equipment, and then synchronize them to the system master station after the upgrade is completed.

[0015] As one implementation method, the mechanism for sending various sub-package upgrade files from the system master station to the power monitoring terminal with ARM+FPGA architecture is designed as a variable frame length mode. The power monitoring terminal does not need to preset a fixed frame length and can automatically identify and adapt to upgrade files of any frame length sent by the system master station.

[0016] A second aspect of the present invention provides a remote upgrade system for power equipment based on ARM and FPGA.

[0017] In one or more embodiments, a remote upgrade system for power equipment based on ARM and FPGA includes: a system master station and a monitoring terminal; the power monitoring terminal is an ARM+FPGA architecture power monitoring terminal; The system master station is configured to: receive the program to be upgraded and complete the communication parameter configuration, and send a remote upgrade instruction frame and various sub-package upgrade files to the power monitoring terminal with ARM+FPGA architecture; the remote upgrade instruction frame includes an upgrade start instruction, an upgrade file identifier and sub-package parameters, and the upgrade file is an ARM program upgrade file and / or an FPGA program upgrade file; The power monitoring terminal is configured to: receive the remote upgrade instruction frame, parse the remote upgrade instruction frame, return a response signal to the system master station, and enter the upgrade ready state. The system master station is also configured to: after confirming receipt of the response signal, send each sub-package upgrade file to the power monitoring terminal in sequence; The power monitoring terminal is also configured to: After receiving each sub-packet upgrade file, perform CRC check on each sub-packet upgrade file according to the parsed sub-packet parameters and record the CRC checksum of the total packet data. After the check is correct, integrate the corresponding upgrade files and store them in the external Flash storage module. Based on the parsed upgrade file identifier, the upgrade target is determined to be ARM / FPGA. The corresponding upgrade start command is responded to and the corresponding ARM / FPGA upgrade process is started. The ARM / FPGA upgrade process is as follows: The ARM / FPGA controller performs a packet CRC read check on the upgrade file in the external Flash storage module, calculates the total packet data CRC checksum II and compares it with the total packet data CRC checksum I. After they match, the ARM / FPGA program storage area is erased, written and the new program is loaded.

[0018] Compared with the prior art, the beneficial effects of the present invention are: This invention addresses the remote upgrade of power monitoring terminals based on an ARM+FPGA architecture. The system master station receives the program to be upgraded and completes the communication parameter configuration. It then sends a remote upgrade command frame and various sub-package upgrade files to the ARM+FPGA power monitoring terminal. The power monitoring terminal determines the upgrade target as the ARM / FPGA based on the parsed upgrade file identifier, responds to the corresponding upgrade start command, and initiates the ARM / FPGA upgrade process accordingly. Independent upgrade operations are performed on the ARM itself or the cooperating FPGA, providing a flexible upgrade method and improving the convenience and efficiency of device function iteration. Furthermore, during the ARM / FPGA upgrade, in addition to the CRC checksums of the sub-package data sent by the master station and the sub-package data read and written from the external Flash, the CRC checksums of the total package data from these two checks are also compared, ensuring that the received upgrade file package is completely consistent with the written upgrade file package data, thus guaranteeing upgrade stability. Attached Figure Description

[0019] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an improper limitation of the invention.

[0020] Figure 1 This is a flowchart of a remote upgrade method for power equipment based on ARM and FPGA according to an embodiment of the present invention; Figure 2 This is a schematic diagram of the multi-verification principle of a remote upgrade system for power equipment based on ARM and FPGA according to an embodiment of the present invention. Figure 3 This is a circuit schematic diagram of an ARM / external Flash for remote upgrading of power equipment based on ARM and FPGA, according to an embodiment of the present invention. Detailed Implementation

[0021] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0022] It should be noted that the following detailed description is illustrative and intended to provide further explanation of the invention. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains.

[0023] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of exemplary embodiments according to the invention. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0024] System main station: Selects power monitoring equipment to be upgraded, uploads and verifies the preset .bin format upgrade file, and then transmits the upgrade file to the target terminal via 4G packet transmission.

[0025] ARM: As the main control unit of power monitoring equipment, it is responsible for fault location algorithm calculation, peripheral control, early warning information generation, and data interaction with the operation and maintenance terminal. The ARM chip storage area is divided into SRAM area and on-chip Flash area. The on-chip Flash area is the physical basis for the chip to start up and the program to run. In addition to caching, the SRAM area loads the function functions required for upgrades during compilation.

[0026] FPGA: The core hardware processing unit, which communicates with ARM via the FMC bus, is controlled by ARM, and works with ARM to acquire analog power line data. It also supports iterative firmware upgrades.

[0027] External Flash: As an independent upgrade data storage carrier, its core function is to provide secure and stable cache and storage support for the upgrade process of ARM and FPGA, and it is completely isolated from the internal Flash of ARM and FPGA.

[0028] Figure 1 A flowchart of a remote power equipment upgrade method based on ARM and FPGA according to an embodiment of the present invention is provided. Figure 1 The remote upgrade method for power equipment based on ARM and FPGA in this embodiment may include the following steps: Step 1: The system master station receives the program to be upgraded and completes the communication parameter configuration. It then sends a remote upgrade instruction frame and various sub-package upgrade files to the power monitoring terminal with the ARM+FPGA architecture. The remote upgrade instruction frame includes an upgrade start instruction, upgrade file identifier, and sub-package parameters. The upgrade files are ARM program upgrade files and / or FPGA program upgrade files.

[0029] In existing automatic upgrade solutions, upgrade file transfer uses a fixed frame length (e.g., 1024B / frame). The master station must strictly match the frame length specification preset by the terminal to complete the transmission. If the master station adjusts the frame length (e.g., 512B / frame, 1000B / frame) due to factors such as communication protocol or bandwidth limitations, the terminal cannot recognize data packets with non-preset frame lengths, will directly determine a transmission error and terminate the upgrade, and requires manual adaptation of the frame length parameters before restarting. This results in extremely low flexibility in adapting to different models / configurations of master stations, and is especially unsuitable for scenarios where multiple manufacturers' master stations coexist in power systems.

[0030] To address the aforementioned issues, in this embodiment, the mechanism for sending upgrade files from the system master station to the ARM+FPGA architecture power monitoring terminal is designed as a variable frame length mode. The power monitoring terminal does not need to preset a fixed frame length; it automatically identifies and adapts to upgrade files of any frame length sent by the system master station. This further optimizes the upgrade file transmission mechanism based on the core design of independent and precise ARM / FPGA upgrades. Through variable frame length adaptive processing logic, it achieves high compatibility with master stations configured with different frame lengths, completely solving the problem of existing solutions only supporting fixed frame length transmission and having poor adaptability.

[0031] Before the system master station issues the upgrade file, it first sends a frame length negotiation instruction frame to the power monitoring terminal. The frame length negotiation instruction frame contains the frame length configuration parameters that the system master station intends to use (such as the number of frame length bytes, frame header / frame tail identifier, and total number of packets). The ARM controller parses the frame length negotiation instruction frame and verifies the validity of the frame length (determines whether the frame length is within the range supported by the terminal: such as within 1KB). If it is valid, it sends a frame length adaptation success response and automatically loads the parsing rules for the corresponding frame length, supporting the writing of upgrade frames of variable length within 1KB to the external Flash storage module.

[0032] In this embodiment, the upgrade file is identified by a preset character code; wherein, the ARM program upgrade file corresponds to the first character code, the FPGA program upgrade file corresponds to the second character code, and the power monitoring terminal determines the upgrade target by recognizing the preset character code.

[0033] The data in each sub-package upgrade file contains "ARM / FPGA exclusive identifier bits", such as 01=ARM upgrade, 02=FPGA upgrade.

[0034] Step 2: The power monitoring terminal receives the remote upgrade command frame, parses the remote upgrade command frame, returns a response signal to the system master station, and enters the upgrade ready state.

[0035] Step 3: After the system master station confirms receipt of the response signal, it sends each sub-package upgrade file to the power monitoring terminal in sequence. After receiving each sub-package upgrade file, the power monitoring terminal performs CRC verification on each sub-package upgrade file according to the parsed sub-package parameters and records the CRC checksum of the total package data. After the verification is correct, the corresponding upgrade files are integrated and stored in the external Flash storage module.

[0036] Figure 3 The circuit schematic of an ARM / external Flash-based remote upgrade system for power equipment based on ARM and FPGA is provided according to an embodiment of the present invention. In specific implementation, the external Flash storage module is connected to the ARM controller via an SPI interface; the data transmission rate is not less than 10Mbps, and it is used for temporary storage of subpackaged upgrade files and temporary data during the upgrade process.

[0037] If the CRC check of a sub-package upgrade file fails, the power monitoring terminal sends a retransmission request to the system master station. The system master station then resends the corresponding sub-package upgrade file until the check succeeds or the preset number of retransmissions is reached. If the check still fails after the preset number of retransmissions is reached, the upgrade is terminated, and an upgrade failure message is sent back to the system master station.

[0038] Step 4: The power monitoring terminal determines that the upgrade target is ARM / FPGA based on the parsed upgrade file identifier, responds to the corresponding upgrade start command, and starts the ARM / FPGA upgrade process accordingly. The ARM / FPGA upgrade process is as follows: The ARM / FPGA controller performs a packet CRC read check on the upgrade file in the external Flash storage module, calculates the total packet data CRC checksum II and compares it with the total packet data CRC checksum I. After they match, the ARM / FPGA program storage area is erased, written, and the new program is loaded.

[0039] During the program erasure, data writing, and new program loading processes, the ARM / FPGA controller monitors the upgrade status in real time. If an abnormal interruption occurs, the upgrade operation is immediately stopped, the program version before the upgrade is restored, and the abnormal information is reported back to the system master station.

[0040] After the power monitoring terminal identifies the target for upgrade, before responding to the corresponding upgrade initiation command, it also includes: The power monitoring terminal loads corresponding exclusive parsing rules according to the hardware upgrade requirements of ARM / FPGA, performs hierarchical and targeted parsing of the parameter fields of the remote upgrade command frame, extracts the exclusive parameters of the target device ARM / FPGA, and filters out parameters irrelevant to the target device.

[0041] When the ARM controller performs the upgrade operation, the basic monitoring function module of the power monitoring terminal is kept running normally. The basic monitoring function module is used to collect and temporarily store the basic voltage and current parameters of the power equipment, and then synchronize them to the system master station after the upgrade is completed.

[0042] If the ARM upgrade identifier is detected, the ARM upgrade process begins: First, the ARM upgrade file data in the external Flash is segmented and CRC-checked. The CRC checksum II of the total packet data is calculated and compared with the CRC checksum I of the received total packet data to ensure consistency between the received ARM upgrade file packet and the written upgrade file packet data. After successful verification, the program in the ARM memory erases the internal Flash storage area. After the erasure operation is complete, the upgrade data stored in the external Flash is written to the internal Flash of the ARM, the ARM is started to load the new program, and the ARM upgrade is completed. If the FPGA upgrade flag is identified, the FPGA upgrade process begins: The ARM program performs CRC read verification on the FPGA upgrade file data in the external Flash memory and calculates the CRC checksum II of the total package data. This checksum II is compared with the CRC checksum I of the received total package data to ensure consistency between the received FPGA upgrade file package and the written upgrade file package data. After successful verification, the ARM program initiates control commands to erase the internal Flash memory area of ​​the FPGA. After erasure, it controls the upgrade data in the external Flash memory to be written to the internal FPGA memory area. After data writing, write and read data verification is performed frame by frame until all verifications pass. The FPGA then starts loading the new program, completing the FPGA upgrade.

[0043] In practice, the remote upgrade of power equipment based on ARM and FPGA includes the following steps: Step a: Issue the upgrade file; Log in to the system master station, select and determine the power monitoring terminals to be upgraded, upload the preset upgrade .bin format file to the system master station server and complete the verification. First, send a "frame length negotiation command frame" to the power monitoring terminal. This command frame contains the frame length configuration parameters to be used by the master station (such as the number of frame length bytes, frame header / frame tail identifier, and total number of packets). After receiving it, the ARM controller parses the frame length parameters and verifies their validity (determines whether the frame length is within the range supported by the terminal: within 1KB). If valid, it sends a "frame length adaptation successful" response to the master station and automatically loads the corresponding frame length parsing rules. Upgrade frames of variable length (within 1024 bytes) can be written to the external Flash storage module. The system master station initiates the upgrade file transfer process, sending an upgrade request message to the corresponding power monitoring terminal. Upon receiving the request message, the power monitoring terminal returns a response frame to the system master station and enters the ready state. After receiving the response frame, the system master station sends the .bin format upgrade file to the power monitoring terminal in packet form via 4G.

[0044] Step b: Verify the upgrade file; After receiving the sub-packet data frames of the upgrade file, the power monitoring terminal first stores them in a temporary data buffer, calculates the CRC checksum of each sub-packet, and records the CRC checksum of the total data packet. It then compares the calculated CRC values ​​of the sub-packet data with the CRC values ​​sent in the data frames one by one until a checksum passes. If any data packet fails the checksum verification, an upgrade cancellation command is returned.

[0045] Step c: Identify the upgrade file; After the packet CRC check passes, the external Flash storage module is erased by sector. After erasure, the packet data is stored from the temporary data buffer into the external Flash storage module. The upgrade identifier in the first packet of the upgrade file is identified to determine whether it is an ARM upgrade identifier or an FPGA upgrade identifier. Step d1: ARM upgrade; if the system is identified as having an ARM upgrade identifier, the ARM upgrade process will begin.

[0046] After identifying the upgrade target, the ARM-specific parsing rules are loaded to perform hierarchical and targeted parsing of other parameter fields within the instruction frame, with refined parsing and extraction of parameters specific to the target device. Once data parsing begins, the ARM upgrade file data from the external Flash storage module is first subjected to packet-by-packet CRC read verification, and the total packet data CRC checksum II is calculated and compared with the received total packet data CRC checksum I to ensure consistency between the received ARM upgrade file package and the written upgrade file package data. After successful verification, the ARM internal SRAM area is started during compilation to load the necessary upgrade functions. Sector erasure is then performed on the ARM internal Flash area. After erasure, the external Flash data is written to the ARM internal Flash storage area. The new ARM program is loaded, completing the ARM upgrade.

[0047] Step d2: FPAG upgrade; if the FPAG upgrade identifier is detected, the FPAG upgrade process will begin.

[0048] The ARM FMC interface is 16 bits wide. The FMC interface connects to the FPGA, sharing the address / data bus. Through timing control and chip select, the FPGA can be treated as an external SRAM for fast read / write operations. To reduce the wiring burden caused by high-speed ADCs, the FMC interface uses an address / data bus multiplexing mode. In hardware, only the lower 16 bits (AD[15:0]) of the address / data lines are connected. The FMC divides the HCLK (system clock) and sends it to the external memory as a synchronization clock signal (FMC_CLK), with a division factor CLKDIV of 2-16.

[0049] After the FPGA upgrade process begins, the FPGA-specific parsing rules are loaded to perform hierarchical and targeted parsing of other parameter fields within the instruction frame, and to perform fine-grained parsing and extraction of FPGA-specific parameters. The ARM program performs packet-by-packet CRC read verification on the FPGA upgrade file data from the external Flash, calculates the total packet data CRC checksum II, and compares it with the received total packet data CRC checksum I to ensure that the received FPGA upgrade file packet data is consistent with the written upgrade file packet data. After successful verification, the ARM sends an upgrade command to the FPGA via the FMC bus. Upon receiving the FPGA's response, the FPGA's internal memory is erased. After erasure, the data read from the external Flash is written to the FPGA's internal memory, and write-read data verification is performed frame by frame. After all verifications pass, the new FPGA program is loaded, completing the FPGA upgrade.

[0050] This invention addresses the issue that existing power monitoring equipment using the "ARM+FPGA" architecture employs a generic design for upgrades, lacking customization tailored to the hardware characteristics and collaborative nature of the "ARM+FPGA" architecture. It continues to use a "holistic automatic upgrade" logic. The aim is to provide a highly efficient and flexible remote upgrade method for ARM+FPGA, splitting the automatic upgrade process to achieve independent and precise automatic upgrades for both ARM and FPGA devices. Only the target device's upgrade process is triggered, while non-target devices maintain normal operation. By enabling the ARM to independently control its own upgrade and the FPGA to upgrade flexibly, the coupling between the two upgrades is reduced, ensuring continuous basic fault monitoring functions during upgrades. Simultaneously, the upgrade process is optimized, incorporating multiple verification mechanisms and a variable frame length mechanism to ensure upgrade stability and master station compatibility, improving upgrade reliability and equipment functional iteration capabilities, fully meeting the intelligent operation and maintenance needs of high-voltage transmission lines.

[0051] In one or more embodiments, a remote upgrade system for power equipment based on ARM and FPGA includes: a system master station and a monitoring terminal; the power monitoring terminal is an ARM+FPGA architecture power monitoring terminal; The system master station is configured to: receive the program to be upgraded and complete the communication parameter configuration, and send remote upgrade command frames and various sub-package upgrade files to the power monitoring terminal with ARM+FPGA architecture; the remote upgrade command frame includes upgrade start command, upgrade file identifier and sub-package parameters, and the upgrade file is ARM program upgrade file and / or FPGA program upgrade file; The power monitoring terminal is configured to: receive remote upgrade command frames, parse the remote upgrade command frames, return a response signal to the system master station, and enter the upgrade ready state. The system master station is also configured to: after confirming receipt of the response signal, send the upgrade files of each sub-package to the power monitoring terminal in sequence; The power monitoring terminal is also configured as follows: After receiving each sub-packet upgrade file, perform CRC check on each sub-packet upgrade file according to the parsed sub-packet parameters and record the CRC checksum of the total packet data. After the check is correct, integrate the corresponding upgrade files and store them in the external Flash storage module. Based on the parsed upgrade file identifier, the upgrade target is determined to be ARM / FPGA. The corresponding upgrade start command is responded to and the corresponding ARM / FPGA upgrade process is started. The ARM / FPGA upgrade process is as follows: The ARM / FPGA controller performs a packet CRC read check on the upgrade file in the external Flash storage module, calculates the total packet data CRC checksum II and compares it with the total packet data CRC checksum I. After they match, the ARM / FPGA program storage area is erased, written and the new program is loaded.

[0052] This invention addresses the issue of the "ARM+FPGA" architecture's hardware characteristics and collaborative nature by implementing customized development. Instead of relying on the "overall automatic upgrade" logic, it designs a dual-identifier automatic recognition mechanism to achieve independent and accurate automatic upgrades for ARM / FPGA, reducing device upgrade coupling, optimizing the upgrade process, and adding multiple verification mechanisms and variable frame length mechanisms during the upgrade process to ensure upgrade stability and master station compatibility.

[0053] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for remotely upgrading power equipment based on ARM and FPGA, characterized in that, include: The system master station receives the program to be upgraded and completes the communication parameter configuration, and sends a remote upgrade instruction frame and various sub-package upgrade files to the power monitoring terminal with ARM+FPGA architecture; the remote upgrade instruction frame includes an upgrade start instruction, an upgrade file identifier and sub-package parameters, and the upgrade file is an ARM program upgrade file and / or an FPGA program upgrade file; The power monitoring terminal receives the remote upgrade command frame, parses the remote upgrade command frame, returns a response signal to the system master station, and enters the upgrade ready state. After the system master station confirms receipt of the response signal, it sends the upgrade files of each sub-package to the power monitoring terminal in sequence; After receiving each sub-package upgrade file, the power monitoring terminal performs CRC verification on each sub-package upgrade file according to the parsed sub-package parameters and records the CRC checksum of the total package data. After the verification is correct, the corresponding upgrade files are integrated and stored in the external Flash storage module. Based on the parsed upgrade file identifier, the power monitoring terminal determines that the upgrade target is ARM / FPGA, responds to the corresponding upgrade start command, and initiates the corresponding ARM / FPGA upgrade process. The ARM / FPGA upgrade process is as follows: the ARM / FPGA controller performs a packet CRC read check on the upgrade file in the external Flash storage module, calculates the total packet data CRC checksum II and compares it with the total packet data CRC checksum I. If they match, the ARM / FPGA program storage area is erased, written, and the new program is loaded.

2. The method for remotely upgrading power equipment based on ARM and FPGA as described in claim 1, characterized in that, The upgrade file is identified by a preset character code; wherein, the ARM program upgrade file corresponds to the first character code, the FPGA program upgrade file corresponds to the second character code, and the power monitoring terminal determines the upgrade target by recognizing the preset character code.

3. The method for remotely upgrading power equipment based on ARM and FPGA as described in claim 1, characterized in that, During the program erasure, data writing, and new program loading processes, the ARM / FPGA controller monitors the upgrade status in real time. If an abnormal interruption occurs, immediately stop the upgrade operation, restore the program version before the upgrade, and report the abnormal information to the system main station.

4. The method for remotely upgrading power equipment based on ARM and FPGA as described in claim 1, characterized in that, After the power monitoring terminal identifies the target for upgrade, before responding to the corresponding upgrade initiation command, it also includes: The power monitoring terminal loads corresponding exclusive parsing rules according to the hardware upgrade requirements of ARM / FPGA, performs hierarchical and targeted parsing of the parameter fields of the remote upgrade command frame, extracts the exclusive parameters of the target device ARM / FPGA, and filters out parameters irrelevant to the target device.

5. The method for remotely upgrading power equipment based on ARM and FPGA as described in claim 1, characterized in that, If the CRC check of a certain sub-package upgrade file fails, the power monitoring terminal sends a retransmission request to the system master station; the system master station re-issues the corresponding sub-package upgrade file until the check succeeds or the preset number of retransmissions is reached.

6. The method for remotely upgrading power equipment based on ARM and FPGA as described in claim 5, characterized in that, If the verification still fails after reaching the preset number of retransmissions, the upgrade will be terminated, and the upgrade failure information will be reported to the system master station.

7. The method for remotely upgrading power equipment based on ARM and FPGA as described in claim 1, characterized in that, Before the system master station issues the upgrade file, it first sends a frame length negotiation instruction frame to the power monitoring terminal. The frame length negotiation instruction frame contains the frame length configuration parameters that the system master station intends to use. The ARM controller parses the frame length negotiation instruction frame and verifies the validity of the frame length. If it is valid, it sends a frame length adaptation success response and automatically loads the parsing rules for the corresponding frame length.

8. The method for remotely upgrading power equipment based on ARM and FPGA as described in claim 1, characterized in that, When the ARM controller performs the upgrade operation, the basic monitoring function module of the power monitoring terminal is kept running normally. The basic monitoring function module is used to collect and temporarily store the basic voltage and current parameters of the power equipment, and then synchronize them to the system master station after the upgrade is completed.

9. The method for remotely upgrading power equipment based on ARM and FPGA as described in claim 1, characterized in that, The mechanism for sending upgrade files from the main system station to the power monitoring terminal with ARM+FPGA architecture is designed as a variable frame length mode. The power monitoring terminal does not need to preset a fixed frame length and can automatically identify and adapt to upgrade files of any frame length sent by the main system station.

10. A remote upgrade system for power equipment based on ARM and FPGA, characterized in that, The remote upgrade method for power equipment based on ARM and FPGA as described in any one of claims 1-9 includes: a system master station and a monitoring terminal; the power monitoring terminal is an ARM+FPGA architecture power monitoring terminal; The system master station is configured to: receive the program to be upgraded and complete the communication parameter configuration, and send a remote upgrade instruction frame and various sub-package upgrade files to the power monitoring terminal with ARM+FPGA architecture; the remote upgrade instruction frame includes an upgrade start instruction, an upgrade file identifier and sub-package parameters, and the upgrade file is an ARM program upgrade file and / or an FPGA program upgrade file; The power monitoring terminal is configured to: receive the remote upgrade instruction frame, parse the remote upgrade instruction frame, return a response signal to the system master station, and enter the upgrade ready state. The system master station is also configured to: after confirming receipt of the response signal, send each sub-package upgrade file to the power monitoring terminal in sequence; The power monitoring terminal is also configured to: After receiving each sub-packet upgrade file, perform CRC check on each sub-packet upgrade file according to the parsed sub-packet parameters and record the CRC checksum of the total packet data. After the check is correct, integrate the corresponding upgrade files and store them in the external Flash storage module. Based on the parsed upgrade file identifier, the upgrade target is determined to be ARM / FPGA. The corresponding upgrade start command is responded to and the corresponding ARM / FPGA upgrade process is started. The ARM / FPGA upgrade process is as follows: The ARM / FPGA controller performs a packet CRC read check on the upgrade file in the external Flash storage module, calculates the total packet data CRC checksum II and compares it with the total packet data CRC checksum I. After they match, the ARM / FPGA program storage area is erased, written and the new program is loaded.

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