Last-level cache dirty data pre-eviction method and device, electronic equipment and storage medium

Abstract

The present disclosure provides a last level cache dirty data pre-eviction method and device, electronic equipment and storage medium, wherein the method comprises: detecting whether the last level cache is in an idle state, and detecting whether a dynamic random access memory (DRAM) controller is in a low load state; when the last level cache is in the idle state and the DRAM controller is in the low load state, triggering an active write-back operation of dirty data in the last level cache; during the execution of the active write-back operation, when it is detected that the last level cache is no longer in the idle state or the DRAM controller is no longer in the low load state, stopping the active write-back operation. The present disclosure actively shifts the dirty data write-back operation to the system idle period for execution by establishing a cooperative gating mechanism of the cache idle state and the DRAM low load state, thereby reducing the business access delay. At the same time, the write-back operation is started only when the system is truly idle and stopped immediately when the business arrives, ensuring zero interference to normal business and high reliability.

Description

Technical Field

[0001] This disclosure relates to the field of computer storage technology, and more specifically, to a method, apparatus, electronic device, and storage medium for pre-eviction of dirty data in the last-level cache. Background Technology

[0002] In existing System-on-a-Chip (SoC) memory subsystems, dirty data eviction from the Last-Level Cache (LLC) employs a passively triggered mechanism. Specifically, a write-back operation is triggered only when a cache replacement event occurs—for example, when a new cache line needs to be filled into a cache set that is full and the selected cache line to be replaced is dirty. This write-back writes the dirty data to Dynamic Random Access Memory (DRAM) to free up space. This eviction timing is entirely determined by the cache replacement event and is independent of the current system bus load and DRAM controller queue pressure.

[0003] This passive triggering mechanism means that write-back operations for dirty data are always passively executed when a cache replacement event occurs. The cache replacement event itself signifies that the system is in a busy period with frequent memory accesses and limited cache resources. Executing a write-back operation at this time will superimpose write-back traffic onto the already busy bus and DRAM controller, causing intense resource contention between write-back operations and normal business read requests and data backfill responses. This significantly increases the latency of business access and reduces overall system performance. Summary of the Invention

[0004] This disclosure provides at least one method, apparatus, electronic device, and storage medium for pre-eviction of dirty data in the final-level cache, in order to solve the aforementioned technical problems.

[0005] In a first aspect, embodiments of this disclosure provide a method for pre-eviction of dirty data in the last-level cache, including:

[0006] Detect whether the last-level cache is idle and whether the dynamic random access memory (DRAM) controller is under low load. When the last-level cache is in an idle state and the DRAM controller is in a low-load state, an active write-back operation is triggered for the dirty data in the last-level cache. During the active write-back operation, the active write-back operation is stopped when it is detected that the last-level cache is no longer in an idle state or the DRAM controller is no longer in a low-load state.

[0007] In one possible implementation, detecting whether the last-level cache is in an idle state includes: The load status of the miss status holding register of the last-level cache and the load status of the pipeline entry of the last-level cache are detected. When the load of the miss status holding register is lower than a first preset condition and the load of the pipeline inlet is lower than a second preset condition, the last-level cache is determined to be in an idle state.

[0008] In one possible implementation, the first preset condition is: the miss status holding register is completely idle, or the occupancy rate of the miss status holding register is lower than a preset first threshold. The second preset condition is: there are no pending memory access requests at the pipeline inlet, or the request arrival rate at the pipeline inlet is lower than a preset second threshold.

[0009] In one possible implementation, detecting whether the dynamic random access memory (DRAM) controller is in a low-load state includes: Detect the current depth of the request queue inside the DRAM controller; Compare the current depth with the preset depth; When the current depth is lower than the preset depth, the DRAM controller is determined to be in a low-load state; when the current depth reaches or exceeds the preset depth, the DRAM controller is determined to be not in a low-load state.

[0010] In one possible implementation, triggering the active write-back operation of dirty data in the last-level cache includes: When the last-level cache is detected to be in an idle state and the DRAM controller is in a low-load state, a preset delay time is waited for the state to continue until the delay time is reached before the active write-back operation of dirty data in the last-level cache is initiated.

[0011] In one possible implementation, the step of waiting for a preset delay time, and then initiating an active write-back operation on the dirty data in the last-level cache after the state has persisted for the delay time, includes: Start the configurable delay counter to begin timing; During the timing period, it is continuously monitored whether the final-level cache remains in an idle state and whether the DRAM controller remains in a low-load state. If the last-level cache is no longer idle or the DRAM controller is no longer under low load during the timing period, the delay counter is reset to terminate the current wait. If the timer reaches the preset delay time and the above conditions are continuously met, the waiting ends and the active write-back operation is initiated.

[0012] In one possible implementation, triggering the active write-back operation of dirty data in the last-level cache includes: Initiate the pre-eviction state machine; The pre-eviction state machine scans the dirty cache lines in the last-level cache, selects a dirty cache line, generates a write-back request, and sends the data of the cache line and the target physical address to the DRAM controller. After receiving the write-back complete indication returned by the DRAM controller, the cache line is marked as clean or invalid. Continue scanning and writing back the next dirty cache line until the pre-eviction state machine is stopped or all dirty cache lines have been written back.

[0013] In one possible implementation, the dirty cache lines in the last-level cache are scanned according to any of the following scanning methods: Scan sequentially according to the increasing order of the cache group index; Dirty cache lines are selected for write-back in the order of least recently used priority; Prioritize writing back dirty cache lines that are physically adjacent; Write back in order of the dirty mark time from earliest to latest.

[0014] In one possible implementation, stopping the active write-back operation includes: During the active write-back operation, if it is detected that the last-level cache is no longer in an idle state or the DRAM controller is no longer in a low-load state, the write-back operation of the currently executing cache line is allowed to continue to complete, and subsequent dirty cache line write-back operations are stopped after the write-back operation is completed.

[0015] In one possible implementation, it also includes: The DRAM controller outputs a grant signal to the last-level cache via a sideband signal line. The grant signal is used to indicate whether the DRAM controller is in a low-load state.

[0016] Secondly, this disclosure also provides a pre-eviction device for dirty data in the final-level cache, comprising: The detection module is used to detect whether the last-level cache is in an idle state and whether the dynamic random access memory (DRAM) controller is in a low-load state. The triggering module is used to trigger an active write-back operation of dirty data in the last-level cache when the last-level cache is in an idle state and the DRAM controller is in a low-load state. An execution module is configured to stop the active write-back operation during the execution of the active write-back operation when it is detected that the last-level cache is no longer in an idle state or the DRAM controller is no longer in a low-load state.

[0017] Thirdly, this disclosure also discloses an electronic device comprising: a processor, a memory, and a bus, wherein the memory stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor communicates with the memory via the bus, and when the machine-readable instructions are executed by the processor, the final-level cache dirty data pre-eviction method is performed as described in any one of the first aspects and various embodiments thereof.

[0018] Fourthly, this disclosure also provides a computer-readable storage medium storing a computer program that, when executed by a processor, performs the final-level cache dirty data pre-eviction method as described in any one of the first aspects and its various embodiments.

[0019] The aforementioned method, apparatus, electronic device, and storage medium for pre-eviction of dirty data in the last-level cache detect whether the last-level cache is in an idle state and whether the dynamic random access memory (DRAM) controller is in a low-load state. When the last-level cache is in an idle state and the DRAM controller is in a low-load state, an active write-back operation for dirty data in the last-level cache is triggered. During the active write-back operation, if it is detected that the last-level cache is no longer in an idle state or the DRAM controller is no longer in a low-load state, the active write-back operation is stopped. This disclosure establishes a collaborative gating mechanism between cache idle state and DRAM low-load state, actively transferring dirty data write-back operations to system idle periods, avoiding resource contention between write-back traffic and normal requests during busy periods, and reducing service access latency. Simultaneously, the write-back operation only starts when the system is truly idle and stops immediately when service arrives, ensuring zero interference with normal services and high reliability.

[0020] Other advantages of this disclosure will be explained in more detail in conjunction with the following description and accompanying drawings.

[0021] It should be understood that the above description is merely an overview of the technical solution of this disclosure, so as to enable a general understanding of the technical means of this disclosure and to implement it in accordance with the contents of the specification. In order to make the above-mentioned objects, features and advantages of this disclosure more apparent and understandable, preferred embodiments are described in detail below with reference to the accompanying drawings. Attached Figure Description

[0022] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings used in the embodiments will be briefly described below. The accompanying drawings are incorporated in and constitute a part of this specification. These drawings illustrate embodiments conforming to this disclosure and, together with the specification, serve to illustrate the technical solutions of this disclosure. It should be understood that the drawings only illustrate certain embodiments of this disclosure and should not be considered as a limitation on the scope of protection. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort. Furthermore, the same reference numerals denote the same components throughout the drawings. In the drawings: Figure 1 A flowchart of a method for pre-eviction of dirty data in the last-level cache provided by an embodiment of this disclosure is shown; Figure 2 This diagram illustrates the working principle between the cache controller and the DRAM controller in the final-level cache dirty data pre-eviction method provided in this embodiment of the present disclosure. Figure 3 The flowchart illustrating the pre-eviction triggering and execution process in the final-level cache dirty data pre-eviction method provided in this embodiment of the disclosure is shown. Figure 4 The flowchart illustrating the generation of the grant signal on the DRAM controller side in the final-level cache dirty data pre-eviction method provided in this embodiment of the present disclosure is shown. Figure 5 A schematic diagram of a dirty data pre-eviction device for the final-level cache provided in an embodiment of this disclosure is shown; Figure 6 A schematic diagram of an electronic device provided in an embodiment of the present disclosure is shown. Detailed Implementation

[0023] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0024] In the description of embodiments disclosed herein, it should be understood that terms such as “comprising” or “having” are intended to indicate the presence of the disclosed features, figures, steps, behaviors, components, portions or combinations thereof in this specification, and do not exclude the possibility of the presence of one or more other features, figures, steps, behaviors, components, portions or combinations thereof.

[0025] Unless otherwise stated, " / " means "or". For example, A / B can mean A or B. In this article, "and / or" is merely a way of describing the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can mean: A alone, A and B at the same time, and B alone.

[0026] The terms "first," "second," etc., are used only for ease of description to distinguish identical or similar technical features and should not be construed as indicating or implying the relative importance or number of these technical features. Therefore, a feature defined by "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, the term "multiple" means two or more.

[0027] Research has revealed that in existing SoC memory subsystems, the eviction of dirty cache lines in the last-level cache employs a passive triggering mechanism: a write-back operation is triggered only when a new cache line needs to be filled into a cache set that is full and the selected cache line to be replaced is dirty, thus freeing up space for the new cache line. The timing of the eviction is entirely determined by the cache replacement event and is independent of the current system bus load and DRAM controller queue pressure.

[0028] The existing technical solutions mainly have the following problems: 1) Eviction timing overlaps with peak business periods. Passive eviction only occurs when the cache set is full and needs replacement, which precisely means that the system is frequently accessing memory and cache resources are strained. At this time, write-back operations of dirty cache lines compete with business requests for bus bandwidth, resulting in traffic overlap and exacerbating bus contention.

[0029] 2) Simultaneous contention among multiple traffic types leads to latency degradation. During peak business hours, three types of traffic coexist on the bus: read requests with cache misses, response traffic from DRAM data refilling, and write-back traffic from dirty cache line evictions. These three types compete for limited bus bandwidth, causing the latency of valid requests (read requests and refilling) to be dragged down by the write-back traffic, resulting in a degraded system performance.

[0030] 3) Concentrated pressure on the DRAM controller queue. Write-back requests for dirty cache lines flood the DRAM controller's request queue during peak business hours, occupying queue capacity, squeezing the queuing space for valid read requests, and further extending the processing path for cache misses.

[0031] 4) Bandwidth waste during system idle periods. The existing mechanism does not perform any eviction operations when the system is idle, leaving bus bandwidth and DRAM controller processing power idle and unused to preemptively process dirty data, resulting in resource waste.

[0032] To at least partially address one or more of the aforementioned problems and other potential issues, this disclosure provides at least one last-level cache dirty data pre-eviction scheme that proactively pre-evictions dirty cache lines when the cache is idle and DRAM queue pressure is low, thereby shifting write-back traffic from busy periods to idle periods.

[0033] To facilitate understanding of this embodiment, a detailed description of the last-level cache dirty data pre-eviction method disclosed in this disclosure embodiment will be provided first. The execution subject of the last-level cache dirty data pre-eviction method provided in this disclosure embodiment is generally an electronic device with a certain computing power. Considering that this disclosure embodiment can mainly be applied to SoC storage subsystems, the electronic device here can be, for example, a last-level cache (LLC) controller or other storage controllers. In some possible implementations, the last-level cache dirty data pre-eviction method can be implemented by the processor calling computer-readable instructions stored in memory.

[0034] See Figure 1 The diagram illustrates a flowchart of a method for pre-eviction of dirty data in the final-level cache provided in this embodiment, the method comprising the following steps S101-S103: S101: Detect whether the last-level cache is idle and whether the dynamic random access memory (DRAM) controller is under low load. S102: When the last-level cache is idle and the DRAM controller is under low load, an active write-back operation for dirty data in the last-level cache is triggered. S103: During the active write-back operation, if it is detected that the last-level cache is no longer in an idle state or the DRAM controller is no longer in a low-load state, the active write-back operation is stopped.

[0035] This embodiment first detects whether the last-level cache is idle and simultaneously detects whether the dynamic random access memory (DRAM) controller is under low load. An active write-back operation for dirty data in the last-level cache is triggered only if both conditions are met. During the active write-back operation, the operation is immediately stopped once it is detected that the last-level cache is no longer idle or the DRAM controller is no longer under low load.

[0036] Traditional passive eviction always performs write-back only during cache replacement (i.e., the busiest time of the system), causing write-back traffic to fiercely compete with business requests for the bus. The embodiments of this disclosure bind the initiation conditions of the write-back operation to the real-time idle state of the system: write-back only begins when the cache is truly idle and the DRAM is capable of receiving additional requests, thereby separating write-back traffic from busy periods; simultaneously, pre-eviction will quickly stop whenever a business request occurs or DRAM pressure increases, avoiding interference with normal business operations.

[0037] like Figure 2 , Figure 3 As shown, last-level cache detection can involve the last-level cache controller monitoring its internal Miss Status Holding Register (MSHR) and pipeline entry points. When all MSHR entries are in good condition (e.g., no cache miss requests are being processed) and the pipeline entry points are in good condition (e.g., no new memory access requests are arriving), the cache side is determined to be in an idle state.

[0038] like Figure 2 , Figure 4 As shown, DRAM controller detection can involve the DRAM controller monitoring the current depth of its internal request queue and comparing this depth with a configurable preset threshold (e.g., depth 8, threshold 4). When the queue depth is below the threshold, the DRAM controller outputs a high-level grant signal (grant=1) to the last-level cache controller via a sideband signal line, indicating that it is in a low-load state; when the queue depth reaches or exceeds the threshold, it outputs a low-level signal (grant=0), indicating that it is not in a low-load state.

[0039] When the last-level cache controller detects that the cache is idle (MSHR is idle and there are no pipeline requests) and the DRAM grant signal is high, it determines that the two conditions are met and then triggers an active write-back operation on the dirty cache lines in the last-level cache. This avoids performing dirty data write-back during the system's busy period, that is, it transfers the write-back operation to the system's idle period, thereby reducing the competition between write-back traffic and normal business requests and reducing business access latency.

[0040] During the active write-back operation, the last-level cache controller continuously monitors the two conditions mentioned above. Once it detects that the cache is no longer idle (e.g., a new request arrives at the pipeline entry point) or the DRAM grant signal goes low (indicating increased queue pressure), the active write-back operation is immediately stopped to avoid interfering with normal business operations.

[0041] To accurately determine whether the last-level cache is idle, the specific implementation of this disclosure detects the load status of the MSHR and the pipeline entry point. When the load of the MSHR is lower than a first preset condition and the load of the pipeline entry point is lower than a second preset condition, the last-level cache is determined to be idle.

[0042] The first prerequisite could be that all MSHRs are available (e.g., Figure 2 (As shown), or it could be that the MSHR utilization rate is lower than a preset first threshold (e.g., not exceeding 25% of the total). The second preset condition could be that there are no pending memory access requests at the pipeline entry point (e.g., Figure 2(As shown), it can also be that the rate at which requests arrive at the pipeline entry point is lower than a preset second threshold (e.g., no more than 1 request per 100 cycles).

[0043] The first and second preset conditions can be combined arbitrarily: for example, all MSHRs are idle combined with no requests in the pipeline, ensuring that there are no requests being processed or waiting, which is suitable for systems with zero tolerance for interference; another example is that the MSHR utilization rate is below a threshold combined with the pipeline request rate being below a threshold, which allows pre-eviction to be triggered even under extremely low load, thereby gaining more write-back opportunities; yet another example is that all MSHRs are idle combined with the pipeline request rate being below a threshold, or the MSHR utilization rate being below a threshold combined with no requests in the pipeline. These determination methods can be flexibly configured or used in combination according to system requirements.

[0044] This disclosure introduces configurable condition combinations, enabling the system to flexibly adjust the strictness of idle determination according to the application scenario, maximizing the pre-eviction effect without interfering with normal business operations.

[0045] Whether the DRAM controller is in a low-load state is determined by detecting the current depth of its internal request queue. Specifically, the current depth is compared with a preset depth (e.g., 4, 8, or 16, which can be configured via registers): if the current depth is lower than the preset depth, the DRAM is determined to be in a low-load state; if the preset depth is reached or exceeded, it is not in a low-load state.

[0046] The DRAM controller internally maintains a request queue to temporarily store read and write requests from various initiating endpoints. This queue has depth counting logic, which can output the number of requests currently pending in the queue (i.e., the queue depth) in real time.

[0047] In specific implementation, such as Figure 2 As shown, a new comparator circuit (i.e., a depth comparator) is added to the DRAM controller. One input of the comparator is connected to the output of the queue depth counting logic, and the other input is connected to a programmable register that stores a preset depth threshold. The comparator compares the current queue depth with the preset depth. If the current depth is less than the preset depth, the comparator outputs a high level (logic 1), indicating that the DRAM controller is in a low-load state and has sufficient capacity to receive additional write-back requests; If the current depth is greater than or equal to the preset depth, the comparator outputs a low level (logic 0), indicating that the DRAM controller is under high load and additional write-back requests should be avoided.

[0048] The output of this comparator is the grant signal, which is transmitted to the final-level cache controller via a separate sideband signal line.

[0049] Since write-back requests are only allowed to be injected when the queue depth is below a threshold, they do not crowd out the queuing space for valid read requests, thus ensuring the quality of service on the DRAM side. Whenever the queue depth rises above the threshold due to an influx of business requests, the DRAM controller automatically cancels the low load indication, and the cache side stops sending new write-back requests.

[0050] In existing technologies, DRAM controllers lack the ability to report their load status to the cache controller, leading to the cache blindly sending write-back requests, which may exacerbate DRAM queue congestion. This disclosure addresses this issue by achieving precise load-aware flow control through queue depth threshold comparison. Specifically, pre-eviction is only allowed when the DRAM is capable of handling write-back requests, ensuring that write-back traffic does not crowd out valid read requests; simultaneously, it reuses existing queue depth counting logic, resulting in minimal hardware overhead (requiring only one comparator).

[0051] In systems where business traffic exhibits bursty characteristics, there may be brief idle intervals between two requests. If pre-eviction is initiated immediately during such intervals, it is very likely that a new request will interrupt the writing of a cached line, causing the state machine to start and stop frequently, which will increase additional overhead.

[0052] Therefore, in this embodiment of the present disclosure, after detecting that both conditions are met, the write-back is not performed immediately. Instead, a preset delay time is waited for the state to continue until the delay time is reached before the active write-back operation is initiated. This is specifically achieved through the following steps: Step 1: Start the configurable delay counter to begin timing; Step 2: During the timing period, continuously monitor whether the final cache remains idle and whether the DRAM controller remains under low load. Step 3: If the last-level cache is no longer idle or the DRAM controller is no longer under low load during the timing period, reset the delay counter and terminate the current wait. Step 4: If the timer reaches the preset delay time and the above conditions are continuously met, the waiting ends and the active write-back operation is initiated.

[0053] like Figure 2 As shown, when the final-level cache controller first detects that the cache is free and grant=1, it does not immediately trigger a write-back. Instead, it starts a configurable delay counter to begin timing. The preset delay time T can be set via register programming, and its typical value ranges from tens to hundreds of clock cycles.

[0054] During the delay counter's timing, the cache free status and the grant signal are continuously monitored. If either condition is no longer met during this period (e.g., a new memory access request arrives, or the grant signal goes low), the delay counter is immediately reset, the current wait is terminated, and pre-eviction is not initiated.

[0055] If the delay counter reaches the preset time T, and both conditions remain met during this period, the system is confirmed to be in a stable idle state, and only then will the active write-back operation be triggered.

[0056] As can be seen, considering that immediate triggering without delay is prone to frequent start-stop of pre-eviction due to short idle gaps, resulting in additional power consumption, the embodiments of this disclosure filter out short idle gaps by using a configurable delay time, and start pre-eviction only after the system has truly entered a stable idle period, thereby improving the efficiency of pre-eviction and reducing unnecessary state switching overhead.

[0057] Once the delay condition is met, the active write-back operation of this embodiment can be performed according to the following steps: Step 1: Start the pre-eviction state machine; Step 2: The pre-eviction state machine scans the dirty cache lines in the last-level cache. After selecting a dirty cache line, a write-back request is generated and the data of the cache line and the target physical address are sent to the DRAM controller. Step 3: After receiving the write-back completion indication from the DRAM controller, mark the cache line as clean or invalid. Step 4: Continue scanning and writing back the next dirty cache line until the pre-eviction state machine is stopped or all dirty cache lines have been written back.

[0058] Combination Figure 3 The flowchart shown illustrates the pre-eviction triggering and execution process. The workflow of the pre-eviction state machine is as follows: 1) Start the state machine: The pre-eviction state machine enters the scan state from the idle state.

[0059] 2) Scanning dirty cache lines: The state machine traverses all cache lines in the last-level cache according to a certain scanning strategy, checking the dirty flag bit of each cache line. If the dirty flag of a cache line is 1, it means that the cache line contains dirty data that has not yet been written back to DRAM.

[0060] 3) Select and Write Back: After selecting a dirty cache line, the state machine generates a write back request, which sends the data of the cache line (usually 64 bytes or the same as the cache line size) and the target physical address to the request queue of the DRAM controller.

[0061] 4) Waiting for completion: The state machine waits for the DRAM controller to return a write-back completion indication signal. After successfully writing data to the DRAM, the DRAM controller sends an acknowledgment signal to the cache controller.

[0062] 5) Update state: After receiving the write-back completion indication, the state machine updates the state of the cache line from "dirty" to "clean" (or marks it as invalid) to free up cache space or avoid repeated write-backs.

[0063] 6) Continue looping: The state machine continues to scan the next dirty cache line, repeating steps 3-5 above, until either of the following occurs: (a) the pre-eviction state machine receives a stop instruction; or (b) all dirty cache lines have been written back.

[0064] When scanning dirty cache lines, this disclosure provides four optional methods that can be configured or selected according to system requirements: Firstly, scan sequentially according to the increasing order of the cache group index. This strategy is simple to implement and has the lowest hardware overhead.

[0065] Secondly, the Least Recently Used (LRU) priority scan prioritizes writing back dirty cache lines. This strategy helps improve cache utilization because LRU lines are less likely to be accessed again, making the space freed up after writing back more efficient.

[0066] Thirdly, address-adjacent batch write-back prioritizes dirty cache lines with adjacent physical addresses and combines them into batch write-back requests. This strategy can improve DRAM line hit rate because adjacent addresses often belong to the same DRAM line, and batch write-back can reduce the number of DRAM line activations / precharges.

[0067] Fourthly, aging-priority scanning prioritizes writing back dirty data that has not been cleaned up for a long time, according to the order of dirty marking time from earliest to latest. This strategy can prevent dirty data from remaining in the cache for a long time and reduce the risk of data loss due to unexpected power outages.

[0068] During proactive write-back execution, service requests may arrive at any time, or DRAM queue pressure may suddenly increase. To avoid pre-eviction interfering with normal services, embodiments of this disclosure continuously monitor stopping conditions. When it is detected that the last-level cache is no longer free or the DRAM is no longer in a low-load state, the current transmission is not immediately interrupted. Instead, the write-back operation of the currently executing cache line is allowed to continue to complete. Subsequent dirty cache line write-back operations are stopped only after the write-back operation is completed.

[0069] During the pre-eviction state machine's active write-back operation (e.g., while writing back the Nth dirty cache line), the last-level cache controller continuously monitors two stopping conditions: Condition 1: A new memory access request appears at the pipeline entry point (the cache is no longer idle); Condition 2: The grant signal output by the DRAM controller goes low (DRAM queue pressure increases and it is no longer in a low load state).

[0070] When any of the above conditions are met, the stop control logic immediately sets a stop flag. However, to avoid compromising the integrity of bus transactions, the pre-eviction state machine does not immediately interrupt the currently ongoing write-back operation. Specifically: If the stop condition is triggered when the state machine is in the process of writing back a cache line (i.e., a write-back request has been sent, but a completion indication from DRAM has not yet been received), the state machine continues to wait for the write-back operation to complete.

[0071] Once the write-back completion indication is received from DRAM, the state machine updates the state of that cache line (marking it as clean or invalid) and then checks the stop flag. Since the stop flag has been set, the state machine no longer scans for the next dirty cache line, but exits the active write-back state and returns to the idle standby state.

[0072] It's important to note that the granularity of the stop action is "one cache line." This means that the write-back operation on the currently executing cache line will definitely complete, while subsequent write-back operations that haven't yet started are canceled. This design ensures that each write-back transaction is complete, preventing invalid transactions from being interrupted midway and avoiding bus protocol errors. In this way, bus resources can be quickly relinquished to normal business operations (with a maximum delay of waiting for one cache line write-back, typically a few dozen clock cycles), while also guaranteeing the integrity of bus transactions and the correctness of data.

[0073] To facilitate further understanding, the method for pre-eviction of dirty data in the final-level cache provided in this disclosure embodiment will be discussed in conjunction with the following... Figures 2-4 Taking a complete runtime sequence as an example, the specific working process of the embodiments of this disclosure will be described in detail.

[0074] When the system is running, the last-level cache controller first continuously monitors the MSHR status and pipeline entry status. When all MSHR entries are idle (i.e., no pending memory access requests) and no new memory access requests arrive at the pipeline entry point, the last-level cache controller determines that it is in an idle state. Simultaneously, the last-level cache controller continuously samples the 1-bit grant signal output by the DRAM controller through a separate sideband signal line. A high level for this signal indicates that the DRAM controller's request queue depth is below a preset threshold (i.e., it is in a low-load state). The two-condition gating only passes when the cache is idle and grant is high.

[0075] After the dual-condition gating is passed, the last-level cache controller does not immediately trigger a write-back. Instead, it starts a configurable delay counter to filter out brief idle gaps and avoid the additional overhead caused by frequent start-stop pre-eviction.

[0076] During the delay timeout, the last-level cache controller continuously checks whether the two conditions are still met: if either condition is no longer met during the timeout (e.g., a new memory access request arrives at the pipeline entry point, or grant goes low), the counter is immediately reset and pre-eviction is not started; only when the delay time T expires and the two conditions remain met throughout the timeout is the system confirmed to be in a stable idle state, at which point the pre-eviction state machine is started.

[0077] After the pre-eviction state machine starts, it enters the active write-back execution phase. The state machine first scans the dirty cache lines in the last-level cache. The scanning strategy can be sequential scanning (incrementing traversal by group index) or a priority scan based on a replacement strategy (e.g., prioritizing the least recently used dirty cache lines). The specific strategy can be configured via registers. After selecting a dirty cache line, the state machine generates a write-back request, sending the data of that cache line and the target physical address to the DRAM controller. Upon receiving the write-back request, the DRAM controller adds it to the normal request queue for scheduling and execution. After the write-back request is completed, the DRAM controller returns a completion indication to the cache side, and the last-level cache controller marks the cache line as clean (or marks it as invalid to release space, depending on the implementation strategy). Subsequently, the state machine repeats the above process, continuing to scan and write back the next dirty cache line until a stop instruction is received or all dirty cache lines have been written back.

[0078] During the active write-back process, the final-level cache controller continuously monitors the stop conditions: (1) a new memory access request appears at the pipeline entry point, and (2) the grant signal goes low (indicating that the DRAM queue pressure is rising). Either condition triggers a stop flag. After the stop flag takes effect, the currently executing cache line write-back operation continues to complete, which is to ensure the integrity of bus transactions. Once the cache line write-back is complete, the pre-eviction state machine exits the working state and returns to normal standby. If both conditions are subsequently met again and continue for a delay time T, the pre-eviction state machine can be restarted to continue scanning from the interrupt location (or start from the beginning, depending on the implementation strategy).

[0079] A typical workflow sequence is as follows: Assuming that at time T0, the service request ends, MSHR is cleared, and there are no new requests at the pipeline entry point, the last-level cache enters an idle state; at time T1, the DRAM controller queue depth drops below a preset threshold, and the grant signal is set to high; after a configurable delay time T, at time T2, the delay counter expires, the pre-eviction state machine starts, and begins scanning dirty cache lines; at time T3, the first write-back request for a dirty cache line is issued; subsequently, write-back operations continue to be executed until at time T5, a new service request arrives (or the grant signal goes low), and the stop flag takes effect; at time T6, the current cache line write-back is completed, pre-eviction immediately stops, and normal services take over the bus. The delay from idle detection to pre-eviction initiation is the configurable parameter T, and the delay from stop triggering to actual stop is equal to the remaining time of the current cache line write-back operation (usually several clock cycles). This design ensures that pre-eviction does not affect the response latency of normal services.

[0080] Thus, the final-level cache dirty data pre-eviction provided in this embodiment of the present disclosure can achieve the following technical effects: 1) Performance: During peak business hours, the write-back traffic of dirty cache lines has already been absorbed during the previous idle period, eliminating the competition between valid requests and eviction write-back traffic on the bus. When a cache miss occurs, data only needs to be read from DRAM and filled back, without having to wait for the dirty cache line write-back to complete before freeing up space. The cache miss processing path is significantly shortened, and memory access latency is reduced.

[0081] 2) In terms of service quality: The DRAM controller's request queue capacity is allocated more to valid read requests and responses, reducing queue queuing latency. Pre-eviction write-back requests are only injected when the DRAM queue pressure is low, without increasing the scheduling burden on the DRAM side, achieving zero interference between write-back traffic and valid service traffic.

[0082] 3) In terms of bandwidth utilization: The bus bandwidth and DRAM processing capacity during the system's idle period are originally idle. This disclosure uses these idle resources to perform dirty data write-back in advance, thereby improving the overall utilization of system bandwidth and realizing traffic peak shaving and valley filling in the time dimension.

[0083] 4) Resource aspect: On the cache side, the existing MSHR idle detection logic and pipeline entry monitoring logic are reused, with only a delay counter and a pre-eviction state machine added (the amount of logic is extremely small); on the DRAM controller side, the existing queue depth counting logic is reused, with only a comparator and a 1-bit grant signal output added. No new storage entries or additional buffers are required, resulting in minimal hardware overhead.

[0084] 5) In terms of reliability: The immediate stop mechanism ensures that pre-eviction will not compete for resources with normal business operations. The stop boundary is based on the integrity of bus transactions, and incomplete transactions with mid-interruption will not occur. The configurable delay time T filters out brief idle gaps and avoids jitter caused by frequent start-stop operations.

[0085] In the description of this specification, references to terms such as "some possible implementations," "some implementations," "example," "specific example," or "some examples" indicate that a specific feature, structure, material, or characteristic described in connection with that implementation or example is included in at least one implementation or example of this disclosure, and the aforementioned terms do not necessarily refer to the same implementation or example. Furthermore, the described specific features, structures, materials, or characteristics can be combined in a suitable manner in any one or more implementations or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different implementations or examples described in this specification, as well as the features of different implementations or examples.

[0086] Regarding the method flowcharts of embodiments of this disclosure, certain operations are described as different steps performed in a certain order. Such flowcharts are illustrative and not restrictive. Some steps described herein may be grouped together and performed in a single operation, or some steps may be divided into multiple sub-steps, and some steps may be performed in an order different from that shown herein. The various steps shown in the flowcharts may be implemented in any way by any circuit structure and / or tangible mechanism (e.g., software running on a computer device, hardware (e.g., logic functions implemented by a processor or chip), and / or any combination thereof).

[0087] Those skilled in the art will understand that in the methods described in the above specific embodiments, the order in which the steps are written does not imply a strict execution order, and the specific execution order of each step should be determined by its function and possible internal logic.

[0088] Based on the same inventive concept, this disclosure also provides a last-level cache dirty data pre-eviction device corresponding to the last-level cache dirty data pre-eviction method. Since the principle of the device in this disclosure for solving the problem is similar to the last-level cache dirty data pre-eviction method described above, the implementation of the device can refer to the implementation of the method, and the repeated parts will not be described again.

[0089] Reference Figure 5 The diagram shown is a schematic of a dirty data pre-eviction device for the last-level cache provided in an embodiment of this disclosure. The device includes: a detection module 201, a triggering module 202, and an execution module 203; wherein, The detection module 201 is used to detect whether the last-level cache is in an idle state and whether the dynamic random access memory (DRAM) controller is in a low-load state. Trigger module 202 is used to trigger an active write-back operation of dirty data in the last-level cache when the last-level cache is in an idle state and the DRAM controller is in a low-load state. The execution module 203 is used to stop the active write-back operation when it is detected that the last-level cache is no longer in an idle state or the DRAM controller is no longer in a low-load state during the execution of the active write-back operation.

[0090] The aforementioned dirty data pre-eviction device for the last-level cache detects both the idle state of the last-level cache and the low-load state of the dynamic random access memory (DRAM) controller. When both the last-level cache and DRAM controller are idle, it triggers an active write-back operation for dirty data in the last-level cache. During the active write-back operation, it stops when it detects that the last-level cache is no longer idle or the DRAM controller is no longer low-load. This disclosure establishes a collaborative gating mechanism between cache idle state and DRAM low-load state, actively transferring dirty data write-back operations to system idle periods. This avoids write-back traffic competing for resources with normal requests during busy periods, reducing service access latency. Furthermore, the write-back operation only starts when the system is truly idle and stops immediately upon service arrival, ensuring zero interference with normal services and high reliability.

[0091] In one possible implementation, the detection module 201 is specifically configured to detect whether the final-level cache is in an idle state according to the following steps: Detect the load status of the miss status holding register of the last-level cache, and detect the load status of the pipeline entry of the last-level cache; When the load of the miss status holding register is lower than the first preset condition and the load of the pipeline entry is lower than the second preset condition, the last-level cache is determined to be in an idle state.

[0092] In one possible implementation, the first preset condition is: the miss status holding register is completely free, or the occupancy rate of the miss status holding register is lower than a preset first threshold. The second preset condition is: there are no pending memory access requests at the pipeline entry point, or the request arrival rate at the pipeline entry point is lower than the preset second threshold.

[0093] In one possible implementation, the detection module 201 is specifically configured to detect whether the dynamic random access memory (DRAM) controller is in a low-load state according to the following steps: Detect the current depth of the request queue inside the DRAM controller; Compare the current depth with the preset depth; When the current depth is lower than the preset depth, the DRAM controller is determined to be in a low-load state; when the current depth reaches or exceeds the preset depth, the DRAM controller is determined to be not in a low-load state.

[0094] In one possible implementation, the triggering module 202 is specifically configured to trigger an active write-back operation on dirty data in the last-level cache according to the following steps: When the last-level cache is detected to be in an idle state and the DRAM controller is in a low-load state, wait for a preset delay time. After the state continues for the delay time, initiate the active write-back operation for dirty data in the last-level cache.

[0095] In one possible implementation, the triggering module 202 is specifically configured to wait for a preset delay time according to the following steps, and after the state continues for the delay time, initiate an active write-back operation on the dirty data in the last-level cache: Start the configurable delay counter to begin timing; During the timing period, it continuously monitors whether the final cache remains idle and whether the DRAM controller remains under low load. If the last-level cache is no longer idle or the DRAM controller is no longer under low load during the timing period, the delay counter is reset and the current wait is terminated. If the preset delay time is reached and the above conditions are continuously met, the waiting will end and the active write-back operation will be initiated.

[0096] In one possible implementation, the triggering module 202 is specifically configured to trigger an active write-back operation on dirty data in the last-level cache according to the following steps: Initiate the pre-eviction state machine; The pre-eviction state machine scans the dirty cache lines in the last-level cache, selects a dirty cache line, generates a write-back request, and sends the data of the cache line and the target physical address to the DRAM controller. After receiving the write-back complete indication from the DRAM controller, the cache line is marked as clean or invalid. Continue scanning and writing back the next dirty cache line until the pre-eviction state machine is stopped or all dirty cache lines have been written back.

[0097] In one possible implementation, the triggering module 202 is configured to scan dirty cache lines in the final cache according to any of the following scanning methods: Scan sequentially according to the increasing order of the cache group index; Dirty cache lines are selected for write-back in the order of least recently used priority; Prioritize writing back dirty cache lines that are physically adjacent; Write back in order of the dirty mark time from earliest to latest.

[0098] In one possible implementation, execution module 203 is specifically configured to stop the active write-back operation according to the following steps: During the execution of an active write-back operation, if it is detected that the last-level cache is no longer in an idle state or the DRAM controller is no longer in a low-load state, the write-back operation of the currently executing cache line is allowed to continue to complete. Once the write-back operation is completed, the subsequent dirty cache line write-back operations will be stopped.

[0099] In one possible implementation, the detection module 201 is further configured to: The DRAM controller outputs a grant signal to the last-level cache via a sideband signal line. The grant signal is used to indicate whether the DRAM controller is in a low-load state.

[0100] It should be noted that the apparatus in this embodiment can implement the various processes of the aforementioned method and achieve the same effects and functions, which will not be elaborated here.

[0101] This disclosure also provides an electronic device, such as... Figure 6 The diagram shown is a schematic representation of an electronic device structure provided in this embodiment of the present disclosure, including: a processor 301, a memory 302, and a bus 303. The memory 302 stores machine-readable instructions executable by the processor 301 (e.g., ...). Figure 5 The device includes the detection module 201, trigger module 202, and execution module 203 (and their corresponding execution instructions). When the electronic device is running, the processor 301 and memory 302 communicate via bus 303. When machine-readable instructions are executed by the processor 301, the following processing is performed: Detect whether the last-level cache is idle and whether the dynamic random access memory (DRAM) controller is under low load. When the last-level cache is idle and the DRAM controller is under low load, an active write-back operation is triggered to the dirty data in the last-level cache. During the active write-back operation, the active write-back operation is stopped when it is detected that the last-level cache is no longer in an idle state or the DRAM controller is no longer in a low-load state.

[0102] This disclosure also provides a computer-readable storage medium storing a computer program that, when executed by a processor, performs the steps of the final-level cache dirty data pre-eviction method described in the above method embodiments. The storage medium can be a volatile or non-volatile computer-readable storage medium.

[0103] This disclosure also provides a computer program product carrying program code. The program code includes instructions that can be used to execute the steps of the last-level cache dirty data pre-eviction method described in the above method embodiments. For details, please refer to the above method embodiments, which will not be repeated here.

[0104] The aforementioned computer program product can be implemented through hardware, software, or a combination thereof. In one optional embodiment, the computer program product is specifically embodied in a computer storage medium; in another optional embodiment, the computer program product is specifically embodied in a software product, such as a software development kit (SDK), etc.

[0105] The various embodiments in this disclosure are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments. In particular, the description of the apparatus, device, and computer-readable storage medium embodiments is simplified because they are basically similar to the method embodiments, and the relevant parts can be referred to the description of the method embodiments.

[0106] The apparatus, device, and computer-readable storage medium provided in this disclosure correspond one-to-one with the method. Therefore, the apparatus, device, and computer-readable storage medium also have similar beneficial technical effects as their corresponding methods. Since the beneficial technical effects of the method have been described in detail above, the beneficial technical effects of the apparatus, device, and computer-readable storage medium will not be repeated here.

[0107] Those skilled in the art will understand that embodiments of this disclosure can be implemented as methods and apparatus (devices or systems), or as computer-readable storage media. Therefore, this disclosure can be implemented entirely in hardware, entirely in software, or in a combination of software and hardware. Furthermore, this disclosure can be implemented as a computer-readable storage medium on one or more computer-readable storage media containing computer-usable program code (including, but not limited to, disk storage, read-only optical disc storage (CD-ROM), optical storage, etc.).

[0108] This disclosure is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (devices or systems), and computer-readable storage media according to embodiments of this disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to create a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in one or more blocks of the flowchart illustrations and / or block diagrams.

[0109] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article including instruction means, wherein the instruction means implement the functions specified in one or more flowcharts and / or one or more blocks in a block diagram.

[0110] These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, such that the instructions, which execute on the computer or other programmable apparatus, provide steps for implementing the functions specified in one or more processes in the flowchart and / or one or more blocks in the block diagram.

[0111] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0112] Memory can include non-persistent storage in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.

[0113] Computer-readable media include permanent and non-permanent, removable and non-removable media, which can store information by any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer-readable storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory, read-only memory, electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transfer medium that can be used to store information accessible by a computing device. Furthermore, although the operations of the methods of this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that these operations must be performed in that specific order, or that all of the operations shown must be performed to achieve the desired result. Additionally, certain steps may be omitted, multiple steps may be combined into one step, and / or a step may be broken down into multiple sub-steps.

[0114] While the spirit and principles of this disclosure have been described above with reference to several specific embodiments, it should be understood that this disclosure is not limited to the disclosed specific embodiments, and the division of aspects does not imply that features in these aspects cannot be combined. This disclosure is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A method for pre-eviction of dirty data in the last-level cache, characterized in that, include: It detects whether the last-level cache is idle and whether the dynamic random access memory (DRAM) controller is under low load. When the last-level cache is in an idle state and the DRAM controller is in a low-load state, an active write-back operation is triggered for the dirty data in the last-level cache. During the active write-back operation, the active write-back operation is stopped when it is detected that the last-level cache is no longer in an idle state or the DRAM controller is no longer in a low-load state.

2. The method according to claim 1, characterized in that, The detection of whether the last-level cache is in an idle state includes: The load status of the miss status holding register of the last-level cache and the load status of the pipeline entry of the last-level cache are detected. When the load of the miss status holding register is lower than a first preset condition and the load of the pipeline inlet is lower than a second preset condition, the last-level cache is determined to be in an idle state.

3. The method according to claim 2, characterized in that, The first preset condition is: the miss status holding register is completely free, or the occupancy rate of the miss status holding register is lower than a preset first threshold. The second preset condition is: there are no pending memory access requests at the pipeline inlet, or the request arrival rate at the pipeline inlet is lower than a preset second threshold.

4. The method according to claim 1, characterized in that, The detection of whether the dynamic random access memory (DRAM) controller is in a low-load state includes: Detect the current depth of the request queue inside the DRAM controller; Compare the current depth with the preset depth; When the current depth is lower than the preset depth, the DRAM controller is determined to be in a low-load state; when the current depth reaches or exceeds the preset depth, the DRAM controller is determined to be not in a low-load state.

5. The method according to claim 1, characterized in that, The triggering of an active write-back operation for dirty data in the last-level cache includes: When the last-level cache is detected to be in an idle state and the DRAM controller is in a low-load state, a preset delay time is waited for the state to continue until the delay time is reached before the active write-back operation of dirty data in the last-level cache is initiated.

6. The method according to claim 5, characterized in that, The process of waiting for a preset delay time, and then initiating an active write-back operation on the dirty data in the last-level cache after the state has persisted for the preset delay time, includes: Start the configurable delay counter to begin timing; During the timing period, it is continuously monitored whether the final-level cache remains in an idle state and whether the DRAM controller remains in a low-load state. If the last-level cache is no longer idle or the DRAM controller is no longer under low load during the timing period, the delay counter is reset to terminate the current wait. If the timer reaches the preset delay time and the above conditions are continuously met, the waiting ends and the active write-back operation is initiated.

7. The method according to claim 1, characterized in that, The triggering of an active write-back operation for dirty data in the last-level cache includes: Initiate the pre-eviction state machine; The pre-eviction state machine scans the dirty cache lines in the last-level cache, selects a dirty cache line, generates a write-back request, and sends the data of the cache line and the target physical address to the DRAM controller. After receiving the write-back complete indication returned by the DRAM controller, the cache line is marked as clean or invalid. Continue scanning and writing back the next dirty cache line until the pre-eviction state machine is stopped or all dirty cache lines have been written back.

8. The method according to claim 7, characterized in that, Scan the dirty cache lines in the last-level cache using any of the following scanning methods: Scan sequentially according to the increasing order of the cache group index; Dirty cache lines are selected for write-back in the order of least recently used priority; Prioritize writing back dirty cache lines that are physically adjacent; Write back in order of the dirty mark time from earliest to latest.

9. The method according to claim 1, characterized in that, The step of stopping the active write-back operation includes: During the active write-back operation, if it is detected that the last-level cache is no longer in an idle state or the DRAM controller is no longer in a low-load state, the write-back operation of the currently executing cache line is allowed to continue to complete, and subsequent dirty cache line write-back operations are stopped after the write-back operation is completed.

10. The method according to claim 1, characterized in that, Also includes: The DRAM controller outputs a grant signal to the last-level cache via a sideband signal line. The grant signal is used to indicate whether the DRAM controller is in a low-load state.

11. A pre-eviction device for dirty data in the final-level cache, characterized in that, include: The detection module is used to detect whether the last-level cache is in an idle state and whether the dynamic random access memory (DRAM) controller is in a low-load state. The triggering module is used to trigger an active write-back operation of dirty data in the last-level cache when the last-level cache is in an idle state and the DRAM controller is in a low-load state. An execution module is configured to stop the active write-back operation during the execution of the active write-back operation when it is detected that the last-level cache is no longer in an idle state or the DRAM controller is no longer in a low-load state.

12. An electronic device, characterized in that, include: The device includes a processor, a memory, and a bus. The memory stores machine-readable instructions executable by the processor. When the electronic device is running, the processor communicates with the memory via the bus. When the machine-readable instructions are executed by the processor, the dirty data pre-eviction method of the last-level cache as described in any one of claims 1 to 10 is performed.

13. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, performs the method for pre-eviction of dirty data in the final cache as described in any one of claims 1 to 10.

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