Consistency management method and apparatus, electronic device, storage medium, and product

Abstract

The application provides a consistency management method and device, electronic equipment, a storage medium and a product. The method comprises the following steps: in response to receiving a memory access instruction, obtaining a process identifier of a target process and a virtual address in the memory access instruction; determining a segment identifier corresponding to the virtual address; reading a corresponding first segment version number from a segment version register matrix of a memory management unit based on the process identifier and the segment identifier, and performing a retrieval operation on a translation lookaside buffer with the virtual address and the process identifier as indexes; in the case that a matching entry is retrieved, reading a stored second segment version number from the matching entry; in the case that the first segment version number is the same as the second segment version number, determining that the matching entry in the translation lookaside buffer is valid; in the case that the first segment version number is different from the second segment version number, determining that the matching entry in the translation lookaside buffer is invalid, thereby narrowing the invalid cache invalidation range and improving the cache hit rate of the translation lookaside buffer.

Description

Technical Field

[0001] This application relates to the field of memory management technology, and in particular to a consistency management method, apparatus, electronic device, storage medium and product. Background Technology

[0002] In the relevant Translation Lookaside Buffer (TLB) consistency management scheme, when the operating system modifies any page table entry of a process, the cache inconsistency problem is usually handled by globally clearing the TLB or invalidating all cache entries of the entire process. This has the problem of coarse cache invalidation granularity, resulting in a low TLB hit rate. Summary of the Invention

[0003] This application provides a consistency management method, apparatus, electronic device, storage medium, and product to solve problems in the related art.

[0004] A first aspect of this application provides a consistency management method applied to a memory management unit, the method comprising: In response to receiving a memory access instruction, the process identifier of the target process and the virtual address in the memory access instruction are obtained; Determine the segment identifier corresponding to the virtual address. The segment identifier is used to indicate the type of memory region to which the virtual address belongs. The type of memory region includes at least one of code segment, data segment, heap, stack, and shared library. Based on the process identifier and the segment identifier, the corresponding first segment version number is read from the segment version register matrix of the memory management unit, and a retrieval operation is performed on the translation back buffer using the virtual address and the process identifier as indexes; If a matching entry is found, the stored second version number is read from the matching entry; If the first segment version number is the same as the second segment version number, the matching entry in the translation backup buffer is determined to be valid; If the version number of the first segment is different from the version number of the second segment, it is determined that the matching entry in the translation backup buffer is invalid.

[0005] In one embodiment, determining the segment identifier corresponding to the virtual address includes: Extract a preset length of bits from the virtual address to obtain the segment encoding field; Based on the encoding mapping relationship pre-stored in the segment mask register, the segment encoding field is mapped to the segment identifier corresponding to the virtual address.

[0006] In one embodiment, reading the corresponding first segment version number from the segment version register matrix of the memory management unit based on the process identifier and the segment identifier includes: Using the process identifier as the row index and the segment identifier as the column index, locate the target register unit in the segment version register matrix; Read the version count value stored in the target register unit and determine the version count value as the first version number.

[0007] In one embodiment, the method provided in this application further includes: In response to a modification operation on the page table entry corresponding to the target virtual address, the segment identifier corresponding to the target virtual address and the process identifier of the current process are determined. An increment operation is performed on the version number at the position corresponding to the segment identifier of the target virtual address and the process identifier of the current process in the segment version register matrix to update the first segment version number; If the version number of the first segment is zeroed after the update, a cache invalidation operation is performed on the memory region corresponding to the segment identifier of the target virtual address and the process identifier of the current process.

[0008] In one embodiment, the method provided in this application further includes: If a matching entry in the translation backup buffer is determined to be valid, address translation is performed based on the physical address stored in the matching entry; If it is determined that a matching entry in the translation backup buffer is invalid, a translation backup buffer missing exception is triggered.

[0009] In one embodiment, after triggering a translation backstop buffer missing exception, the method provided in this application further includes: Read the new page table entry corresponding to the virtual address from the off-chip memory; Extract the physical address from the new page table entry, and determine the segment identifier corresponding to the physical address in the new page table entry; Based on the virtual address, the physical address in the new page table entry, the segment identifier corresponding to the physical address in the new page table entry, the process identifier, and the first segment version number, a new translation back buffer entry is generated; The new translation backup buffer entry is written into the storage unit of an idle translation backup buffer. The new translation backup buffer entry is extended with a segment version field on the basis of the original entry structure. The segment version field is used to store the first segment version number.

[0010] A second aspect of this application provides a consistency management device applied to a memory management unit, the device comprising: The acquisition unit is configured to, in response to receiving a memory access instruction, acquire the process identifier of the target process and the virtual address in the memory access instruction; The first determining unit is used to determine the segment identifier corresponding to the virtual address. The segment identifier is used to indicate the memory region type to which the virtual address belongs. The memory region type includes at least one of code segment, data segment, heap, stack, and shared library. The reading unit is configured to read the corresponding first segment version number from the segment version register matrix of the memory management unit based on the process identifier and the segment identifier, and to perform a retrieval operation on the translation back buffer using the virtual address and the process identifier as indexes. The second determining unit is used to read the stored second version number from the matching entry when a matching entry is found. The third determining unit is used to determine that the matching entry in the translation backup buffer is valid when the first segment version number is the same as the second segment version number; The fourth determining unit is used to determine that the matching entry in the translation backup buffer is invalid when the version number of the first segment is different from the version number of the second segment.

[0011] A third aspect of this application provides an electronic device comprising: At least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the methods described in the first aspect of the present application.

[0012] A fourth aspect of this application provides a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to cause a computer to perform the methods described in the first aspect of this application.

[0013] A fifth aspect of this application provides a computer program product including a computer program that, when executed by a processor, implements the methods described in the first aspect of this application.

[0014] In summary, this application proposes a consistency management method, which includes: in response to receiving a memory access instruction, obtaining the process identifier of the target process and the virtual address in the memory access instruction; determining the segment identifier corresponding to the virtual address, wherein the segment identifier is used to indicate the memory region type to which the virtual address belongs, and the memory region type includes at least one of code segment, data segment, heap, stack, and shared library; based on the process identifier and the segment identifier, reading the corresponding first segment version number from the segment version register matrix of the memory management unit, and performing a retrieval operation on the translation back buffer using the virtual address and the process identifier as indexes; if a matching entry is found, reading the stored second segment version number from the matching entry; if the first segment version number and the second segment version number are the same, determining that the matching entry in the translation back buffer is valid; if the first segment version number and the second segment version number are different, determining that the matching entry in the translation back buffer is invalid.

[0015] According to the solution provided in this application, in response to receiving a memory access instruction, the process identifier and virtual address of the target process are obtained, and the segment identifier corresponding to the virtual address is determined to distinguish the memory region type. Based on the process identifier and segment identifier, the first segment version number stored in the segment version register matrix is ​​read, and the second segment version number stored in the entry is retrieved from the translation back buffer. The validity of the cache entry is determined by comparing the two segment version numbers. Independent version control for each process and memory region is achieved by relying on the process identifier and segment identifier. The corresponding cache is marked as invalid by only modifying the version number of the corresponding memory region. There is no need to clear the translation back buffer globally or for the entire process. By narrowing the scope of invalid cache, the cache hit rate of the translation back buffer is improved.

[0016] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application, and do not constitute an undue limitation of this application.

[0018] Figure 1 A flowchart illustrating a consistency management method provided in an embodiment of this application; Figure 2 A schematic diagram of the structure of a translation backup buffer entry provided in this application embodiment; Figure 3 A schematic diagram of a two-dimensional indexed register array provided in an embodiment of this application; Figure 4 A flowchart illustrating a method for translating a backup buffer query, provided as an embodiment of this application; Figure 5 This is a schematic diagram of the structure of a consistency management device provided in an embodiment of this application; Figure 6 This is a schematic diagram of the hardware composition structure of the electronic device provided in the embodiments of this application. Detailed Implementation

[0019] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application.

[0020] To facilitate a better understanding of the technical solutions described in the embodiments of this application by those skilled in the art, the technical terms in the embodiments of this application are explained as follows before introducing the embodiments of this application.

[0021] The following is a brief introduction to several consistency management methods in related technologies: Global TLB refresh scheme: Scenarios such as page table modification and process switching that directly trigger the global TLB have no effect, and all cache entries are cleared.

[0022] Traditional Address Space Identifier (ASID) process-level scheme: Assigns a unique ASID to each process for address space isolation, uses process-level version number control, and only implements process-level TLB invalidation.

[0023] Single Page Table Entry (PTE) version bit scheme: A dedicated version bit is added to a single page table entry. Each time a TLB hit occurs, the memory page table is read back to compare the version and determine the cache validity.

[0024] Software instruction intervention scheme: Relying on single-page invalidation instructions such as global page invalidation instruction (Invalidate Page, INVLPG) and multi-core synchronous broadcast, the software actively performs TLB invalidation scheduling, address calculation and multi-core synchronization.

[0025] The basic system memory management unit (SMMU) level translation scheme only completes multi-level address translation of StreamID, Stage1, and Stage2, without in-process address partitioning linkage and without fine-grained TLB consistency control logic.

[0026] The above solution has the following drawbacks: The global TLB refresh solution completely clears the TLB cache, causing a large number of missing address translations and a sharp increase in address translation latency. This results in significant performance jitter in multi-core and multi-process concurrent scenarios.

[0027] Traditional ASID process-level solutions only support process-level version control, which is extremely coarse-grained. Modification of a single page mapping within a single process will trigger a full-process TLB failure, inadvertently affecting a large number of valid cached items and causing a significant drop in TLB hit rate.

[0028] The single PTE version bit solution requires reading the memory page table to compare the version every time the TLB hits, which violates the core design principle of TLB to reduce memory access, introduces additional timing loss and memory bandwidth waste, and cannot be adapted to high-performance scenarios.

[0029] Software instruction intervention scheme: Relies on INVLPG single-page invalid instruction and multi-core synchronous broadcast to achieve consistency. The software needs to participate in failure scheduling, address calculation and synchronization waiting. The kernel development is complex and has poor real-time performance. It is prone to cache inconsistency due to synchronization delay.

[0030] The basic SMMU multi-level translation scheme does not take into account the linkage between in-process address partitioning and multi-level translation. The TLB cache is prone to failure gaps, which can damage the integrity of the multi-level address translation link and create blind spots in consistency control.

[0031] In relevant TLB consistency management schemes, when the operating system modifies any page table entry of a process, the cache inconsistency problem is usually handled by globally clearing the TLB or invalidating all cache entries of the entire process. This has the problem of coarse cache invalidation granularity, resulting in a low TLB hit rate.

[0032] To address the shortcomings of related technologies, this application, upon receiving a memory access instruction, obtains the process identifier and virtual address of the target process, determines the segment identifier corresponding to the virtual address for distinguishing memory region types, reads the first segment version number stored in the segment version register matrix based on the process identifier and segment identifier, and retrieves the second segment version number stored within the entry from the translation back buffer. The validity of the cache entry is determined by comparing the two segment version numbers. Independent version control for each process and memory region is achieved by relying on the process identifier and segment identifier. The corresponding cache can be marked as invalid simply by modifying the version number of the corresponding memory region, without needing to clear the translation back buffer globally or for the entire process. By narrowing the scope of invalid caches, the cache hit rate of the translation back buffer is improved.

[0033] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0034] The consistency management method provided in this application embodiment can be applied to processor virtual address cache consistency control scenarios, such as the validity verification scenario of translation backup buffer in automotive on-chip systems and embedded real-time operating systems.

[0035] like Figure 1 As shown, Figure 1 This is a flowchart illustrating a consistency management method provided in an embodiment of this application. The consistency management method provided in this application is applied to a memory management unit and includes the following steps: Step 101: In response to receiving a memory access instruction, obtain the process identifier of the target process and the virtual address in the memory access instruction; In one embodiment, the Memory Management Unit (MMU) is a hardware address management circuit built into the processor, which is responsible for translating virtual addresses to physical addresses, checking memory permissions, and maintaining cache consistency.

[0036] In one embodiment, the memory access instruction is a memory access operation instruction issued by the processor core, and the memory access instruction may include any one of the following: instruction read instruction, data read instruction, and data write instruction.

[0037] In one embodiment, the target process refers to the currently running process, and the process identifier is a unique identifier assigned to each independent process by the operating system. It is used to isolate the virtual address spaces of different processes in a multi-process concurrent scenario and avoid address mapping confusion of the same virtual address in different processes.

[0038] In one embodiment, the virtual address is a 64-bit or 32-bit complete virtual address corresponding to a memory access instruction, which is address data within the operating system process address space used to locate the virtual memory location.

[0039] In one embodiment, different processes can reuse the same virtual address, which needs to be converted into a unique physical memory address by the MMU.

[0040] In one embodiment, the MMU monitors the memory access instruction pipeline of the processor core. Once a valid memory access instruction is captured, the current hardware context information is immediately latched, and the virtual address corresponding to this access and the process identifier of the currently running process are extracted.

[0041] In one embodiment, the virtual address can be obtained synchronously during the instruction decoding stage, and the current process identifier can be read in real time from the process context switching register; alternatively, when a valid enable signal for a memory access instruction is detected, a dedicated register can be triggered to latch the virtual address and the process identifier.

[0042] Step 102: Determine the segment identifier corresponding to the virtual address. The segment identifier is used to indicate the type of memory region to which the virtual address belongs. The memory region type includes at least one of the following: code segment, data segment, heap, stack, and shared library. In one embodiment, the segment identifier is an encoded identifier generated by the memory management unit based on the high-order bits of the virtual address. It is used to perform fine-grained region division of the complete virtual address space of the process, so as to realize independent management of different memory regions within the same process.

[0043] In one embodiment, the memory management unit is pre-configured with a segment mask register. By configuring a fixed bit truncation rule through the segment mask register, a preset number of bits are truncated from the high bits of the virtual address to generate a segment encoding field, and a preset mapping relationship is matched to obtain a unique corresponding segment identifier.

[0044] In one embodiment, the code segment stores program execution instructions, and the page table mapping changes very rarely; it is a static segment. The data segment stores global and static variables, and the mapping changes very infrequently. The heap is a dynamic memory allocation area, and the mapping changes at a moderate frequency. The stack is a storage area for thread calls and local variables, and the mapping changes very frequently. The shared library / peripheral mapping segment stores dynamic link libraries and input / output (I / O) mappings, and the change frequency is low.

[0045] In one embodiment, different types of memory regions correspond to fixed segment identifier codes. For example, code segments correspond to first-type segment identifiers, data segments correspond to second-type segment identifiers, heaps correspond to third-type segment identifiers, stacks correspond to fourth-type segment identifiers, and shared libraries correspond to fifth-type segment identifiers. The segment identifiers for different memory regions are different.

[0046] In one embodiment, different virtual addresses of the same process can correspond to different segment identifiers, and all virtual addresses within the same memory region can uniformly correspond to the same segment identifier, so as to achieve partition version management granularity based on memory region.

[0047] In one embodiment, the segment identifier corresponding to the virtual address can be determined by a fixed high-order bit truncation method. Specifically, the highest 2 or 3 bits of the virtual address are truncated, and the segment code is obtained through hardware mask AND operation, which is then mapped to the segment identifiers corresponding to the code segment, data segment, heap, stack, and shared library.

[0048] In one embodiment, the corresponding memory segment type and segment identifier can also be obtained by comparing the address range where the virtual address is located through the MMU's built-in segment base address register / segment mask register.

[0049] Step 103: Based on the process identifier and the segment identifier, read the corresponding first segment version number from the segment version register matrix of the memory management unit, and perform a retrieval operation on the translation back buffer using the virtual address and the process identifier as indexes; In one embodiment, the segment version register matrix is ​​a two-dimensional hardware register array built into the memory management unit, with process identifier as the row index and segment identifier as the column index. Each row and column intersection in the matrix corresponds to an independent version storage unit, and the storage units are isolated from each other.

[0050] In one embodiment, the first version number is the latest version value stored in the hardware register matrix in real time, which is used to indicate the latest page table mapping status of the memory region corresponding to the current process.

[0051] In one embodiment, the translation back buffer is a high-speed cache built into the MMU, used to cache high-frequency virtual address-physical address mapping relationships, reduce page table traversal memory access overhead, and improve address translation speed. In this application, the TLB retrieval adopts a retrieval method of virtual address and process identifier joint index. By matching the virtual address and process identifier, the cache entry corresponding to the current virtual address of the current process can be accurately located, avoiding cache cross-interference of different processes with the same virtual address in multi-process scenarios.

[0052] In one embodiment, the operation of reading the first version number and the TLB retrieval operation are executed in parallel by the hardware pipeline, without sequential waiting overhead, without increasing the address translation pipeline latency, and can ensure high-speed memory access.

[0053] In one embodiment, row and column decoding hardware circuitry can be used to decode the process identifier and segment identifier, select a unique matrix cell in the segment version register matrix, read the version count value, and obtain the first segment version number; alternatively, register array parallel reading can be used to traverse all column cells of the corresponding row in one pass and filter the first segment version number by segment identifier.

[0054] Step 104: If a matching entry is found, read the stored second version number from the matching entry; In one embodiment, a matching entry refers to a cached entry in the TLB retrieval process that has a completely matching virtual address and process identifier and a valid (VLD) bit.

[0055] In one embodiment, the second version number is a version snapshot stored internally by the TLB matching entry. It is a version value read from and written to the segment version register matrix when the TLB entry is created and the page table mapping is loaded, and is used to record the mapping status of the corresponding memory region when the cache is generated.

[0056] Step 105: If the version number of the first segment is the same as the version number of the second segment, determine that the matching entry in the translation backup buffer is valid. In one embodiment, if the first version number and the second version number are the same, it means that the page table entries in the memory region have not been modified since the TLB entry cache was generated, the TLB matching entry mapping relationship has not expired, the entry is determined to be valid, and the entry can be directly reused to complete the conversion from virtual address to physical address.

[0057] Step 106: If the version number of the first segment is different from the version number of the second segment, determine that the matching entry in the translation backup buffer is invalid.

[0058] In one embodiment, if the first version number and the second version number are inconsistent, it indicates that the page table entry corresponding to the memory region has been modified by the operating system, the current TLB cache entry is expired data, the entry is determined to be invalid, and a TLB missing exception needs to be triggered to reload the latest page table mapping.

[0059] In one embodiment, the determination of the validity of the matching entry in the translation backup buffer based on the first version number and the second version number is completed in real time by the hardware combination logic of the memory management unit, without the need for software intervention or off-chip memory access to read version information, and the comparison process is completed in a single cycle.

[0060] In one embodiment, if a valid entry is found in the TLB retrieval, the validity of the matching entry in the translation backup buffer is determined based on the first version number and the second version number; if no matching entry is found, the TLB missing traversal process is directly entered without performing the aforementioned version comparison operation.

[0061] In one embodiment, if the first and second version numbers are the same, it means that the real-time baseline version value of the current memory segment read from the segment version register matrix is ​​completely identical in bit sequence to the snapshot version value cached in the segment version field of the TLB matching entry. This indicates that the memory segment to which the virtual address belongs has not undergone page table entry modification, mapping relationship update, or memory permission adjustment since the TLB entry cache was generated. The address mapping data stored in the current TLB matching entry is consistent with the off-chip real page table data, and the cached entry is valid and usable. If the first and second version numbers are different, it means that the real-time baseline version value of the current memory segment read from the segment version register matrix is ​​different in bit sequence from the snapshot version value cached in the segment version field of the TLB matching entry. This indicates that the memory segment to which the virtual address belongs has undergone page table entry update modification, the baseline version of the hardware register matrix has been iteratively updated, the mapping data stored in the current TLB matching entry is expired snapshot data, inconsistent with the real page table state, and the cached entry is invalid and unusable.

[0062] In one embodiment, the validity of a TLB entry refers to whether the currently retrieved and matched cached entry has a valid and usable virtual address-physical address mapping relationship, which can be divided into two types: valid entry and invalid entry.

[0063] In one embodiment, a hardware parallel comparison circuit can be used to verify the numerical consistency between the first version number and the second version number, and the comparison result can be output in real time.

[0064] In one embodiment, the two version numbers can be input into the hardware comparison logic unit through a preset version verification rule. Based on the two results of whether the values ​​are consistent or inconsistent, the corresponding address translation process is executed respectively. That is, address translation or an exception triggering process is performed based on the physical address stored in the matching entry. Before triggering the translation backup buffer missing exception, the matching entry can also be marked as invalid to avoid the TLB finding the old (invalid) mapping relationship when performing virtual address lookup.

[0065] For example, the first segment version number stored in the segment version register matrix corresponding to the process identifier and segment identifier of the target process in real time is 01, and the second segment version number stored in the current TLB matching entry is also 01. The two segment version number values ​​are completely consistent, indicating that since the TLB entry cache was generated, no page table entry modification, mapping change, or permission adjustment operation has occurred in this memory region, and the TLB cache entry mapping relationship is completely matched with the current real page table mapping state.

[0066] For example, the first version number corresponding to the target process is updated to 10, while the second version number fixed in the TLB matching entry is still 01. The two version number values ​​are inconsistent, indicating that the page table entry corresponding to this memory region has been modified and updated by the operating system. The mapping data stored in the current TLB cache entry is expired and invalid data, which cannot be used for normal address translation.

[0067] By constructing a two-dimensional index based on process identifiers and segment identifiers, fine-grained TLB consistency verification is achieved across multiple processes and memory regions. This solves the problem of coarse-grained management methods that involve clearing the global TLB and invalidating the entire process TLB. Instead, the local version number is updated only when the page table of the corresponding memory region changes, thus narrowing the scope of TLB failures and improving the TLB cache hit rate.

[0068] In one embodiment, determining the segment identifier corresponding to the virtual address includes: Extract a preset length of bits from the virtual address to obtain the segment encoding field; Based on the encoding mapping relationship pre-stored in the segment mask register, the segment encoding field is mapped to the segment identifier corresponding to the virtual address.

[0069] In one embodiment, the preset length of bits is the number of high-order bits that the memory management unit can configure, such as 2 bits or 3 bits, to adapt to different memory region partitioning scenarios. The number of bits can be flexibly configured according to the complexity of the process memory layout.

[0070] In one embodiment, the segment coding field is a fixed bit sequence extracted from the high bits of the virtual address.

[0071] In one embodiment, the segment mask register is a configuration register built into the memory management unit and is pre-configured by the operating system during process initialization or process switching to solidify the virtual address bit truncation rules and encoding mapping rules.

[0072] In one embodiment, the segment mask register stores a pre-defined encoding mapping relationship, which is a one-to-one mapping rule between the bit encoding value, memory region type, and segment identifier, and can convert the high-order bit field into a segment identifier that can distinguish the function.

[0073] In one embodiment, the high-order bits of the virtual address can be extracted and a mask AND operation can be performed on the combinational logic circuit inside the memory management unit to obtain the segment code field.

[0074] In one embodiment, the mask parameters of the segment mask register can be adjusted according to system configuration requirements to change the position and number of bits of the captured virtual address bits, so as to adapt to the memory segmentation requirements of different processes.

[0075] For example, the system is configured with a preset truncation length of 3 bits, and 3 bits of data are truncated from the highest bit of the 64-bit virtual address as the segment encoding field; wherein, the pre-stored encoding mapping relationship in the segment mask register is as follows: segment encoding field 000 corresponds to the code segment, segment encoding field 001 corresponds to the data segment, segment encoding field 010 corresponds to the heap space, segment encoding field 011 corresponds to the stack space, and segment encoding field 100 corresponds to the shared library area.

[0076] For example, when the high 3 bits of the virtual address carried by the memory access instruction are 011, the segment code field is extracted as 011. After matching through the mapping relationship of the segment mask register, the corresponding segment identifier is determined to be the standard code identifier corresponding to the stack space.

[0077] In one embodiment, different memory region types correspond to unique segment identifiers, and all virtual addresses within the same memory region correspond to the same segment identifier, so as to achieve fine-grained group management based on memory functional regions.

[0078] This embodiment obtains the segment code field by extracting preset bits from the virtual address, and then generates a standardized segment identifier based on the pre-stored mapping relationship of the segment mask register. This can quickly determine the memory region to which the virtual address belongs, without the need for software to traverse the address range for comparison. The segment recognition speed is fast and the hardware overhead is small.

[0079] In one embodiment, reading the corresponding first segment version number from the segment version register matrix of the memory management unit based on the process identifier and the segment identifier includes: Using the process identifier as the row index and the segment identifier as the column index, locate the target register unit in the segment version register matrix; Read the version count value stored in the target register unit and determine the version count value as the first version number.

[0080] In one embodiment, the segment version register matrix can be located using a two-dimensional index mapping method. The process identifier is fixed as the matrix row index, and the segment identifier is fixed as the matrix column index. Through row index and column index constraints, the corresponding register storage unit is uniquely locked.

[0081] In one embodiment, a hardware decoding circuit can also be used to complete the index positioning. The decoding circuit performs logical decoding on the process identifier and segment identifier to select the unique target register unit in the matrix, thus avoiding the problem of multi-unit matching conflicts.

[0082] For example, the process identifier of the currently running target process is 05, and the segment identifier obtained by the current virtual address resolution is 011. Using process identifier 05 as the row index and segment identifier 011 as the column index, the register unit corresponding to the 5th row and 3rd column in the two-dimensional segment version register matrix is ​​located. This unit is the target register unit corresponding to the current memory access.

[0083] In one embodiment, the target register unit is a hardware storage unit with a unique row and column index match in the segment version register matrix. Each target register unit independently stores the version count value of the corresponding process and the corresponding memory segment. Each storage unit is independent of the others and does not interfere with each other.

[0084] In one embodiment, the version count value can be a hardware-maintained 2-bit cycle count value used to record the update iteration status of the page table mapping of the corresponding memory segment. Each time a page table entry modification operation occurs in the corresponding memory segment, the version count value will be incremented and updated. The version count value can also be a hardware-maintained 3-bit cycle count value, which is not limited in this application.

[0085] In one embodiment, the first version number is the latest version count value read from the target register unit, which is the latest memory segment mapping state recognized by the current hardware level.

[0086] In one embodiment, the stored data of the target register unit can be read directly through hardware parallel read logic, without the need for software traversal query or off-chip memory access, and the acquisition of the first version number can be completed in a single cycle.

[0087] In one embodiment, a register latching mechanism can also be used to latch the current version count value when a memory access instruction arrives, ensuring that the first segment of version number data remains stable and does not jump during a single address translation, thereby avoiding version read errors.

[0088] This embodiment uses process identifiers and segment identifiers to construct a two-dimensional index to locate the target register unit of the segment version register matrix, and reads the real-time version count value as the first segment version number. This enables fine-grained independent reading and management of multiple processes and memory segments, matching the latest memory segment version status corresponding to the current access address, and avoiding the precision problem caused by the unified global version management.

[0089] In one embodiment, the consistency management method further includes: In response to a modification operation on the page table entry corresponding to the target virtual address, the segment identifier corresponding to the target virtual address and the process identifier of the current process are determined. An increment operation is performed on the version number at the position corresponding to the segment identifier of the target virtual address and the process identifier of the current process in the segment version register matrix to update the first segment version number; If the version number of the first segment is zeroed after the update, a cache invalidation operation is performed on the memory region corresponding to the segment identifier of the target virtual address and the process identifier of the current process.

[0090] In one embodiment, the target virtual address refers to the virtual address to be updated corresponding to this page table modification operation. This virtual address is a specific memory region in the process's virtual address space, corresponding to a unique segment identifier and process identifier.

[0091] In one embodiment, the modification operation of a page table entry refers to the modification operation performed by the operating system kernel on the page table entry corresponding to the process's virtual address, which may include, but is not limited to, page table permission modification, virtual address and physical address mapping relationship change, valid bit flipping, and other operations.

[0092] In one embodiment, the corresponding segment identifier can be obtained by extracting and mapping the high-order bits of the modified target virtual address; the process identifier of the target process corresponding to the current operation can be obtained by reading the current central processing unit (CPU) running context.

[0093] In one embodiment, the operating system can also simultaneously carry the process identifier and segment identifier when issuing page table modification instructions, and obtain the segment identifier corresponding to the target virtual address and the process identifier of the current process through hardware registers.

[0094] For example, when the operating system modifies the page table permissions of a virtual address in the stack segment of the process with process identifier 06, the hardware captures this page table modification event, parses the segment identifier corresponding to the target virtual address as the preset code corresponding to the stack segment, and finally determines the index parameters corresponding to this update as: process identifier 06, segment identifier as stack segment code.

[0095] In one embodiment, the version number at the corresponding location can be updated through a hardware automatic accumulation mechanism. Whenever any page table entry is modified in the corresponding memory segment, the hardware automatically increments the version count value in the target register unit by 1 to complete the first segment version number iteration update.

[0096] In one embodiment, version accumulation updates can also be actively triggered by the operating system's write register instruction, with the update location specified by the software and the hardware completing the numerical iteration and latching.

[0097] In one embodiment, the version number adopts a finite bit cyclic counting mechanism, preferably a 2-bit counting mode, and the version count value can be cyclically taken as 00, 01, 10, 11; when the version number is accumulated to the maximum value, it is accumulated again, and the counting is automatically reset to zero to complete the version cyclic iteration.

[0098] In one embodiment, the cache invalidation operation refers to the operation of invalidating all cache entries stored in the translation back buffer that correspond to the current process identifier and the current segment identifier, in order to clear expired cache mapping relationships.

[0099] In one embodiment, all TLB entries in the corresponding memory region can be marked as invalid by automatically clearing the valid bits in hardware, thus preventing subsequent accesses from hitting expired cache entries.

[0100] In one embodiment, hardware matching of process identifiers and segment identifiers can be used to batch filter all TLB entries in the corresponding region, uniformly invalidate and reclaim them, and achieve local cache cleanup.

[0101] For example, the 2-bit version count is currently 11. After the page table modification triggers the accumulation operation, the version value is reset to zero. The hardware automatically matches all TLB cache entries corresponding to the process identifier and segment identifier, and clears the expired cache in the memory area in batches. Only the cache data of the currently modified segment is invalidated, without affecting the valid cache of other memory areas such as code segment and data segment under the same process. By narrowing the scope of invalid cache, the cache hit rate of the translation back buffer is improved.

[0102] This embodiment triggers the cumulative update of the version number of the corresponding memory segment through page table entry modification operations, and achieves fine-grained version iteration by relying on process identifier and segment identifier. After the version cycle reaches zero, it automatically performs local cache invalidation operation without global TLB refresh or clearing of the entire process cache, which greatly reduces the scope of cache invalidation and reduces unnecessary cache invalidation overhead. In this way, it can improve the overall cache hit rate of the translation back buffer, reduce memory address translation latency, and improve system memory access performance.

[0103] In one embodiment, the consistency management method further includes: If a matching entry in the translation backup buffer is determined to be valid, address translation is performed based on the physical address stored in the matching entry; If it is determined that a matching entry in the translation backup buffer is invalid, a translation backup buffer missing exception is triggered.

[0104] In one embodiment, when the first version number is the same as the second version number, the TLB matching entry is determined to be valid. Based on the mapping information such as virtual address, physical address, and access permissions pre-stored in the matching entry, the address translation operation of this memory access instruction is completed without reading off-chip page table entries.

[0105] In one embodiment, when the first version number is different from the second version number, it is determined that the TLB matching entry is in an invalid state, the cached mapping data of the entry is invalidated and cannot be reused, and then the translation backup buffer missing exception is actively triggered.

[0106] In one embodiment, the TLB miss exception is a pipeline exception signal built into the memory management unit, used to interrupt the current cache hit process, jump to the slow page table traversal path, and load the latest page table mapping information from off-chip memory.

[0107] This embodiment compares the latest first segment version number of the hardware register matrix with the second segment version number of the TLB entry snapshot, and performs fast address translation or TLB missing exception logic in two scenarios respectively. This achieves fine-grained hardware TLB cache consistency verification, avoiding the problems of false clearing of valid cache and low cache hit rate caused by traditional coarse-grained cache failure methods. At the same time, it can avoid the performance overhead of software clearing of TLB, thereby improving memory address translation efficiency and system memory access performance.

[0108] In one embodiment, after triggering a translation backstop buffer missing exception, the consistency management method further includes: Read the new page table entry corresponding to the virtual address from the off-chip memory; Extract the physical address from the new page table entry, and determine the segment identifier corresponding to the physical address in the new page table entry; Based on the virtual address, the physical address in the new page table entry, the segment identifier corresponding to the physical address in the new page table entry, the process identifier, and the first segment version number, a new translation back buffer entry is generated; The new translation backup buffer entry is written into the storage unit of an idle translation backup buffer. The new translation backup buffer entry is extended with a segment version field on the basis of the original entry structure. The segment version field is used to store the first segment version number.

[0109] In one embodiment, off-chip memory refers to the system main memory outside the memory management unit, used to persistently store complete multi-level page table data of the process, and TLB cache is only a high-speed cache of off-chip page tables.

[0110] In one embodiment, the new page table entry is the latest valid page table data read from off-chip memory after the multi-level page table traversal is completed. It is the latest page table content after the operating system updates the mapping relationship, modifies page permissions, and adjusts memory attributes, rather than expired old page table cache data in the TLB.

[0111] In one embodiment, the physical address is the final physical memory address stored in the new page table entry, which is used to complete the address translation from virtual address to physical address. The physical address in the new page table entry is the hardware memory address that the processor ultimately accesses.

[0112] In one embodiment, the page table traversal logic of the memory management unit can be used to read the L4, L3, L2, and L1 page tables level by level, and finally obtain the latest leaf page table entry corresponding to the current virtual address from the off-chip memory to obtain the new page table entry.

[0113] In one embodiment, the page table cache reuse mechanism can be used to reuse the unchanged page directory entries of the upper level, and only the changed lower level page table hierarchy can be traversed to quickly obtain the latest new page table entries, thereby reducing the number of off-chip memory accesses.

[0114] For example, when a TLB entry version mismatch triggers a missing exception, the MMU initiates a page table traversal process, indexing the multi-level off-chip page tables level by level based on the current virtual address, and reads the updated new page table entries. These new page table entries store core information such as the updated physical address, page permissions, and validity flags.

[0115] In one embodiment, the virtual address, the physical address in the new page table entry, the segment identifier, the process identifier, and the first segment version number can be integrated with the TLB permission field and the validity flag bit and encapsulated in a structured manner into a new TLB entry.

[0116] In one embodiment, the parameters can be allocated and data filled according to the preset TLB entry bit width definition rules to generate a new TLB entry that conforms to the hardware storage specification.

[0117] In one embodiment, the traditional TLB entry structure only stores the virtual address, physical address, permission bits, and validity bits. The new translation back buffer entry, based on the traditional TLB entry structure, adds an independent segment version field, such as... Figure 2 As shown, Figure 2 This is a schematic diagram of the structure of a translation backup buffer entry provided in an embodiment of this application. The extended segment version field of this application is used to fix the first segment version number read this time, which will be used as the second segment version number for the next memory access.

[0118] In one embodiment, the storage unit of the idle translation back buffer refers to the cache entry space within the TLB where the valid VLD bit is 0, it is unoccupied, and can be overwritten.

[0119] In one embodiment, when there are no free units, a replacement strategy can also be used, such as the Least Recently Used (LRU) strategy, to replace old and invalid entries and complete the writing of new translation back buffer entries.

[0120] For example, the first segment version number read is 10. When a new TLB entry is generated, the version number 10 is written into the newly added segment version field. This field data will be cached with the TLB entry for a long time until the entry is replaced or expired. When the virtual address is accessed again, the value of this field will be used as the second segment version number for segment version number comparison and verification.

[0121] This embodiment reads the new page table entry corresponding to the virtual address from off-chip memory; extracts the physical address from the new page table entry and determines the segment identifier corresponding to the physical address in the new page table entry; generates a new translation back buffer entry based on the virtual address, the physical address in the new page table entry, the segment identifier corresponding to the physical address in the new page table entry, the process identifier, and the first segment version number; and writes the new translation back buffer entry into the storage unit of an idle translation back buffer. The new translation back buffer entry extends the original entry structure with a segment version field, which is used to store the first segment version number, so that each TLB cache entry carries the latest version information of the corresponding memory segment, providing an accurate version comparison basis for TLB consistency verification, avoiding address translation errors caused by cache version lag, and eliminating the need for a global TLB refresh, which can reduce cache update overhead and improve TLB cache hit rate and overall memory access performance.

[0122] In one embodiment, this application also provides a specific consistency management method applied to a memory management unit. The memory management unit includes an ASID identification unit, an address segment resolution unit, a segment version register matrix, and a TLB entry extension module. Specifically: ASID Identifier Unit: It adopts the native ASID register group of the MMU without adding new hardware circuits. Each running process is assigned a unique and non-repeating ASID code to distinguish the address spaces of different processes. The TLB index uses a combination of virtual address (VA) and ASID key value to eliminate TLB cache confusion of multiple processes from the root and ensure the isolation between processes.

[0123] The address segment resolution unit is a pure combinational logic circuit, with no clock dependency and no register latch. An additional "segment base address / mask register" is added to the MMU. During process switching or memory layout initialization, the operating system informs the hardware which 3 VA bits correspond to which SegID, and then extracts the corresponding bits of the virtual address (VA) as the segment identifier (SegID). The specific mapping relationship is as follows: SegID=000 (3-bit encoding) / 00 (2-bit encoding): Code segment, stores program execution instructions, page table mapping rarely changes, belongs to static segment; SegID=001 / 01: Data segment, storing global variables and static variables, with extremely low mapping change frequency; SegID=010 / 10: Heap space, dynamic memory allocation area, with a medium frequency of mapping changes; SegID=011 / 11: Stack space, a storage area for thread calls and local variables, with extremely high mapping change frequency; SegID=100: Shared library / peripheral mapping segment, storing dynamic link libraries and IO mappings, with a low change frequency.

[0124] This module only requires gate circuits to implement bit extraction, the hardware area is negligible, and it supports granularity requirements of different scenarios by configuring the number of bit switching segments.

[0125] The segment version register matrix uses a register array with two-dimensional indices of ASID and SegID. The hardware design rules are as follows: Bit width design: Each segment is allocated only 2 bits for version (asid_segment_version[ASID][SegID]), and a version accumulation mechanism is used; Capacity design: Configured based on the maximum number of ASIDs (e.g., 256) × the maximum number of segments (5 segments); Read / write mechanism: The software can directly read and write the corresponding version bit through the MMU configuration port, complete the update operation in a single cycle, and the hardware synchronizes the version value to the TLB comparison logic in real time.

[0126] like Figure 3 As shown, Figure 3This is a schematic diagram of a two-dimensional indexed register array provided in an embodiment of this application. Specifically, it is a two-dimensional storage structure of a segment version register matrix built into the memory management unit. The row dimension of the matrix is ​​the address space identifier (ASID), including address space identifier 0 (ASID0), address space identifier 1 (ASID1), and other address space identifiers (ASID...). The column dimension of the matrix represents various memory regions, namely code segment, data segment, heap space, stack space, and shared library / peripheral mapping segment. Each row and column intersection storage unit in the matrix stores a version bit. Each unique combination of address space identifier (ASID) and memory region is independently allocated a dedicated version bit to record the page table mapping iteration state of the corresponding process and the corresponding memory region. This version bit is read during memory access as the first segment version number and used to perform consistency comparison with the second segment version number stored in the translation back buffer entry.

[0127] The TLB entry extension module adds only 2 bits to the original TLB entries (VA, Physical Address (PA), permission bits, and validity bits), resulting in a negligible impact on the overall TLB area. When loading page table entries, the TLB synchronously obtains the SegID from the address segment resolution unit and the corresponding version value from the segment version matrix, completing the full field write in one go without duplicate memory accesses or additional timing overhead.

[0128] Based on the aforementioned memory management unit, the consistency management method is divided into three timing phases, each of which is a single cycle or native timing phase with no latency accumulation: Phase 1: Standard TLB hit process.

[0129] 1. When an instruction fetch / memory access is issued, the MMU receives the Virtual Address (VA). The Address Segment Resolution Unit (ASU) extracts the high-order bits of the VA in real time to generate the SegID. The MMU obtains the ASID of the current process and uses the VA and ASID as indexes to search the TLB. The search process is completely consistent with the native TLB. After a TLB hit, the cached SegID and segment version bit are read in parallel. The hardware combinational logic directly compares the TLB cache segment version with the segment version register matrix [current ASID][current SegID]. If the comparison is consistent, the physical address (PA) and permission information are directly output, and the address translation is completed. The timing is exactly the same as the native TLB, with no additional delay. If the comparison is inconsistent, the valid bit of the TLB entry is immediately set to 0, marking it as expired and invalid. A TLB miss interrupt is triggered synchronously, and the reload process begins.

[0130] Phase 2: Page table modification and version triggering process.

[0131] The operating system kernel modifies the page table entry (PTE) corresponding to a virtual address, including operations such as mapping changes, valid bit flipping, and permission modifications. The kernel locates the SegID and process ASID corresponding to this VA through the MMU configuration interface, and updates the 2-bit version bit of the corresponding segment in a single cycle. The operation instruction is a simplified XOR instruction, without multi-core synchronization, broadcasting, or INVLPG instruction issuance. After the version bit flip, the hardware takes effect immediately without software waiting for synchronization. Subsequent TLB accesses to this segment automatically trigger invalidation checks, while the TLB caches of other segments and processes remain operational. If the 2-bit version bit returns to its initial value of all 0s, a global invalidation of the corresponding segment is automatically performed.

[0132] Phase 3: TLB Missing and Page Table Reloading Process.

[0133] After a TLB miss is triggered, the MMU calls the native Page Table Walk logic to read the latest page table entry data from the off-chip DDR / Flash; it re-parses the VA to generate the SegID, reads the latest segment version value from the segment version register matrix, and synchronously writes the VA, PA, ASID, SegID, segment version bit, and permission bit into the TLB free entry; after the TLB entry is updated, the failure mark is cleared, and subsequent access to this address will directly hit, restoring the high-performance conversion mode. The reload process only applies to the missing entry and does not perform a full refresh.

[0134] like Figure 4 As shown, Figure 4 This is a flowchart illustrating a method for querying a translation back buffer (TLB) according to an embodiment of this application. The method receives a Virtual Address (VA) translation request and enters a regular Translation Back Buffer (TLB) hit process. If no match is found in the TLB hit process, the method enters a Translation Back Buffer Miss (TLB Miss) process. If a match is found in the TLB hit process, the TLB cache segment version is compared with the version value stored in the segment version register matrix [Current Address Space Identifier (ASID)][Current Segment Identifier (SegID)]. If they are equal, it is determined that a page table entry has been hit, and the cache can be directly reused to complete the address translation. If they are not equal, it is determined that a page table entry has been missed, and the current match is invalidated.

[0135] In summary, the solution provided in this application is as follows: In response to a received memory access instruction, the process identifier and virtual address of the target process are obtained, and the segment identifier corresponding to the virtual address is determined to distinguish the memory region type. Based on the process identifier and segment identifier, the first segment version number stored in the segment version register matrix is ​​read, and the second segment version number stored in the entry is retrieved from the translation back buffer. The validity of the cache entry is determined by comparing the two segment version numbers. Independent version control by process and memory region is achieved by relying on the process identifier and segment identifier. The corresponding cache is marked as invalid by only modifying the version number of the corresponding memory region. There is no need to clear the translation back buffer globally or for the entire process. By narrowing the scope of invalid cache, the cache hit rate of the translation back buffer is improved.

[0136] To implement the consistency management method provided in the embodiments of this application, the embodiments of this application also provide a consistency management device, such as... Figure 5 As shown. Figure 5 This is a schematic diagram of a consistency management device provided in an embodiment of this application. The consistency management device 500 is applied to a memory management unit and includes: The acquisition unit 501 is used to acquire the process identifier of the target process and the virtual address in the memory access instruction in response to receiving a memory access instruction; The first determining unit 502 is used to determine the segment identifier corresponding to the virtual address. The segment identifier is used to indicate the memory region type to which the virtual address belongs. The memory region type includes at least one of code segment, data segment, heap, stack, and shared library. The reading unit 503 is used to read the corresponding first segment version number from the segment version register matrix of the memory management unit based on the process identifier and the segment identifier, and to perform a retrieval operation on the translation back buffer using the virtual address and the process identifier as indexes. The second determining unit 504 is used to read the stored second version number from the matching entry when a matching entry is obtained; The third determining unit 505 is used to determine that the matching entry in the translation backup buffer is valid when the first segment version number is the same as the second segment version number. The fourth determining unit 506 is used to determine that the matching entry in the translation backup buffer is invalid when the first segment version number is different from the second segment version number.

[0137] In one embodiment, the first determining unit 502 is specifically used for: Extract a preset length of bits from the virtual address to obtain the segment encoding field; Based on the encoding mapping relationship pre-stored in the segment mask register, the segment encoding field is mapped to the segment identifier corresponding to the virtual address.

[0138] In one embodiment, the reading unit 503 is specifically used for: Using the process identifier as the row index and the segment identifier as the column index, locate the target register unit in the segment version register matrix; Read the version count value stored in the target register unit and determine the version count value as the first version number.

[0139] In one embodiment, the consistency management device 500 further includes an update unit, which is used to: In response to a modification operation on the page table entry corresponding to the target virtual address, the segment identifier corresponding to the target virtual address and the process identifier of the current process are determined. An increment operation is performed on the version number at the position corresponding to the segment identifier of the target virtual address and the process identifier of the current process in the segment version register matrix to update the first segment version number; If the version number of the first segment is zeroed after the update, a cache invalidation operation is performed on the memory region corresponding to the segment identifier of the target virtual address and the process identifier of the current process.

[0140] In one embodiment, the consistency management device 500 further includes a conversion unit, which is used to: If a matching entry in the translation backup buffer is determined to be valid, address translation is performed based on the physical address stored in the matching entry; If it is determined that a matching entry in the translation backup buffer is invalid, a translation backup buffer missing exception is triggered.

[0141] In one embodiment, the consistency management device 500 further includes a writing unit, which is used for: Read the new page table entry corresponding to the virtual address from the off-chip memory; Extract the physical address from the new page table entry, and determine the segment identifier corresponding to the physical address in the new page table entry; Based on the virtual address, the physical address in the new page table entry, the segment identifier corresponding to the physical address in the new page table entry, the process identifier, and the first segment version number, a new translation back buffer entry is generated; The new translation backup buffer entry is written into the storage unit of an idle translation backup buffer. The new translation backup buffer entry is extended with a segment version field on the basis of the original entry structure. The segment version field is used to store the first segment version number.

[0142] It should be noted that the consistency management device provided in the above embodiments is only illustrated by the division of the above program modules when performing consistency management. In practical applications, the above processing can be assigned to different program modules as needed, that is, the internal structure of the consistency management device can be divided into different program modules to complete all or part of the processing described above. In addition, the consistency management device provided in the above embodiments and the consistency management method provided in the embodiments of this application belong to the same concept, and the specific implementation process can be found in the method embodiments, which will not be repeated here.

[0143] Figure 6 This is a schematic diagram of the hardware composition structure of the electronic device provided in the embodiments of this application, such as... Figure 6 As shown, the electronic device 600 includes at least one processor 602; and a memory 601 communicatively connected to at least one processor 602; wherein the memory 601 stores instructions that can be executed by at least one processor 602, and the instructions are executed by at least one processor 602 to implement the steps of the consistency management method of the embodiments of this application.

[0144] Optionally, the electronic device may specifically be a consistency management device in the embodiments of this application, and the electronic device may implement the corresponding processes implemented by the consistency management device in the various methods of the embodiments of this application. For the sake of brevity, it will not be described in detail here.

[0145] It is understood that the electronic device also includes a communication interface 603. Various components in the electronic device are coupled together via a bus system 604. It is understood that the bus system 604 is used to implement communication between these components. In addition to a data bus, the bus system 604 also includes a power bus, a control bus, and a status signal bus. However, for clarity, in... Figure 6 The general designated all buses as Bus System 604.

[0146] It is understood that memory 601 can be volatile memory or non-volatile memory, or both. Non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), ferromagnetic random access memory (FRAM), flash memory, magnetic surface memory, optical disc, or compact disc read-only memory (CD-ROM); magnetic surface memory can be disk storage or magnetic tape storage. Volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as Static Random Access Memory (SRAM), Synchronous Static Random Access Memory (SSRAM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), Double Data Rate Synchronous Dynamic Random Access Memory (DDRSDRAM), Enhanced Synchronous Dynamic Random Access Memory (ESDRAM), SyncLink Dynamic Random Access Memory (SLDRAM), and Direct Rambus Random Access Memory (DRRAM).The memory 601 described in this embodiment of the invention is intended to include, but is not limited to, these and any other suitable types of memory.

[0147] The methods disclosed in the above embodiments of this application can be applied to processor 602, or implemented by processor 602. Processor 602 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the integrated logic circuit of the hardware in processor 602 or by instructions in the form of software. The processor 602 may be a general-purpose processor, DSP, or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Processor 602 can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this invention. The general-purpose processor may be a microprocessor or any conventional processor, etc. The steps of the methods disclosed in the embodiments of this invention can be directly manifested as being executed by a hardware decoding processor, or being executed by a combination of hardware and software modules in the decoding processor. The software modules may be located in a storage medium, which is located in memory 601. Processor 602 reads the information in memory 601 and combines its hardware to complete the steps of the aforementioned method.

[0148] In an exemplary embodiment, the electronic device may be implemented by one or more application-specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), complex programmable logic devices (CPLDs), FPGAs, general-purpose processors, controllers, MCUs, microprocessors, or other electronic components to perform the aforementioned method.

[0149] This application also provides a non-transitory computer-readable storage medium storing computer instructions, which are used to cause a computer to execute the steps of the consistency management method of the present invention.

[0150] Optionally, the computer-readable storage medium can be applied to the consistency management device in the embodiments of this application, and the computer instructions cause the computer to execute the corresponding processes implemented by the consistency management device in the various methods of the embodiments of this application. For the sake of brevity, they will not be described in detail here.

[0151] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the consistency management method provided in this invention.

[0152] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed can be through some interfaces, and the indirect coupling or communication connection between devices or units can be electrical, mechanical, or other forms.

[0153] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0154] In addition, in the various embodiments of the present invention, each functional unit can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit; the integrated unit can be implemented in hardware or in the form of hardware plus software functional units.

[0155] Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps of the above method embodiments. The aforementioned storage medium includes various media that can store program code, such as mobile storage devices, ROM, RAM, magnetic disks, or optical disks.

[0156] Alternatively, if the integrated units of this invention are implemented as software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of the embodiments of this invention, or the parts that contribute to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the methods of the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, ROM, RAM, magnetic disks, or optical disks.

[0157] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A consistency management method, characterized in that, Applied to a memory management unit, the method includes: In response to receiving a memory access instruction, the process identifier of the target process and the virtual address in the memory access instruction are obtained; Determine the segment identifier corresponding to the virtual address. The segment identifier is used to indicate the type of memory region to which the virtual address belongs. The type of memory region includes at least one of code segment, data segment, heap, stack, and shared library. Based on the process identifier and the segment identifier, the corresponding first segment version number is read from the segment version register matrix of the memory management unit, and a retrieval operation is performed on the translation back buffer using the virtual address and the process identifier as indexes; If a matching entry is found, the stored second version number is read from the matching entry; If the first segment version number is the same as the second segment version number, the matching entry in the translation backup buffer is determined to be valid; If the version number of the first segment is different from the version number of the second segment, it is determined that the matching entry in the translation backup buffer is invalid.

2. The method according to claim 1, characterized in that, Determining the segment identifier corresponding to the virtual address includes: Extract a preset length of bits from the virtual address to obtain the segment encoding field; Based on the encoding mapping relationship pre-stored in the segment mask register, the segment encoding field is mapped to the segment identifier corresponding to the virtual address.

3. The method according to claim 1, characterized in that, The step of reading the corresponding first segment version number from the segment version register matrix of the memory management unit based on the process identifier and the segment identifier includes: Using the process identifier as the row index and the segment identifier as the column index, locate the target register unit in the segment version register matrix; Read the version count value stored in the target register unit and determine the version count value as the first version number.

4. The method according to claim 3, characterized in that, The method further includes: In response to a modification operation on the page table entry corresponding to the target virtual address, the segment identifier corresponding to the target virtual address and the process identifier of the current process are determined. An increment operation is performed on the version number at the position corresponding to the segment identifier of the target virtual address and the process identifier of the current process in the segment version register matrix to update the first segment version number; If the version number of the first segment is zeroed after the update, a cache invalidation operation is performed on the memory region corresponding to the segment identifier of the target virtual address and the process identifier of the current process.

5. The method according to claim 1, characterized in that, The method further includes: If a matching entry in the translation backup buffer is determined to be valid, address translation is performed based on the physical address stored in the matching entry; If it is determined that a matching entry in the translation backup buffer is invalid, a translation backup buffer missing exception is triggered.

6. The method according to claim 5, characterized in that, After the trigger translation backup buffer missing exception occurs, the method further includes: Read the new page table entry corresponding to the virtual address from the off-chip memory; Extract the physical address from the new page table entry, and determine the segment identifier corresponding to the physical address in the new page table entry; Based on the virtual address, the physical address in the new page table entry, the segment identifier corresponding to the physical address in the new page table entry, the process identifier, and the first segment version number, a new translation back buffer entry is generated; The new translation backup buffer entry is written into the storage unit of an idle translation backup buffer. The new translation backup buffer entry is extended with a segment version field on the basis of the original entry structure. The segment version field is used to store the first segment version number.

7. A consistency management device, characterized in that, Applied to the memory management unit, including: The acquisition unit is configured to, in response to receiving a memory access instruction, acquire the process identifier of the target process and the virtual address in the memory access instruction; The first determining unit is used to determine the segment identifier corresponding to the virtual address. The segment identifier is used to indicate the memory region type to which the virtual address belongs. The memory region type includes at least one of code segment, data segment, heap, stack, and shared library. The reading unit is configured to read the corresponding first segment version number from the segment version register matrix of the memory management unit based on the process identifier and the segment identifier, and to perform a retrieval operation on the translation back buffer using the virtual address and the process identifier as indexes. The second determining unit is used to read the stored second version number from the matching entry when a matching entry is found. The third determining unit is used to determine that the matching entry in the translation backup buffer is valid when the first segment version number is the same as the second segment version number; The fourth determining unit is used to determine that the matching entry in the translation backup buffer is invalid when the version number of the first segment is different from the version number of the second segment.

8. An electronic device, characterized in that, include: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1 to 6.

9. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to perform the method according to any one of claims 1 to 6.

10. A computer program product, characterized in that, It includes a computer program that, when executed by a processor, implements the method of any one of claims 1 to 6.

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