A method, system, device and storage medium for generating a signal simulation model
By automatically constructing signal simulation models using deep learning models, the problem of poor signal simulation inheritance in existing technologies is solved, enabling fast and accurate simulation and correction in hardware design and testing, and improving universality and efficiency.
Patent Information
- Application Number
- CN202610776851.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-06-01
- Publication Date
- 2026-08-25
AI Technical Summary
Existing signal simulation technologies require manual data sourcing, have poor model inheritance and weak universality, cannot be used on a large scale, and cannot identify problems in hardware design in advance.
By acquiring the electrical schematic and test plan of the device under test, the data link direction is determined using a deep learning model, the simulation model is disassembled and reassembled, and a pre-trained graph neural network is used to construct graph structure data to automatically build a signal simulation model.
It achieves automation and universality of signal simulation, enabling rapid and accurate identification and correction of design defects during hardware design and testing, saving manpower and material resources.
Smart Images
Figure CN122635232A_ABST
Abstract
Description
Technical Field
[0001] This disclosure belongs to the field of signal simulation technology, and specifically relates to a method, system, device and storage medium for generating signal simulation models. Background Technology
[0002] Current signal simulation requires manually finding data and building models, which has poor inheritance and weak universality, making it unsuitable for widespread use.
[0003] However, in single-board hardware design and testing applications, signal simulation can identify problems in advance and guide the direction of modification, which greatly helps the success rate of the first version and the stability of the BOM. Summary of the Invention
[0004] To address the above problems, this disclosure provides a method for generating a signal simulation model, the method comprising: Obtain the electrical schematic and test plan of the device under test; Extract the data points from the electrical schematic and test plan of the device under test to obtain the data link; Determine the direction of the data link using a deep learning model; The data link is disassembled according to the link direction and then reassembled to obtain the simulation model.
[0005] Preferably, determining the data link direction through deep learning includes: Graph-structured data is constructed by treating data points in the data link as nodes and electrical connections between data points as edges. Generate a feature vector containing the attributes of each data point node; Input the graph structure data and node feature vectors into the deep learning model to predict the direction of each edge in the graph structure data. The prediction result is the direction of the data link. The deep learning model uses a pre-trained graph neural network.
[0006] Preferably, before determining the data link direction using a deep learning model, the method further includes: Assigning attributes to data points includes: staff manually assigning attributes to the data points, or automatically predicting data point attributes based on historical data; The data point attributes include a master attribute for identifying the signal driver, a null attribute for identifying intermediate transmission nodes, and a slave attribute for identifying the signal receiver.
[0007] Preferably, the step of disassembling the data link according to the link direction includes: Taking the data link after the direction is determined as input, the data link is decomposed into independent minimum functional units according to the decomposition rules; The smallest functional unit includes an input port and an output port, and its internal nodes only contain source nodes with primary or empty attributes and destination nodes with secondary or empty attributes.
[0008] Preferably, the disassembly rules include: Using the chip pin boundaries, signal bus physical boundaries, and test point nodes defined in the test scheme as disassembly points, the data link is divided into multiple minimum functional units.
[0009] Preferably, the disassembled data link is reassembled to obtain a simulation model, including: Obtain the source node of the primary attribute and the destination node of the secondary attribute from the disassembled data link; By traversing the smallest functional units obtained after decomposition using a depth-first search or path matching algorithm, a path can be found that starts from the source node of the main attribute, passes through one or more smallest functional units, and finally reaches the destination node of the subordinate attribute. The smallest functional units contained in the found path are combined according to their connection order to form a complete signal link from the source node of the primary attribute to the sink node of the secondary attribute, which serves as the simulation model. In the path finding process, the destination node of the previous smallest functional unit and the source node of the next smallest functional unit are allowed to be the same node.
[0010] Preferably, after obtaining the simulation model, the process further includes: Run the topology of the simulation model to obtain the simulation prediction results; The electrical schematic or PCB of the device under test is corrected based on the simulation prediction results.
[0011] This disclosure also proposes a signal simulation model generation system, the system comprising: The acquisition module is used to acquire the electrical schematic and test plan of the device under test. The extraction module is used to extract data points from the electrical schematic and test plan of the device under test to obtain the data link; The determination module is used to determine the direction of the data link through a deep learning model; The disassembly and reassembly module is used to disassemble the data link according to the link direction and reassemble it to obtain the simulation model.
[0012] This disclosure also proposes an electronic device, comprising: Processor and memory; The processor invokes the computer program stored in the memory to execute the method for generating the signal simulation model.
[0013] This disclosure also proposes a computer-readable storage medium. The computer-readable storage medium stores a computer program that, when executed by a processor, enables the processor to perform the method for generating the signal simulation model.
[0014] This disclosure has the following beneficial effects: (1) This disclosure can be widely used in hardware design and testing processes. It can simulate not only key signals, such as high-speed signals and clock signals, but also ordinary signals, such as I2C and SPI. It has the characteristics of strong inheritance, strong universality, and time and effort saving. (2) The model automatically builds in this disclosure, which has strong inheritance, high universality, and accurate data, and is convenient and fast; (3) This disclosure can be applied in the schematic and PCB design stages to simulate and predict common low-speed buses and high-speed buses, and correct the design; (4) Based on the multidimensionality of data and the reasonable modeling, this disclosure also considers signal simulation to replace white-box testing for some non-critical signals based on the actual measurement results, thereby saving manpower, material resources and time.
[0015] Other features and advantages of this disclosure will be set forth in the following description and will be apparent in part from the description or may be learned by practicing the disclosure. The objects and other advantages of this disclosure may be realized and obtained by means of the structures pointed out in the description and the accompanying drawings. Attached Figure Description
[0016] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0017] Figure 1 A diagram illustrating the method for generating a signal simulation model in an embodiment of this disclosure is shown. Figure 2 This diagram illustrates a hardware design flowchart for signal simulation guidance in an embodiment of this disclosure. Figure 3a This diagram illustrates a data link in an embodiment of the present disclosure. Figure 3b This diagram illustrates the disassembly of the data link in an embodiment of this disclosure. Figure 3c This diagram illustrates the reassembly of the disassembled data link in an embodiment of the present disclosure; Figure 4 This diagram illustrates the generation system of the signal simulation model in an embodiment of the present disclosure. Figure 5 A diagram of an electronic device according to an embodiment of this disclosure is shown. Detailed Implementation
[0018] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this disclosure more comprehensive and complete, and to fully convey the concept of the example embodiments to those skilled in the art. The described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a full understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced with one or more of the specific details omitted, or other methods, components, apparatus, steps, etc., can be employed. In other instances, well-known technical solutions are not shown or described in detail to avoid obscuring various aspects of this disclosure.
[0019] Furthermore, the accompanying drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware units or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.
[0020] The flowchart shown in the attached diagram is merely an illustrative example and does not necessarily include all steps. For example, some steps may be broken down, while others may be combined or partially combined; therefore, the actual execution order may change depending on the specific circumstances.
[0021] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented, for example, in orders other than those illustrated or described herein.
[0022] Furthermore, the terms “comprising” and “having”, and any variations thereof, are intended to cover non-exclusive inclusion, such that a process, method, system, product, or device that includes a series of steps or sub-modules is not necessarily limited to those steps or sub-modules that are explicitly listed, but may include other steps or sub-modules that are not explicitly listed or that are inherent to such process, method, product, or device.
[0023] like Figure 1 As shown, this disclosure proposes a method for generating a signal simulation model, the method comprising: Obtain the electrical schematic and test plan of the device under test; Extract the data points from the electrical schematic and test plan of the device under test to obtain the data link; Determine the direction of the data link using a deep learning model; The data link is disassembled according to the link direction and then reassembled to obtain the simulation model.
[0024] In this embodiment, the test scheme refers to the test scheme for the device under test, such as a single-disk white-box test scheme, which includes test items, such as I2C / SPI, etc. Under each item are specific test entries, including tag number, test point, pass criteria and other information.
[0025] Specifically, determining the data link direction through deep learning includes: Graph-structured data is constructed by treating data points in the data link as nodes and electrical connections between data points as edges. Generate a feature vector containing the attributes of each data point node; Input the graph structure data and node feature vectors into the deep learning model to predict the direction of each edge in the graph structure data. The prediction result is the direction of the data link. The deep learning model uses a pre-trained graph neural network.
[0026] In this embodiment, a graph neural network (GNN) is used as the deep learning model. GNNs can naturally process graph-structured data and are suitable for analyzing the connections between data points. Each data point is treated as a node in the GNN, and the attributes of the data points are encoded as node feature vectors. The electrical connections between data points (such as net connections) are treated as edges of the graph, forming graph-structured data. The trained GNN performs multiple rounds of message passing and iterative updates of node states on the graph-structured data, enabling each node to aggregate information from its neighbors. Finally, the edge state prediction module (e.g., a fully connected layer that takes the states of the nodes at both ends of an edge as input) outputs the directed direction of each edge, i.e., the direction from the driver to the receiver, as the data link direction. The training process of the graph neural network includes: constructing a training set consisting of multiple historical circuit diagrams with known link directions and their test schemes; for each training sample, extracting data points and connection relationships to form a graph structure, and using manually labeled link directions (i.e., the correct direction of each edge) as supervision labels; using the cross-entropy loss function and the Adam optimizer, updating the parameters of the graph neural network through backpropagation, iterating for multiple cycles until the loss converges.
[0027] A specific implementation of determining data link direction using deep learning: Graph Convolutional Network (GCN) is used as the graph neural network model. First, all data points are extracted as nodes from the netlist file derived from the circuit schematic. The original information of the data points includes: tag number (e.g., U1), pin name (e.g., PIN23), NET name (e.g., I2C_SCL), and IC type (e.g., CPU, FPGA, FLASH). Subsequently, engineers manually assign master, null, or slave attributes to each data point based on experience (e.g., CPU output pins are labeled "master," intermediate buffer pins are labeled "null," and receiver input pins are labeled "slave"). These three attributes are one-hot encoded to obtain a 3D vector, which is then concatenated with the IC type embedding vector (e.g., mapping different types of ICs to 32-dimensional vectors) and pin direction features (input / output / bidirectional, encoded as 3D vectors) to form the final node feature vector (e.g., 38-dimensional). Edge definition: If two data points belong to the same NET name, an undirected edge is established between them. This constructs a graph structure G=(V, E, X), where X is the node feature matrix.
[0028] The GCN model consists of two layers of graph convolutions, each with an output dimension of 64, and uses ReLU as the activation function. After the output of the second layer, for each edge (u,v), the state vectors h_u and h_v of its two endpoints are taken and input into a fully connected layer (128-dimensional input, 3-dimensional output). After passing through Softmax, the probability of the edge direction being "u→v", "v→u", or "bidirectional" is obtained. The direction with the highest output probability is taken as the predicted direction of the link.
[0029] During training, 100 historical single-board datasets from completed simulations were used, where the correct direction of each edge was known. The loss function was cross-entropy, the optimizer was Adam, the learning rate was 0.001, and the training lasted for 30 epochs. After training, the model can automatically infer the direction of the data link for a new single-board.
[0030] Specifically, before determining the data link direction through a deep learning model, the following steps are also included: Assign attributes to data points.
[0031] Specifically, the data point attributes include a master attribute for identifying the signal driving end, an empty attribute for identifying intermediate transmission nodes, and a slave attribute for identifying the signal receiving end.
[0032] In this embodiment, before inputting the graph neural network, one-hot encoding or embedding encoding is used to convert the primary attribute, null attribute, and secondary attribute into fixed-dimensional numerical vectors, which are then concatenated with features such as the data point's tag number, pin type, and network name to form node feature vectors. This allows empirical knowledge (manually assigned subordinate relationships) to be integrated into the deep learning model.
[0033] Specifically, the step of disassembling the data link according to the link direction includes: Taking the data link after the direction is determined as input, the data link is decomposed into independent minimum functional units according to the decomposition rules; The smallest functional unit includes an input port and an output port, and its internal nodes only contain source nodes with primary or empty attributes and destination nodes with secondary or empty attributes.
[0034] In this embodiment, the complete data link (with directional labels) after determining its direction is taken as input. Based on chip boundaries (e.g., connections between different ICs), signal bus boundaries (e.g., physical segments of the I2C bus SCL / SDA), and test point nodes defined in the test plan, the complete data link is decomposed into multiple independent minimum functional units. Each minimum functional unit has a unique input port and output port, and its internal nodes contain only one source node (primary or empty) and one sink node (slave or empty). The purpose of this decomposition is to break down the complex network into independently reusable basic modules. For example, "CPU output pin → level converter" is one minimum functional unit, and "level converter → temperature sensor input" is another minimum functional unit.
[0035] Specifically, the disassembly rules include: Using the chip pin boundaries, signal bus physical boundaries, and test point nodes defined in the test scheme as disassembly points, the data link is divided into multiple minimum functional units.
[0036] Specifically, the disassembled data links are reassembled to obtain a simulation model, including: Obtain the source node of the primary attribute and the destination node of the secondary attribute from the disassembled data link; By traversing the smallest functional units obtained after decomposition using a depth-first search or path matching algorithm, a path can be found that starts from the source node of the main attribute, passes through one or more smallest functional units, and finally reaches the destination node of the subordinate attribute. The smallest functional units contained in the found path are combined according to their connection order to form a complete signal link from the source node of the primary attribute to the sink node of the secondary attribute, which serves as the simulation model. In the path finding process, the destination node of the previous smallest functional unit and the source node of the next smallest functional unit are allowed to be the same node.
[0037] In this embodiment, the source node (usually a master node, such as a CPU output pin) and destination node (usually a slave node, such as a temperature sensor input pin) of the signal link to be simulated specified in the test plan are obtained. Then, from all the decomposed minimum functional units, a path search algorithm (e.g., depth-first search) is used to find all paths that start from the source node, pass through several minimum functional units, and finally reach the destination node. During the path search, the allowed connection conditions are: the destination node of the previous functional unit and the source node of the next functional unit must be the same node, and the attribute of the node can be empty (i.e., intermediate node). The search is not limited by the number of empty attribute nodes, and various topologies such as "master-empty-slave" and "master-empty-empty-slave" can be formed. By combining all the matched minimum functional units in the connection order, a complete link from the specified master attribute source node to the specified slave attribute destination node can be generated. This link retains all the intermediate empty attribute nodes (such as test points, connectors, wiring segments, etc.), so that the simulation model can accurately reflect every physical node on the actual signal transmission path, thereby meeting the simulation accuracy requirements. The generated link topology can be directly used for signal integrity simulation.
[0038] In this embodiment, the specific implementation method for the step "disassembling and reassembling the simulation model" is as follows: Figures 3a-3c As shown: Taking the I2C bus in an actual single-board unit as an example. After the direction is determined, the complete data link (with direction) includes the following nodes and edges (simplified representation), such as... Figure 3a As shown: Node A (CPU, Master) → Node B (Connector Pin, Empty) → Node C (Level Shifter Input Pin, Empty) → Node D (Level Shifter Output Pin, Empty) → Node E (Temperature Sensor Pin, Slave).
[0039] At the same time, node D is also connected to another node F (EEPROM pin, slave attribute), forming a branch.
[0040] During the disassembly phase, the chip is disassembled into its smallest functional units based on chip boundaries, bus boundaries, and test points (e.g., test points are located at connector node B), as follows: Figure 3b As shown: Unit 1: CPU (A main) → Connector pin (B empty) (Source end = A main, Destination end = B empty) Unit 2: Connector pin (B empty) → Level shifter input pin (C empty), (Source end = B empty, Destination end = C empty) Unit 3: Level converter internals (input → output), (source = C blank, destination = D blank) Unit 4: Level Shifter Output Pin (D Empty) → Temperature Sensor Pin (E Slave), (Source = D Empty, Destination = E Slave) Unit 5: Level Shifter Output Pin (D Empty) → EEPROM Pin (F Slave), (Source = D Empty, Destination = F Slave) During the assembly phase, one test item in the test plan is: "Test the I2C signal from the CPU (master attribute) to the temperature sensor (slave attribute)".
[0041] The starting unit is determined to be unit 1 (source end = A), and the ending unit is determined to be unit 4 (destination end = E).
[0042] Starting from cell 1, its destination is empty (B). Searching for cells with B as the source, we get cell 2 (source = empty B). Cell 2's destination is empty (C). Searching for cells with C as the source, we get cell 3 (source = empty C). Cell 3's destination is empty (D). Searching for cells with D as the source, we get cell 4 (source = empty D). Cell 4's destination is empty (D). Searching for cells with D as the source, we get cell 4 (source = empty D). Cell 4's destination is E (from), matching the termination condition.
[0043] like Figure 3c As shown, the nodes are connected in sequence: Unit 1 → Unit 2 → Unit 3 → Unit 4, forming a complete link: CPU (master) → B (empty) → C (empty) → D (empty) → temperature sensor (slave). All intermediate empty attribute nodes (B, C, D) are retained in the link, which can be directly used for signal integrity simulation.
[0044] If the test plan requires "testing the IIC signal from the CPU to the EEPROM", then the path search will result in Unit 1 → Unit 2 → Unit 3 → Unit 5, another complete link.
[0045] Through the specific decomposition (decomposing into the smallest functional units by boundary) and assembly (matching and connecting by empty nodes) algorithms described above, this disclosure can automatically generate an accurate simulation model containing all necessary intermediate nodes from a complex, well-defined complete data link, based on the simplified source-destination requirements of the test scheme, without the need for manual construction.
[0046] Specifically, assigning attributes to data points includes: staff manually assigning data point attributes to the data points, or automatically predicting data point attributes based on historical data.
[0047] like Figure 2 As shown, after obtaining the simulation model, it includes: Run the simulation model and obtain the simulation prediction results; The electrical schematic or PCB of the device under test is corrected based on the simulation prediction results.
[0048] like Figure 4 As shown, this disclosure also proposes a signal simulation model generation system, the system comprising: The acquisition module is used to acquire the electrical schematic and test plan of the device under test. The extraction module is used to extract data points from the electrical schematic and test plan of the device under test to obtain the data link; The determination module is used to determine the direction of the data link through a deep learning model; The disassembly and reassembly module is used to disassemble the data link according to the link direction and reassemble it to obtain the simulation model.
[0049] like Figure 5 As shown, corresponding to the topology generation method for signal simulation models provided above, this disclosure also provides a topology generation device for signal simulation models. Since the embodiment of this device is similar to the above method embodiment, the description is relatively simple; relevant details can be found in the description of the above method embodiment section. The device described below is merely illustrative. This device may include: a processor 1, a memory 2, a communication bus (i.e., the aforementioned device bus), and a lookup engine. The processor 1 and memory 2 communicate with each other via the communication bus and communicate with external systems via a communication interface. The processor 1 can call logical instructions in the memory 2 to execute the topology generation method for the signal simulation model.
[0050] Furthermore, the logical instructions in the aforementioned memory 2 can be implemented as software functional units and sold or used as independent products, and can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this disclosure, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this disclosure. The aforementioned storage medium includes various media capable of storing program code, such as memory chips, USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
[0051] On the other hand, this disclosure also provides a processor-readable storage medium storing a computer program 3, which, when executed by a processor 1, implements the topology generation method for the signal simulation model provided in the above embodiments.
[0052] The processor-readable storage medium can be any available medium or data storage device that the processor 1 can access, including but not limited to magnetic memory (e.g., floppy disk, hard disk, magnetic tape, magneto-optical disk (MO)), optical memory (e.g., CD, DVD, BD, HVD), and semiconductor memory (e.g., ROM, EPROM, EEPROM, non-volatile memory (NAND FLASH), solid-state drive (SSD)).
[0053] Those skilled in the art should understand that, despite the detailed description of this disclosure with reference to the foregoing embodiments, modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this disclosure.
Claims
1. A method for generating a signal simulation model, characterized in that, The method includes: Obtain the electrical schematic and test plan of the device under test; Extract the data points from the electrical schematic and test plan of the device under test to obtain the data link; Determine the direction of the data link using a deep learning model; The data link is disassembled according to the link direction and then reassembled to obtain the simulation model.
2. The method for generating a signal simulation model according to claim 1, characterized in that, The method of determining the data link direction through deep learning includes: Graph-structured data is constructed by treating data points in the data link as nodes and electrical connections between data points as edges. Generate a feature vector containing the attributes of each data point node; Input the graph structure data and node feature vectors into the deep learning model to predict the direction of each edge in the graph structure data. The prediction result is the direction of the data link. The deep learning model uses a pre-trained graph neural network.
3. The method for generating a signal simulation model according to claim 1, characterized in that, Before determining the data link direction using a deep learning model, the following is also included: Assigning attributes to data points includes: staff manually assigning attributes to the data points, or automatically predicting data point attributes based on historical data; The data point attributes include a master attribute for identifying the signal driver, a null attribute for identifying intermediate transmission nodes, and a slave attribute for identifying the signal receiver.
4. The method for generating a signal simulation model according to claim 1, characterized in that, The process of disassembling the data link according to the link direction includes: Taking the data link after the direction is determined as input, the data link is decomposed into independent minimum functional units according to the decomposition rules; The smallest functional unit includes an input port and an output port, and its internal nodes only contain source nodes with primary or empty attributes and destination nodes with secondary or empty attributes.
5. The method for generating a signal simulation model according to claim 4, characterized in that, The disassembly rules include: Using the chip pin boundaries, signal bus physical boundaries, and test point nodes defined in the test scheme as disassembly points, the data link is divided into multiple minimum functional units.
6. The method for generating a signal simulation model according to claim 4, characterized in that, The disassembled data link was reassembled to obtain the simulation model, including: Obtain the source node of the primary attribute and the destination node of the secondary attribute from the disassembled data link; By traversing the smallest functional units obtained after decomposition using a depth-first search or path matching algorithm, a path can be found that starts from the source node of the main attribute, passes through one or more smallest functional units, and finally reaches the destination node of the subordinate attribute. The smallest functional units contained in the found path are combined according to their connection order to form a complete signal link from the source node of the primary attribute to the sink node of the secondary attribute, which serves as the simulation model. In the path finding process, the destination node of the previous smallest functional unit and the source node of the next smallest functional unit are allowed to be the same node.
7. The method for generating a signal simulation model according to claim 1, characterized in that, After obtaining the simulation model, the process also includes: Run the simulation model and obtain the simulation prediction results; The electrical schematic or PCB of the device under test is corrected based on the simulation prediction results.
8. A signal simulation model generation system, characterized in that, The system includes: The acquisition module is used to acquire the electrical schematic and test plan of the device under test. The extraction module is used to extract data points from the electrical schematic and test plan of the device under test to obtain the data link; The determination module is used to determine the direction of the data link through a deep learning model; The disassembly and reassembly module is used to disassemble the data link according to the link direction and reassemble it to obtain the simulation model.
9. An electronic device, characterized in that, include: Processor and memory; The processor invokes the computer program stored in the memory to execute the signal simulation model generation method according to any one of claims 1 to 7.
10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, enables the processor to perform the method for generating the signal simulation model according to any one of claims 1 to 7.