A pixel driving circuit, display device and driving method

Abstract

The present disclosure relates to the technical field of display, and discloses a pixel driving circuit, a display device and a driving method. The pixel driving circuit comprises a driving transistor, a gating sub-circuit, a brightness control sub-circuit, a first light-emitting control sub-circuit and a light-emitting device. The first light-emitting control sub-circuit turns on the driving transistor and the light-emitting device in response to a signal of a first node. The brightness control sub-circuit is coupled between the first node and the gating sub-circuit, and provides a signal of a pulse control signal end or a signal of a light-emitting control signal end to the first node in response to a signal of a second node. The gating sub-circuit is coupled between the brightness control sub-circuit and a brightness gating control end, and provides a signal of the brightness gating control end to the second node in response to a signal of a first control end and a signal of a second control end. The setting of the gating sub-circuit reduces the high logic power consumption of the related switch tube caused by the high voltage driving requirement of the light-emitting device, and avoids the problem of switch tube failure.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and provides a pixel driving circuit, a display device, and a driving method. Background Technology

[0002] In related technologies, multiple shift registers are required to generate drive signals to drive the pixel drive circuit to work. Furthermore, the light-emitting devices in the pixel drive circuit require high drive signals to work properly. The aforementioned high-voltage drive requirements result in high logic power consumption of the relevant switching transistors, and in severe cases, may even cause some switching transistors in the shift registers to fail. Summary of the Invention

[0003] This disclosure provides a pixel driving circuit, a display device, and a driving method to reduce the high logic power consumption of the shift register caused by the high voltage driving requirements of the light-emitting device, thereby avoiding the failure of the switching transistor in the shift register.

[0004] The specific technical solution provided in this disclosure is as follows:

[0005] In a first aspect, embodiments of this disclosure provide a pixel driving circuit, including: a driving transistor, a gating sub-circuit, a brightness modulation sub-circuit, a first light emission control sub-circuit, and a light emission device;

[0006] The first light-emitting control sub-circuit is coupled between the driving transistor and the light-emitting device, and is configured to turn on the driving transistor and the light-emitting device in response to a signal from the first node.

[0007] The brightness control sub-circuit is coupled between the first node and the gating sub-circuit and is configured to respond to the signal of the second node by providing the signal from the pulse control signal terminal or the signal from the light emission control signal terminal to the first node.

[0008] The gating sub-circuit is coupled between the brightness control sub-circuit and the brightness gating control terminal, and is configured to respond to the signals of the first control terminal and the second control terminal, providing the signal of the brightness gating control terminal to the second node.

[0009] In some possible implementations, the gating sub-circuit includes: a first switching transistor, a second switching transistor, and a first capacitor, wherein the first switching transistor and the second switching transistor have opposite polarities;

[0010] The control terminal of the first switching transistor is coupled to the first control terminal, the first terminal of the first switching transistor is coupled to the second node, and the second terminal of the first switching transistor is coupled to the brightness gating control terminal.

[0011] The control terminal of the second switching transistor is coupled to the second control terminal, the first terminal of the second switching transistor is coupled to the second node, and the second terminal of the second switching transistor is coupled to the brightness gating control terminal.

[0012] The first terminal of the first capacitor is coupled to the second node, and the second terminal of the first capacitor is coupled to the ground terminal.

[0013] In some possible implementations, the gating sub-circuit includes: a third switching transistor and a second capacitor, wherein the third switching transistor includes a first gate and a second gate;

[0014] The first gate is coupled to the second control terminal, the second gate is coupled to the brightness gating control terminal, the first terminal of the third switching transistor is coupled to the second node, and the second terminal of the third switching transistor is coupled to the brightness gating control terminal.

[0015] The first terminal of the second capacitor is coupled to the second node, and the second terminal of the second capacitor is coupled to the ground terminal.

[0016] In some possible implementations, the brightness control sub-circuit includes a fourth switching transistor and a fifth switching transistor, wherein the fourth switching transistor and the fifth switching transistor have opposite polarities;

[0017] The control terminal of the fourth switching transistor is coupled to the second node, the first terminal of the fourth switching transistor is coupled to the light emission control signal terminal, and the second terminal of the fourth switching transistor is coupled to the first node.

[0018] The control terminal of the fifth switching transistor is coupled to the second node, the first terminal of the fifth switching transistor is coupled to the first node, and the second terminal of the fifth switching transistor is coupled to the pulse control signal terminal.

[0019] In some possible implementations, the first light-emitting control sub-circuit includes: a sixth switching transistor;

[0020] The control terminal of the sixth switching transistor is coupled to the first node, the first terminal of the sixth switching transistor is coupled to the second terminal of the driving transistor, and the second terminal of the sixth switching transistor is coupled to the anode of the light-emitting device.

[0021] In some possible implementations, a turn-on control sub-circuit is also included, which is coupled between the control terminal of the driving transistor and the second terminal of the driving transistor.

[0022] The turn-on control sub-circuit is configured to turn on the control terminal of the drive transistor and the second terminal of the drive transistor in response to the signal at the turn-on control signal terminal.

[0023] In some possible implementations, the turn-on control sub-circuit includes: a seventh switching transistor;

[0024] The control terminal of the seventh switching transistor is coupled to the conduction control signal terminal, the first terminal of the seventh switching transistor is coupled to the control terminal of the driving transistor, and the second terminal of the seventh switching transistor is coupled to the second terminal of the driving transistor.

[0025] In some possible implementations, a data writing sub-circuit is also included, which is coupled between the driving transistor and the data signal terminal;

[0026] The data writing sub-circuit is configured to provide a signal from the data signal terminal to the first terminal of the driving transistor in response to a signal from the first control terminal.

[0027] In some possible implementations, the data writing sub-circuit includes: an eighth switching transistor;

[0028] The control terminal of the eighth switching transistor is coupled to the first control terminal, the first terminal of the eighth switching transistor is coupled to the first terminal of the driving transistor, and the second terminal of the eighth switching transistor is coupled to the data signal terminal.

[0029] In some possible implementations, a second light-emitting control sub-circuit is also included, which is coupled between the first power supply terminal and the driving transistor.

[0030] The second light-emitting control sub-circuit is configured to turn on the first power supply terminal and the first terminal of the driving transistor in response to the signal at the light-emitting control signal terminal.

[0031] In some possible implementations, the second light-emitting control sub-circuit includes: a ninth switching transistor;

[0032] The control terminal of the ninth switching transistor is coupled to the light-emitting control signal terminal, the first terminal of the ninth switching transistor is coupled to the first power supply terminal, and the second terminal of the ninth switching transistor is coupled to the first terminal of the driving transistor.

[0033] In some possible implementations, a first reset circuit is also included, which is coupled between the driving transistor and the initialization signal terminal;

[0034] The first reset circuit is configured to provide the initialization signal to the control terminal of the driving transistor in response to the reset control signal.

[0035] In some possible implementations, the first reset circuit includes: a tenth switching transistor;

[0036] The control terminal of the tenth switching transistor is coupled to the reset control signal terminal, the first terminal of the tenth switching transistor is coupled to the control terminal of the driving transistor, and the second terminal of the tenth switching transistor is coupled to the initialization signal terminal.

[0037] In some possible implementations, a second reset circuit is also included, which is coupled between the light-emitting device and the initialization signal terminal;

[0038] The second reset circuit is configured to provide the initialization signal to the anode of the light-emitting device in response to the reset control signal.

[0039] In some possible implementations, the second reset circuit includes an eleventh switching transistor;

[0040] The control terminal of the eleventh switching transistor is coupled to the reset control signal terminal, the first terminal of the eleventh switching transistor is coupled to the initialization signal terminal, and the second terminal of the eleventh switching transistor is coupled to the anode of the light-emitting device.

[0041] In some possible implementations, a third capacitor is also included;

[0042] The first terminal of the third capacitor is coupled to the first power supply terminal, and the second terminal of the third capacitor is coupled to the control terminal of the driving transistor.

[0043] Secondly, embodiments of this disclosure also provide a display device including the pixel driving circuit of any of the above.

[0044] Thirdly, embodiments of this disclosure also provide a driving method for the pixel driving circuit of any of the above claims, comprising:

[0045] Initialization phase: The first reset sub-circuit responds to the signal at the reset control signal terminal by providing the signal at the initialization signal terminal to the control terminal of the driving transistor; and the second reset sub-circuit responds to the signal at the reset control signal terminal by providing the signal at the initialization signal terminal to the anode of the light-emitting device.

[0046] Data writing stage: The data writing sub-circuit responds to the signal at the first control terminal and provides the signal at the data signal terminal to the control terminal of the driving transistor;

[0047] Brightness control phase: The gating sub-circuit responds to the signal of the first control terminal by providing the signal of the brightness gating control terminal to the second node, and the brightness control sub-circuit responds to the signal of the second node by providing the signal of the light emission control signal terminal to the first node; or, the gating sub-circuit responds to the signal of the second control terminal by providing the signal of the brightness gating control terminal to the second node, and the brightness control sub-circuit responds to the signal of the second node by providing the signal of the pulse control signal terminal to the first node.

[0048] Light emission stage: In response to the signal at the light emission control signal terminal, the second light emission control sub-circuit turns on the first power supply terminal and the first terminal of the driving transistor; and in response to the signal at the first node, the first light emission control sub-circuit turns on the second terminal of the driving transistor and the anode of the light emission device.

[0049] The beneficial effects of this disclosure are as follows:

[0050] In summary, this disclosure provides a pixel driving circuit, a display device, and a driving method. The pixel driving circuit includes a driving transistor, a gating sub-circuit, a brightness control sub-circuit, a first light emission control sub-circuit, and a light-emitting device. The first light emission control sub-circuit is coupled between the driving transistor and the light-emitting device and is configured to turn on the driving transistor and the light-emitting device in response to a signal from a first node. The brightness control sub-circuit is coupled between the first node and the gating sub-circuit and is configured to provide the first node with a signal from a pulse control signal terminal or a light emission control signal terminal in response to a signal from a second node. The gating sub-circuit is coupled between the brightness control sub-circuit and a brightness gating control terminal and is configured to provide the second node with a signal from the brightness gating control terminal in response to a signal from a first control terminal and a signal from a second control terminal. The above-mentioned gating sub-circuit effectively reduces the high logic power consumption of the shift register caused by the high voltage driving requirement of the light-emitting device, thereby avoiding the problem of failure of some switching transistors in the shift register that may be caused by high voltage driving.

[0051] Other features and advantages of this disclosure will be set forth in the following description and will be apparent in part from the description or may be learned by practicing the disclosure. The objects and other advantages of this disclosure may be realized and obtained by means of the structures particularly pointed out in the written description, claims, and drawings. Attached Figure Description

[0052] The accompanying drawings, which are included to provide a further understanding of this disclosure and form part of this disclosure, illustrate exemplary embodiments of the present disclosure and are used to explain the disclosure, but do not constitute an undue limitation of the disclosure. In the drawings:

[0053] Figure 1 This is a circuit connection diagram of a shift register in related technologies;

[0054] Figure 2 This is a circuit connection diagram of a pixel driving circuit in related technologies;

[0055] Figure 3 This is a connection diagram of the first pixel driving circuit in an embodiment of this disclosure;

[0056] Figure 4 This is a circuit connection diagram of the first pixel driving circuit in the embodiments of this disclosure;

[0057] Figure 5 This is a circuit connection diagram of the second pixel driving circuit in an embodiment of this disclosure;

[0058] Figure 6 This is a connection diagram of the second pixel driving circuit in an embodiment of this disclosure;

[0059] Figure 7 This is a circuit connection diagram of the third pixel driving circuit in the embodiments of this disclosure;

[0060] Figure 8 This is a connection diagram of the third pixel driving circuit in an embodiment of this disclosure;

[0061] Figure 9 This is a circuit connection diagram of the fourth pixel driving circuit in the embodiments of this disclosure;

[0062] Figure 10 This is a connection diagram of the fourth pixel driving circuit in the embodiments of this disclosure;

[0063] Figure 11 This is a circuit connection diagram of the fifth pixel driving circuit in the embodiments of this disclosure;

[0064] Figure 12 This is a connection diagram of the fifth pixel driving circuit in the embodiments of this disclosure;

[0065] Figure 13 This is a circuit connection diagram of the sixth pixel driving circuit in the embodiments of this disclosure;

[0066] Figure 14 This is a connection diagram of the sixth pixel driving circuit in the embodiments of this disclosure;

[0067] Figure 15 This is a circuit connection diagram of the seventh pixel driving circuit in the embodiments of this disclosure;

[0068] Figure 16 This is a circuit connection diagram of the eighth pixel driving circuit in the embodiments of this disclosure;

[0069] Figure 17 This is a first timing diagram of a pixel driving circuit according to an embodiment of the present disclosure;

[0070] Figure 18 This is a second timing diagram of a pixel driving circuit according to an embodiment of the present disclosure;

[0071] Figure 19 This is a flowchart of a driving method applied to a pixel driving circuit according to an embodiment of the present disclosure. Detailed Implementation

[0072] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the technical solutions of this disclosure, and not all embodiments. Based on the embodiments recorded in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the technical solutions of this disclosure.

[0073] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in sequences other than those illustrated or described herein.

[0074] In related technologies, multiple shift registers are required to generate drive signals to drive the pixel drive circuit to work. Furthermore, the light-emitting devices in the pixel drive circuit require high drive signals to work properly. The aforementioned high-voltage drive requirements result in high logic power consumption of the relevant switching transistors, and in severe cases, may even cause some switching transistors in the shift registers to fail.

[0075] Combination Figure 1 , Figure 2 As shown in Table 1, to achieve the function of the pixel driving circuit—that is, to turn the switching transistors in the pixel driving circuit on or off—the VGH / VGL generated by the shift registers corresponding to different driving signals needs to be designed differently. For example, the VGH / VGL corresponding to the EM driving signal required by the pixel driving circuit is 10V / 0V, and the VGH / VGL corresponding to the Gate-GT driving signal required by the pixel driving circuit is 20V / -6V, etc. The corresponding logic power consumption P = CV for each switching transistor is... 2 F (where C is the capacitance connecting the signal line of the switching transistor, F is the charging and discharging frequency of the signal line of the switching transistor, and V is the voltage difference between the high and low levels of the signal line of the switching transistor) are different. Obviously, the logic power consumption of the Gate-GT drive signal accounts for a larger proportion, that is... Figure 2 The high logic power consumption of the switching transistor M3 in the pixel driver circuit can lead to… Figure 1 The switching transistor m5 in the shift register is prone to problems such as Vth offset, I-on reduction and burnout. In severe cases, the switching transistor m5 may even fail.

[0076]

[0077]

[0078] The preferred embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0079] See Figure 3 As shown in the embodiment of this application, a pixel driving circuit includes: a driving transistor DTFT, a gating sub-circuit 10, a brightness control sub-circuit 20, a first light emission control sub-circuit 30, and a light-emitting device LED.

[0080] The first light-emitting control sub-circuit 30 is coupled between the driving transistor DTFT and the light-emitting device LED, and is configured to turn on the driving transistor DTFT and the light-emitting device LED in response to the signal of the first node N1.

[0081] During implementation, when the signal of the first node N1 is valid, the first light-emitting control sub-circuit 30 is turned on, and the second terminal of the driving transistor DTFT is turned on through the first light-emitting control sub-circuit 30 and the anode of the light-emitting device LED.

[0082] The brightness control sub-circuit 20 is coupled between the first node N1 and the gating sub-circuit 10 and is configured to provide the signal of the pulse control signal terminal HF or the signal of the light emission control signal terminal EM to the first node N1 in response to the signal of the second node N2.

[0083] During implementation, when the signal of the second node N2 is valid, the brightness control sub-circuit 20 is turned on, and the signal of the pulse control signal terminal HF is provided to the first node N1 through the brightness control sub-circuit 20, or the signal of the light emission control signal terminal EM is provided to the first node N1 through the brightness control sub-circuit 20.

[0084] The gating sub-circuit 10 is coupled between the brightness control sub-circuit 20 and the brightness gating control terminal DATA_T, and is configured to provide the signal of the brightness gating control terminal DATA_T to the second node N2 in response to the signal of the first control terminal Gate and the signal of the second control terminal Gate-GT.

[0085] During implementation, when the signal of the first control terminal Gate is valid, the gating sub-circuit 10 is turned on, and the signal of the brightness gating control terminal DATA_T is provided to the second node N2 through the gating sub-circuit 10. Also, when the signal of the second control terminal Gate-GT is valid, the gating sub-circuit 10 is turned on, and the signal of the brightness gating control terminal DATA_T is provided to the second node N2 through the gating sub-circuit 10.

[0086] In summary, in this embodiment, the design of the gating sub-circuit 10 enables the time-division writing of the signal from the brightness gating control terminal DATA_T to the brightness modulation sub-circuit 20. Thus, the signal from the light emission control signal terminal EM, or the signal from the light emission control signal terminal EM combined with the pulse modulation signal terminal HF, will time-division control the signal from the first node N1. This achieves the goal of the first light emission control sub-circuit 30 driving the LED to emit light with low current density. The voltage difference required for the second control terminal Gate-GT during this process will decrease; that is, the VGH / VGL signal corresponding to the second control terminal Gate-GT will decrease from 20V / -6V to 15V / -3V, effectively reducing the high logic power consumption of the relevant switching transistors in the shift register.

[0087] In one embodiment, see [reference] Figure 4 As shown, the above-mentioned selection sub-circuit 10 includes: a first switching transistor T1, a second switching transistor T2 and a first capacitor C1, wherein the polarities of the first switching transistor T1 and the second switching transistor T2 are opposite.

[0088] The control terminal of the first switching transistor T1 is coupled to the first control terminal Gate, the first terminal of the first switching transistor T1 is coupled to the second node N2, and the second terminal of the first switching transistor T1 is coupled to the brightness gating control terminal DATA_T.

[0089] For example, the first switching transistor T1 can be turned on under the control of the effective level of the first control terminal Gate, and can be turned off under the control of the ineffective level of the first control terminal Gate. For example, if the first switching transistor T1 is set to an N-type transistor, then the effective level of the signal at the first control terminal Gate is a high level, and the ineffective level of the signal at the first control terminal Gate is a low level. Alternatively, if the first switching transistor T1 is set to a P-type transistor, then the effective level of the signal at the first control terminal Gate is a low level, and the ineffective level of the signal at the first control terminal Gate is a high level.

[0090] See Figure 4 As shown, the first switching transistor T1 is a P-type transistor. When the signal of the first control terminal Gate is low, the first switching transistor T1 is turned on, and the signal of the brightness selection control terminal DATA_T is provided to the second node N2 through the turned-on first switching transistor T1.

[0091] The control terminal of the second switching transistor T2 is coupled to the second control terminal Gate-GT, the first terminal of the second switching transistor T2 is coupled to the second node N2, and the second terminal of the second switching transistor T2 is coupled to the brightness gating control terminal DATA_T.

[0092] For example, the second switching transistor T2 can be turned on under the control of the active level of the second control terminal Gate-GT, and can be turned off under the control of the inactive level of the second control terminal Gate-GT. For example, if the second switching transistor T2 is set as an N-type transistor, then the active level of the signal at the second control terminal Gate-GT is a high level, and the inactive level of the signal at the second control terminal Gate-GT is a low level. Alternatively, if the second switching transistor T2 is set as a P-type transistor, then the active level of the signal at the second control terminal Gate-GT is a low level, and the inactive level of the signal at the second control terminal Gate-GT is a high level.

[0093] See Figure 4 As shown, the second switching transistor T2 is an N-type transistor. When the signal at the second control terminal Gate-GT is high, the second switching transistor T2 is turned on, and the signal at the brightness selection control terminal DATA_T is provided to the second node N2 through the turned-on second switching transistor T2.

[0094] The first terminal of the first capacitor C1 is coupled to the second node N2, and the second terminal of the first capacitor C1 is coupled to the ground terminal.

[0095] The aforementioned setting of the first capacitor C1 enables the storage of the signal from the brightness gating control terminal DATA_T.

[0096] In another embodiment, see [link to relevant documentation] Figure 5 As shown, the above-mentioned selection sub-circuit 10 includes: a third switching transistor T3 and a second capacitor C2, wherein the third switching transistor T3 includes a first gate and a second gate.

[0097] The first gate is coupled to the second control terminal Gate-GT, the second gate is coupled to the brightness gating control terminal DATA_T, the first terminal of the third switching transistor T3 is coupled to the second node N2, and the second terminal of the third switching transistor T3 is coupled to the brightness gating control terminal DATA_T.

[0098] In one embodiment, the first gate of the third switching transistor T3 can be turned on under the control of the effective level of the second control terminal Gate-GT, and turned off under the control of the ineffective level of the second control terminal Gate-GT. For example, when the first gate is N-type, the effective level of the signal at the second control terminal Gate-GT is high, and the ineffective level of the signal at the second control terminal Gate-GT is low. Alternatively, when the third switching transistor T3 is P-type, the effective level of the signal at the second control terminal Gate-GT is low, and the ineffective level of the signal at the second control terminal Gate-GT is high.

[0099] See Figure 5As shown, the first gate of the third switching transistor T3 is N-type. When the signal of the second control terminal Gate-GT is high, the third switching transistor T3 is turned on, and the signal of the brightness selection control terminal DATA_T is provided to the second node N2 through the turned-on third switching transistor T3.

[0100] In another embodiment, the second gate of the third switching transistor T3 can be turned on under the control of the active level of the brightness gating control terminal DATA_T, and turned off under the control of the inactive level of the brightness gating control terminal DATA_T. For example, when the second gate is N-type, the active level of the signal at the brightness gating control terminal DATA_T is high, and the inactive level of the signal at the brightness gating control terminal DATA_T is low. Alternatively, when the third switching transistor T3 is P-type, the active level of the signal at the brightness gating control terminal DATA_T is low, and the inactive level of the signal at the brightness gating control terminal DATA_T is high.

[0101] See Figure 5 As shown, the second gate of the third switching transistor T3 is N-type. When the signal of the brightness gating control terminal DATA_T is high, the third switching transistor T3 is turned on, and the signal of the brightness gating control terminal DATA_T is provided to the second node N2 through the turned-on third switching transistor T3.

[0102] The first end of the second capacitor C2 is coupled to the second node N2, and the second end of the second capacitor C2 is coupled to the ground terminal.

[0103] Similarly, the aforementioned second capacitor C2 enables the storage of the signal from the brightness gating control terminal DATA_T.

[0104] See Figure 4 and Figure 5 As shown, the brightness control sub-circuit 20 includes a fourth switching transistor T4 and a fifth switching transistor T5, wherein the fourth switching transistor T4 and the fifth switching transistor T5 have opposite polarities.

[0105] The control terminal of the fourth switching transistor T4 is coupled to the second node N2, the first terminal of the fourth switching transistor T4 is coupled to the light emission control signal terminal EM, and the second terminal of the fourth switching transistor T4 is coupled to the first node N1.

[0106] For example, the fourth switching transistor T4 can be turned on under the control of the active level of the second node N2, and turned off under the control of the inactive level of the second node N2. For example, if the fourth switching transistor T4 is set as an N-type transistor, then the active level of the signal at the second node N2 is a high level, and the inactive level of the signal at the second node N2 is a low level. Alternatively, if the fourth switching transistor T4 is set as a P-type transistor, then the active level of the signal at the second node N2 is a low level, and the inactive level of the signal at the second node N2 is a high level.

[0107] See Figure 4 and Figure 5 As shown, the fourth switching transistor T4 is an N-type transistor. When the signal of the second node N2 is high, the fourth switching transistor T4 is turned on, and the signal of the light emission control signal terminal EM is provided to the first node N1 through the turned-on fourth switching transistor T4.

[0108] The control terminal of the fifth switching transistor T5 is coupled to the second node N2, the first terminal of the fifth switching transistor T5 is coupled to the first node N1, and the second terminal of the fifth switching transistor T5 is coupled to the pulse control signal terminal HF.

[0109] For example, the fifth switching transistor T5 can be turned on under the control of the effective level of the second node N2, and turned off under the control of the ineffective level of the second node N2. For example, if the fifth switching transistor T5 is set as an N-type transistor, then the effective level of the signal at the second node N2 is a high level, and the ineffective level of the signal at the second node N2 is a low level. Alternatively, if the fifth switching transistor T5 is set as a P-type transistor, then the effective level of the signal at the second node N2 is a low level, and the ineffective level of the signal at the second node N2 is a high level.

[0110] See Figure 4 and Figure 5 As shown, the fifth switching transistor T5 is a P-type transistor. When the signal of the second node N2 is low, the fifth switching transistor T5 is turned on, and the signal of the pulse control signal terminal HF is provided to the first node N1 through the turned-on fifth switching transistor T5.

[0111] See Figure 4 and Figure 5 As shown, the first light-emitting control sub-circuit 30 includes: a sixth switching transistor T6.

[0112] The control terminal of the sixth switching transistor T6 is coupled to the first node N1, the first terminal of the sixth switching transistor T6 is coupled to the second terminal of the driving transistor DTFT, and the second terminal of the sixth switching transistor T6 is coupled to the anode of the light-emitting device LED.

[0113] For example, the sixth switching transistor T6 can be turned on under the control of the effective level of the first node N1, and can be turned off under the control of the ineffective level of the first node N1. For example, if the sixth switching transistor T6 is set as an N-type transistor, then the effective level of the signal of the first node N1 is a high level, and the ineffective level of the signal of the first node N1 is a low level. Alternatively, if the sixth switching transistor T6 is set as a P-type transistor, then the effective level of the signal of the first node N1 is a low level, and the ineffective level of the signal of the first node N1 is a high level.

[0114] See Figure 4 and Figure 5 As shown, the sixth switching transistor T6 is a P-type transistor. When the signal of the first node N1 is low, the sixth switching transistor T6 is turned on, and the second terminal of the driving transistor DTFT is connected to the anode of the light-emitting device LED through the sixth switching transistor T6.

[0115] See Figure 6 As shown, the pixel driving circuit also includes a turn-on control sub-circuit 40, which is coupled between the control terminal of the driving transistor DTFT and the second terminal of the driving transistor DTFT.

[0116] The turn-on control sub-circuit 40 is configured to turn on the control terminal of the driving transistor DTFT and the second terminal of the driving transistor DTFT in response to the signal of the turn-on control signal terminal Gate-N.

[0117] During implementation, when the signal at the Gate-N control terminal is valid, the control circuit 40 is turned on, and the control terminal of the driving transistor DTFT is connected to the second terminal of the driving transistor DTFT via the control circuit 40.

[0118] See Figure 7 As shown, the conduction control sub-circuit 40 includes: a seventh switching transistor T7.

[0119] The control terminal of the seventh switching transistor T7 is coupled to the gate-N control signal terminal, the first terminal of the seventh switching transistor T7 is coupled to the control terminal of the driving transistor DTFT, and the second terminal of the seventh switching transistor T7 is coupled to the second terminal of the driving transistor DTFT.

[0120] For example, the seventh switching transistor T7 can be turned on under the control of an active level at the gate-N control signal terminal, and can be turned off under the control of an inactive level at the gate-N control signal terminal. For example, if the seventh switching transistor T7 is configured as an N-type transistor, then the active level of the gate-N control signal terminal is high, and the inactive level is low. Alternatively, if the seventh switching transistor T7 is configured as a P-type transistor, then the active level of the gate-N control signal terminal is low, and the inactive level is high.

[0121] See Figure 7 As shown, the seventh switching transistor T7 is an N-type transistor. When the signal at the Gate-N control terminal is high, the seventh switching transistor T7 is turned on, and the control terminal of the driving transistor DTFT is connected to the second terminal of the driving transistor DTFT through the seventh switching transistor T7.

[0122] See Figure 8 As shown, the pixel driving circuit also includes a data writing sub-circuit 50, which is coupled between the driving transistor DTFT and the data signal terminal DATA_I.

[0123] The data writing sub-circuit 50 is configured to provide the data signal terminal DATA_I to the first terminal of the driving transistor DTFT in response to the signal of the first control terminal Gate.

[0124] During implementation, when the signal of the first control terminal Gate is valid, the data writing sub-circuit 50 is turned on, and the signal of the data signal terminal DATA_I is provided to the first terminal of the driving transistor DTFT through the turned-on data writing sub-circuit 50.

[0125] See Figure 9 As shown, the data writing sub-circuit 50 includes: an eighth switching transistor T8.

[0126] The control terminal of the eighth switching transistor T8 is coupled to the first control terminal Gate, the first terminal of the eighth switching transistor T8 is coupled to the first terminal of the driving transistor DTFT, and the second terminal of the eighth switching transistor T8 is coupled to the data signal terminal DATA_I.

[0127] For example, the eighth switching transistor T8 can be turned on under the control of the effective level of the first control terminal Gate, and can be turned off under the control of the ineffective level of the first control terminal Gate. For example, if the eighth switching transistor T8 is set as an N-type transistor, then the effective level of the signal at the first control terminal Gate is a high level, and the ineffective level of the signal at the first control terminal Gate is a low level. Alternatively, if the eighth switching transistor T8 is set as a P-type transistor, then the effective level of the signal at the first control terminal Gate is a low level, and the ineffective level of the signal at the first control terminal Gate is a high level.

[0128] See Figure 9 As shown, the eighth switching transistor T8 is a P-type transistor. When the signal at the first control terminal Gate is low, the eighth switching transistor T8 is turned on, and the signal at the data signal terminal DATA_I is provided to the first terminal of the driving transistor DTFT through the turned-on eighth switching transistor T8.

[0129] See Figure 10 As shown, the pixel driving circuit also includes a second light-emitting control sub-circuit 60, which is coupled between the first power supply terminal VDD and the driving transistor DTFT.

[0130] The second light-emitting control sub-circuit 60 is configured to turn on the first power supply terminal VDD and the first terminal of the driving transistor DTFT in response to the signal of the light-emitting control signal terminal EM.

[0131] During implementation, when the signal of the light emission control signal terminal EM is valid, the second light emission control sub-circuit 60 is turned on, and the first power supply terminal VDD is turned on through the turned-on second light emission control sub-circuit 60 and the first terminal of the driving transistor DTFT.

[0132] See Figure 11 As shown, the second light-emitting control sub-circuit 60 includes: a ninth switching transistor T9.

[0133] The control terminal of the ninth switching transistor T9 is coupled to the light emission control signal terminal EM, the first terminal of the ninth switching transistor T9 is coupled to the first power supply terminal VDD, and the second terminal of the ninth switching transistor T9 is coupled to the first terminal of the driving transistor DTFT.

[0134] For example, the ninth switching transistor T9 can be turned on under the control of the effective level of the light-emitting control signal terminal EM, and can be turned off under the control of the ineffective level of the light-emitting control signal terminal EM. For example, if the ninth switching transistor T9 is set as an N-type transistor, then the effective level of the signal at the light-emitting control signal terminal EM is a high level, and the ineffective level of the signal at the light-emitting control signal terminal EM is a low level. Alternatively, if the ninth switching transistor T9 is set as a P-type transistor, then the effective level of the signal at the light-emitting control signal terminal EM is a low level, and the ineffective level of the signal at the light-emitting control signal terminal EM is a high level.

[0135] See Figure 11 As shown, the ninth switching transistor T9 is a P-type transistor. When the signal at the light emission control signal terminal EM is low, the ninth switching transistor T9 is turned on, and the first power supply terminal VDD is connected to the first terminal of the driving transistor DTFT through the turned-on ninth switching transistor T9.

[0136] See Figure 12 As shown, the pixel driving circuit also includes a first reset circuit 70, which is coupled between the driving transistor DTFT and the initialization signal terminal Vinit.

[0137] The first reset circuit 70 is configured to provide the initialization signal Vinit to the control terminal of the driving transistor DTFT in response to the reset control signal terminal RST.

[0138] During implementation, when the reset control signal terminal RST is valid, the first reset sub-circuit 70 is turned on, and the initialization signal terminal Vinit is provided to the control terminal of the driving transistor DTFT through the turned-on first reset sub-circuit 70.

[0139] See Figure 13 As shown, the first reset circuit 70 includes: a tenth switching transistor T10.

[0140] The control terminal of the tenth switching transistor T10 is coupled to the reset control signal terminal RST, the first terminal of the tenth switching transistor T10 is coupled to the control terminal of the driving transistor DTFT, and the second terminal of the tenth switching transistor T10 is coupled to the initialization signal terminal Vinit.

[0141] For example, the tenth switching transistor T10 can be turned on under the control of the active level of the reset control signal terminal RST, and can be turned off under the control of the inactive level of the reset control signal terminal RST. For example, if the tenth switching transistor T10 is set as an N-type transistor, then the active level of the reset control signal terminal RST is a high level, and the inactive level of the reset control signal terminal RST is a low level. Alternatively, if the tenth switching transistor T10 is set as a P-type transistor, then the active level of the reset control signal terminal RST is a low level, and the inactive level of the reset control signal terminal RST is a high level.

[0142] See Figure 13 As shown, the tenth switching transistor T10 is an N-type transistor. When the reset control signal RST is high, the tenth switching transistor T10 is turned on, and the initialization signal Vinit is provided to the control terminal of the driving transistor DTFT through the turned-on tenth switching transistor T10.

[0143] See Figure 14 As shown, the pixel driving circuit also includes a second reset circuit 80, which is coupled between the light-emitting device LED and the initialization signal terminal Vinit.

[0144] The second reset circuit 80 is configured to provide the initialization signal Vinit to the anode of the light-emitting device LED in response to the reset control signal RST.

[0145] During implementation, when the reset control signal terminal RST is valid, the second reset sub-circuit 80 is turned on, and the initialization signal terminal Vinit is provided to the anode of the light-emitting device LED through the turned-on second reset sub-circuit 80.

[0146] See Figure 15 As shown, the second reset circuit 80 includes an eleventh switching transistor T11.

[0147] The control terminal of the eleventh switching transistor T11 is coupled to the reset control signal terminal RST, the first terminal of the eleventh switching transistor T11 is coupled to the initialization signal terminal Vinit, and the second terminal of the eleventh switching transistor T11 is coupled to the anode of the light-emitting device LED.

[0148] For example, the eleventh switching transistor T11 can be turned on under the control of the active level of the reset control signal terminal RST, and can be turned off under the control of the inactive level of the reset control signal terminal RST. For example, if the eleventh switching transistor T11 is set as an N-type transistor, then the active level of the reset control signal terminal RST is a high level, and the inactive level of the reset control signal terminal RST is a low level. Alternatively, if the eleventh switching transistor T11 is set as a P-type transistor, then the active level of the reset control signal terminal RST is a low level, and the inactive level of the reset control signal terminal RST is a high level.

[0149] See Figure 15 As shown, the eleventh switching transistor T11 is an N-type transistor. When the reset control signal terminal RST is high, the eleventh switching transistor T11 is turned on, and the initialization signal terminal Vinit is provided to the anode of the light-emitting device LED through the turned-on eleventh switching transistor T11.

[0150] In addition, see Figure 16 As shown, the pixel driving circuit described above also includes a third capacitor C3.

[0151] The first terminal of the third capacitor C3 is coupled to the first power supply terminal VDD, and the second terminal of the third capacitor C3 is coupled to the control terminal of the driving transistor DTFT.

[0152] During implementation, the voltage across the third capacitor C3 changes with the voltage at the control terminal of the driving transistor DTFT, thereby completing operations such as initialization and data writing at the control terminal of the driving transistor DTFT.

[0153] The following section describes the circuit connection. Figure 16 Timing diagram Figure 17 Timing diagram Figure 18 The operation of the pixel driving circuit in the embodiments of this application is described in detail.

[0154] In this context, 0 represents a low signal level, and 1 represents a high signal level.

[0155] Timing stage t1: VDD=1, VSS=0, EM=1, HF=1, RST=1, Gate=1, Gate-N=0, Gate-GT=0, DATA_I=1, DATA_T=0

[0156] When the reset control signal RST is high, the tenth switching transistor T10 is turned on. The initialization signal Vinit is provided to the control terminal of the driving transistor DTFT via the turned-on tenth switching transistor T10, thereby initializing the control terminal of the driving transistor DTFT. When the reset control signal RST is high, the eleventh switching transistor T11 is turned on. The initialization signal Vinit is provided to the anode of the light-emitting device LED via the turned-on eleventh switching transistor T11, thereby initializing the anode of the light-emitting device LED.

[0157] Timing t2 stage: VDD=1, VSS=0, EM=1, HF=1, RST=0, Gate=0, Gate-N=1, Gate-GT=0, DATA_I=1, DATA_T=1

[0158] When the signal at the first control terminal Gate is low, the eighth switching transistor T8 is turned on, and the data signal DATA_I is supplied to the first terminal of the driving transistor DTFT via the turned-on eighth switching transistor T8. When the signal at the conduction control terminal Gate-N is high, the seventh switching transistor T7 is turned on, and the second terminal of the driving transistor DTFT is connected to the control terminal of the driving transistor DTFT via the turned-on seventh switching transistor T7, thereby writing the data signal DATA_I to the control terminal of the driving transistor DTFT and storing the data signal DATA_I in the third capacitor C3.

[0159] Simultaneously, when the signal at the first control terminal Gate is low, the first switching transistor T1 is turned on, and the high-level signal of the brightness selection control terminal DATA_T is written into the first capacitor C1 through the turned-on first switching transistor T1. The second node N2 is high, the fourth switching transistor T4 is turned on, and the high-level signal of the light emission control signal terminal EM is written into the first node N1 through the turned-on fourth switching transistor T4.

[0160] Timing t3 stage: VDD=1, VSS=0, EM=1, HF=1, RST=0, Gate=1, Gate-N=0, Gate-GT=1, DATA_I=1, DATA_T=1

[0161] The second node N2 maintains a high-level signal, the fourth switching transistor T4 is turned on, and the high-level signal of the light emission control signal terminal EM is written to the first node N1 through the turned-on fourth switching transistor T4.

[0162] Timing stage t4: VDD=1, VSS=0, EM=0, HF is a pulse signal from 0 to 1, RST=0, Gate=1, Gate-N=0, Gate-GT=0, DATA_I=1, DATA_T=0

[0163] When the light-emitting control signal EM is low, the ninth switching transistor T9 is turned on, and the first power supply terminal VDD is connected to the first terminal of the driving transistor DTFT via the turned-on ninth switching transistor T9. The second node N2 remains high, and the fourth switching transistor T4 is turned on. The low-level signal of the light-emitting control signal EM is written to the first node N1 via the turned-on fourth switching transistor T4. When the first node N1 is low, the sixth switching transistor T6 is turned on, and the second terminal of the driving transistor DTFT is connected to the anode of the light-emitting device LED via the turned-on sixth switching transistor T6, causing the LED to emit light.

[0164] Timing t3' stage: VDD=1, VSS=0, EM=1, HF is a pulse signal from 0 to 1, RST=0, Gate=1, Gate-N=0, Gate-GT=1, DATA_I=1, DATA_T=0

[0165] When the signal at the second control terminal Gate-GT is high, the second switching transistor T2 is turned on, and the low-level signal of the brightness selection control terminal DATA_T is provided to the second node N2 through the turned-on second switching transistor T2. When the second node N2 is low, the fifth switching transistor T5 is turned on, and the high-level signal of the pulse control signal terminal HF is provided to the first node N1 through the turned-on fifth switching transistor T5.

[0166] Timing stage t4': VDD=1, VSS=0, EM=0, HF is a pulse signal from 0 to 1, RST=0, Gate=1, Gate-N=0, Gate-GT=0, DATA_I=1, DATA_T=0

[0167] When the light-emitting control signal EM is low, the ninth switching transistor T9 is turned on. The first power supply terminal VDD is connected to the first terminal of the driving transistor DTFT via the turned-on ninth switching transistor T9. The second node N2 remains low, and the fifth switching transistor T5 is turned on. The low-level signal of the pulse control signal terminal HF is written to the first node N1 via the turned-on fifth switching transistor T5. When the first node N1 is low, the sixth switching transistor T6 is turned on. The second terminal of the driving transistor DTFT is connected to the anode of the light-emitting device LED via the turned-on sixth switching transistor T6, and the light-emitting device LED emits light.

[0168] The timing sequences t3, t4 and t3', t4' are executed alternately to achieve time-division multiplexing of the sixth switching transistor T6.

[0169] Based on the same inventive concept, this disclosure provides a display device including any of the pixel driving circuits described above.

[0170] In this embodiment of the invention, the display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of the display device are understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting the invention.

[0171] Based on the same inventive concept, this disclosure provides a driving method applied to a pixel driving circuit, see reference. Figure 19 As shown, it includes:

[0172] Step 201: Initialization stage: In response to the reset control signal RST, the first reset sub-circuit 70 provides the initialization signal Vinit to the control terminal of the driving transistor DTFT; and the second reset sub-circuit 80 provides the initialization signal Vinit to the anode of the light-emitting device LED in response to the reset control signal RST.

[0173] During implementation, when the reset control signal terminal RST is valid, the first reset sub-circuit 70 is turned on, and the initialization signal terminal Vinit is provided to the control terminal of the driving transistor DTFT through the turned-on first reset sub-circuit 70, thereby realizing the reset of the control terminal of the driving transistor DTFT.

[0174] Furthermore, when the reset control signal terminal RST is valid, the second reset sub-circuit 80 is turned on, and the initialization signal terminal Vinit is provided to the anode of the light-emitting device LED through the turned-on second reset sub-circuit 80 for reset.

[0175] Step 202: Data writing stage: In response to the signal of the first control terminal Gate, the data writing sub-circuit 50 provides the signal of the data signal terminal DATA_I to the control terminal of the driving transistor DTFT.

[0176] During implementation, when the signal of the first control terminal Gate is valid, the data writing sub-circuit 50 is turned on. The signal of the data signal terminal DATA_I is provided to the control terminal of the driving transistor DTFT through the turned-on data writing sub-circuit 50, thereby realizing the writing of data voltage, and then causing the driving transistor DTFT to generate driving current under the action of data voltage.

[0177] Step 203: Brightness control stage: In response to the signal of the first control terminal Gate, the gating sub-circuit 10 provides the signal of the brightness gating control terminal DATA_T to the second node N2, and in response to the signal of the second node N2, the brightness control sub-circuit 20 provides the signal of the light emission control signal terminal EM to the first node N1; or, in response to the signal of the second control terminal Gate-GT, the gating sub-circuit 10 provides the signal of the brightness gating control terminal DATA_T to the second node N2, and in response to the signal of the second node N2, the brightness control sub-circuit 20 provides the signal of the pulse control signal terminal HF to the first node N1.

[0178] During implementation, when the signal from the first control terminal Gate is valid, the gating sub-circuit 10 is activated, providing the signal from the brightness gating control terminal DATA_T to the second node N2 via the gating sub-circuit 10. Then, when the signal from the second node N2 is high, the brightness control sub-circuit 20 is activated, providing the signal from the light emission control signal terminal EM to the first node N1 via the activated brightness control sub-circuit 20. Alternatively, when the signal from the second control terminal Gate-GT is valid, the gating sub-circuit 10 is activated, providing the signal from the brightness gating control terminal DATA_T to the second node N2 via the gating sub-circuit 10. Then, when the signal from the second node N2 is low, the brightness control sub-circuit 20 is activated, providing the signal from the pulse control signal terminal HF to the first node N1 via the activated brightness control sub-circuit 20.

[0179] Step 204: Light emission stage: In response to the signal of the light emission control signal terminal EM, the second light emission control sub-circuit 60 turns on the first power supply terminal VDD and the first terminal of the driving transistor DTFT. In response to the signal of the first node N1, the first light emission control sub-circuit 30 turns on the second terminal of the driving transistor DTFT and the anode of the light emission device LED.

[0180] During implementation, when the signal of the light emission control signal terminal EM is valid, the second light emission control sub-circuit 60 is turned on, and the first power supply terminal VDD is turned on through the turned-on second light emission control sub-circuit 60 and the first terminal of the driving transistor DTFT.

[0181] Furthermore, when the signal of the first node N1 is valid, the first light-emitting control sub-circuit 30 is turned on, and the second terminal of the driving transistor DTFT is turned on through the turned-on first light-emitting control sub-circuit 30 and the anode of the light-emitting device LED, and the light-emitting device LED emits light under the action of the aforementioned driving current.

[0182] In summary, the pixel driving circuit, display device, and driving method provided in this disclosure include a pixel driving circuit comprising a driving transistor, a gating sub-circuit, a brightness control sub-circuit, a first light emission control sub-circuit, and a light-emitting device. The first light emission control sub-circuit is coupled between the driving transistor and the light-emitting device and is configured to turn on the driving transistor and the light-emitting device in response to a signal from a first node. The brightness control sub-circuit is coupled between the first node and the gating sub-circuit and is configured to provide a signal from a pulse control signal terminal or a light emission control signal terminal to the first node in response to a signal from a second node. The gating sub-circuit is coupled between the brightness control sub-circuit and a brightness gating control terminal and is configured to provide a signal from the brightness gating control terminal to the second node in response to a signal from a first control terminal and a signal from a second control terminal. The above-mentioned gating sub-circuit effectively reduces the logic power consumption of the shift register caused by the high-voltage driving requirement of the light-emitting device, thereby avoiding the problem of failure of some switching transistors in the shift register that may be caused by high-voltage driving.

[0183] Those skilled in the art will understand that embodiments of this disclosure can be provided as methods, systems, or computer program product systems. Therefore, this disclosure can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this disclosure can take the form of a computer program product system implemented on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0184] This disclosure is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program product systems according to this disclosure. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0185] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0186] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0187] Obviously, those skilled in the art can make various modifications and variations to this disclosure without departing from its spirit and scope. Therefore, if such modifications and variations fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include such modifications and variations.

Claims

1. A pixel driving circuit, characterized in that, include: The components include a driving transistor, a gating sub-circuit, a brightness control sub-circuit, a first light-emitting control sub-circuit, and a light-emitting device. The first light-emitting control sub-circuit is coupled between the driving transistor and the light-emitting device, and is configured to turn on the driving transistor and the light-emitting device in response to a signal from the first node; The brightness control sub-circuit is coupled between the first node and the gating sub-circuit and is configured to respond to the signal of the second node by providing the signal of the pulse control signal terminal or the signal of the light emission control signal terminal to the first node. The gating sub-circuit is coupled between the brightness control sub-circuit and the brightness gating control terminal, and is configured to provide the signal of the brightness gating control terminal to the second node in response to the signal of the first control terminal and the signal of the second control terminal.

2. The pixel driving circuit as described in claim 1, characterized in that, The gating sub-circuit includes: a first switching transistor, a second switching transistor, and a first capacitor, wherein the first switching transistor and the second switching transistor have opposite polarities; The control terminal of the first switching transistor is coupled to the first control terminal, the first terminal of the first switching transistor is coupled to the second node, and the second terminal of the first switching transistor is coupled to the brightness gating control terminal. The control terminal of the second switching transistor is coupled to the second control terminal, the first terminal of the second switching transistor is coupled to the second node, and the second terminal of the second switching transistor is coupled to the brightness gating control terminal. The first end of the first capacitor is coupled to the second node, and the second end of the first capacitor is coupled to the ground terminal.

3. The pixel driving circuit as described in claim 1, characterized in that, The gating sub-circuit includes: a third switching transistor and a second capacitor, wherein the third switching transistor includes a first gate and a second gate; The first gate is coupled to the second control terminal, the second gate is coupled to the brightness gating control terminal, the first terminal of the third switching transistor is coupled to the second node, and the second terminal of the third switching transistor is coupled to the brightness gating control terminal. The first end of the second capacitor is coupled to the second node, and the second end of the second capacitor is coupled to the ground terminal.

4. The pixel driving circuit as described in claim 1, characterized in that, The brightness control sub-circuit includes a fourth switching transistor and a fifth switching transistor, wherein the fourth switching transistor and the fifth switching transistor have opposite polarities. The control terminal of the fourth switching transistor is coupled to the second node, the first terminal of the fourth switching transistor is coupled to the light emission control signal terminal, and the second terminal of the fourth switching transistor is coupled to the first node. The control terminal of the fifth switching transistor is coupled to the second node, the first terminal of the fifth switching transistor is coupled to the first node, and the second terminal of the fifth switching transistor is coupled to the pulse control signal terminal.

5. The pixel driving circuit as described in claim 1, characterized in that, The first light-emitting control sub-circuit includes: a sixth switching transistor; The control terminal of the sixth switching transistor is coupled to the first node, the first terminal of the sixth switching transistor is coupled to the second terminal of the driving transistor, and the second terminal of the sixth switching transistor is coupled to the anode of the light-emitting device.

6. The pixel driving circuit as described in claim 1, characterized in that, It also includes a conduction control sub-circuit, which is coupled between the control terminal of the driving transistor and the second terminal of the driving transistor; The conduction control sub-circuit is configured to conduct the control terminal of the driving transistor to the second terminal of the driving transistor in response to a signal at the conduction control signal terminal.

7. The pixel driving circuit as described in claim 6, characterized in that, The conduction control sub-circuit includes: a seventh switching transistor; The control terminal of the seventh switching transistor is coupled to the conduction control signal terminal, the first terminal of the seventh switching transistor is coupled to the control terminal of the driving transistor, and the second terminal of the seventh switching transistor is coupled to the second terminal of the driving transistor.

8. The pixel driving circuit as described in claim 1, characterized in that, It also includes a data writing sub-circuit, which is coupled between the driving transistor and the data signal terminal; The data writing sub-circuit is configured to provide a signal from the data signal terminal to the first terminal of the driving transistor in response to a signal from the first control terminal.

9. The pixel driving circuit as described in claim 8, characterized in that, The data writing sub-circuit includes: an eighth switching transistor; The control terminal of the eighth switching transistor is coupled to the first control terminal, the first terminal of the eighth switching transistor is coupled to the first terminal of the driving transistor, and the second terminal of the eighth switching transistor is coupled to the data signal terminal.

10. The pixel driving circuit as described in claim 1, characterized in that, It also includes a second light-emitting control sub-circuit, which is coupled between the first power supply terminal and the driving transistor; The second light-emitting control sub-circuit is configured to turn on the first power supply terminal and the first terminal of the driving transistor in response to the signal of the light-emitting control signal terminal.

11. The pixel driving circuit as described in claim 10, characterized in that, The second light-emitting control sub-circuit includes: a ninth switching transistor; The control terminal of the ninth switching transistor is coupled to the light-emitting control signal terminal, the first terminal of the ninth switching transistor is coupled to the first power supply terminal, and the second terminal of the ninth switching transistor is coupled to the first terminal of the driving transistor.

12. The pixel driving circuit as described in claim 1, characterized in that, It also includes a first reset circuit, which is coupled between the driving transistor and the initialization signal terminal; The first reset sub-circuit is configured to provide the signal from the initialization signal terminal to the control terminal of the driving transistor in response to the signal from the reset control signal terminal.

13. The pixel driving circuit as described in claim 12, characterized in that, The first reset circuit includes: a tenth switching transistor; The control terminal of the tenth switching transistor is coupled to the reset control signal terminal, the first terminal of the tenth switching transistor is coupled to the control terminal of the driving transistor, and the second terminal of the tenth switching transistor is coupled to the initialization signal terminal.

14. The pixel driving circuit as described in claim 1, characterized in that, It also includes a second reset circuit, which is coupled between the light-emitting device and the initialization signal terminal; The second reset sub-circuit is configured to provide the signal from the initialization signal terminal to the anode of the light-emitting device in response to the signal from the reset control signal terminal.

15. The pixel driving circuit as described in claim 14, characterized in that, The second reset circuit includes: an eleventh switching transistor; The control terminal of the eleventh switching transistor is coupled to the reset control signal terminal, the first terminal of the eleventh switching transistor is coupled to the initialization signal terminal, and the second terminal of the eleventh switching transistor is coupled to the anode of the light-emitting device.

16. The pixel driving circuit as described in claim 1, characterized in that, It also includes: a third capacitor; The first end of the third capacitor is coupled to the first power supply terminal, and the second end of the third capacitor is coupled to the control terminal of the driving transistor.

17. A display device, characterized in that, include: The pixel driving circuit as described in any one of claims 1 to 16.

18. A driving method applied to a pixel driving circuit as described in any one of claims 1 to 16, characterized in that, include: Initialization phase: In response to the signal at the reset control signal terminal, the first reset sub-circuit provides the signal at the initialization signal terminal to the control terminal of the driving transistor; and in response to the signal at the reset control signal terminal, the second reset sub-circuit provides the signal at the initialization signal terminal to the anode of the light-emitting device. Data writing stage: The data writing sub-circuit responds to the signal at the first control terminal and provides the signal at the data signal terminal to the control terminal of the driving transistor; Brightness control phase: The gating sub-circuit responds to the signal of the first control terminal by providing the signal of the brightness gating control terminal to the second node, and the brightness control sub-circuit responds to the signal of the second node by providing the signal of the light emission control signal terminal to the first node; or, the gating sub-circuit responds to the signal of the second control terminal by providing the signal of the brightness gating control terminal to the second node, and the brightness control sub-circuit responds to the signal of the second node by providing the signal of the pulse control signal terminal to the first node; Light emission stage: In response to the signal at the light emission control signal terminal, the second light emission control sub-circuit connects the first power supply terminal to the first terminal of the driving transistor, and the first light emission control sub-circuit connects the second terminal of the driving transistor to the anode of the light emission device in response to the signal at the first node.

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