Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device and a method of fabricating the same are disclosed. The method of fabricating the semiconductor device includes forming an element isolation structure in a substrate to define an active region, wherein the active region includes a peripheral region and a central region between the peripheral region, forming a well region in the active region, and forming a gate structure across the active region on the substrate. The average doping concentration of the peripheral region under the gate structure is less than the average doping concentration of the central region under the gate structure by the LDD region. Source / drain regions are formed in the LDD region.

Description

Technical Field

[0001] This invention relates to a semiconductor manufacturing process, and more particularly to a semiconductor device and its manufacturing method. Background Technology

[0002] Current metal-oxide-semiconductor (MOS) devices have developed a gate-last fabrication process, using metal gates instead of polysilicon gates to solve electrical problems caused by gate size reduction.

[0003] However, the active region edge of a wide-edge device is prone to premature triggering, causing a double hump phenomenon in the subcritical region of the IV curve, which affects the properties of the semiconductor device. Summary of the Invention

[0004] This invention provides a semiconductor device and its manufacturing method, which can solve the double-peak problem and can be integrated into CMOS fabrication process.

[0005] A method for manufacturing a semiconductor device according to the present invention includes the following steps: Forming a device isolation structure within a substrate to define an active region, wherein the active region includes an edge region and a central region located between the edge regions. Forming a well region within the active region. First forming a plurality of lightly doped drain (LDD) regions within the well region, then forming a gate structure spanning the active region on the substrate, wherein the average doping concentration of the edge regions of the active region below the gate structure is less than the average doping concentration of the central region below the gate structure through the LDD regions. Forming source / drain regions within the LDD regions.

[0006] In one embodiment of the present invention, the method for forming the plurality of LDD regions includes forming a doped region having a first width in an edge region and forming a doped region having a second width in a central region, wherein the first width is smaller than the second width.

[0007] In one embodiment of the present invention, the method for forming the above-mentioned plurality of LDDs includes forming two rectangular doped regions in the well region and performing a reverse doping process on the two rectangular doped regions in the edge region to reduce the average doping concentration of the edge region.

[0008] In one embodiment of the present invention, the method for forming the above-mentioned plurality of LDDs includes forming two rectangular doped regions in the well region, and performing another ion implantation process on the two rectangular doped regions in the central region to increase the average doping concentration in the central region.

[0009] In one embodiment of the present invention, the steps of forming the above-mentioned gate structure include sequentially forming a gate oxide layer, a high dielectric constant material layer, a barrier layer, a dummy gate layer and a hard mask layer on the surface of a substrate; patterning the hard mask layer; using the patterned hard mask layer as an etching mask to etch the dummy gate layer, the barrier layer, the high dielectric constant material layer and the gate oxide layer; and using a gate replacement fabrication process to replace the dummy gate layer with a metal gate.

[0010] In one embodiment of the present invention, the steps of forming the above-described gate structure include sequentially forming a gate oxide layer, a gate layer, and a hard mask layer on the surface of a substrate; patterning the hard mask layer; using the patterned hard mask layer as an etching mask to etch the gate layer and the gate oxide layer; and removing the hard mask layer.

[0011] In one embodiment of the present invention, the plurality of LDD regions are two asymmetric L-shaped doped regions.

[0012] A semiconductor device according to the present invention includes a substrate, a device isolation structure, a well region, a gate structure, a plurality of LDD regions, and a plurality of source / drain regions. The device isolation structure is formed on the substrate to define an active region, wherein the active region includes edge regions and a central region located between the edge regions. A well region is formed within the active region. A gate structure is formed on the surface of the substrate and spans the active region. A plurality of LDD regions are formed within the well region such that the average doping concentration of an edge region of the active region below the gate structure is less than the average doping concentration of the central region below the gate structure. Source / drain regions are formed within the plurality of LDD regions.

[0013] In another embodiment of the present invention, the LDD region includes a doped region having a first width in the edge region and a doped region having a second width in the central region, wherein the first width is smaller than the second width.

[0014] In another embodiment of the present invention, the gate structure described above includes an HKMG structure or a poly-SiON structure.

[0015] In various embodiments of the present invention, in a top view, the edge of the doped region having a first width may be aligned with the sidewall of the gate structure, the doped region having a first width may partially overlap with the gate structure, or the doped region having a first width may not overlap with the gate structure.

[0016] To make the above features of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0017] Figures 1A to 1H This is a cross-sectional view of the manufacturing process of a semiconductor device according to the first embodiment of the present invention;

[0018] Figure 2 yes Figure 1A A top view of the structure;

[0019] Figure 3 yes Figure 2 A cross-sectional view of the XX line;

[0020] Figure 4 yes Figure 1H A top view of a semiconductor device;

[0021] Figure 5 yes Figure 4 A cross-sectional view of the XX line;

[0022] Figure 6 These are IV curves of a general semiconductor device and the semiconductor device of the first embodiment;

[0023] Figures 7A to 7E This is a top view of various examples of the semiconductor device of the second embodiment.

[0024] Symbol Explanation

[0025] 100: Base

[0026] 100s: Surface

[0027] 102: Component isolation structure

[0028] 104: Tunnel

[0029] 106, 106': LDD area

[0030] 108: Patterned Mask

[0031] 110: Ion Implantation Fabrication Process

[0032] 112: Gate oxide layer

[0033] 114: High dielectric constant material layer

[0034] 116: Barrier Layer

[0035] 118: Dummy Gate Layer

[0036] 120: Hard mask layer

[0037] 122, 122a: Spacer wall

[0038] 124: Source / Drain Region

[0039] 126: Metal silicide layer

[0040] 128: Etching Stop Layer

[0041] 130: ILD layer

[0042] 132: Opening

[0043] 200, 700: Edge Zone

[0044] 202, 702: Central District

[0045] 704: Rectangular doped region

[0046] 706: Undoped region

[0047] AA: Active (Active) Region

[0048] dp1, dp2, 708: Doped regions

[0049] HKMG: Gate Structure

[0050] L1, L2: Length

[0051] MG: Metal gate layer

[0052] s1, s2: sidewalls

[0053] w1, w1', w1”, w2: width Detailed Implementation

[0054] The invention can be understood by referring to the following detailed description and the accompanying drawings. Furthermore, the dimensions of the various regions in the drawings are for illustrative purposes only and are not intended to limit the scope of the invention.

[0055] Figures 1A to 1H This is a cross-sectional view of the manufacturing process of a semiconductor device according to the first embodiment of the present invention.

[0056] Please refer to Figure 1A A device isolation structure 102 is formed within the substrate 100 to define the active region AA. Then, a well region 104 is formed within the active region AA, and then multiple lightly doped drain (LDD) regions 106 are formed within the well region 104. The LDD regions 106 are formed, for example, by first forming a patterned mask 108 on the surface 100s of the substrate 100, and then performing an ion implantation fabrication process 110.

[0057] Figure 2 yes Figure 1A The structure is shown in a top view, wherein the active region AA includes edge regions 200 and a central region 202 located between the edge regions 200. In one embodiment, the sum of the lengths L1 of the upper edge region 200 and the lower edge region 200 is approximately 5% to 40% of the total length L2 of the active region AA, for example, 5% to 30% or 5% to 20%.

[0058] Please refer to the following at the same time Figure 1A and Figure 2The method of forming LDD region 106 is, for example, forming a doped region dp1 with a first width w1 in the edge region 200 and forming a doped region dp2 with a second width w2 in the central region 202, wherein the first width w1 is smaller than the second width w2.

[0059] Figure 3 yes Figure 2 A cross-sectional view of the XX line. Figure 3 This shows the doped region dp1 with a first width w1 in the edge region 200, which is... Figure 2 Part of LDD zone 106. (and) Figure 1A Compared to the doped region dp2 with a second width w2, the average doping concentration of the edge region 200 is lower than that of the central region 202 because the doped region dp1 occupies a smaller area. The "average doping concentration" in this text refers to the average doping concentration of all doped regions in the cross-section; Figure 2 Taking the central area 202 as an example, its cross-section is Figure 1A ,and Figure 1A The area of ​​the doped region dp2 is significantly larger than that of the doped region dp2. Figure 3 The doped region dp1 is such that the average doping concentration of the central region 202 is greater than that of the edge region 200.

[0060] Please refer to Figure 1B In removal Figure 1A Following the patterned mask 108, a gate oxide layer 112, a high-dielectric-constant material layer 114, a barrier layer 116, a dummy gate layer 118, and a hard mask layer 120 are sequentially formed over the surface 100s of the substrate 100. The high-dielectric-constant material layer 114 may include a dielectric material having a high dielectric constant. For example, the dielectric material having a high dielectric constant may be a material with a dielectric constant greater than that of silicon oxide (approximately 3.9). In some embodiments, the high-dielectric-constant material layer 114 may be, for example, HfO2, TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, ZrSiO2, LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, Al2O3, Si3N4, SiON, or combinations thereof. The barrier layer 116 may include TiN or other suitable materials. The dummy gate layer 118 may include polysilicon. The hard mask layer 120 may include oxide, nitride, or a combination thereof. The hard mask layer 120 is then patterned using photolithography and etching processes to expose a portion of the dummy gate layer 118.

[0061] Please refer to Figure 1CUsing a patterned hard mask layer 120 as an etching mask, the dummy gate layer 118, barrier layer 116, high dielectric constant material layer 114, and gate oxide layer 112 are etched until the surface 100 of the substrate 100 is exposed. Subsequently, a gate replacement fabrication process can be used to replace the dummy gate layer 118 with a metal gate. For example, a spacer wall 122 can be formed on the sidewall s1 first. The spacer wall 122 may include silicon oxide, silicon nitride, or a combination thereof.

[0062] Please refer to Figure 1D Using an ion implantation process, a source / drain region 124 is formed within the LDD region 106, and then a metal silicide layer 126 can be formed on the exposed surface 100s of the substrate 100. Afterwards, Figure 1C The hard mask layer 120 is removed, along with a portion of the spacer wall 122, resulting in spacer walls 122a located on both sides of the dummy gate layer 118.

[0063] Please refer to Figure 1E First, an etch stop layer 128 is deposited to cover the surface of the metal silicide layer 126, the spacer wall 122a and the dummy gate layer 118. Then, an ILD layer 130 is formed to cover the etch stop layer 128 and the entire dummy gate layer 118.

[0064] Please refer to Figure 1F A planarization process, such as CMP, is performed on the ILD layer 130 and the etch stop layer 128 until the layer beneath the etch stop layer 128 is exposed. Figure 1E The dummy gate layer 118 is then removed to obtain the opening 132. The opening 132 is the space formed by the spacer wall 122a and the barrier layer 116.

[0065] Please refer to Figure 1G A metal gate layer MG is formed above the substrate 100, and the metal gate layer MG fills the opening 132. The metal gate layer MG may include tantalum nitride (TaN), nickel silicon (NiSi), cobalt silicon (CoSi), molybdenum (Mo), copper (Cu), tungsten (W), aluminum (Al), cobalt (Co), zirconium (Zr), platinum (Pt), or other suitable materials.

[0066] Please refer to Figure 1H A planarization process, such as CMP, is performed on the metal gate layer MG to form the gate structure HKMG. The gate structure HKMG may include a gate oxide layer 112, a high dielectric constant material layer 114, a barrier layer 116, and the metal gate layer MG.

[0067] Besides the HKMG gate structure formed using a gate replacement fabrication process, this invention can also be used in fabrication processes where the gate structure is a poly-SiON structure. For example, in Figure 1BIn this process, after forming the gate oxide layer 112, a polysilicon layer (not shown) is formed directly, without the need to form the barrier layer 116 and the high dielectric constant material layer 114, and then via... Figure 1C The etching process forms a poly-SiON structure. Then, as... Figure 1D The semiconductor device of an embodiment of the present invention can be completed by forming the source / drain region 124 in the LDD region 106.

[0068] Figure 4 That is Figure 1H The top view of the structure, with some components omitted for clarity, such as... Figure 1H The ILD layer 130, etch stop layer 128, spacer 122a, source / drain region 124 and metal silicide layer 126 are included. Figure 5 That is Figure 4 A cross-sectional view of the XX line.

[0069] Please refer to the following at the same time Figure 4 and Figure 5 The doped region dp1 with a first width w1 partially overlaps with the gate structure HKMG, and the average doping concentration of the edge region 200 below the gate structure HKMG is less than the average doping concentration of the central region 202 below the gate structure HKMG.

[0070] Figure 6 This is an IV curve diagram comparing a typical semiconductor device with that of the semiconductor device in the first embodiment. Please refer to... Figure 6 In general, the IV curve of a semiconductor device will have a double hump phenomenon. However, in the semiconductor device of the first embodiment, because the average doping concentration at the edge of the active region is small, the critical voltage (Vth) of this region is pulled up, resulting in an IV curve without double hump, thereby avoiding premature turn-on at the edge region.

[0071] To reduce the average doping concentration of the edge region (active region) below the gate structure to be less than the average doping concentration of the central region (active region) below the gate structure, various techniques can be employed, such as... Figures 7A to 7E Multiple examples are shown.

[0072] exist Figure 7A In this structure, the edge of the doped region dp1 with a first width w1' can be aligned with the sidewall s2 of the gate structure HKMG.

[0073] exist Figure 7B In this structure, the doped region dp1 with a first width w1” can be non-overlapping with the gate structure HKMG.

[0074] exist Figure 7CIn this design, LDD region 106' consists of two asymmetric L-shaped doped regions. That is, the left LDD region 106' is not mirror-symmetric with the right LDD region 106'. In some embodiments, the area of ​​the left LDD region 106' is the same as the area of ​​the right LDD region 106'.

[0075] In addition, by controlling the manufacturing process, the average doping concentration of the edge region 700 below the gate structure HKMG can be made lower than the average doping concentration of the central region 702 below the gate structure HKMG.

[0076] For example Figure 7D The two rectangular doped regions 704 are first formed in the well region 104 through an ion implantation process, wherein the rectangular doped regions 704 cover the upper edge region 700, the lower edge region 700, and the central region 702. Next, the two rectangular doped regions 704 in the edge region 700 can be dedoped to form the dedoped region 706, thereby reducing the average doping concentration of the edge region 700.

[0077] exist Figure 7E In the process, two rectangular doped regions 704 are first formed in the trap region 104 through an ion implantation process. Then, another ion implantation process is performed on the two rectangular doped regions 704 in the central region 702 to form the doped region 708, thereby increasing the average doping concentration of the central region 702.

[0078] Based on the above, the present invention adopts the method of forming the LDD region first and then forming the gate, so that the LDD region of a specific shape can be fabricated according to the requirements and the double peak phenomenon of the semiconductor device can be eliminated.

[0079] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be defined by the appended claims.

Claims

1. A method for manufacturing a semiconductor device, comprising: A component isolation structure is formed within the substrate to define an active region, wherein the active region includes an edge region and a central region located between the edge regions; A trap region is formed within this active region; Multiple lightly doped drain (LDD) regions are formed within this well region; A gate structure spanning the active region is formed on the substrate, and through the plurality of LDD regions, the average doping concentration of the edge region below the gate structure is made less than the average doping concentration of the central region below the gate structure; and Source / drain regions are formed within these multiple LDD regions.

2. The method of manufacturing a semiconductor device as claimed in claim 1, wherein the method of forming the plurality of LDD regions includes forming a doped region having a first width in the edge region and forming a doped region having a second width in the central region, wherein the first width is smaller than the second width.

3. The method of manufacturing a semiconductor device as claimed in claim 2, wherein, in a top view, the edge of the doped region having the first width is aligned with the sidewall of the gate structure.

4. The method of manufacturing a semiconductor device as claimed in claim 2, wherein, in a top view, the doped region having the first width partially overlaps with the gate structure.

5. The method of manufacturing a semiconductor device as claimed in claim 2, wherein, in a top view, the doped region having the first width does not overlap with the gate structure.

6. The method of manufacturing a semiconductor device as claimed in claim 1, wherein, in a top view, the plurality of LDD regions are two asymmetric L-shaped doped regions.

7. The method of manufacturing a semiconductor device as claimed in claim 1, wherein the method of forming the plurality of LDD regions comprises: Two rectangular doped regions are formed within the well region; as well as The two rectangular doped regions within the edge region are subjected to an anti-doping process to reduce the average doping concentration in the edge region.

8. The method of manufacturing a semiconductor device as claimed in claim 1, wherein the method of forming the plurality of LDD regions comprises: Two rectangular doped regions are formed within the well region; as well as Another ion implantation process is performed on the two rectangular doped regions within the central region to increase the average doping concentration in the central region.

9. The method of manufacturing a semiconductor device as claimed in claim 1, wherein the step of forming the gate structure comprises: A gate oxide layer, a high dielectric constant material layer, a barrier layer, a polysilicon layer, a dummy gate layer, and a hard mask layer are sequentially formed on the surface of the substrate. Pattern the hard mask layer; Using the patterned hard mask layer as an etching mask, the dummy gate layer, the barrier layer, the high-dielectric-constant material layer, and the gate oxide layer are etched; and The dummy gate layer is replaced with a metal gate using a gate replacement fabrication process.

10. The method of manufacturing a semiconductor device as claimed in claim 1, wherein the step of forming the gate structure comprises: A gate oxide layer, a gate layer, and a hard mask layer are sequentially formed on the surface of the substrate; Pattern the hard mask layer; The patterned hard mask layer is used as an etching mask to etch the gate layer and the gate oxide layer; as well as Remove the hard mask layer.

11. A semiconductor device, comprising: Base; A component isolation structure is formed on the substrate to define an active region, wherein the active region includes an edge region and a central region located between the edge regions. The trap region is formed within this active region; A gate structure is formed on the surface of the substrate and spans the active region; A plurality of lightly doped drain (LDD) regions are formed within the well region, such that the average doping concentration of the edge region below the gate structure is less than the average doping concentration of the central region below the gate structure; and The source / drain regions are formed within these multiple LDD regions.

12. The semiconductor device of claim 11, wherein the plurality of LDD regions include a doped region having a first width in the edge region and a doped region having a second width in the central region, and the first width is smaller than the second width.

13. The semiconductor device of claim 12, wherein, in a top view, the edge of the doped region having the first width is aligned with the sidewall of the gate structure.

14. The semiconductor device of claim 12, wherein, in a top view, the doped region having the first width partially overlaps with the gate structure.

15. The semiconductor device of claim 12, wherein, in a top view, the doped region having the first width does not overlap with the gate structure.

16. The semiconductor device of claim 11, wherein the plurality of LDD regions are two asymmetric L-shaped doped regions.

17. The semiconductor device of claim 11, wherein the gate structure comprises an HKMG structure or a poly-SiON structure.

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