Semiconductor device and method of manufacturing the same

Abstract

The present disclosure relates to semiconductor devices and methods of manufacturing the same. Embodiments of the present disclosure provide a semiconductor device and a method of forming the same, the semiconductor device including a diffusion barrier layer formed on a semiconductor channel layer. The diffusion barrier layer formed on the semiconductor channel layer mitigates diffusion from an adjacent sacrificial channel layer, thereby improving crystallinity of the semiconductor channel layer in a multi-channel device.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices and methods for manufacturing the same. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate, and using photolithography to pattern the various material layers to form circuit components and elements thereon.

[0003] The semiconductor industry continuously improves the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that need to be addressed. Summary of the Invention

[0004] According to one embodiment of this disclosure, a method of forming a semiconductor device is provided, comprising: forming a fin stack on a substrate, wherein the fin stack includes: a semiconductor channel layer; a sacrificial channel layer; and a first capping layer disposed between the semiconductor channel layer and the sacrificial channel layer, wherein the first capping layer includes a material different from the materials of the semiconductor channel layer and the sacrificial channel layer; forming a fin structure from the fin stack; forming a sacrificial gate structure on the fin structure; performing recess etching on the fin structure; forming a source / drain region on opposite sides of the sacrificial gate structure, wherein the source / drain region is connected to the semiconductor channel layer; removing the sacrificial gate structure; removing the sacrificial channel layer; and forming a gate structure around the semiconductor channel layer and the first capping layer.

[0005] According to one embodiment of this disclosure, a method for forming a semiconductor device is provided, comprising: forming a sacrificial channel layer on a substrate, wherein the sacrificial channel layer comprises a first element; forming a semiconductor channel layer on the sacrificial channel layer, wherein the semiconductor channel layer is doped with a second element having an atomic radius smaller than that of the first element; forming a fin structure from a stack comprising the sacrificial channel layer and the semiconductor channel layer; forming a sacrificial gate structure on the fin structure; forming source / drain regions on both sides of the sacrificial gate structure; selectively removing the portion of the sacrificial channel layer and the semiconductor channel layer doped with the second element from the fin structure; and forming a gate structure around the semiconductor channel layer.

[0006] According to one embodiment of this disclosure, a semiconductor device is provided, comprising: a first source / drain region; a second source / drain region; and a channel region connected between the first source / drain region and the second source / drain region, wherein the channel region comprises: a semiconductor channel layer including a first element; a first capping layer disposed on a first surface of the semiconductor channel layer, wherein the semiconductor channel layer is doped with a second element having an atomic radius smaller than the first element; a gate dielectric layer formed around the channel region; and a gate electrode layer disposed on the gate dielectric layer. Attached Figure Description

[0007] The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced.

[0008] Figure 1 This is a flowchart of a method for manufacturing a semiconductor device according to embodiments of the present disclosure.

[0009] Figures 2 to 7 , Figures 7A to 7C , Figures 8 to 14 , Figures 15A to 15B as well as Figure 16 , Figures 16A to 16C The various stages of manufacturing a semiconductor device according to embodiments of the present disclosure are illustrated schematically.

[0010] Figures 17A to 17B The stages of manufacturing a semiconductor device according to embodiments of the present disclosure are illustrated schematically. Detailed Implementation

[0011] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. To simplify this disclosure, specific examples of components and arrangements are described below. These are, of course, merely examples and not limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Furthermore, this disclosure may repeat reference numerals and / or letters in various examples. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0012] Furthermore, spatially related terms (e.g., "below," "below," "lower," "above," "above," "top," "higher," etc.) may be used herein to readily describe the relationship of one element or feature shown in the figure relative to another element(s) or feature(s). In addition to the orientations shown in the figures, spatially related terms are also intended to encompass different orientations of the semiconductor device being used or operated. The device may be oriented in other directions (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein may be interpreted similarly accordingly.

[0013] The foregoing provides a general overview of some aspects of the embodiments described in this disclosure. While some embodiments described herein are described in the context of nanosheet channel FETs, implementations of some aspects of this disclosure can be used in other processes and / or other devices, such as planar FETs, FinFETs, Horizontal Gate All Around (HGAA) FETs, Vertical Gate All Around (VGAA) FETs, and other suitable devices. Those skilled in the art will readily understand that other modifications may be made within the scope of this disclosure. Furthermore, while method embodiments may be described in a particular order, various other method embodiments may be performed in any logical order and may include fewer or more steps than those described herein. One or more source / drain regions may individually or collectively refer to a source or drain, depending on the context. In this disclosure, source / drain refers to a source and / or drain. Source and drain may be used interchangeably.

[0014] Fins can be patterned using any suitable method. For example, fins can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing the patterns to be created to have smaller spacing, for example, than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fins.

[0015] Embodiments of this disclosure provide a semiconductor device comprising two or more stacked semiconductor channel layers, wherein at least one surface of the semiconductor channel layer includes a diffusion barrier layer. In some embodiments, the two or more stacked semiconductor channel layers may be epitaxially grown on a semiconductor substrate, wherein a sacrificial channel layer is located therebetween. In some embodiments, a diffusion barrier layer is formed between the semiconductor channel layer and an adjacent semiconductor sacrificial layer. In some embodiments, the semiconductor sacrificial layer may include a first semiconductor element, which may not be included in the semiconductor channel layer or may be included in the semiconductor channel layer at a significantly different concentration. The presence of the first semiconductor element or the concentration difference of the first semiconductor element benefits the etch selectivity between the semiconductor channel layer and the sacrificial channel layer, thereby allowing the sacrificial channel layer to be removed during processing. However, the first semiconductor element may diffuse from the semiconductor sacrificial layer into the adjacent semiconductor channel layer, creating a rough surface on the semiconductor channel layer. The diffusion barrier layer prevents the first semiconductor element from diffusing into the semiconductor channel layer, thereby creating a sharp planar surface on the semiconductor channel layer. The diffusion barrier layer improves gate control in the transistor, for example, reducing subthreshold wobbling and DIBL (drain-induced barrier reduction). In some embodiments, the diffusion barrier layer may be an epitaxial growth layer doped with a dopant to prevent diffusion across semiconductor layers. In some embodiments, the diffusion barrier layer may be an epitaxial growth layer doped with an element that mitigates the diffusion of a first semiconductor element. In some embodiments, the first semiconductor element is germanium, and the doping element is carbon. In some embodiments, the diffusion barrier film may include C, SiC, SiGeC, GeC, etc.

[0016] Figure 1 This is a flowchart of a method 100 for manufacturing a semiconductor device 200 according to an embodiment of the present disclosure. Figures 2 to 7 , Figures 7A to 7B , Figures 8 to 14 , Figures 15A to 15B , Figure 16 and Figures 16A to 16C The various stages of manufacturing an exemplary semiconductor device 200 according to embodiments of the present disclosure are illustrated schematically. Specifically, it can be based on... Figure 1 Method 100 is used to manufacture semiconductor devices 200.

[0017] Semiconductor device 200 includes a GAA transistor formed from a stack of semiconductor layers. For example... Figures 2 to 7 As shown in operations 102, 104, 106 and 108, a stack 209 of semiconductor layers according to the present disclosure is formed on substrate 202. Figures 2 to 7 This is a schematic perspective view of a semiconductor device 200 according to embodiments of the present disclosure during various manufacturing stages.

[0018] like Figure 7As shown, stack 209 includes two or more sacrificial channel layers 206 between two or more semiconductor channel layers 208. The sacrificial channel layers 206 may be sandwiched between a first diffusion barrier layer 205 and a second diffusion barrier layer 207. The diffusion barrier layers 205 and 207 are configured to prevent elements (such as germanium) in the sacrificial channel layers 206 from diffusing into the adjacent semiconductor channel layers 208. The diffusion barrier layers 205 and 207 may also be referred to as capping layers.

[0019] like Figure 2 As shown, a substrate 202 is provided for forming a semiconductor device 200 thereon. The substrate 202 may include a single-crystal semiconductor material, such as, but not limited to, Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. The substrate 202 may include various doping configurations depending on the circuit design. Figure 2 In the substrate 202, there are p-doped regions (or p-wells) 204a and n-doped regions (or n-wells) 204b. One or more n-type devices, such as NFETs, will be formed on and / or within the p-well 204a. One or more p-type devices, such as PFETs, will be formed on and / or within the n-well 204b. Figure 2 The p-well 204a is shown in a doped local region of the doped substrate, but this is not limiting. In other embodiments, the p-well 204a and n-well 204b may be separated by one or more insulators (e.g., STI).

[0020] In operation 102, such as Figure 3 As shown, a first diffusion barrier layer 205 is formed on substrate 202. The first diffusion barrier layer 205 is designed to prevent diffusion from the subsequently formed sacrificial channel layer 206. The first diffusion barrier layer 205 can be formed by doping an epitaxially formed semiconductor layer.

[0021] In some embodiments, an epitaxial semiconductor layer 205' can be formed first on the substrate 202, followed by a doping process 205d, such as... Figures 3A to 3B As shown, Figures 3A to 3B This is a partial cross-sectional view of the semiconductor device 200. In some embodiments, the first diffusion barrier layer 205 may be configured to prevent a first semiconductor element (such as germanium) from diffusing into a semiconductor layer of a second semiconductor element (such as silicon). In some embodiments, the doping process 205d is configured to add carbon to the first diffusion barrier layer 205, i.e., the first diffusion barrier layer 205 is a carbon-doped epitaxial film.

[0022] In some embodiments, a diffusion barrier layer 205 can be formed by depositing an epitaxial growth film 205' and then doping the epitaxial growth film 205'. For example, the epitaxial growth film 205' can be an epitaxially grown carbon film, an epitaxially grown silicon film, an epitaxially grown silicon-germanium film, or an epitaxially grown germanium film. A doping process can be performed to implant one or more elements (e.g., carbon) into the epitaxially grown film.

[0023] Doping can be performed using epitaxial growth, implantation, atomic layer deposition, and other processes. In some embodiments, doping agents including SiH4, SiH2Cl2, Si2H6, GeH4, Ge2H6, SiH3CH3, and C can be used. x H y Doping is performed using process gases such as HCl, Cl2, H2, N2, or combinations thereof. In some embodiments, doping is performed via an epitaxial process. Doping can be performed at pressures of about 1 Torr to about 760 Torr and temperatures of about 300°C to about 800°C. The precursor gas flow can be in the range of about 1 sccm to about 1000 sccm. The purge gas and carrier gas can flow in gas flows in the range of about 1 slm to about 50 slm.

[0024] In other embodiments, the diffusion barrier layer 205 can be formed by directly performing a doping process on the substrate 202 or the semiconductor channel layer 208, such as... Figures 3C to 3D As shown, Figures 3C to 3D This is a partial cross-sectional view of the semiconductor device 200. The doping process creates a first diffusion barrier layer 205 on the top portion of the substrate 202 or the semiconductor channel layer 208.

[0025] In some embodiments, the first diffusion barrier layer 205 may have a thickness T205 along the z-direction. In some embodiments, the thickness T205 is in the range between about 0.01 nm and about 10 nm, for example, between about 0.01 nm and about 0.1 nm, between about 0.1 nm and about 1.0 nm, and between about 1.0 nm and about 10 nm. If the thickness T205 of the first diffusion barrier layer 205 is greater than 10 nm, the electrical performance of the semiconductor device 200 may be adversely affected. If the thickness T205 of the first diffusion barrier layer 205 is less than 0.01 nm, the first diffusion barrier layer 205 may be insufficient to prevent diffusion into the semiconductor channel layer 208. The thickness T205 can be selected according to the thickness of the semiconductor channel layer 208. For example, for a thicker semiconductor channel layer 208, the thickness T205 can be thicker, and for a thinner semiconductor channel layer 208, the thickness T205 can be thinner. In some embodiments, the thickness of the semiconductor channel layer 208 is in the range of about 0.1 nm to about 10 nm. In some embodiments, the ratio of thickness T205 to the thickness of the semiconductor channel layer 208 is in the range of about 0.001 to about 100. If the thickness ratio of the first diffusion barrier layer 205 to the semiconductor channel layer 208 is less than 0.001, the first diffusion barrier layer 205 may not be thick enough to provide diffusion barrier to the semiconductor channel layer 208. If the thickness ratio of the first diffusion barrier layer 205 to the semiconductor channel layer 208 is greater than 100, the electrical performance of the semiconductor device 200 may be adversely affected.

[0026] It has been observed that elements with atomic radii smaller than those of Ge and / or Si can be used to form diffusion barrier layers against Ge and / or Si or as dopants for implantation. In some embodiments, the first diffusion barrier layer 205 comprises one or more elements with atomic radii smaller than those of Ge and / or Si. In some embodiments, the diffusion barrier layer 205 may be an epitaxially grown film comprising one or more elements with atomic radii smaller than those of Ge and Si to prevent diffusion into or out of the semiconductor channel layer 208. In some embodiments, the first diffusion barrier layer 205 comprises carbon, boron, arsenic, silicon carbide, boron silicon, arsenic silicon, carbon-doped silicon, boron-doped silicon, arsenic-doped silicon, germanium silicon carbide, germanium carbide, or combinations thereof. Suitable elements having smaller atomic radii may include carbon, boron, arsenic, or combinations thereof.

[0027] In some embodiments, the first diffusion barrier layer 205 may be an epitaxially grown film comprising carbon, silicon carbide (SiC), SiGeC, GeC, etc. In some embodiments, the concentration of the dopant (such as carbon) is approximately 1E19 cm⁻¹. -3 1E22cm -3 Within the range of, for example, at approximately 1E19cm -3And about 1E20cm -3 Between, at approximately 1E20cm -3 1E21cm -3 Between, at approximately 1E21cm -3 1E22cm -3 Between. If the dopant concentration is below 1E19cm -3 Then the first diffusion barrier layer 205 can provide sufficient barrier to resist diffusion. If the dopant concentration is greater than 1E22cm⁻¹ -3 If the dopant concentration in the first diffusion barrier film 205 is too high, it may adversely affect transistor performance without providing additional barrier functionality. In some embodiments, the atomic concentration of the dopant (such as carbon) is in the range of about 0.02% to about 20%, for example, between about 0.02% and about 0.2%, between about 0.2% and about 2%, and between about 2% and about 20%. If the atomic concentration of the dopant is below 0.02%, the first diffusion barrier layer 205 can provide sufficient barrier to diffusion. If the atomic concentration of the dopant is greater than 20%, the dopant concentration in the first diffusion barrier film 205 may adversely affect transistor performance without providing additional barrier functionality. The dopant concentration can be selected based on the thickness of the first barrier layer 205. For example, a higher dopant concentration can be used for a thinner diffusion barrier layer 205, while a lower dopant concentration can be used for a thicker diffusion barrier layer 205.

[0028] In operation 104, a sacrificial channel layer 206 is formed above the first diffusion barrier layer 205, such as Figure 4 As shown. In some embodiments, the sacrificial channel layer 206 may include silicon germanium (SiGe). The sacrificial channel layer 206 may be a SiGe layer comprising a molar ratio of Ge greater than 25%. For example, the sacrificial channel layer 206 may be a SiGe layer comprising a molar ratio of Ge in the range of 25% to 50%. The sacrificial channel layer 206 may be formed by molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), and / or other suitable epitaxial growth processes. The sacrificial channel layer 206 has a thickness T206 along the z-direction. In some embodiments, the thickness T206 is in the range of about 5 nm to about 50 nm.

[0029] In operation 106, a second diffusion barrier layer 207 is formed above the sacrificial channel layer 206, such as Figure 5 As shown. The second diffusion barrier layer 207 is designed to prevent diffusion from the sacrificial channel layer 206 to the subsequently formed semiconductor channel layer 208.

[0030] In some embodiments, the second diffusion barrier layer 207 can be formed by doping an epitaxially formed semiconductor layer. In some embodiments, an epitaxial semiconductor layer 207' can be formed first on the sacrificial channel layer 206, followed by a doping process 207d, such as... Figure 5A As shown, Figure 5A This is a partial cross-sectional view of the semiconductor device 200. In some embodiments, the second diffusion barrier layer 207 may be configured to prevent elements (such as germanium) in the sacrificial channel layer 206 from diffusing into the subsequently formed semiconductor channel layer 208. In some embodiments, the doping process 207d is configured to add carbon to the second diffusion barrier layer 207, i.e., the second diffusion barrier layer 207 is a carbon-doped epitaxial film. The epitaxially grown film 207' may be an epitaxially grown carbon film, an epitaxially grown silicon film, an epitaxially grown silicon-germanium film, or an epitaxially grown germanium film. The doping process may be performed to implant one or more elements (e.g., carbon) into the epitaxially grown film 207'.

[0031] Doping can be performed using epitaxial growth, implantation, atomic layer deposition, and other processes. In some embodiments, doping agents including SiH4, SiH2Cl2, Si2H6, GeH4, Ge2H6, SiH3CH3, and C can be used. x H y Doping is performed using process gases such as HCl, Cl2, H2, N2, or combinations thereof. In some embodiments, doping is performed via an epitaxial process. Doping can be performed at pressures of about 1 Torr to about 760 Torr and temperatures of about 300°C to about 800°C. The precursor gas flow can be in the range of about 1 sccm to about 1000 sccm. The purge gas and carrier gas can flow in gas flows in the range of about 1 slm to about 50 slm.

[0032] In other embodiments, the second diffusion barrier layer 207 can be formed by directly performing a doping process on the sacrificial channel layer 206, such as... Figure 5B As shown, Figure 5B This is a partial cross-sectional view of the semiconductor device 200. The doping process creates a second diffusion barrier layer 207 from the top portion of the sacrificial channel layer 206.

[0033] In some embodiments, the second diffusion barrier layer 207 may have a thickness T207 along the z-direction. In some embodiments, the thickness T207 is in the range of about 0.01 nm to about 10 nm, for example, between about 0.01 nm and about 0.1 nm, between about 0.1 nm and about 1.0 nm, and between about 1.0 nm and about 10 nm. If the thickness T207 of the first diffusion barrier layer 207 is greater than 10 nm, the electrical performance of the semiconductor device 200 may be adversely affected. If the thickness T207 of the first diffusion barrier layer 207 is less than 0.01 nm, the first diffusion barrier layer 207 may be insufficient to prevent diffusion into the semiconductor channel layer 208. The thickness T207 can be selected according to the thickness of the semiconductor channel layer 208. For example, for a thicker semiconductor channel layer 208, the thickness T207 can be thicker, and for a thinner semiconductor channel layer 208, the thickness T207 can be thinner. In some embodiments, the ratio of thickness T207 to the thickness of semiconductor channel layer 208 is in the range of about 0.001 to about 100. If the thickness ratio of the first diffusion barrier layer 207 to the semiconductor channel layer 208 is less than 0.001, the first diffusion barrier layer 207 may not be thick enough to provide diffusion barrier to the semiconductor channel layer 208. If the thickness ratio of the first diffusion barrier layer 207 to the semiconductor channel layer 208 is greater than 100, the electrical performance of the semiconductor device 200 may be adversely affected.

[0034] In some embodiments, the second diffusion barrier layer 207 may be an epitaxially grown film comprising carbon, silicon carbide (SiC), SiGeC, GeC, etc. In some embodiments, the concentration of the dopant (such as carbon) is approximately 1E19 cm⁻¹. -3 1E22cm -3 Within the range of, for example, at approximately 1E19cm -3 And about 1E20cm -3 Between, at approximately 1E20cm -3 1E21cm -3 Between, at approximately 1E21cm -3 1E22cm -3 In some embodiments, the atomic concentration of the dopant (such as carbon) is in the range of about 0.02% to about 20%, for example, between about 0.02% and about 0.2%, between about 0.2% and about 2%, and between about 2% and about 20%. The doping concentration can be selected according to the thickness of the second diffusion barrier layer 207. For example, a thicker second diffusion barrier layer 207 may have a higher dopant concentration, while a thicker second diffusion barrier layer 207 may have a lower dopant concentration.

[0035] The first diffusion barrier layer 205 and the second diffusion barrier layer 207 may have the same or different compositions. In some embodiments, the first diffusion barrier layer 205 (comprising SiC) may be formed by treating the top portion of the substrate 202 / semiconductor channel layer 208 with carbon, and the second diffusion barrier layer 207 (comprising SiGeC) may be formed by treating the top portion of the sacrificial channel layer 206 with carbon. In other embodiments, both the first diffusion barrier layer 205 and the second diffusion barrier layer 207 are formed from doped epitaxial silicon layers and include SiC.

[0036] In operation 108, a semiconductor channel layer 208 is formed on top of the second diffusion barrier layer 207, such as Figure 6 As shown. In some embodiments, the semiconductor channel layer 208 may include silicon, Ge, compound semiconductors (such as SiC, GeAs, GaP, InP, InAs and / or InSb), alloy semiconductors (such as SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP and / or GaInAsP), or combinations thereof. In some embodiments, the semiconductor channel layer 208 may include undoped silicon. In a later fabrication stage, a portion of the semiconductor channel layer 208 forms a nanosheet channel in a multi-gate device. The semiconductor channel layer 208 may be formed by molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), and / or other suitable epitaxial growth processes. The semiconductor channel layer 208 has a thickness T208 along the z-direction. In some embodiments, the thickness T208 is in the range of about 5 nm and about 50 nm.

[0037] like Figure 6 As shown, after operations 102, 104, 106, and 108, a pair of sacrificial channel layers 206 and semiconductor channel layers 208 are formed, wherein the sacrificial channel layer 206 is sandwiched between a first diffusion barrier layer 205 and a second diffusion barrier layer 207. Operations 102, 104, 106, and 108 can be repeated for the additional pair of sacrificial channel layers 206 and semiconductor channel layers 208 to form a stack 209 having layers 205, 206, 207, and 208. Figure 7 As shown, as an example, three sacrificial channel layers 206 and three semiconductor channel layers 208 are arranged alternately. More or fewer pairs of sacrificial channel layers 206 and semiconductor channel layers 208 may be included, depending on the desired number of channels in the semiconductor device to be formed. In some embodiments, the number of pairs of sacrificial channel layers 206 and semiconductor channel layers 208 may be between 1 and 10.

[0038] In some embodiments, the diffusion barrier layers 205, 207 in each pair of sacrificial channel layers 206 and semiconductor channel layers 208 have substantially the same thickness T205, T207. In other embodiments, the diffusion barrier layers 205, 207 in different pairs of sacrificial channel layers 206 and semiconductor channel layers 208 have substantially different thicknesses depending on the device design.

[0039] In some embodiments, although the doping process is performed via an epitaxial process, operations 102, 104, 106, and 108 can be sequentially performed in the same epitaxial processing chamber by changing the process gas to obtain epitaxial films with different compositions. Therefore, the first diffusion barrier layer 205, the sacrificial channel layer 206, the second diffusion barrier layer 207, and the semiconductor channel layer 208 are formed sequentially in the same epitaxial processing chamber.

[0040] As described above, the first diffusion barrier layer 205 and the second diffusion barrier layer 207 prevent elements (such as germanium) in the sacrificial channel layer 206 from diffusing into the semiconductor channel layer 208, thereby maintaining crystallinity at the interface between the sacrificial channel layer 206 and the semiconductor channel layer 208.

[0041] Figure 7A The diffusion blocking effect of diffusion barrier layers 205 / 207 is schematically shown. Figure 7A The germanium concentration distribution along a stack of layers including a sacrificial channel layer 206, a diffusion barrier layer 207, and a semiconductor channel layer 208 is shown. The sacrificial channel layer 206 comprises SiGe, the diffusion barrier layer 207 comprises carbon-doped silicon, and the semiconductor channel layer 208 comprises silicon. Curves 704 and 708 represent the carbon and germanium concentrations along the depth of the stack including the sacrificial channel layer 206, the diffusion barrier layer 207, and the semiconductor channel layer 208, respectively. As shown by curves 708 and 704, the germanium concentration drops sharply and becomes insignificant after passing through the carbon-doped diffusion barrier layer 207. Curves 702 and 706 represent the carbon and germanium concentrations along the stack of sacrificial channel layer 206 and semiconductor channel layer 208 without the diffusion barrier layer 207. As shown by curves 706 and 702, without the diffusion barrier layer 207, germanium in the SiGe layer diffuses significantly into the silicon layer. A comparison of curves 708 and 706 shows that the carbon-doped diffusion barrier layer 207 effectively prevents germanium from diffusing from the SiGe layer to the Si layer.

[0042] Figure 7B Schematic illustration along Figure 7 The distribution of germanium and carbon in the stack 209. Figure 7BThe germanium concentration distribution along a stack 209 comprising a first diffusion barrier layer 205, a sacrificial channel layer 206, a diffusion barrier layer 207, and a semiconductor channel layer 208 arranged sequentially is shown. The sacrificial channel layer 206 comprises SiGe, the diffusion barriers 205 and 207 comprise carbon, and the semiconductor channel layer 208 comprises silicon. Curves 714 and 716 represent the carbon and germanium concentrations along the depth of the stack 209, respectively. As shown by curves 716 and 714, the germanium concentration in the semiconductor channel layer 208 decreases sharply after passing through the diffusion barriers 205 / 207. Curves 712 and 718 represent the carbon and germanium concentrations along the stack of the sacrificial channel layer 206 and the semiconductor channel layer 208 without the diffusion barriers 205 / 207. As shown by curves 718 and 712, without the diffusion barriers 205 / 207, germanium in the sacrificial channel layer 206 diffuses significantly into the semiconductor channel layer 208.

[0043] Figure 7C Schematic illustration of cross Figure 7 germanium gradient on the top and bottom surfaces of the semiconductor channel layer 208 in the stack 209. Figure 7C The germanium gradients at interfaces 1, 2, 3, and 4, marked in stack 209, are shown. The gray bars represent the germanium gradients at interfaces 1, 2, 3, and 4 without carbon doping. The gray bars represent the germanium gradients at interfaces 1, 2, 3, and 4 with carbon doping. Figure 7C As shown, by introducing carbon doping, the germanium gradient at the interface between the SiGe layer and the Si layer decreases, indicating that the diffusion of Ge across the interface is reduced.

[0044] At operation 110, a fin structure 210 is formed on substrate 202 using one or more etching processes, such as Figure 8 , 9 As shown in figures 10, 11, and 12. Figure 8As shown, according to some embodiments, a mask stack 211 is formed on top of stack 209. As an example, mask stack 211 may include a first dielectric layer 211a, a second dielectric layer 211b, a third dielectric layer 211c, a polysilicon layer 211d, an advanced patterning film (APF) 211e, and a bottom anti-reflective coating (BARC) 211f. Typically, the first dielectric layer 211a, the second dielectric layer 211b, and the third dielectric layer 211c serve as a hard mask, while the combination of the polysilicon layer 211d, the APF 211e, and the BARC 211f is used to pattern the hard mask and for critical size control in order to obtain and control the desired size of the patterned hard mask (e.g., the first dielectric layer 211a, the second dielectric layer 211b, and the third dielectric layer 211c). In some embodiments, the first dielectric layer 211a, the second dielectric layer 211b, and the third dielectric layer 211c include an oxide-nitride-oxide (ONO) layer, wherein the first dielectric layer 211a may be an oxide (such as silicon oxide), the second dielectric layer 211b is a nitride (such as silicon nitride), and the third dielectric layer 211c may be an oxide (such as silicon oxide).

[0045] The masking stack 211 can be sequentially patterned to eventually form a fin structure 210. Each fin structure 210 may include a stack portion and a well portion 204, the stack portion including layers 205, 206, 207, and 208.

[0046] In operation 112, an isolation layer 212 is filled into the trenches between the fin structures 210, and then etched back to the stacked portion below the fin structures 210. The isolation layer 212 can be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD), or other suitable deposition processes. In some embodiments, the isolation layer 212 may comprise silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric, or combinations thereof.

[0047] In operation 114, a sacrificial gate structure 214 is formed above the isolation layer 212 and around the exposed portion of the fin structure 210, as shown below. Figure 13 As shown, a sacrificial gate structure 214 is formed over the portion of the fin structure 210 that will become a channel region. A trench is formed between adjacent sacrificial gate structures 214. The sacrificial gate structures 214 are substantially perpendicular to the fin structure 210.

[0048] A sacrificial gate dielectric layer 218 can be conformally formed over the fin structure 210 and the isolation layer 212. In some embodiments, the sacrificial gate dielectric layer 218 can be deposited using CVD, subatmospheric CVD (SACVD), FCVD, ALD, PVD, or other suitable processes. The sacrificial gate dielectric layer 218 may comprise one or more layers of dielectric material, such as SiO2, SiN, high-k dielectric material, and / or other suitable dielectric material.

[0049] A sacrificial gate electrode layer 220 can be blanket-deposited on the sacrificial gate dielectric layer 218. The sacrificial gate electrode layer 220 comprises silicon, such as polycrystalline silicon or amorphous silicon. The thickness of the sacrificial gate electrode layer is in the range of about 42 nm to about 200 nm. In some embodiments, the sacrificial gate electrode layer 220 is planarized. The sacrificial gate electrode layer 220 can be deposited using CVD (including LPCVD and PECVD), PVD, ALD, or other suitable processes.

[0050] Subsequently, a pad layer 222 and a mask layer 224 are formed over the sacrificial gate electrode layer 220. The pad layer 222 may include silicon nitride. The mask layer 224 may include silicon oxide. Next, a process sequence including patterning and etching is performed on the mask layer 224, the pad layer 222, the sacrificial gate electrode layer 220, and the sacrificial gate dielectric layer 218 to form the sacrificial gate structure 214. Portions of the sacrificial gate electrode layer 220 and the sacrificial gate dielectric layer 218 are sequentially removed using the pattern formed in the mask layer 224 to form the sacrificial gate structure 214.

[0051] In operation 116, a gate sidewall spacer layer 216 can be deposited on the semiconductor device 200 by blanket deposition of one or more insulating materials, such as... Figure 13 As shown. The gate sidewall spacer layer 216 may include two or more layers of dielectric material. In some embodiments, the gate sidewall spacer layer 216 may include one or more insulating materials. The gate sidewall spacer layer 216 may include silicon nitride-based materials, such as SiN, SiON, SiOCN, or SiCN and combinations thereof.

[0052] In operation 118, the fin structures 210 not covered by the sacrificial gate structure 214 are first etched to expose the well portion of each fin structure 210, thereby forming source / drain recesses. In some embodiments, suitable dry and / or wet etching may be used to etch back layers 205, 206, 207, 208 together or separately. After the fin structures 210 are recessed, portions of the fin sidewall spacers 216 may be retained. The height of the remaining fin sidewall spacers 216 can be used to control the shape of the subsequently formed epitaxial source / drain regions.

[0053] In operation 120, after the fin structure 210 is etched into a recess, a source / drain recess 234 is formed. Figure 15B The internal spacer 232 is shown. To form the internal spacer 232, the sacrificial channel layer 206 beneath the gate sidewall spacer 216 is selectively etched from the semiconductor layer 208 and the diffusion barrier layers 205, 207 in a horizontal or x-direction to form a spacer cavity. In some embodiments, the sacrificial channel layer 206 can be selectively etched using a wet etchant (e.g., but not limited to, ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine catechol (EDP), or potassium hydroxide (KOH) solution). After forming the spacer cavity, an insulating layer is conformally deposited in the spacer cavity and then partially removed to form the internal spacer 232. The insulating layer can be formed by ALD or any other suitable method. The subsequent etching process removes most of the insulating layer except for the insulating layer inside the cavity, resulting in the internal spacer 232.

[0054] In operation 122, source / drain regions 236 and 238 are formed, such as Figure 14 As shown, Figure 14 This is a schematic perspective view of semiconductor device 200. In some embodiments, epitaxial source / drain regions 236, 238 can be used for different types of devices and can be individually formed using patterning processes. In some embodiments, epitaxial source / drain regions 236 for N-type devices are formed from the exposed surface of fin structure 210b. Epitaxial source / drain regions 236 for N-type devices may include one or more layers of Si, SiP, SiC, and SiCP. Epitaxial source / drain regions 236 also include N-type dopants, such as phosphorus (P), arsenic (As), etc. In some embodiments, epitaxial source / drain regions 236 may be a Si layer including phosphorus (P) dopants.

[0055] The epitaxial source / drain region 238 can be used in a P-type device. The epitaxial source / drain region 238 can be formed by any suitable method (e.g., by CVD, CVD epitaxy, molecular beam epitaxy (MBE), or any suitable deposition technique). In some embodiments, the epitaxial source / drain region 238 for a p-type device may comprise one or more layers of Si, SiGe, or Ge having a p-type dopant (e.g., boron (B)) for a p-type device (e.g., a pFET). In some embodiments, the epitaxial source / drain region 238 may be a SiGe material including boron as a dopant. The formation order of the epitaxial source / drain of NMOS and PMOS can be interchanged according to process requirements. The shapes of the epitaxial source / drain regions of NMOS and PMOS may vary depending on the design of the film scheme.

[0056] In operation 124, a contact etch stop layer (CESL) 240 and an interlayer dielectric (ILD) layer 242 are conformally formed on the semiconductor device 200, such as Figure 15B As shown, Figure 15B It is along Figure 14 A cross-sectional view of the semiconductor device 200 with a BB line. A CESL 240 is formed on the exposed surface of the semiconductor device 200. The CESL 240 is formed on the epitaxial source / drain regions 236, 238, the gate sidewall spacer 216, the fin sidewall spacer 216, and the isolation layer 212. The CESL 240 may comprise Si3N4, SiON, SiCN, or any other suitable material, and can be formed by CVD, PVD, or ALD.

[0057] An ILD layer 242 is formed over the contact etch stop layer 240. The material of the ILD layer 242 includes compounds comprising Si, O, C, and / or H, such as silicon oxide, SiCOH, and SiOC. Organic materials (e.g., polymers) may be used for the ILD layer 242. In some embodiments, the ILD layer 242 may be formed by flowable CVD (FCV). The ILD layer 242 and the CESL layer 240 protect the epitaxial source / drain regions 236, 238 during the removal of the sacrificial gate structure 214. In some embodiments, a planarization process may be performed after depositing the ILD layer 242 to expose the sacrificial gate structure 214.

[0058] In operation 126, the sacrificial gate structure 214 and the sacrificial channel layer 206 are removed to form as shown. Figure 15A and 15B The gate cavity 251 shown is... Figure 15A and 15B They are along Figure 14 A cross-sectional view of the semiconductor device 200 with AA and BB lines. First, the sacrificial gate electrode layer 220 and the sacrificial gate dielectric layer 216 are removed to expose the fin structure 210 covered by the sacrificial gate structure 214. The sacrificial gate electrode layer 220 can be removed using plasma dry etching and / or wet etching. After removing the sacrificial gate electrode layer 220, the sacrificial gate dielectric layer 218 is exposed. An etching process can be performed to selectively remove the sacrificial gate dielectric layer 218, exposing the first diffusion barrier layer 205, the sacrificial channel layer 206, the second diffusion barrier layer 207, and the semiconductor channel layer 208.

[0059] Partial removal of the sacrificial channel layer 206 to expose the first diffusion barrier layer 205, the second diffusion barrier layer 207, and the semiconductor channel layer 208, such as... Figures 15A to 15BAs shown. The sacrificial channel layer 206 can be selectively etched using a suitable etching method, while the first diffusion barrier layer 205, the second diffusion barrier layer 207, and the semiconductor channel layer 208 remain substantially intact. The sacrificial channel layer 206 can be selectively etched using a suitable wet etchant or a dry etching process. In some embodiments, a dry etching process can be performed using an etching gas comprising fluorocarbon gases (such as CF4, C2F6, C3F8, CHF3, or CH2F2) to selectively remove the sacrificial channel layer 206.

[0060] Because diffusion barrier layers 205 and 207 prevent diffusion from the sacrificial channel layer 206 to the adjacent semiconductor channel layer 208, etch selectivity between the sacrificial channel layer 206 and the semiconductor channel layer 208 is essentially maintained.

[0061] After operation 126, the semiconductor channel layer 208 is still covered by the first diffusion barrier layer 205 and / or the second diffusion barrier layer 207. The top surface 208t and bottom surface 208b of the semiconductor channel layer 208 are substantially flat. Specifically, the bottom surface 208b of the topmost semiconductor channel layer 208 is covered by the second diffusion barrier layer 207, while the top surface 208t of the topmost semiconductor channel layer 208 is exposed. The semiconductor channel layer 208 below the topmost semiconductor channel layer 208 has a first diffusion barrier layer 205 covering the top surface 208t and a second diffusion barrier layer 207 covering the bottom surface 208b. The side surfaces 208s are exposed to the gate cavity 251. In some embodiments, the first diffusion barrier layer 205 and the second diffusion barrier layer 207 may be at least partially removed in operation 126 to improve the electrical characteristics of the semiconductor device 200. In some embodiments, the first diffusion barrier layer 205 and the second diffusion barrier layer 207 may be completely removed in operation 126. However, residues of dopants, such as carbon residues, can be detected in the diffusion barrier layers 205 and 207 in the semiconductor channel layer 208.

[0062] In operation 128, a replacement gate structure 252 is formed around the semiconductor channel layer 208, such as Figure 16 , Figure 16A and Figure 16B As shown. The replacement gate structure 252 includes a gate dielectric layer 244 and a gate electrode layer 246. The gate dielectric layer 244 is formed on the exposed surface in the gate cavity. Figure 16A and Figure 16BAs shown, a gate dielectric layer 244 is formed around the semiconductor channel layer 208. In some embodiments, a first diffusion barrier layer 205 is disposed between the semiconductor channel layer 208 and the gate dielectric layer 244, and a second diffusion barrier layer 207 is disposed between the semiconductor channel layer 208 and the gate dielectric layer 244. On the side surface 208s of the semiconductor channel layer 208, the gate dielectric layer 244 is disposed on the semiconductor channel layer 208 without any barrier layer.

[0063] In some embodiments, an interface layer 245 is formed along the exposed surfaces of the semiconductor channel layer 208, the first diffusion barrier layer 205, and the second diffusion barrier layer 207. A gate dielectric layer 244 is formed over the interface layer 245. The interface layer 245 helps to buffer the subsequently formed high-k dielectric layer from the underlying semiconductor material. In some embodiments, the interface layer 245 is a chemically formed silicon oxide that can be chemically reacted. For example, the chemical oxide can be formed using deionized water and ozone (DIO3), NH4OH + H2O2 + H2O (APM), or other methods. In some embodiments, different materials or processes can be used to form the interface layer 245. In some embodiments, the interface layer 235 may have approximately 3 Approximately 7 The thickness.

[0064] The gate dielectric layer 244 of N-type and P-type devices can have different compositions and dimensions, and can be formed individually using patterned mask layers and different deposition formulations. The gate dielectric layer 244 may comprise one or more layers of dielectric materials, such as silicon oxide, silicon nitride, or high-k dielectric materials, other suitable dielectric materials, and / or combinations thereof. Examples of high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, alumina, titanium oxide, hafnium dioxide-alumina (HfO2-Al2O3) alloys, other suitable high-k dielectric materials, and / or combinations thereof. The gate dielectric layer 244 can be formed by CVD, ALD, or any suitable method.

[0065] A gate electrode layer 246 is formed on the gate dielectric layer 244 to fill the gate cavity. The gate electrode layer 246 may comprise one or more layers of conductive materials, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or combinations thereof. In some embodiments, the gate electrode layer 246 may be formed by CVD, ALD, electroplating, or other suitable methods. The gate electrode layer 246 of N-type devices and P-type devices may have different compositions and dimensions, and may be formed individually using patterned mask layers and different deposition formulations. In some embodiments, the gate electrode layer 246 of an N-type device may comprise TiAl. The gate electrode layer 246 of a P-type device may comprise TiN and TiAl.

[0066] like Figures 16A to 16B As shown, the internal spacer 232 is in contact with the first diffusion barrier layer 205 and the second diffusion barrier layer 207. The first diffusion barrier layer 205 and the second diffusion barrier layer 207 are in contact with the source / drain regions 236 / 238 at their end portions.

[0067] like Figures 16A to 16B As shown, the first diffusion barrier layer 205 and the second diffusion barrier layer 207 are retained in the semiconductor device 200 and clad on the semiconductor channel layer 208. The first diffusion barrier layer 205 and the second diffusion barrier layer 207 can be detected by the dopant concentration. Figure 16C This is a schematic dopant distribution along the z-direction across the semiconductor channel layer 208 according to an embodiment of this disclosure. Figure 16 As shown, the dopant (carbon) concentration exhibits an outer peak C205 / 207 near the top surface 208t and the bottom surface 208b, and an inner peak C208 near the middle portion. In some embodiments, the ratio of the outer peak C205 / 207 to the inner peak C208 is in the range of about 5 to about 50.0.

[0068] The diffusion barrier layer according to this disclosure may include a single layer, as shown in the embodiments above. In some embodiments, the diffusion barrier layer (such as diffusion barrier layers 205, 207) may include two or more doped layers. The two or more doped layers may include different epitaxial materials, different doping distributions, different dopants, or combinations thereof.

[0069] Figures 17A to 17B The stages of manufacturing a semiconductor device 200a according to an embodiment of the present disclosure are illustrated schematically. Figure 17A This is a schematic cross-sectional view of the semiconductor layer stack for the fin structure used in semiconductor device 200a. Figure 17B This is a schematic cross-sectional view of the semiconductor device 200a after operation 128.

[0070] Semiconductor device 200a is similar to semiconductor device 200, except that in semiconductor device 200a, the diffusion barrier layers 205 and 207 include two or more sublayers. Figure 17A In the example, the first diffusion barrier layer 205 includes a first sublayer 205a and a second sublayer 205b stacked together; and the second diffusion barrier layer 205 includes a first sublayer 207a and a second sublayer 207b.

[0071] In the first diffusion barrier layer 205, a first sublayer 205a faces or is in contact with the semiconductor channel layer 208, while a second sublayer 205b faces or is in contact with the sacrificial channel layer 206. In some embodiments, the first sublayer 205a and the second sublayer 205b have different doping profiles. It has been observed that higher dopant concentrations provide better diffusion prevention effects and are therefore desirable to place closer to the sacrificial channel layer 206. In some embodiments, the second sublayer 205b comprises a higher dopant concentration than the first sublayer 205a. In some embodiments, the first sublayer 205a is formed by doping an epitaxial layer having the same composition as the semiconductor channel layer 208, while the second sublayer 205b is formed by doping an epitaxial layer having the same composition as the sacrificial channel layer 206. For example, the first sublayer 205a comprises a doped epitaxial silicon layer, and the second sublayer 205b comprises a doped epitaxial SiGe layer. In some embodiments, the first sublayer 205a and the second sublayer 205b may be doped with different dopants. In some embodiments, the first sublayer 205a and the second sublayer 205b may have different thicknesses. In some embodiments, one or more additional sublayers may be disposed between the first sublayer 205a and the second sublayer 205b. In some embodiments, the dopant concentration distribution of the first sublayer 205a and the second sublayer 205b may be gradient or constant. When one or both of the dopant concentration distributions of the first sublayer 205a and the second sublayer 205b are gradient, the average dopant concentration of the second sublayer 205b is higher than the average dopant concentration of the first sublayer 205a.

[0072] In the second diffusion barrier layer 207, the first sublayer 207a faces or is in contact with the semiconductor channel layer 208, while the second sublayer 207b faces or is in contact with the sacrificial channel layer 206. In some embodiments, the first sublayer 207a and the second sublayer 207b have different doping profiles. In some embodiments, the second sublayer 207b has a higher dopant concentration than the first sublayer 207a. In some embodiments, the first sublayer 207a is formed by doping an epitaxial layer having the same composition as the semiconductor channel layer 208, while the second sublayer 207b is formed by doping an epitaxial layer having the same composition as the sacrificial channel layer 206. For example, the first sublayer 207a includes a doped epitaxial silicon layer, and the second sublayer 207b includes a doped epitaxial SiGe layer. In some embodiments, the first sublayer 207a and the second sublayer 207b can be doped with different dopants. In some embodiments, the first sublayer 205a and the second sublayer 207b can have different thicknesses. In some embodiments, one or more additional sublayers may be provided between the first sublayer 207a and the second sublayer 207b.

[0073] The various embodiments or examples described herein offer several advantages over the prior art. A diffusion barrier layer formed on the semiconductor channel layer mitigates diffusion from adjacent sacrificial channel layers, thereby improving the crystallinity of the semiconductor channel layer in a multi-channel device.

[0074] In some aspects, the techniques described herein relate to a method comprising: forming a fin stack on a substrate, wherein the fin stack includes: a semiconductor channel layer; a sacrificial channel layer; and a first capping layer disposed between the semiconductor channel layer and the sacrificial channel layer, wherein the first capping layer includes a material different from the materials of the semiconductor channel layer and the sacrificial channel layer; forming a fin structure from the fin stack; forming a sacrificial gate structure over the fin structure; performing recessed etching on the fin structure; forming source / drain regions on opposite sides of the sacrificial gate structure, wherein the source / drain regions are connected to the semiconductor channel layer; removing the sacrificial gate structure; removing the sacrificial channel layer; and forming a gate structure around the semiconductor channel layer and the first capping layer.

[0075] In some aspects, the techniques described herein relate to a method comprising: forming a sacrificial channel layer on a substrate, wherein the sacrificial channel layer comprises a first element; forming a semiconductor channel layer on the sacrificial channel layer, wherein the semiconductor channel layer is doped with a second element having an atomic radius smaller than that of the first element; forming a fin structure from a stack comprising the sacrificial channel layer and the semiconductor channel layer; forming a sacrificial gate structure on the fin structure; forming source / drain regions on both sides of the sacrificial gate structure; selectively removing the doped portions of the sacrificial channel layer and the semiconductor channel layer from the fin structure; and forming a gate structure around the semiconductor channel layer.

[0076] In some aspects, the technology described herein relates to a semiconductor device including: a first source / drain region; a second source / drain region; and a channel region connecting the first source / drain region and the second source / drain region, wherein the channel region includes: a semiconductor channel layer including a first element; a first capping layer disposed on a first surface of the semiconductor channel layer, wherein the semiconductor channel layer is doped with a second element having an atomic radius smaller than that of the first element; a gate dielectric layer formed around the channel region; and a gate electrode layer disposed on the gate dielectric layer.

[0077] The foregoing disclosure outlines features of several embodiments, enabling those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to perform the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

[0078] Example 1 is a method of forming a semiconductor device, comprising: forming a fin stack on a substrate, wherein the fin stack includes: a semiconductor channel layer; a sacrificial channel layer; and a first capping layer disposed between the semiconductor channel layer and the sacrificial channel layer, wherein the first capping layer includes a material different from the materials of the semiconductor channel layer and the sacrificial channel layer; forming a fin structure from the fin stack; forming a sacrificial gate structure on the fin structure; performing recess etching on the fin structure; forming source / drain regions on opposite sides of the sacrificial gate structure, wherein the source / drain regions are connected to the semiconductor channel layer; removing the sacrificial gate structure; removing the sacrificial channel layer; and forming a gate structure around the semiconductor channel layer and the first capping layer.

[0079] Example 2 is the method described in Example 1, wherein forming the fin stack includes: forming a first epitaxial growth layer on the semiconductor channel layer; and doping the first epitaxial growth layer with a first element.

[0080] Example 3 is the method described in Example 2, wherein forming the fin stack further includes: forming the semiconductor channel layer on the first capping layer; and forming a second capping layer on the semiconductor channel layer.

[0081] Example 4 is the method described in Example 3, wherein forming the second capping layer includes: forming a second epitaxial growth layer on the semiconductor channel layer; and doping the second epitaxial growth layer with the first element.

[0082] Example 5 is the method described in Example 4, wherein the first element is one of carbon, boron, and arsenic.

[0083] Example 6 is the method of Example 2, wherein forming the first epitaxial growth layer includes: doping the first element into the top portion of the semiconductor channel layer.

[0084] Example 7 is the method described in Example 1, wherein the first capping layer includes: a first sub-layer facing the semiconductor channel layer; and a second sub-layer facing the sacrificial channel layer.

[0085] Example 8 is the method described in Example 7, wherein the first sublayer and the second sublayer have different doping distributions.

[0086] Example 9 is a method of forming a semiconductor device, comprising: forming a sacrificial channel layer on a substrate, wherein the sacrificial channel layer comprises a first element; forming a semiconductor channel layer on the sacrificial channel layer, wherein the semiconductor channel layer is doped with a second element having an atomic radius smaller than that of the first element; forming a fin structure from a stack comprising the sacrificial channel layer and the semiconductor channel layer; forming a sacrificial gate structure on the fin structure; forming source / drain regions on both sides of the sacrificial gate structure; selectively removing the portion of the sacrificial channel layer and the semiconductor channel layer doped with the second element from the fin structure; and forming a gate structure around the semiconductor channel layer.

[0087] Example 10 is the method of Example 9, further comprising: forming a first cap layer prior to forming the sacrificial trench layer.

[0088] Example 11 is the method described in Example 10, wherein forming the first capping layer includes: forming an epitaxial layer doped with the second element.

[0089] Example 12 is the method described in Example 11, wherein the epitaxial layer is a second semiconductor channel layer formed on the substrate.

[0090] Example 13 is the method of Example 11, further comprising: forming the epitaxial layer on the substrate prior to doping with the second element.

[0091] Example 14 is the method described in Example 9, wherein the second element has an atomic radius smaller than that of silicon or germanium.

[0092] Example 15 is the method described in Example 9, wherein the second element is one of carbon, boron, and arsenic.

[0093] Example 16 is a semiconductor device comprising: a first source / drain region; a second source / drain region; and a channel region connecting the first source / drain region and the second source / drain region, wherein the channel region comprises: a semiconductor channel layer comprising a first element; a first capping layer disposed on a first surface of the semiconductor channel layer, wherein the semiconductor channel layer is doped with a second element having an atomic radius smaller than that of the first element; a gate dielectric layer formed around the channel region; and a gate electrode layer disposed on the gate dielectric layer.

[0094] Example 17 is the semiconductor device described in Example 16, wherein the channel region further includes: a second capping layer disposed on a second surface of the semiconductor channel layer.

[0095] Example 18 is the semiconductor device described in Example 16, wherein the first capping layer includes an epitaxial layer doped with the second element.

[0096] Example 19 is the semiconductor device described in Example 18, wherein the second element is one of carbon, boron, and arsenic.

[0097] Example 20 is the semiconductor device described in Example 16, further comprising: an internal spacer disposed on an end portion of the channel region and between the first source / drain region and the gate dielectric layer, and the internal spacer being in contact with the first capping layer.

Claims

1. A method for forming a semiconductor device, comprising: A fin stack is formed on a substrate, wherein the fin stack comprises: Semiconductor channel layer; Sacrificial channel layer; and A first capping layer is disposed between the semiconductor channel layer and the sacrificial channel layer, wherein the first capping layer comprises a material different from the materials of the semiconductor channel layer and the sacrificial channel layer; The fin structure is formed from the stacked fins; A sacrificial gate structure is formed on the fin structure; The fin structure is etched with recesses; Source / drain regions are formed on opposite sides of the sacrificial gate structure, wherein the source / drain regions are connected to the semiconductor channel layer; Remove the sacrificial gate structure; Remove the sacrificial channel layer; and A gate structure is formed around the semiconductor channel layer and the first capping layer.

2. The method according to claim 1, wherein, Forming the fin stack includes: A first epitaxial growth layer is formed on the semiconductor channel layer; and The first epitaxial growth layer is doped with the first element.

3. The method according to claim 2, wherein, Forming the fin stack also includes: The semiconductor channel layer is formed on the first cap layer; and A second capping layer is formed on the semiconductor channel layer.

4. The method according to claim 3, wherein, Forming the second cap layer includes: A second epitaxial growth layer is formed on the semiconductor channel layer; and The second epitaxial growth layer is doped with the first element.

5. The method according to claim 4, wherein, The first element is one of carbon, boron, and arsenic.

6. The method according to claim 2, wherein, Forming the first epitaxial growth layer includes doping the first element into the top portion of the semiconductor channel layer.

7. The method according to claim 1, wherein, The first cap layer includes: The first sublayer facing the semiconductor channel layer; and The second sublayer facing the sacrificial trench layer.

8. The method according to claim 7, wherein, The first sublayer and the second sublayer have different doping distributions.

9. A method for forming a semiconductor device, comprising: A sacrificial trench layer is formed on a substrate, wherein the sacrificial trench layer comprises a first element; A semiconductor channel layer is formed on the sacrificial channel layer, wherein the semiconductor channel layer is doped with a second element whose atomic radius is smaller than that of the first element; A fin structure is formed from a stack including the sacrificial channel layer and the semiconductor channel layer; A sacrificial gate structure is formed on the fin structure; Source / drain regions are formed on both sides of the sacrificial gate structure; Selectively remove the portion of the sacrificial channel layer and the semiconductor channel layer doped with the second element from the fin structure; and A gate structure is formed around the semiconductor channel layer.

10. A semiconductor device, comprising: First source / drain region; Second source / drain region; as well as A channel region, connecting the first source / drain region and the second source / drain region, wherein the channel region includes: Semiconductor channel layer, including the first element; A first capping layer is disposed on a first surface of the semiconductor channel layer, wherein the semiconductor channel layer is doped with a second element whose atomic radius is smaller than that of the first element; A gate dielectric layer is formed around the channel region; and A gate electrode layer is disposed on the gate dielectric layer.

Images