Semiconductor device and method of manufacturing the same

Abstract

The application provides a semiconductor device and a manufacturing method thereof. The device comprises: a trench gate structure extending along a second direction; a source region of a first conductive type located on both sides of the trench gate structure and adjacent to the sidewall of the trench gate structure; a body region of a second conductive type located below the source region; a contact region of the second conductive type located on a side of the source region and the body region away from the trench gate structure; a shielding region of the second conductive type located below the contact region; a doped region of the first conductive type located below the body region and in a region between the contact region and the shielding region; the shielding regions are spaced apart along the second direction and extend along a first direction; the shielding region is adjacent to the contact region, so that adjacent shielding regions are electrically connected through the contact region. The application electrically connects the shielding regions located on both sides of the trench to the source metal layer, so that the potential of the shielding region is clamped by the source, thereby effectively suppressing the electric field peak at the corner of the trench in the blocking state.

Description

Technical Field

[0001] This application relates to the field of semiconductor device technology, and in particular to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] Silicon carbide (SiC), as a third-generation wide-bandgap semiconductor material, has become the preferred material for high-voltage, high-frequency, and high-power devices due to its high critical breakdown electric field, high thermal conductivity, and excellent carrier transport characteristics. Among them, SiC trench metal-oxide-semiconductor field-effect transistors (TMOS, also known as SiC trench MOSFETs) are expected to achieve lower specific on-resistance (Ron,sp) due to their smaller cell spacing and higher channel mobility on the trench sidewalls, making them extremely valuable for applications in power electronics fields such as new energy vehicles, photovoltaic inverters, and rail transportation.

[0003] However, in the blocked state, SiC trench MOSFET devices are prone to electric field concentration at the gate oxide layer at the trench corners. Over long-term use, this can lead to reliability issues such as gate oxide breakdown and threshold voltage drift, severely limiting the device's lifespan and stability. To alleviate the electric field concentration effect at the trench corners, the industry commonly adopts a structure design that introduces a P+ shielding region. However, existing mainstream P-well shielding structures all suffer from technical bottlenecks that make it difficult to balance conduction performance and reliability. Furthermore, forming a P+ shielding region with a depth greater than 1µm requires a high-energy ion implantation process, which is technically challenging and expensive.

[0004] In summary, the existing P-well shielding structure of SiC trench MOSFETs cannot simultaneously achieve low on-resistance, low electric field concentration, and high process compatibility, making it difficult to meet the mass production requirements of high-performance and high-reliability high-voltage power devices. There is an urgent need to optimize the device structure to resolve the above-mentioned technical contradictions. Summary of the Invention

[0005] In view of the above problems, the purpose of this application is to provide a semiconductor device and its manufacturing method, which effectively suppresses the electric field peak at the trench corner by electrically connecting the shielding regions located on both sides of the trench to the source metal layer, thereby clamping the potential of the shielding regions to the source metal layer and thus effectively suppressing the electric field peak at the trench corner in the blocking state; the manufacturing method can reduce ion implantation energy and improve the device's conduction performance and reliability.

[0006] According to one aspect of this application, a semiconductor device is provided, comprising a plurality of cell units, each cell unit comprising: a drift layer of a first conductivity type; a trench gate structure extending into the drift layer; a source region of the first conductivity type located above the drift layer and on both sides of the trench gate structure and adjacent to the sidewalls of the trench gate structure; a body region of a second conductivity type located between the source region and the drift layer, and on both sides of the trench gate structure and adjacent to the sidewalls of the trench gate structure; contact regions of the second conductivity type located on both sides of the trench gate structure and adjacent to the side of the source region and the body region away from the trench gate structure, at least a portion of the contact regions extending along the depth direction of the trench gate structure below the bottom surface of the trench gate structure; and a shielding region of the second conductivity type located below the two contact regions and adjacent to the bottom of the contact regions, with the upper surface of the shielding region located below the bottom of the trench gate structure; wherein the shielding regions are spaced apart along a second direction, and at least a portion of the shielding regions form a beam-like structure with two sides connected below the bottom of the trench gate structure.

[0007] In some embodiments, the cell unit further includes: a doped region of a first conductivity type, located between the body region and the drift layer, and between the contact region and the shielding region, wherein the doping concentration of the doped region is greater than the doping concentration of the drift layer.

[0008] In some embodiments, at least a portion of the bottom surface of the contact area has the same depth as the bottom or top surface of the shielding area.

[0009] In some embodiments, at least a portion of the bottom surface of the contact area has the same depth as the bottom surface of the body area.

[0010] In some embodiments, the shielding area is perpendicular to the projection of the trench grid structure onto the XY plane.

[0011] In some embodiments, along the second direction, the width of the shielding area is less than or equal to the interval between two adjacent shielding areas.

[0012] In some embodiments, along the second direction, the ratio of the width of the shielding area to the interval between two adjacent shielding areas is greater than or equal to 1 / 5 and less than or equal to 1.

[0013] In some embodiments, the doping concentration of the contact area and the shielding area is the same.

[0014] According to another aspect of the present invention, a method for manufacturing a semiconductor device is provided, comprising: providing a substrate; forming a drift layer of a first conductivity type on the substrate; forming a first epitaxial layer of the first conductivity type on the drift layer; doping a first region of the first epitaxial layer to form a shielding region of a second conductivity type, wherein the undoped first epitaxial layer is a first doped region; forming a second epitaxial layer of the first conductivity type on the first epitaxial layer; doping a first region of the second epitaxial layer to form a first contact region of the second conductivity type, wherein the undoped second epitaxial layer is a second doped region; forming a third epitaxial layer of the second conductivity type on the second epitaxial layer; doping a first region of the third epitaxial layer to form a second contact region of the second conductivity type; doping a second region of the third epitaxial layer to form a source region of the first conductivity type, wherein the undoped third epitaxial layer is a body region; and forming a trench gate structure, an interlayer dielectric layer, and a source metal layer.

[0015] In some embodiments, the shielding areas are spaced apart along a second direction, and at least a portion of the shielding areas form a beam-like structure with both sides connected below the bottom of the trench grid structure.

[0016] In some embodiments, the first doped region and the second doped region have the same doping concentration and are combined to form a doped region with a doping concentration greater than that of the drift layer; or the first doped region and the second doped region have the same doping concentration and the same doping concentration as that of the drift region, and are combined to form a part of the drift region.

[0017] In some embodiments, the steps of forming the shielding region and the first doped region further include: doping a second region of the first epitaxial layer to form a third contact region of a second conductivity type, the third contact regions being spaced between adjacent shielding regions.

[0018] In some embodiments, the steps of forming the second contact region, source region, and body region include: forming a first mask layer on the third epitaxial layer, wherein a first region does not have the first mask layer, and performing ion implantation on the third epitaxial layer via the first mask layer to form a second contact region of a second conductivity type; removing the first mask layer; forming a second mask layer on the third epitaxial layer, wherein a second region does not have the second mask layer, and performing ion implantation on the third epitaxial layer via the second mask layer to form a source region of a first conductivity type, wherein the source region extends from a first surface to a second surface of the third epitaxial layer, the second surface of the source region is located in the third epitaxial layer, and the region of the third epitaxial layer not subjected to ion implantation is a body region; removing the mask layer, wherein the first region of the third epitaxial layer corresponds to the second contact region, the second region corresponds to the source region, and the second contact region is correspondingly connected to the first contact region.

[0019] In some embodiments, the ion implantation energy for forming the second contact region is greater than the ion implantation energy for forming the source region.

[0020] In some embodiments, the first region of the second epitaxial layer is doped by ion implantation to form a first contact region of a second conductivity type; the first region of the first epitaxial layer is doped by ion implantation to form a shielding region of a second conductivity type; wherein the ion implantation energy for forming the shielding region is less than the energy for forming the first contact region.

[0021] In some embodiments, the ion implantation energy forming the shielding region is less than the ion implantation energy forming the second contact region.

[0022] The semiconductor device and its manufacturing method provided in this application clamp the potential of the shielding region to the source metal layer by electrically connecting the shielding region to the source metal layer (via a contact region). When the device is in a blocking state (high-voltage turn-off), the electric field peak at the bottom corner of the trench gate structure is effectively suppressed, preventing the gate oxide layer from breaking down due to electric field concentration, thus significantly improving the reliability and lifespan of the device. At the same time, the direct connection between the shielding region and the source avoids the gate leakage current problem that may be caused by traditional "floating" shielding regions.

[0023] In some embodiments, both the contact region and the shielding region are of a second conductivity type (such as P-type) and have the same doping concentration, thereby forming a low-resistance path. This ensures efficient coupling of the source potential to the shielding region and enhances the electric field modulation effect. Furthermore, it avoids abrupt changes in interface potential or carrier scattering due to differences in doping, thus improving device stability.

[0024] In some embodiments, along the second direction, the first dimension of the shielding region is smaller than the second dimension between two adjacent shielding regions. This helps to effectively regulate the electric field at the corner of the bottom of the trench gate structure even when the channel current path width is large, thereby further mitigating the electric field peak of the gate oxide layer in the off state and extending the device lifetime.

[0025] In some embodiments, the positional relationship between the drift layer and the doped region is clearly defined. The doped region is located below the body region and the trench gate, separating adjacent shielding regions. The higher doping concentration in the doped region compared to the drift region reduces the JFET region resistance and improves conduction efficiency. The shielding regions are separated by the doped region, which on the one hand realizes the channel path, on the other hand prevents mutual interference of electric fields, and optimizes the breakdown voltage capability.

[0026] In some embodiments, the drift layer is of a low concentration first conductivity type, and the doped region is of a high concentration first conductivity type. The drift layer ensures a high breakdown voltage, and the doped region reduces the on-resistance, thereby achieving synergistic optimization of breakdown voltage and efficiency.

[0027] Furthermore, in the manufacturing method of semiconductor devices, the shielding region, contact region, source region and body region are formed by successively doping three epitaxial layers. This method has strong process compatibility, avoids complex etching steps, improves yield and reduces costs. Attached Figure Description

[0028] The above and other objects, features and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0029] Figure 1 A three-dimensional structural diagram of a semiconductor device according to a first embodiment of this application is shown;

[0030] Figures 2a to 2c It shows according to Figure 1 A vertical cross-sectional view of the semiconductor device obtained by the dashed line in the middle;

[0031] Figures 3a to 3c It shows according to Figure 2a A horizontal cross-sectional view of a semiconductor device obtained by the dashed line in the middle;

[0032] Figure 4 A flowchart illustrating a method for manufacturing a semiconductor device according to a first embodiment of this application is shown;

[0033] Figures 5a to 5i A vertical cross-sectional view of each stage of a method for manufacturing a semiconductor device according to a first embodiment of this application is shown;

[0034] Figures 6a to 6c A schematic diagram of a semiconductor device according to a second embodiment of this application is shown;

[0035] Figures 7a to 7c A schematic diagram of a semiconductor device according to a third embodiment of this application is shown. Detailed Implementation

[0036] The present application will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown. For simplicity, a semiconductor device obtained after several steps can be depicted in a single figure.

[0037] It should be understood that when describing the structure of a device, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above another layer or region, or that there are other layers or regions between it and another layer or region. Furthermore, if the device is flipped, that layer or region will be located "below" or "under" another layer or region.

[0038] To describe a situation where it is directly above another layer or another area, this article will use expressions such as "directly above" or "above and adjacent to".

[0039] Many specific details of this application, such as the structure, materials, dimensions, processing techniques, and methods of the devices, are described below to provide a clearer understanding of the application. However, as those skilled in the art will understand, this application may be implemented without adhering to these specific details.

[0040] The specific implementation methods of this application will be further described in detail below with reference to the accompanying drawings and embodiments.

[0041] In the embodiments of this application, for the sake of clarity in describing the specific implementation of this application, the first direction is defined as the X direction, the second direction as the Y direction, and the third direction as the Z direction, and the first direction, the second direction, and the third direction are mutually perpendicular. The plane containing the first and second directions is a horizontal plane, and the plane containing the third direction is a vertical plane.

[0042] The semiconductor device of this application includes multiple cell units. Figures 2a to 3c For example, an example diagram with two cell units is shown. In the following description, an exemplary description will be given with a structure of one cell unit.

[0043] In this application, Figure 2a For example, along Figure 1 A vertical cross-sectional view obtained in the direction indicated by the dashed line AA; Figure 2b For example, along Figure 1 Vertical cross-sectional view obtained in the direction indicated by the dashed line BB; Figure 2c For example, along Figure 1 The vertical cross-sectional view obtained in the direction indicated by the dashed line CC. Figure 3a For example, along Figure 2a A horizontal cross-sectional view obtained in the direction indicated by the dashed line D; Figure 3b For example, along Figure 2a A horizontal cross-sectional view obtained in the direction indicated by the dashed line E; Figure 3c For example, along Figure 2a A horizontal cross-sectional view obtained in the direction indicated by the dashed line F.

[0044] like Figure 1 , Figures 2a to 2c As shown, the semiconductor device 100 of the first embodiment of this application includes: a substrate 110, a drift layer 120, a trench gate structure 130, a source region 141, a body region 142, a doped region 143, a contact region 151, a shielding region 152, an interlayer dielectric layer 161, a source metal layer 162, and a drain metal layer 163.

[0045] The substrate 110 has a first surface S1 and a second surface S2 disposed opposite to each other, and the substrate 110 serves as the drain region of the semiconductor device 100.

[0046] In this embodiment, the substrate 110 is made of silicon carbide (SiC), for example. In other embodiments, the substrate 110 may also be made of elemental semiconductor materials such as silicon (Si) or germanium (Ge), group IV compound semiconductor materials such as silicon-germanium (SiGe), binary, ternary, or quaternary III-V semiconductor materials such as gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium gallium phosphide (InGaPa), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), aluminum gallium indium nitride (AlGaInN), or indium gallium arsenide phosphide (InGaAsP). However, this embodiment is not limited to these, and those skilled in the art can make other settings for the material of the substrate 110 as needed.

[0047] The substrate 110 is of the first conductivity type, and the crystal orientation of the substrate 110 may include the m plane (1-100) or the a plane (11-20).

[0048] The drift layer 120 is located on the first surface S1 of the substrate 110 and has a first surface and a second surface disposed opposite to each other. The second surface of the drift layer 120 is adjacent to the first surface S1 of the substrate 110, and the first surface of the drift layer 120 is away from the first surface S1 of the substrate 110.

[0049] The drift layer 120 may be made of the same or different semiconductor material as the substrate 110.

[0050] The drift layer 120 is of the first conductivity type, and its thickness and doping concentration can be designed according to the device's voltage withstand capability and on-resistance requirements. In this embodiment, the doping concentration of the drift layer 120 is less than that of the substrate 110.

[0051] In some embodiments, the doping concentration of the drift layer 120 is, for example, 5 × 10⁻⁶. 15 ~1.2×10 16 cm -3 .

[0052] The trench gate structure 130 is located in the trench on the drift layer 120, and the bottom of the trench gate structure 130 is separated from the first surface of the drift layer 120 by a certain distance.

[0053] The trench gate structure 130 includes a gate dielectric layer 131 and a gate conductor 132.

[0054] The gate dielectric layer 131 covers the sidewalls and bottom of the trench, and its material can be selected from silicon oxide, silicon nitride or high-k dielectric material to improve gate control capability and reduce leakage current.

[0055] The gate conductor 132 fills the cavity enclosed by the gate dielectric layer 131. Its material can be polysilicon, metal, or metal-polysilicon composite structure to achieve low contact resistance and high thermal stability.

[0056] The gate dielectric layer 131 separates the gate conductor 132 from the doped region 143 to prevent leakage and ensure effective control of the gate over the channel region.

[0057] The trench gate structure 130 includes multiple trench gate structures 130, which are spaced apart along a first direction and extend parallel to each other along a second direction to form a regularly arranged trench gate array, such as... Figure 1 As shown.

[0058] The source region 141 is located on both sides of the trench gate structure 130 and is adjacent to the two sidewalls of the trench gate structure 130. The first surface of the source region 141 and the first surface of the trench gate structure 130 are located on the same horizontal plane.

[0059] The source region 141 is of the first conductivity type, and its doping concentration is higher than that of the drift layer 120.

[0060] The depth of the source region 141 extending from the first surface to the second surface is less than the depth of the trench gate structure 130 extending from the first surface to the second surface.

[0061] The first surface of the body region 142 is adjacent to the second surface of the source region 141. The body region 142 is located on both sides of the trench gate structure 130 and is adjacent to the two sidewalls of the trench gate structure 130. The horizontal plane where the second surface of the body region 142 is located passes through the trench gate structure 130.

[0062] Body region 142 is of the second conductivity type. The first conductivity type is the opposite of the second conductivity type; the first conductivity type is either P-type or N-type, and the second conductivity type is either P-type or N-type.

[0063] The doped region 143 is located below the body region 142. Its first surface is adjacent to the second surface of the body region 142, the bottom of the trench gate structure 130, and part of the sidewalls, such that the sidewalls of the trench gate structure 130 are adjacent to the source region 141, the body region 142, and the doped region 143 sequentially from the first surface to the second surface; part of the second surface of the doped region 143 is adjacent to the first surface of the drift layer 120.

[0064] The doped region 143 is adjacent to at least a portion of the sidewalls on both sides of the trench gate structure 130 to form an effective channel region, thereby precisely controlling the current path under gate voltage drive, such as Figure 2a and Figure 3a As shown.

[0065] The doped region 143 is of the first conductivity type, and the doping concentration of the doped region 143 is less than that of the source region 141.

[0066] In some embodiments, the doping concentration of the doped region 143 is, for example, 1 × 10⁻⁶. 17 ~5×10 17 cm -3 .

[0067] In some embodiments, the doping concentration of the doped region 143 is greater than the doping concentration of the drift region 120.

[0068] In some embodiments, the doping concentration of the doped region 143 is equal to the doping concentration of the drift region 120, and is part of the drift region 120.

[0069] In some embodiments, the sidewall of the doped region 143 adjacent to the trench gate structure 130 forms the main control interface of the channel, and its doping concentration is greater than that of the drift layer 120, thereby reducing the JFET region resistance and improving the device switching speed while ensuring sufficient channel conduction capability.

[0070] Contact regions 151 are located on both sides of the trench gate structure 130, specifically on the side of the source region 141 and body region 142 away from the trench gate structure 130. The sidewalls of contact regions 151 are adjacent to the source region 141, body region 142 and doped region 143 along the first surface to the second surface. The first surface of contact regions 151 and the first surface of source region 141 are located on the same horizontal plane.

[0071] Contact region 151 is of the second conductivity type, and its doping concentration is greater than that of the bulk region.

[0072] In some embodiments, the doping concentration of the contact region 151 is, for example, 1 × 10⁻⁶. 18 ~5×10 18 cm -3 .

[0073] In this embodiment, at least a portion of the contact area 151 extends along the depth direction of the trench grid structure 130 below the bottom surface of the trench grid structure 130, so that the contact area 151 can be adjacent to the shielding area 152.

[0074] The shielding area 152 is located below the contact areas 151 on both sides of the trench grid structure 130 and is adjacent to the bottom of the contact areas 151. The depth of the shielding area 152 is lower than the depth of the bottom of the trench grid structure 130, and at least the upper surface of the shielding area 152 is located below the bottom of the trench grid structure 130.

[0075] A portion of the first surface and sidewalls of the shielding region 152 are also adjacent to the second surface of the doped region 143. Adjacent shielding regions 152 are separated by the doped region 143, and are further separated by the inner doped region 143 between the shielding region 152 and the bottom of the trench gate structure 130, as shown below. Figure 2c and Figure 3c As shown.

[0076] The shielding region 152 is of the second conductivity type, and its doping concentration is higher than that of the body region 142 and equal to that of the contact region 151.

[0077] In some embodiments, the doping concentration of the shielding region 152 is, for example, 1 × 10⁻⁶. 18 ~3×10 18 cm -3 .

[0078] The shielding area 152 includes multiple shielding areas 152, which are arranged at intervals along the second direction and extend along the first direction, such as... Figure 2b and Figure 3b As shown. At least a portion of the shielding area 152 extends toward the trench grid structure 130, such that at least a portion of the shielding area 152 forms a beam-like structure with both sides connected below the bottom of the trench grid structure 130. That is, the projection of the shielding area 152 onto the XY plane containing the first and second directions penetrates the projection of the trench grid structure 130 onto the XY plane.

[0079] In some embodiments, all shielding areas 152 extend toward the trench grid structure 130, such that all shielding areas 152 form a beam-like structure with both sides connected below the bottom of the trench grid structure 130.

[0080] In some embodiments, the shielding region 152 extending toward the trench gate structure 130 is perpendicular to the projection of the trench gate structure 130 onto the XY plane, that is, the extending direction of the shielding region 152 is perpendicular to the extending direction of the trench gate structure 130. This orthogonal arrangement significantly optimizes the electric field distribution, enabling the shielding region 152 to more effectively suppress electric field concentration in the drift layer 120 and improve the breakdown voltage.

[0081] Reference Appendix Figure 2c Along the second direction, the width of the shielding area 152 is the first dimension D1, and the interval between two adjacent shielding areas 152 is the second dimension D2.

[0082] In some embodiments, the first dimension D1 is less than or equal to the second dimension D2, that is, the width of the shielding region 152 is less than or equal to the interval between two adjacent shielding regions 152. When the path width of the channel current is large, the shielding region 152 can also adjust the electric field at the corner of the bottom of the trench gate structure 130, thereby further alleviating the electric field peak of the gate oxide layer in the off state and extending the device lifetime.

[0083] In some embodiments, the ratio of the first dimension D1 of the shielding area 152 to the second dimension D2 between two adjacent shielding areas 152 is greater than or equal to 1 / 5 and less than or equal to 1.

[0084] In some embodiments, the shielding region 152 does not directly contact the sidewall of the trench gate structure 130, but by precisely controlling the dimensional relationship between D1 and D2, effective modulation of the electric field at the bottom corner can still be achieved. At the same time, channels can be formed on both sidewalls of the trench gate structure 130, which significantly increases the conduction current density and reduces the conduction resistance. Compared with other structures, it is more conducive to reducing the cell spacing and reducing manufacturing costs.

[0085] The interlayer dielectric layer 161 is located on the first surface of the trench gate structure 130, and it shields the first surface of the trench gate structure 130 and partially shields the first surface of the source region 141, such as Figure 2a As shown.

[0086] The material of the interlayer dielectric layer 161 is an oxide, such as silicon dioxide or silicon oxynitride.

[0087] The source metal layer 162 is located above the source region 141 and the contact region 142, forming an ohmic contact with the source region 141 and the contact region 142, and extends to cover the surface of the interlayer dielectric layer 161. As an insulating layer, the interlayer dielectric layer 161 effectively isolates the direct electrical connection between the source metal layer 162 and the trench gate structure 130, preventing the risk of short circuit.

[0088] The source metal layer 162 is made of aluminum, titanium, nickel or a stacked structure thereof, which balances low contact resistance and high temperature stability.

[0089] In some embodiments, the source metal layer 162 forms a low-resistance path with the shielding region 152 via the contact region 151, enabling the source potential to be coupled more uniformly to the bottom of the trench, further suppressing the electric field distortion at the gate edge. This structure significantly reduces the peak electric field at the bottom of the trench under reverse bias. Combined with the deep bottom P-well and direct connection design to the source pad, the bottom corner of the trench gate structure 130 can better withstand high electric field stress under reverse bias.

[0090] The drain metal layer 163 is located on the second surface S2 of the substrate 110 and forms an ohmic contact with the drift layer 120 and the substrate 110 to enable current conduction in the vertical direction of the device.

[0091] The drain metal layer 163 uses a highly conductive metal material, such as a copper / titanium / nickel / silver stack, to ensure low contact resistance and thermal stability.

[0092] In addition, such as Figure 4 and Figures 5a to 5i As shown, the method for manufacturing a semiconductor device according to the first embodiment of this application includes the following steps.

[0093] Step S10: Provide a substrate and form a drift layer of a first conductivity type on the substrate.

[0094] In this step, an epitaxial growth process is used to form a drift layer 120 of a first conductivity type on the first surface of the substrate 110, such as... Figure 5a As shown.

[0095] The substrate 110 is provided with opposing first surfaces S1 and second surfaces S2, and serves as the drain region of the semiconductor device 100.

[0096] The drift layer 120 is located on the first surface S1 of the substrate 110, and its thickness H2 is greater than the thickness H1 of the substrate 110.

[0097] The substrate 110 has the same conductivity type as the drift layer 120, both being the first conductivity type, and the doping concentration of the substrate 110 is higher than that of the drift layer 120.

[0098] In some embodiments, the doping concentration of the drift layer 120 is, for example, 5 × 10⁻⁶. 15 ~1.2×10 16 cm -3 .

[0099] Step S20: A first epitaxial layer of a first conductivity type is formed on the drift layer, and a first region of the first epitaxial layer is doped to form a shielding region of a second conductivity type. The undoped first epitaxial layer is the first doped region.

[0100] In this step, an epitaxial growth process is used to form a first epitaxial layer 101 on the first surface of the drift layer 120, such as... Figure 5a As shown.

[0101] The first epitaxial layer 101 is of the first conductivity type, and its doping concentration is higher than that of the drift layer 120 but lower than that of the substrate 110, so as to balance the breakdown voltage and the on-resistance.

[0102] In some embodiments, the thickness H3 of the first epitaxial layer 101 is less than the thickness H2 of the drift layer 120.

[0103] In some embodiments, the thickness H3 of the first epitaxial layer 101 is less than the thickness H1 of the substrate 110.

[0104] After forming the first epitaxial layer 101, a patterned mask layer is formed on the first surface of the first epitaxial layer 101. Then, an ion implantation process is performed on the first region of the first epitaxial layer 101 via the mask layer to dope and form a shielding region 152 of a second conductivity type in the first region of the first epitaxial layer 101. The mask layer is then removed. Figure 5b As shown.

[0105] In this embodiment, the first region of the first epitaxial layer 101 corresponds to the shielding region 152, the first regions are spaced apart along the second direction and extend along the first direction.

[0106] The shielding region 152 extends from the first surface of the first epitaxial layer 101 to the second surface, such that the second surface of the shielding region 152 is adjacent to the first surface of the drift layer 120.

[0107] Shielding zones 152 are arranged at intervals along the second direction, such as... Figure 5b As shown in (2) above, and the shielding area 152 extends along the first direction, as shown in (2) above. Figure 5b As shown in (1) of the table.

[0108] In this embodiment, the region of the first epitaxial layer 101 covered by the mask layer retains the first conductivity type after ion implantation, serving as the first doped region 143a.

[0109] In some embodiments, the doping concentration of the shielding region 152 of the second conductivity type is, for example, 1 × 10⁻⁶. 18 ~3×10 18 cm -3 The doping concentration of the first doped region 143a of the first conductivity type is, for example, 1 × 10⁻⁶. 17 ~5×10 17 cm -3 .

[0110] In some embodiments, since the first epitaxial layer 101 located on the surface of the semiconductor structure in this step is directly ion implanted to form a shielding region 152, the ion implantation depth is significantly reduced compared to the ion implantation depth in conventional methods, thereby the ion implantation energy can also be significantly reduced.

[0111] In some embodiments, the shielding region 152 requires an ion implantation depth of more than 1 μm and an ion implantation energy of more than 1 MeV in conventional methods; however, in this application, the shielding region 152 requires an ion implantation depth of 0.2~0.4 μm and an energy of only 30~220 keV.

[0112] Step S30: A second epitaxial layer of a first conductivity type is formed on the first epitaxial layer. A first region of the second epitaxial layer is doped to form a first contact region of a second conductivity type. The undoped second epitaxial layer is the second doped region.

[0113] In this step, an epitaxial growth process is used to form a second epitaxial layer 102 on the first surface of the first epitaxial layer 101, such as... Figure 5c As shown.

[0114] The second epitaxial layer 102 is of the first conductivity type, and its doping concentration is the same as that of the first epitaxial layer 101.

[0115] In some embodiments, the thickness H4 of the second epitaxial layer 102 is greater than the thickness H3 of the first epitaxial layer 101.

[0116] After forming the second epitaxial layer 102, a patterned mask layer is formed on the first surface of the second epitaxial layer 102. Then, an ion implantation process is performed via the mask layer in the first region of the second epitaxial layer 102 to dope and form a first contact region 151a of a second conductivity type in the first region of the second epitaxial layer 102. Subsequently, the mask layer is removed. Figure 5d As shown.

[0117] In this embodiment, the first regions of the second epitaxial layer 102 are arranged at intervals along the first direction and extend along the second direction.

[0118] The first contact area 151a extends from the first surface of the second epitaxial layer 102 to its second surface, such that the second surface of the first contact area 151a is adjacent to the first surface of the shielding area 152.

[0119] In this process, the region of the second epitaxial layer 102 covered by the mask layer retains the first conductivity type after ion implantation and serves as the second doped region 143b. The second doped region 143b is connected to the first doped region 143a, and the two together serve as the doped region 143.

[0120] In some embodiments, the ion implantation energy for forming the shielding region 152 is less than the ion implantation energy for forming the first contact region 151a. The doping concentration of the first contact region 151a of the second conductivity type is, for example, 1 × 10⁻⁶. 18 ~5×10 18 cm -3 The doping concentration of the second doped region 143b of the first conductivity type is, for example, 1 × 10⁻⁶. 17 ~5×10 17 cm -3 .

[0121] In some embodiments, the first doped region 143a and the second doped region 143b have the same doping concentration and are combined to form a doped region 143 with a doping concentration greater than that of the drift layer 120.

[0122] In some embodiments, the first doped region 143a and the second doped region 143 have the same doping concentration, and the doping concentration is the same as that of the drift region 120, and together they form a part of the drift region 120.

[0123] Step S40: A third epitaxial layer of the second conductivity type is formed on the second epitaxial layer. The first region of the third epitaxial layer is doped to form a second contact region of the second conductivity type. The second region of the third epitaxial layer is doped to form a source region of the first conductivity type. The undoped third epitaxial layer is the body region.

[0124] In this step, an epitaxial growth process is used to form a third epitaxial layer 103 on the first surface of the second epitaxial layer 102, such as... Figure 5e As shown.

[0125] The third epitaxial layer 103 is of the second conductivity type, and its doping concentration is lower than that of the shielding region 152 and the first contact region 151a.

[0126] In some embodiments, the thickness H5 of the third epitaxial layer 103 is greater than the thickness H4 of the second epitaxial layer 102 to ensure that the source region 141 and the body region 142 have sufficient junction depth and doping gradient.

[0127] After forming the third epitaxial layer 103, a patterned first mask layer is formed on the first surface of the third epitaxial layer 103. No first mask layer is formed in the first region. Then, an ion implantation process is performed on the third epitaxial layer 103 via the first mask layer to form a second contact region 151b of a second conductivity type in the first region of the third epitaxial layer 103. Subsequently, the first mask layer is removed. Figure 5f As shown.

[0128] The second contact area 151b extends from the first surface of the third epitaxial layer 103 to its second surface, and the second surface of the second contact area 151b is adjacent to the first surface of the first contact area 151a.

[0129] The second contact area 151b is electrically connected to the first contact area 151a, and the dimension D11 of the first contact area 151a along the first direction is equal to the dimension D12 of the second contact area 151b along the first direction. The sidewalls of the two are located on the same vertical plane, so the first contact area 151a and the second contact area 151b together constitute the contact area 151 of a continuous low-resistance path.

[0130] After forming the second contact region 151b, a patterned second mask layer is formed on the first surface of the third epitaxial layer 103. No second mask layer is formed in the second region. An ion implantation process is performed on the third epitaxial layer 103 via the second mask layer to form a source region 141 of a first conductivity type in the second region of the third epitaxial layer 103. Then, the second mask layer is removed. Figure 5g As shown.

[0131] In this embodiment, the first surface of the third epitaxial layer 103 includes a first region and a second region. The first region corresponds to the second contact region 151b, and the second region corresponds to the source region 141. Thus, after the formation of the first mask layer, the third epitaxial layer 103 is ion implanted to form the second contact region 151b in the first region, and after the formation of the second mask layer, the third epitaxial layer 103 is ion implanted to form the source region 141 in the second region.

[0132] Furthermore, the ion implantation energy for forming the second contact region 151b is greater than the ion implantation energy for forming the source region 141, and the ion implantation energy for forming the shielding region 152 is less than the ion implantation energy for forming the second contact region 151b.

[0133] The source region 141 extends from the first surface of the third epitaxial layer 103 to the second surface to a certain depth, but does not penetrate the entire third epitaxial layer 103. The second surface of the source region 141 is located inside the third epitaxial layer 103.

[0134] The region of the third epitaxial layer 103 that is not implanted with ions is designated as the body region 142. The source region 141, the body region 142, and the doped region 143 are located between two adjacent contact regions 151.

[0135] In some embodiments, the doping concentration of the second contact region 151b of the second conductivity type is, for example, 1 × 10⁻⁶. 18 ~5×10 18 cm -3 The doping concentration of the source region 141 of the first conductivity type is, for example, 5 × 10⁻⁶. 18 ~2×10 19 cm -3 The doping concentration of the body region 142 of the second conductivity type is 1 × 10⁻⁶. 17 ~1×10 18 cm -3 .

[0136] In this embodiment, the contact region 151 is divided into a first contact region 151a and a second contact region 151b, which significantly reduces the depth of ion implantation in a single operation. In some embodiments, the maximum depth of the complete contact region 151 exceeds 0.8 μm, and the energy required for ion implantation is 700-1100 keV. However, in this application, after dividing the contact region into a first contact region 151a and a second contact region 151b, the maximum depth does not exceed 0.4 μm, and the ion implantation energy is significantly reduced to 200-300 keV.

[0137] In this embodiment, the source region 141 requires an ion implantation energy of 30~220 keV. The body region 142 is formed by epitaxially growing a third epitaxial layer 103, which does not require additional ion implantation, resulting in better doping uniformity, more uniform doping concentration in both depth and width directions, no obvious concentration gradient, and more precise control over the depth of the body region 142, leading to better channel quality.

[0138] Step S50: Etch to form trenches and form a trench gate structure in the trenches.

[0139] In this step, a patterned mask layer is formed on the first surface of the third epitaxial layer 103, and then an etching process is performed through the mask layer, for example, dry etching is used to form a trench that penetrates the source region 141, the body region 142, and part of the doped region 143. Then, a gate dielectric layer 131 and a gate conductor 132 are sequentially deposited in the trench to form a complete trench gate structure 130. Figure 5h As shown.

[0140] The bottom of the trench gate structure 130 is located within the doped region 143 and is completely isolated from the shielding region 152 by the doped region 143, ensuring that the gate electric field is not directly coupled to the shielding region 152.

[0141] Step S60: Form an interlayer dielectric layer, a source metal layer, and a drain metal layer.

[0142] In this step, a deposition process, such as chemical vapor deposition (CVD) or physical vapor deposition (PVD), is used to form an interlayer dielectric layer 161 on the first surface of the trench gate structure 130. Then, a source metal layer 162 is formed on the contact region 151, the source region 141, and the first surface of the interlayer dielectric layer 161 using a deposition process. Finally, a drain metal layer 163 is formed on the second surface of the substrate 110 using a deposition process. Figure 5i As shown.

[0143] The interlayer dielectric layer 161 completely covers the top of the trench gate structure 130 and can also cover part of the source region 141 near the first surface area of ​​the trench gate structure 130 to achieve electrical isolation between the gate and the source.

[0144] Figures 6a to 6c A schematic diagram of a semiconductor device according to a second embodiment of this application is shown. Compared with the first embodiment, the first contact regions 151a of the semiconductor device in the second embodiment are spaced apart. The similarities with the first embodiment will not be repeated here, only the differences will be described.

[0145] in, Figure 6b For example, along Figure 6a The cross-sectional view obtained by the dashed line GG. Figure 6c For example, along Figure 6aThe cross-sectional view obtained by the dashed line HH.

[0146] like Figure 6a As shown, at least a portion of the bottom surface of the contact area 151 has the same depth as the bottom surface of the body area 142. Specifically, the contact area 151 includes a first contact area 151a and a second contact area 151b.

[0147] The first contact region 151a includes multiple regions, and is located above the shielding region 152 and between the body region 142. The first contact region 151a is separated from the trench gate structure 130 by a doped region 143. The first contact regions 151a are spaced apart along both the first and second directions to form an array structure, such as... Figure 6c As shown.

[0148] The second contact area 151b is located between adjacent trench gate structures 130, and the sidewall of the body region 142 away from the trench gate structure 130 is adjacent to the second contact area 151b. The source region 141 is located on the body region 142, and the sidewall of the source region 141 away from the trench gate structure 130 is adjacent to the second contact area 151b. Thus, the sidewall of the second contact area 151b is adjacent to the sidewalls of the source region 141 and the body region 142 in sequence.

[0149] The second contact area 151b is located on the first contact area 151a. At least a portion of the second surface of the second contact area 151b is adjacent to the first surface of the first contact area 151a, so that the first contact area 151a and the second contact area 151b together form a channel for realizing the electrical connection between the source metal layer 162 and the shielding area 152.

[0150] In some embodiments, along a first direction, the size D11 of the first contact area 151a is equal to the size D12 of the second contact area 151b, referenced. Figure 5f .

[0151] In some embodiments, along the first direction, the size D11 of the first contact area 151a is larger than the size D12 of the second contact area 151b, but smaller than the distance between the sidewalls of two adjacent trench grid structures 130, so that the first contact area 151a does not directly contact the trench grid structure 130.

[0152] In some embodiments, along the first direction, the size D11 of the first contact area 151a is smaller than the size D12 of the second contact area 151b.

[0153] In step S30 of the semiconductor device manufacturing method, a second epitaxial layer of a first conductivity type is formed on a first epitaxial layer, a first region of the second epitaxial layer is doped to form a first contact region of a second conductivity type, and the undoped second epitaxial layer is a second doped region. In this step, the first region of the second epitaxial layer 102 is arranged at intervals along a first direction and a second direction to form an array structure.

[0154] Figures 7a to 7c A schematic diagram of a semiconductor device according to a third embodiment of this application is shown.

[0155] Compared to the first embodiment, the contact region 151 of the semiconductor device in the third embodiment further includes a third contact region 151c. The similarities with the first embodiment will not be repeated here; only the differences will be described.

[0156] in, Figure 7b For example, along Figure 7a The cross-sectional view obtained by the dashed line II. Figure 7c For example, along Figure 7b The cross-sectional view obtained by the dashed line J.

[0157] like Figure 7a As shown, at least a portion of the bottom surface of the contact area 151 has the same depth as the bottom surface of the shielding area 152. Specifically, the contact area 151 includes a first contact area 151a, a second contact area 151b, and a third contact area 151c.

[0158] The first contact region 151a is located above the shielding region 152 and between the body region 142, and the first contact region 151a is separated from the trench gate structure 130 by a doped region 143. The first contact regions 151a are spaced apart along a first direction and extend along a second direction, as shown in the reference. Figure 3b As shown.

[0159] The second contact area 151b is located between adjacent trench gate structures 130, and the sidewall of the body region 142 away from the trench gate structure 130 is adjacent to the second contact area 151b. The source region 141 is located on the body region 142, and the sidewall of the source region 141 away from the trench gate structure 130 is adjacent to the second contact area 151b. Thus, the sidewall of the second contact area 151b is adjacent to the sidewalls of the source region 141 and the body region 142 in sequence.

[0160] The second contact area 151b is located on the first contact area 151a, and the second surface of the second contact area 151b is adjacent to the first surface of the first contact area 151a. Thus, the first contact area 151a and the second contact area 151b together form a channel for realizing the electrical connection between the source metal layer 162 and the shielding area 152.

[0161] In some embodiments, along a first direction, the size D11 of the first contact area 151a is equal to the size D12 of the second contact area 151b, referenced. Figure 5f .

[0162] In some embodiments, along the first direction, the size D11 of the first contact area 151a is larger than the size D12 of the second contact area 151b, but smaller than the distance between the sidewalls of two adjacent trench grid structures 130, so that the first contact area 151a does not directly contact the trench grid structure 130.

[0163] In some embodiments, along the first direction, the size D11 of the first contact area 151a is smaller than the size D12 of the second contact area 151b.

[0164] Multiple third contact regions 151c are included and located between adjacent shielding regions 152. Adjacent third contact regions 151c are separated by doped regions 143 or shielding regions 152. The third contact regions 151c are spaced apart along the first and second directions, thus forming an array structure, such as... Figure 7b and Figure 7c As shown.

[0165] In some embodiments, along the first direction, the size D13 of the third contact area 151c is greater than or equal to the size D11 of the first contact area 151a.

[0166] In step S20 of the semiconductor device manufacturing method, in the steps of forming a first epitaxial layer of a first conductivity type on a drift layer, doping a first region of the first epitaxial layer to form a shielding region of a second conductivity type, and the undoped first epitaxial layer being a first doped region, the method further includes: doping a second region of the first epitaxial layer to form a third contact region.

[0167] In this embodiment, the second region of the first epitaxial layer 101 is distributed at intervals along the first direction and the second direction, thereby forming an array structure.

[0168] As described above, these embodiments of the present application do not exhaustively cover all details, nor do they limit the invention to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the present application, thereby enabling those skilled in the art to make good use of the present application and modifications based on it. The present application is limited only by the claims and their full scope and equivalents.

Claims

1. A semiconductor device, wherein, It includes multiple cellular units, wherein the cellular units include: Drift layer of the first conductivity type; A trench grid structure extends into the drift layer; The source region of the first conductivity type is located above the drift layer, on both sides of the trench gate structure, and adjacent to the sidewall of the trench gate structure; The second conductivity type of body region is located between the source region and the drift layer, and on both sides of the trench gate structure and adjacent to the sidewall of the trench gate structure; The contact area of ​​the second conductivity type is located on both sides of the trench gate structure and is adjacent to the side of the source region and the body region away from the trench gate structure. At least a portion of the contact area extends along the depth direction of the trench gate structure below the bottom surface of the trench gate structure. The shielding area of ​​the second conductivity type is located below the contact areas on both sides and adjacent to the bottom of the contact areas, and the upper surface of the shielding area is located below the bottom of the trench grid structure; The shielding areas are arranged at intervals along the second direction, and at least a portion of the shielding areas form a beam-like structure with two sides connected below the bottom of the trench grid structure.

2. The semiconductor device according to claim 1, wherein, The cellular unit also includes: A doped region of a first conductivity type is located between the body region and the drift layer, and between the contact region and the shielding region, wherein the doping concentration of the doped region is greater than the doping concentration of the drift layer.

3. The semiconductor device according to claim 1, wherein, At least a portion of the bottom surface of the contact area has the same depth as the bottom or top surface of the shielding area.

4. The semiconductor device according to claim 1, wherein, At least a portion of the bottom surface of the contact area has the same depth as the bottom surface of the body area.

5. The semiconductor device according to claim 1, wherein, The shielding area and the projection of the trench grid structure onto the XY plane are perpendicular to each other.

6. The semiconductor device according to any one of claims 1-5, wherein, Along the second direction, the width of the shielding area is less than or equal to the interval between two adjacent shielding areas.

7. The semiconductor device according to claim 6, wherein, Along the second direction, the ratio of the width of the shielding area to the interval between two adjacent shielding areas is greater than or equal to 1 / 5 and less than or equal to 1.

8. The semiconductor device according to any one of claims 1-5, wherein, The doping concentration is the same in the contact area and the shielding area.

9. A method for manufacturing a semiconductor device, wherein, include: A substrate is provided, and a drift layer of a first conductivity type is formed on the substrate; A first epitaxial layer of a first conductivity type is formed on the drift layer, and a first region of the first epitaxial layer is doped to form a shielding region of a second conductivity type. The undoped first epitaxial layer is the first doped region. A second epitaxial layer of a first conductivity type is formed on the first epitaxial layer, and a first region of the second epitaxial layer is doped to form a first contact region of a second conductivity type. The undoped second epitaxial layer is a second doped region. A third epitaxial layer of a second conductivity type is formed on the second epitaxial layer. A first region of the third epitaxial layer is doped to form a second contact region of the second conductivity type. A second region of the third epitaxial layer is doped to form a source region of the first conductivity type. The undoped third epitaxial layer is the body region. Forming a trench gate structure, an interlayer dielectric layer, and a source metal layer; The shielding areas are arranged at intervals along the second direction, and at least a portion of the shielding areas form a beam-like structure with two sides connected below the bottom of the trench grid structure.

10. The manufacturing method according to claim 9, wherein, The first doped region and the second doped region have the same doping concentration, and together they form a doped region with a doping concentration greater than that of the drift layer; or The first doped region and the second doped region have the same doping concentration, and their doping concentrations are the same as those of the drift region, together forming a part of the drift region.

11. The manufacturing method according to claim 9, wherein, The steps of forming the shielding region and the first doped region also include: The second region of the first epitaxial layer is doped to form a third contact region of a second conductivity type, the third contact regions being spaced between adjacent shielding regions.

12. The manufacturing method according to any one of claims 9-11, wherein, The steps for forming the second contact region, source region, and volume region include: A first mask layer is formed on the third epitaxial layer, but no first mask layer is formed in the first region. Ion implantation is performed on the third epitaxial layer through the first mask layer to form a second contact region of the second conductivity type. Remove the first mask layer; A second mask layer is formed on the third epitaxial layer. No second mask layer is formed in the second region. Ion implantation is performed on the third epitaxial layer through the second mask layer to form a source region of a first conductivity type. The source region extends from the first surface of the third epitaxial layer to the second surface. The second surface of the source region is located in the third epitaxial layer. The region of the third epitaxial layer that is not ion implanted is the bulk region. Remove the mask layer. The first region of the third epitaxial layer corresponds to the second contact region, the second region corresponds to the source region, and the second contact region is connected to the first contact region.

13. The manufacturing method according to claim 12, wherein, The ion implantation energy for forming the second contact region is greater than the ion implantation energy for forming the source region.

14. The manufacturing method according to claim 12, wherein, The first region of the second epitaxial layer is doped by ion implantation to form a first contact region of the second conductivity type; The first region of the first epitaxial layer is doped by ion implantation to form a shielding region of the second conductivity type; The ion implantation energy for forming the shielding region is less than the energy for forming the first contact region.

15. The manufacturing method according to claim 14, wherein, The ion implantation energy for forming the shielding region is less than the ion implantation energy for forming the second contact region.

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