A semiconductor device and a method of fabricating the same

Abstract

The application provides a semiconductor device and a preparation method thereof. The semiconductor device comprises a substrate, an epitaxial layer, a front trench, a first dielectric layer, a shielding gate, an interlayer oxide layer, a gate dielectric layer, a polysilicon gate, a body region, a source region, an interlayer dielectric layer, a gate metal layer, a back trench and a stress balancing layer. The back trench is located on a second surface of the substrate, and the stress balancing layer is located on the sidewall of the back trench. The stress balancing layer on the sidewall introduces a controlled compressive stress on the back of the substrate, effectively offsets the stress generated when the deep trench process is performed on the first surface of the substrate and the trench gate is formed, significantly reduces the warping of the wafer, and makes the drain metal layer directly contact with the substrate, thereby ensuring that the on-resistance of the device is not affected. In addition, the integrated drain metal layer increases the cross-sectional area and improves the heat dissipation capacity of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit manufacturing technology, and in particular to a semiconductor device and its fabrication method. Background Technology

[0002] Shielded gate transistors (SMTs), a crucial component of power semiconductors, are primarily used for frequency conversion, voltage transformation, rectification, power conversion, and management in power electronic equipment. They are widely applied in new energy vehicles, charging piles, photovoltaic inverters, and data centers. With the transition of the wafer industry to 12-inch production lines, wafer warpage during SMT fabrication has become increasingly prominent, representing a core bottleneck restricting capacity expansion and yield improvement.

[0003] To improve the power density and reliability of shielded gate transistors (SGTs), the traditional SGT fabrication process involves etching deep trenches in the epitaxial layer on the front side of the substrate and then depositing high-temperature deposition within these trenches to form a trench gate structure. This trench gate structure, from bottom to top, includes a field oxide layer, source shielding polysilicon, an isolation layer, and a gate polysilicon layer. Due to the thermal expansion coefficient mismatch between the dielectric materials forming the field oxide layer and the isolation layer and the monocrystalline silicon substrate, significant residual tensile stress is introduced into the trench sidewalls, bottom, and back of the wafer during subsequent cooling, ultimately causing wafer warpage. Furthermore, as the wafer size increases, this wafer warpage effect is further amplified, severely impacting the yield and reliability of subsequent packaging and mounting processes.

[0004] Those skilled in the art have attempted to improve stress-induced wafer warpage by adjusting the thickness of the field oxide layer, etc. However, while reducing the thickness of the field oxide layer can reduce stress to some extent, it affects the device's breakdown voltage characteristics and gate-drain capacitance control. Furthermore, patent CN116110804A mentions forming a back trench on the back side of the substrate and simultaneously forming silicon oxide films on the back side of the substrate, the top, sidewalls, and the bottom of the back trench. This achieves stress offset against the compressive stress of the silicon oxide film on the sidewalls of the front trench, alleviating the severe saddle-shaped warpage caused by the mismatch between the compressive stress generated by the silicon oxide film on the sidewalls of the front trench and the compressive stress generated by the silicon oxide film on the back side of the substrate. However, the silicon oxide film at the bottom of the back trench and on the back surface prevents the drain metal from making direct contact with the substrate silicon, introducing additional contact resistance and affecting the resistance between the drain and source in the on-state. Moreover, the silicon oxide film at the bottom of the back trench and on the back surface also reduces the device's heat dissipation capacity.

[0005] Therefore, how to effectively suppress stress-induced wafer warpage in deep trench processes for large-size wafers without affecting the on-resistance and heat dissipation capacity of the devices has become a technical problem that urgently needs to be solved in the field of shielded gate transistor manufacturing. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a semiconductor device and its fabrication method, which improves wafer warpage, increases wafer heat dissipation capacity, and reduces device on-resistance.

[0007] To achieve the above and other related objectives, the present invention provides a semiconductor device comprising:

[0008] A substrate having a first surface and a second surface disposed opposite to each other, and an epitaxial layer disposed on the first surface of the substrate;

[0009] Multiple front-side device structures are located in the epitaxial layer;

[0010] Multiple trench structures, each trench structure including a back trench and a stress balancing layer, wherein the back trench extends from a second surface of the substrate toward the interior of the substrate, and the stress balancing layer is located on the sidewall of the back trench;

[0011] A drain metal layer covers the second surface of the substrate and completely fills the back trench, and forms an electrical connection with the bottom of the back trench and the second surface of the substrate.

[0012] Optionally, the cross-sectional shape of the back groove can be any one of a rectangle, trapezoid, or U-shape.

[0013] Optionally, the depth of the back groove is 15μm to 30μm.

[0014] Optionally, the width of the back groove is 15μm to 30μm.

[0015] Optionally, the stress balancing layer is any one of a silicon oxide layer, a silicon nitride layer, or a silicon oxide / silicon nitride composite layer.

[0016] Optionally, the thickness of the stress balancing layer is 10 nm to 5000 nm.

[0017] Optionally, the drain metal layer is a single metal layer structure or a multilayer metal stack structure.

[0018] Optionally, the front-side device structure includes multiple shielding trench gate structures, wherein each of the shielding trench gate structures includes:

[0019] A front trench is located in the epitaxial layer and extends along the direction of the epitaxial layer toward the substrate;

[0020] Both the shielding gate and the polysilicon gate are located in the front trench, and the shielding gate is located directly below the polysilicon gate;

[0021] An interlayer oxide layer is located between the shielding gate and the polysilicon gate;

[0022] A first dielectric layer is located at the bottom of the front trench and between the inner wall of the front trench and the outer wall of the shielding gate, and the top surface of the first dielectric layer is flush with the upper surface of the shielding gate.

[0023] A gate dielectric layer is located between the inner wall of the front trench and the outer wall of the polysilicon gate, and the top surface of the gate dielectric layer is flush with the upper surface of the polysilicon gate.

[0024] Optionally, a second conductivity type body region is located on the upper surface of the epitaxial layer and adjacent to the sidewall of the front trench, and the bottom surface of the body region is not lower than the lower surface of the polysilicon gate.

[0025] A first conductivity type source region is located on the upper surface of the body region and the bottom surface of the source region is lower than the upper surface of the polysilicon gate.

[0026] An interlayer dielectric layer is located on the upper surface of the epitaxial layer, and the interlayer dielectric layer has a plurality of gate vias that penetrate the interlayer dielectric layer and expose the polysilicon gate at the bottom.

[0027] A gate metal layer is located on the interlayer dielectric layer and fills the gate via.

[0028] This invention also provides a method for fabricating a semiconductor device, comprising the following steps:

[0029] A substrate is provided, the substrate having a first surface and a second surface disposed opposite to each other;

[0030] An epitaxial layer is formed on the first surface of the substrate;

[0031] Multiple front-side device structures are formed in the epitaxial layer;

[0032] The substrate is flipped over, and photolithography and etching processes are performed on the second surface of the substrate to form a back trench, which extends from the second surface of the substrate into the interior of the substrate.

[0033] A stress balancing layer is formed on the sidewalls, bottom, and second surface of the substrate of the back trench, and the stress balancing layer on the second surface of the substrate and the bottom of the back trench is removed.

[0034] A drain metal layer is formed by depositing metal on the second surface of the substrate, wherein the drain metal layer fills the back trench and forms an electrical connection with the second surface of the substrate and the substrate exposed at the bottom of the back trench.

[0035] Optionally, the stress balancing layer is any one of a silicon oxide layer, a silicon nitride layer, or a silicon oxide / silicon nitride composite layer.

[0036] Optionally, the thickness of the stress balancing layer is 10 nm to 5000 nm.

[0037] Optionally, the step of forming the front device structure includes: etching from the surface of the epitaxial layer into the interior of the epitaxial layer to form a plurality of parallel front trenches;

[0038] A first dielectric layer is formed on the sidewalls and bottom wall of the front trench, and polysilicon is deposited in the front trench to form a shielding gate;

[0039] An interlayer oxide layer is formed on the surface of the shielding gate and the first dielectric layer;

[0040] A gate dielectric layer is formed on the sidewall of the front trench, and a polysilicon gate is formed in the front trench;

[0041] Ion implantation of a second conductivity type is performed on the upper surface of the epitaxial layer to form a bulk region;

[0042] Ion implantation of a first conductivity type is performed on the upper surface of the body region to form a source region. Attached Figure Description

[0043] Figure 1 The diagram shown is a cross-sectional view of the semiconductor device 100 of the present invention.

[0044] Figure 2 The diagram shown is a process flow diagram of the semiconductor device fabrication method 200 of the present invention.

[0045] Figures 3 to 15 The diagram shows a cross-sectional structure of each step in the semiconductor device fabrication method 200 of the present invention.

[0046] Component designation explanation

[0047] 10. Substrate; 11. Epitaxial layer; 12. Front trench; 13. First dielectric layer; 14. Shielding gate; 15. Interlayer oxide layer; 16. Gate dielectric layer; 17. Polysilicon gate; 18. Body region; 19. Source region; 20. Interlayer dielectric layer; 22. Gate metal layer; 23. Back trench; 24. Stress balancing layer; 25. Drain metal layer; S1~S6, Steps. Detailed Implementation

[0048] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

[0049] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0050] Please see Figures 1 to 15 It should be understood that the structures, proportions, sizes, etc., illustrated in the accompanying drawings are merely for illustrative purposes to aid those skilled in the art and to facilitate understanding. They are not intended to limit the scope of the invention and therefore have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effectiveness and purpose of the invention, should still fall within the scope of the technical content disclosed herein. Furthermore, the terms "upper," "lower," "left," "right," "middle," "first," and "second," etc., used in this specification are merely for clarity and not intended to limit the scope of the invention. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of the invention.

[0051] This embodiment provides a semiconductor device 100. For example... Figure 1 As shown, the semiconductor device 100 includes: a substrate 10 having a first surface and a second surface disposed opposite to each other, and an epitaxial layer 11 disposed on the first surface of the substrate 10; a plurality of front-side device structures located in the epitaxial layer 11; a plurality of trench structures, each trench structure including a back trench 23 and a stress balancing layer 24, wherein the back trench 23 extends from the second surface of the substrate 10 toward the interior of the substrate 10, and the stress balancing layer 24 is located on the sidewall of the back trench 23; and a drain metal layer 25 covering the second surface of the substrate 10 and completely filling the back trench 23, and forming an electrical connection with the bottom of the back trench 23 and the second surface of the substrate 10.

[0052] In this embodiment, the semiconductor device introduces a back trench 23 on the second surface of the substrate 10 and deposits silicon oxide or silicon nitride on the sidewalls of the back trench 23 to form stress balancing layers 24 of different thicknesses. This introduces controlled compressive stress on the second surface of the substrate 10, effectively offsetting the stress generated when forming the front device structure by performing a deep trench process on the epitaxial layer 11. This significantly reduces wafer warpage, and the formed drain metal layer 25 further enhances the heat dissipation capability of the semiconductor device.

[0053] It should be noted here that, as Figure 1 and the following Figures 3-15The diagram shows only a partial repeating unit of the formed semiconductor device. The actual semiconductor device consists of several partial repeating units as shown in the diagram.

[0054] Specifically, in this embodiment, the substrate 10 is a first conductivity type doped substrate 10, and an epitaxial layer 11 of the first conductivity type is formed on the first surface of the substrate 10. The substrate 10 is heavily doped, and the epitaxial layer 11 is lightly doped. The material of the substrate 10 includes silicon, germanium silicon, silicon carbide, gallium nitride, or other suitable semiconductor materials.

[0055] As an example, the cross-sectional shape of the back groove 23 is any one of rectangle, trapezoid or U-shape, and the number of the back grooves 23 is one or more.

[0056] Specifically, in this embodiment, there are multiple back grooves 23, which are placed at intervals, and the spacing between any two adjacent back grooves 23 is variable. That is, the spacing between any two adjacent back grooves 23 can be the same or different. The cross-sectional shape of the back groove 23 includes rectangular, trapezoidal or U-shaped. Of course, under the premise of meeting the performance of the semiconductor device, the shape and number of back grooves 23 can be selected according to the actual situation, and are not limited here.

[0057] As an example, the depth H of the back groove 23 is 15~30μm, and the width D of the back groove 23 is 15~30μm.

[0058] Specifically, in this embodiment, the depth H of the back trench 23 is 15~30μm, where the depth H refers to the length of the back trench 23 extending from the second surface of the substrate 10 into the interior of the substrate 10, and the width D of the back trench 23 is 15~30μm, where the width D refers to the longest distance of the back trench 23 in the transverse direction along the cross-sectional structure.

[0059] As an example, the stress balancing layer 24 is any one of a silicon oxide layer, a silicon nitride layer, or a silicon oxide / silicon nitride composite layer.

[0060] Specifically, in this embodiment, a stress balancing layer 24 is provided on the sidewall of each back trench 23. The stress balancing layer 24 is any one of a silicon oxide layer, a silicon nitride layer, or a silicon oxide / silicon nitride composite layer. The thickness of the stress balancing layer 24 is 10~5000nm. The stress balancing layer 24 is used to introduce controlled compressive stress, thereby offsetting the stress generated when forming the front device structure and reducing wafer warpage.

[0061] As an example, the drain metal layer 25 is a single metal layer structure or a stacked structure formed by multiple metal layers.

[0062] Specifically, in this embodiment, the drain metal layer 25 is a multilayer metal stacked structure, and the drain metal layer 25 forms an ohmic contact with the substrate 10 exposed at the bottom of the back trench 23 and the second surface of the substrate 10 to achieve electrical connection.

[0063] Specifically, the material of the drain metal layer 25 includes titanium, titanium nitride, silver, gold, copper, aluminum, tungsten, or other suitable conductive materials.

[0064] In another embodiment of the present invention, the front-side device structure includes a plurality of shielding trench gate structures, wherein each shielding trench gate structure includes: a front-side trench 12 located in the epitaxial layer 11 and extending in the direction of the epitaxial layer 11 toward the substrate 10; a shielding gate 14 and a polysilicon gate 17, both located in the front-side trench 12, and the shielding gate 14 being located directly below the polysilicon gate 17; an interlayer oxide layer 15 located between the shielding gate 14 and the polysilicon gate 17; a first dielectric layer 13 located at the bottom of the front-side trench 12 and between the inner wall of the front-side trench 12 and the outer wall of the shielding gate 14, and the top surface of the first dielectric layer 13 being flush with the upper surface of the shielding gate 14; and a gate dielectric layer 16 located between the inner wall of the front-side trench 12 and the outer wall of the polysilicon gate 17, and the top surface of the gate dielectric layer 16 being flush with the upper surface of the polysilicon gate 17.

[0065] In another embodiment of the present invention, the front-side device structure further includes: a second conductivity type body region 18, located on the upper surface of the epitaxial layer 11 and adjacent to the sidewall of the front-side trench 12, with the bottom surface of the body region 18 not lower than the lower surface of the polysilicon gate 17; a first conductivity type source region 19, located on the upper surface of the body region 18, with the bottom surface of the source region 19 lower than the upper surface of the polysilicon gate 17; an interlayer dielectric layer 20, located on the upper surface of the epitaxial layer 11, having a plurality of gate vias penetrating the interlayer dielectric layer 20 and exposing the polysilicon gate 17 at the bottom; and a gate metal layer 22, located on the interlayer dielectric layer 20 and filling the gate vias.

[0066] It should be noted that, in addition to the shielding trench gate structure described above, the front device structure in this embodiment can also be other ordinary trench gate structures, and there are no restrictions here.

[0067] Specifically, the body region 18 has a first conductivity type, and the source region 19 has a second conductivity type, wherein the first conductivity type is different from the second conductivity type. For example, the first conductivity type is P-type and the second conductivity type is N-type, or the first conductivity type is N-type and the second conductivity type is P-type.

[0068] This embodiment also provides a method 200 for fabricating a semiconductor device, used to fabricate the aforementioned semiconductor device 100. For example... Figure 2 As shown, the preparation method 200 includes the following steps:

[0069] S1: A substrate 10 is provided, the substrate 10 having a first surface and a second surface disposed opposite to each other.

[0070] S2: An epitaxial layer 11 is formed on the first surface of the substrate 10.

[0071] S3: Multiple front-side device structures are formed in the epitaxial layer 11.

[0072] S4: Flip the substrate 10 and perform photolithography and etching processes on the second surface of the substrate 10 to form a back trench 23, so that the back trench 23 extends from the second surface of the substrate 10 into the interior of the substrate 10.

[0073] S5: A stress balancing layer is formed on the sidewalls and bottom of the back trench 23 and the second surface of the substrate 10, and the stress balancing layer 24 on the second surface of the substrate 10 and the bottom of the back trench 23 is removed.

[0074] S6: Deposit metal on the second surface of the substrate 10 to form a drain metal layer 25, wherein the drain metal layer 25 fills the back trench 23 and forms an electrical connection with the second surface of the substrate 10 and the substrate 10 exposed at the bottom of the back trench 23.

[0075] In this embodiment, a deep silicon etching process is performed on the second surface of the substrate 10 to form multiple back trenches 23 on the second surface of the substrate 10. Silicon oxide or silicon nitride is deposited on the sidewalls of the back trenches 23 to form a stress balancing layer 24, thereby introducing controlled compressive stress on the second surface of the substrate 10. This effectively counteracts the stress generated when forming multiple front device structures, significantly reducing wafer warpage. Furthermore, the bottom of the back trenches 23 and the drain metal layer 25 on the second surface of the substrate 10 are in direct contact with the substrate 10, ensuring that the on-resistance of the device is not affected. The drain metal layer 25 directly fills the back trenches 23, which also improves the heat dissipation capability of the semiconductor device.

[0076] The method for fabricating the semiconductor device of this embodiment will now be described in detail with reference to the accompanying drawings.

[0077] like Figure 3 As shown, steps S1 and S2 are performed first, a substrate 10 is provided, the substrate 10 has a first surface and a second surface disposed opposite to each other, and an epitaxial layer 11 is formed on the first surface of the substrate 10.

[0078] Specifically, such as Figure 3 The diagram shows a cross-sectional view of the substrate 10. In this embodiment, the substrate 10 is a substrate of the first conductivity type. The substrate 10 has a first surface and a second surface disposed opposite to each other, and an epitaxial layer 11 of the first conductivity type is formed on the first surface of the substrate 10. The doping concentration of the substrate 10 and the epitaxial layer 11 decreases sequentially. While ensuring the performance of the semiconductor device, the thickness, size, doping concentration and shape of the substrate 10 and the epitaxial layer 11 can be selected according to the actual situation.

[0079] As a preferred example, the substrate 10 is an N+ type doped silicon substrate 10 or a silicon carbide substrate 10, and the epitaxial layer 11 is an N- type doped single-crystal silicon epitaxial layer 11. Before performing the epitaxial process, the substrate 10 is first cleaned, for example, by using a diluted acid solution to remove the native oxide layer on the surface of the substrate 10, followed by cleaning with deionized water, and finally drying.

[0080] like Figures 4 to 12 As shown, step S3 is then performed to form a plurality of front-side device structures in the epitaxial layer 11.

[0081] As a specific example, the steps of forming the front-side device structure include: etching from the surface of the epitaxial layer 11 into the interior of the epitaxial layer 11 to form a plurality of parallel front-side trenches 12; forming a first dielectric layer 13 on the sidewalls and bottom walls of the front-side trenches 12, and depositing polysilicon in the front-side trenches 12 to form a shielding gate 14, wherein the top surface of the first dielectric layer 13 is flush with the upper surface of the shielding gate 14; forming an interlayer oxide layer on the surfaces of the shielding gate 14 and the first dielectric layer 13; forming a gate dielectric layer 16 on the sidewalls of the front-side trenches 12, and forming a polysilicon gate 17 in the front-side trenches 12, wherein the top surface of the gate dielectric layer 16 is flush with the upper surface of the polysilicon gate 17.

[0082] Specifically, such as Figure 4 As shown, a patterned first mask (not shown) is first formed on the surface of the epitaxial layer 11; then, a deep silicon etching process is performed on the epitaxial layer 11 based on the patterned first mask to form a plurality of parallel front trenches 12 in the epitaxial layer 11. The deep silicon etching process includes dry etching, wet etching or other suitable methods.

[0083] Specifically, such as Figure 6 As shown, a first dielectric layer 13 and a shielding gate 14 are sequentially formed in the front trench 12. The first dielectric layer 13 can be a high-k dielectric layer, including but not limited to silicon oxide, silicon nitride, aluminum oxide or other suitable dielectric materials. The shielding gate 14 is made of polysilicon. The methods for forming the first dielectric layer 13 and the shielding gate 14 include thermal oxidation, chemical vapor deposition, physical vapor deposition or other suitable methods.

[0084] As a specific example, the steps for forming the first dielectric layer 13 and the shielding gate 14 are as follows: First, as Figure 5 As shown, a first dielectric layer 13 is formed covering the sidewalls and bottom wall of the front trench 12 and the surface of the epitaxial layer 11. Then, a polysilicon layer is deposited in the front trench 12 to form the shielding gate 14, as shown. Figure 6 As shown, the first dielectric layer 13 and the shielding gate 14 in the front trench 12 are etched and planarized so that the first dielectric layer 13 and the shielding gate 14 have flush surfaces. Specifically, while ensuring the performance of the semiconductor device, the height of the shielding gate 14 and the first dielectric layer 13 can be selected according to the actual situation, and is not limited here.

[0085] Specifically, the methods for etching and planarizing the first dielectric layer 13 and the shielding gate 14 include dry etching, wet etching, chemical mechanical polishing, or other suitable methods.

[0086] Specifically, such as Figure 7 As shown, after etching and planarizing the first dielectric layer 13 and the shielding gate 14, a dielectric material is deposited on the surface of the first dielectric layer 13 and the shielding gate 14 to form an interlayer oxide layer 15. The interlayer oxide layer 15 and the first dielectric layer 13 completely enclose the shielding gate 14. The method for forming the interlayer oxide layer 15 includes thermal oxidation, HDP process or other suitable methods.

[0087] Specifically, such as Figure 9 As shown, a gate dielectric layer 16 and a polysilicon gate 17 are formed in the front trench 12 above the first dielectric layer 13 and the shielding gate 14. The gate dielectric layer 16 can be a high-k dielectric layer, including but not limited to silicon oxide, silicon nitride, aluminum oxide or other suitable dielectric materials. The polysilicon gate 17 is a polysilicon layer. The methods for forming the gate dielectric layer 16 and the polysilicon gate 17 include thermal oxidation, chemical vapor deposition, physical vapor deposition or other suitable methods.

[0088] As a specific example, the steps for forming the gate dielectric layer 16 and the polysilicon gate 17 are as follows: First, as Figure 8 As shown, a gate dielectric layer 16 is formed covering the sidewalls of the front trench 12, the interlayer dielectric layer 20, and the surface of the epitaxial layer 11. Then, a polysilicon layer is deposited in the remaining front trench 12 in the middle of the gate dielectric layer 16 and on the surface of the epitaxial layer 11 to form the polysilicon gate 17. Figure 9 As shown, the gate dielectric layer 16 and the polysilicon gate 17 in the front trench 12 are subjected to anisotropic etching and the surfaces of the gate dielectric layer 16 and the polysilicon gate 17 are planarized so that the upper surface of the gate dielectric layer 16 is flush with the polysilicon gate 17, and finally multiple front device structures located in the epitaxial layer 11 are obtained.

[0089] Specifically, the planarization process for the gate dielectric layer 16 and the polysilicon gate 17 includes chemical mechanical polishing, dry etching, wet etching, or other suitable methods.

[0090] As a specific example, the steps of forming the front-side device structure further include: performing ion implantation of a second conductivity type on the upper surface of the epitaxial layer 11 to form a body region 18; performing ion implantation of a first conductivity type on the upper surface of the body region 18 to form a source region 19; forming an interlayer dielectric layer 20 on top of the source region 19, and etching the interlayer dielectric layer 20 to form a plurality of gate vias penetrating the interlayer dielectric layer 20 and exposing the polysilicon gate 17; depositing metal on the interlayer dielectric layer 20 to form a gate metal layer 22, and the gate metal layer 22 filling the gate vias.

[0091] Specifically, the method for forming the solid region 18 includes ion implantation and high-temperature annealing. For example, second conductivity type ion implantation is performed on the top of the epitaxial layer 11 on both sides of the front trench 12, followed by a high-temperature annealing process, such as... Figure 10 As shown, the top of the epitaxial layer 11 of the first conductivity type is inverted into a body region 18 of the second conductivity type. The body region 18 is insulated from the polysilicon gate 17 by the gate dielectric layer 16.

[0092] Specifically, the method for forming the source region 19 includes ion implantation and high-temperature annealing. For example, ion implantation of the first conductivity type is performed on the top of the body region 18 of the second conductivity type, followed by a high-temperature annealing process to invert the top of the body region 18 of the second conductivity type back into the source region 19 of the first conductivity type. Figure 11As shown, the source region 19 of the first conductivity type, the gate dielectric layer 16, and the upper surface of the polysilicon gate 17 are flush, and the source region 19 of the first conductivity type and the polysilicon gate 17 are insulated and isolated from each other through the gate dielectric layer 16.

[0093] Specifically, an interlayer dielectric layer 20 is formed on top of the source region 19 of the first conductivity type. The method for forming the interlayer dielectric layer 20 includes chemical vapor deposition, physical vapor deposition, or other suitable methods. The interlayer dielectric layer 20 includes one or a combination of silicon oxide layer, silicon nitride layer, and silicon phosphate glass layer.

[0094] Specifically, such as Figure 12 As shown, a patterned photoresist masking layer is formed on the upper surface of the interlayer dielectric layer 20. Based on the patterned second masking layer, the interlayer dielectric layer 20 and the polysilicon gate 17 are etched to form the gate via. The method for forming the gate via includes dry etching, wet etching, or other suitable methods. Preferably, this embodiment uses a dry etching process to etch the interlayer dielectric layer 20 and the polysilicon gate 17. Because dry etching has good anisotropy, it hardly increases the manufacturing cost. Figure 12 As shown, a gate metal layer 22 is formed by depositing metal on the interlayer dielectric layer 20, and the gate metal fills the gate via. The gate metal layer 22 is electrically connected to the polysilicon gate 17. The material forming the gate metal layer 22 includes titanium, silver, gold, copper, aluminum, tungsten, or other suitable conductive materials. The method for forming the gate metal layer 22 includes sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods.

[0095] like Figure 13 and Figure 14 As shown, steps S4 and S5 are then performed, the substrate 10 is flipped, and photolithography and etching processes are performed on the second surface of the substrate 10 to form a back trench 23, so that the back trench 23 extends from the second surface of the substrate 10 into the interior of the substrate 10; a stress balancing layer is formed on the sidewalls, bottom and second surface of the back trench 23 and the second surface of the substrate 10, and the stress balancing layer 24 on the second surface of the substrate 10 and the bottom of the back trench 23 is removed.

[0096] Specifically, such as Figure 13 As shown, the substrate 10 is flipped over, and an etching process is performed on the second surface of the substrate 10 to form a back trench 23, as shown. Figure 14As shown, a stress balance layer 24 is formed by a deposition process in the back trench 23, and the back trench 23 and the stress balance layer 24 form a plurality of trench structures.

[0097] As a preferred example, the steps of forming multiple trench structures include: forming a hard mask layer on the second surface of the substrate 10, spin-coating photoresist on the hard mask layer to form a photoresist mask, photolithographically patterning the photoresist mask to define a window region, performing a deep silicon etching process on the hard mask layer and the substrate 10 exposed in the window region to form a back trench 23, the back trench 23 extending from the second surface of the substrate 10 into the interior of the substrate 10, performing a thermal oxidation process or a CVD deposition process on the sidewalls, bottom, and second surface of the back trench 23 to form a stress balancing layer 24, and removing the stress balancing layer 24 from the second surface of the substrate 10 and the bottom of the back trench 23 by a dry etching process.

[0098] As an example, the cross-sectional shape of the back groove 23 is any one of rectangle, trapezoid or U-shape, and the number of the back grooves 23 is one or more.

[0099] Specifically, there are multiple back grooves 23, which are placed at intervals, and the spacing between any two adjacent back grooves 23 is variable. That is, the spacing between any two adjacent back grooves 23 can be the same or different. The cross-sectional shape of the back grooves 23 includes rectangular, trapezoidal or U-shaped. Of course, under the premise of meeting the performance of the semiconductor device, the shape and number of back grooves 23 can be selected according to the actual situation, and are not limited here.

[0100] As an example, the depth H of the back groove 23 is 15~30μm, and the width D of the back groove 23 is 15~30μm.

[0101] Specifically, in this embodiment, the depth H of the back trench 23 is 15~30μm, where the depth H refers to the length of the back trench 23 extending from the second surface of the substrate 10 into the interior of the substrate 10, and the width D of the back trench 23 is 15~30μm, where the width D refers to the longest distance of the back trench 23 in the transverse direction along the cross-sectional structure.

[0102] As an example, the thickness of the stress balancing layer 24 is 10~5000nm. The CTE difference between the stress balancing layer 24 and the silicon substrate 10 can introduce controlled compressive stress in the substrate 10, which can effectively offset the stress generated when the first surface of the substrate 10 is subjected to deep trench process, significantly reduce wafer warpage, and the thickness of the stress balancing layer 24 can be adjusted within the above range, thereby adapting to the needs of different wafer warpage.

[0103] As an example, the stress balancing layer 24 can be any one of a silicon oxide layer, a silicon nitride layer, or a silicon oxide / silicon nitride composite layer. Furthermore, by adjusting the ratio of the silicon oxide layer to the silicon nitride layer, the stress magnitude can be controlled more precisely.

[0104] like Figure 15 As shown, step S6 is then performed, in which a drain metal layer 25 is deposited on the second surface of the substrate 10, wherein the drain metal layer 25 fills the back trench 23 and forms an electrical connection with the substrate 10 exposed at the bottom of the back trench 23 and the second surface of the substrate 10.

[0105] Specifically, such as Figure 15 As shown, a drain metal layer 25 is formed by depositing metal on the second surface of the substrate 10. The drain metal layer 25 fills the back trench 23. The method for forming the drain metal layer 25 includes sputtering, physical vapor deposition, chemical vapor deposition, atomic layer deposition or other suitable methods. The material for forming the drain metal layer 25 includes titanium, silver, gold, copper, aluminum, tungsten or other suitable conductive materials.

[0106] As an example, the drain metal layer 25 is a single metal layer structure or a multilayer metal stack structure. The drain metal layer 25 forms an electrical connection with the substrate 10 exposed at the bottom of the back trench 23 and the second surface of the substrate 10. Since the drain metal layer 25 forms a direct ohmic contact with the substrate 10, it ensures that the on-resistance of the semiconductor device is not affected by the back-side process of the substrate 10. Furthermore, the integrated process of the drain metal layer 25 increases the cross-sectional area of ​​the drain and improves the back-side heat dissipation capability of the semiconductor device.

[0107] In summary, the semiconductor device structure and fabrication method of the present invention introduce multiple back trenches on the second surface of the substrate and deposit silicon oxide or silicon nitride on the sidewalls of the back trenches to form stress balancing layers of different thicknesses. This introduces controlled compressive stress on the second surface of the substrate, effectively offsetting the stress generated when forming the front device structure by deep trenching on the first surface of the substrate, significantly reducing wafer warpage. Furthermore, the bottom of the back trenches and the back side of the substrate are not covered with stress balancing layers, allowing the drain metal layer to form a direct electrical connection with the substrate, ensuring that the on-resistance of the semiconductor device is not affected. The drain metal layer directly fills the back trenches, increasing the cross-sectional area of ​​the drain metal and improving the heat dissipation capacity of the semiconductor device. In addition, the fabrication process of the present invention is relatively simple, compatible with conventional MOS device fabrication processes, improving production efficiency and facilitating mass production integration, while also reducing production costs, thus possessing high industrial value.

[0108] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A semiconductor device, characterized in that, include: A substrate having a first surface and a second surface disposed opposite to each other, and an epitaxial layer disposed on the first surface of the substrate; Multiple front-side device structures are located in the epitaxial layer; Multiple trench structures, each trench structure including a back trench and a stress balancing layer, wherein the back trench extends from a second surface of the substrate toward the interior of the substrate, and the stress balancing layer is located on the sidewall of the back trench; A drain metal layer covers the second surface of the substrate and completely fills the back trench, and forms an electrical connection with the bottom of the back trench and the second surface of the substrate.

2. The semiconductor device according to claim 1, characterized in that: The cross-sectional shape of the back groove can be any one of a rectangle, trapezoid, or U-shape.

3. The semiconductor device according to claim 1, characterized in that: The depth of the back groove is 15μm to 30μm.

4. The semiconductor device according to claim 1, characterized in that: The width of the back groove is 15μm to 30μm.

5. The semiconductor device according to claim 1, characterized in that: The stress balancing layer is any one of a silicon oxide layer, a silicon nitride layer, or a silicon oxide / silicon nitride composite layer.

6. The semiconductor device according to claim 1, characterized in that: The thickness of the stress balancing layer is 10nm~5000nm.

7. The semiconductor device according to claim 1, characterized in that: The drain metal layer is a single metal layer structure or a multilayer metal stack structure.

8. The semiconductor device according to claim 1, characterized in that, The front-side device structure includes multiple shielding trench gate structures, wherein each of the shielding trench gate structures includes: A front trench is located in the epitaxial layer and extends along the direction of the epitaxial layer toward the substrate; Both the shielding gate and the polysilicon gate are located in the front trench, and the shielding gate is located directly below the polysilicon gate; An interlayer oxide layer is located between the shielding gate and the polysilicon gate; A first dielectric layer is located at the bottom of the front trench and between the inner wall of the front trench and the outer wall of the shielding gate, and the top surface of the first dielectric layer is flush with the upper surface of the shielding gate. A gate dielectric layer is located between the inner wall of the front trench and the outer wall of the polysilicon gate, and the top surface of the gate dielectric layer is flush with the upper surface of the polysilicon gate.

9. The semiconductor device according to claim 8, characterized in that, The front-side device structure also includes: The second conductivity type body region is located on the upper surface of the epitaxial layer and adjacent to the sidewall of the front trench, and the bottom surface of the body region is not lower than the lower surface of the polysilicon gate. A first conductivity type source region is located on the upper surface of the body region and the bottom surface of the source region is lower than the upper surface of the polysilicon gate. An interlayer dielectric layer is located on the upper surface of the epitaxial layer, and the interlayer dielectric layer has a plurality of gate vias that penetrate the interlayer dielectric layer and expose the polysilicon gate at the bottom. A gate metal layer is located on the interlayer dielectric layer and fills the gate via.

10. A method for fabricating a semiconductor device, characterized in that, Includes the following steps: A substrate is provided, the substrate having a first surface and a second surface disposed opposite to each other; An epitaxial layer is formed on the first surface of the substrate; Multiple front-side device structures are formed in the epitaxial layer; The substrate is flipped over, and photolithography and etching processes are performed on the second surface of the substrate to form a back trench, which extends from the second surface of the substrate into the interior of the substrate. A stress balancing layer is formed on the sidewalls, bottom, and second surface of the substrate of the back trench, and the stress balancing layer on the second surface of the substrate and the bottom of the back trench is removed. A drain metal layer is formed by depositing metal on the second surface of the substrate, wherein the drain metal layer fills the back trench and forms an electrical connection with the second surface of the substrate and the substrate exposed at the bottom of the back trench.

11. The method for fabricating a semiconductor device according to claim 10, characterized in that: The stress balancing layer is any one of a silicon oxide layer, a silicon nitride layer, or a silicon oxide / silicon nitride composite layer.

12. The method for fabricating a semiconductor device according to claim 10, characterized in that: The thickness of the stress balancing layer is 10nm~5000nm.

13. The method for fabricating a semiconductor device according to claim 10, characterized in that: The steps for forming the front-side device structure include: Etching from the surface of the epitaxial layer into the interior of the epitaxial layer forms multiple parallel front trenches; A first dielectric layer is formed on the sidewalls and bottom wall of the front trench, and polysilicon is deposited in the front trench to form a shielding gate; An interlayer oxide layer is formed on the surface of the shielding gate and the first dielectric layer; A gate dielectric layer is formed on the sidewall of the front trench, and a polysilicon gate is formed in the front trench; Ion implantation of a second conductivity type is performed on the upper surface of the epitaxial layer to form a bulk region; Ion implantation of a first conductivity type is performed on the upper surface of the body region to form a source region.

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