A high-voltage gallium oxide monolithic integrated bidirectional switch using p-type nickel oxide and gate field plate and a preparation method thereof

Abstract

The application provides a high-voltage gallium oxide monolithic integrated bidirectional switch realized by using P-type nickel oxide and gate field plates and a preparation method thereof. The high-voltage gallium oxide monolithic integrated bidirectional switch comprises a substrate, an N-type gallium oxide epitaxial layer provided with a first source region high-doped N-type gallium oxide region, a second source region high-doped N-type gallium oxide region, a first gate side P-type nickel oxide layer, a second gate side P-type nickel oxide layer, a dielectric layer, a passivation layer, a first gate metal layer, a second gate metal layer, a first gate metal field plate layer, a second gate metal field plate layer, a first source metal layer and a second source metal layer. The structure is completely symmetrical in the lateral direction, so that the bidirectional conduction and bidirectional blocking capabilities of the structure are almost completely the same on a single chip. Moreover, the P-type nickel oxide layer and the N-type gallium oxide epitaxial layer form a longitudinal PN junction, auxiliary lateral depletion, and in combination with the gate field plate to relieve the gate side electric field concentration, so that the uniformity of the electric field distribution of the device is significantly improved, and the bidirectional voltage resistance capability of the device is greatly improved.

Description

Technical Field

[0001] This invention belongs to the field of power semiconductor technology, and in particular to a high-voltage gallium oxide monolithic integrated bidirectional switch and its fabrication method that utilizes P-type nickel oxide and a gate field plate. Background Technology

[0002] The breakdown voltage capability of lateral power devices is supported by both the lateral and longitudinal breakdown voltage structures. When subjected to reverse bias, the device breaks down once the peak electric field in any part reaches the critical breakdown electric field. However, due to the effect of the two-dimensional electric field, the surface electric field distribution in its drift region is not as close to the characteristics of an ideal diode as the bulk longitudinal junction, causing the surface region to reach the critical breakdown electric field earlier than the bulk longitudinal structure. Therefore, compared to vertical power devices, lateral structures are at a disadvantage in terms of breakdown voltage performance.

[0003] Resurgence (RESURF) technology, by adjusting the doping concentration and thickness of the epitaxial layer or introducing a vertical PN junction, enhances the vertical depletion effect to assist lateral depletion, reshaping the surface electric field of the drift region. This significantly improves the breakdown voltage of lateral power devices. Field plate technology, through the extension of electrode metal to form a field plate structure, attracts some of the electric field lines that originally pointed to the gate edge, terminating them at the field plate. This reduces the original electric field peak on the gate side and generates a new electric field peak at the end of the field plate, thereby improving the uniformity of the electric field distribution in the drift region, mitigating electric field accumulation caused by curvature effects, and improving the device's breakdown voltage.

[0004] Due to the self-compensation effect caused by gallium and oxygen vacancies in β-Ga₂O₃, coupled with its flat valence band leading to a significant increase in the effective hole mass, effective P-type doping is currently difficult to achieve. To improve the breakdown voltage performance of gallium oxide monolithic bidirectional switches (MBDS) using RESURF technology, a vertical PN junction needs to be constructed to assist in the expansion of the lateral depletion region. Therefore, how to effectively apply RESURF technology in gallium oxide MBDS has become a key technical challenge. Summary of the Invention

[0005] The purpose of this invention is to propose a high-voltage gallium oxide monolithically integrated bidirectional switch and its fabrication method using P-type nickel oxide and a gate field plate. This effectively suppresses the peak value of the surface electric field on the gate side, improves the uniformity of the electric field distribution of the device, thereby withstanding higher bidirectional breakdown voltage and obtaining a high-performance gallium oxide MBDS device.

[0006] To achieve the above objectives, the technical solution of the present invention is as follows:

[0007] A high-voltage gallium oxide monolithically integrated bidirectional switch utilizing P-type nickel oxide and a gate field plate includes: a substrate 1, an N-type gallium oxide epitaxial layer 2, a first P-type nickel oxide layer 3, a second P-type nickel oxide layer 4, a first dielectric layer 5, a second dielectric layer 6, a first gate metal layer 7, a second gate metal layer 8, a first gate metal field plate layer 9, a second gate metal field plate layer 10, a first source metal layer 13, and a second source metal layer 14;

[0008] The substrate 1 and the N-type gallium oxide epitaxial layer 2 are stacked sequentially from bottom to top. A first highly doped N-type gallium oxide region 11 and a second highly doped N-type gallium oxide region 12 are formed at both ends of the N-type gallium oxide epitaxial layer 2, and the lower surfaces of both regions are in contact with the substrate 1. A first source metal layer 13 is deposited on the upper surface of the first highly doped N-type gallium oxide region 11, and a second source metal layer 14 is deposited on the upper surface of the second highly doped N-type gallium oxide region 12. A first P-type nickel oxide layer 3 and a second P-type nickel oxide layer 4 are both deposited on the upper surface of the non-highly doped region of the N-type gallium oxide epitaxial layer 2, with the first P-type nickel oxide layer 3 and the second P-type nickel oxide layer 4 adjacent to each other at a predetermined distance, with the first P-type nickel oxide layer 3 closer to the first source metal layer 13 and the second P-type nickel oxide layer 4 closer to the second source metal layer 14. A first dielectric layer 5 covers the first source metal layer 11. The first P-type nickel oxide layer 3, the second P-type nickel oxide layer 4, and the N-type gallium oxide epitaxial layer 2 are deposited on the undeposited surface between layer 13 and the second source metal layer 14; the first gate metal layer 7 and the second gate metal layer 8 are deposited on the upper surface of the first dielectric layer 5, with the first gate metal layer 7 located between the first P-type nickel oxide layer 3 and the first source metal layer 13, and the second gate metal layer 8 located between the second P-type nickel oxide layer 4 and the second source metal layer 14; the second dielectric layer 6 covers the undeposited surface of the first dielectric layer 5 between the first source metal layer 13 and the second source metal layer 14; the first gate metal field plate layer 9 and the second gate metal field plate layer 10 are deposited on the second dielectric layer 6, with one side of the first gate metal field plate layer 9 contacting the first gate metal layer 7 and extending a predetermined length toward the second gate metal layer 8, and one side of the second gate metal field plate layer 10 contacting the second gate metal layer 8 and extending a predetermined length toward the first gate metal layer 7.

[0009] Preferably, the substrate 1 is an alumina heterostructure substrate or an iron-doped gallium oxide homostructure high-resistivity substrate.

[0010] Preferably, the thickness of the N-type gallium oxide epitaxial layer 2 is 0.1~1 μm, and the electron concentration in the non-highly doped region is 10. 17 ~5.0×10 17 cm -3The electron concentration of the first highly doped N-type gallium oxide region 11 and the second highly doped N-type gallium oxide region 12 is 10. 18 ~10 20 cm -3 .

[0011] Preferably, the thickness of the first P-type nickel oxide layer 3 is 0.1~2 μm, and the hole concentration is 10. 17 ~10 19 cm -3 The distance between the second p-type nickel oxide layer 4 and the first gate metal layer 7 is 1~5 μm; the thickness of the second p-type nickel oxide layer 4 is 0.1~2 μm, and the hole concentration is 10. 17 ~10 19 cm -3 The distance between the second gate metal layer 8 and the second gate metal layer 8 is 1~5 μm.

[0012] Preferably, the thickness of the first dielectric layer 5 is 10~50 nm, and it is made of alumina, silicon nitride or silicon dioxide.

[0013] Preferably, the thickness of the second dielectric layer 6 is 0.2 to 2 μm, and it is made of alumina, silicon nitride or silicon dioxide.

[0014] Preferably, the first gate metal layer 7, the second gate metal layer 8, the first gate metal field plate layer 9, and the second gate metal field plate layer 10 are selected from at least one metal selected from Au, Ni, Pt, Cu, and TiN, wherein the first gate metal field plate layer 9 extends from its contact surface with the first gate metal layer 7 toward the second gate metal layer 8 for a length of 1 to 3 μm, and the second gate metal field plate layer 10 extends from its contact surface with the second gate metal layer 8 toward the first gate metal layer 7 for a length of 1 to 3 μm.

[0015] Preferably, the first source metal layer 13 and the second source metal layer 14 are made of Pt metal.

[0016] A method for fabricating a high-voltage gallium oxide monolithically integrated bidirectional switch using P-type nickel oxide and a gate field plate, the method being used to fabricate any of the above-mentioned high-voltage gallium oxide monolithically integrated bidirectional switches, comprising the following steps:

[0017] Step 1: Perform a pretreatment on substrate 1 to remove surface contaminants;

[0018] Step 2: An N-type gallium oxide epitaxial layer 2 is epitaxially grown on the upper surface of the pretreated substrate 1;

[0019] Step 3: Spin-coat photoresist on the surface of the N-type gallium oxide epitaxial layer 2, form an opening pattern using standard photolithography, grow nickel oxide on the surface, and peel off the photoresist to form the first P-type nickel oxide layer 3 and the second P-type nickel oxide layer 4.

[0020] Step 4: Grow a first dielectric layer 5 on the surface of the first P-type nickel oxide layer 3 and the second P-type nickel oxide layer 4, and on the undeposited upper surface of the N-type gallium oxide epitaxial layer 2;

[0021] Step 5: Grow a second dielectric layer 6 on the upper surface of the first dielectric layer 5;

[0022] Step 6: Spin-coat photoresist onto the upper surface of the second dielectric layer 6, and form the opening pattern of the first gate metal layer 7 and the second gate metal layer 8 using standard photolithography. According to the opening pattern, etch the second dielectric layer 6 using reactive ion etching until it reaches the upper surface of the first dielectric layer 5.

[0023] Step 7: Spin-coat photoresist onto the upper surface of the second dielectric layer 6, and form the opening pattern of the first gate metal layer 7, the second gate metal layer 8, the first gate metal field plate layer 9 and the second gate metal field plate layer 10 using standard photolithography process.

[0024] Step 8: Deposit metal on the upper surfaces of the first dielectric layer 5 and the second dielectric layer 6 using evaporation or sputtering processes, and peel off the photoresist to form the first gate metal layer 7, the second gate metal layer 8, the first gate metal field plate layer 9 and the second gate metal field plate layer 10.

[0025] Step 9: Spin-coat photoresist onto the upper surfaces of the second dielectric layer 6, the first gate metal layer 7, and the second gate metal layer 8, and form the opening patterns of the first source metal layer 13 and the second source metal layer 14 using standard photolithography.

[0026] Step 10: According to the opening pattern, the first dielectric layer 5 and the second dielectric layer 6 are etched using reactive ion etching process until the upper surface of the N-type gallium oxide epitaxial layer 2 is reached.

[0027] Step 11: The upper surface of the etched gallium oxide epitaxial layer 2 is subjected to ion implantation to form a first highly doped N-type gallium oxide region 11 and a second highly doped N-type gallium oxide region 12;

[0028] Step 12: Deposit metal on the upper surfaces of the first highly doped N-type gallium oxide region 11 and the second highly doped N-type gallium oxide region 12 using evaporation or sputtering processes, and peel off the photoresist to form the first source metal layer 13 and the second source metal layer 14.

[0029] Preferably, in step 2, an N-type gallium oxide epitaxial layer 2 is epitaxially grown on the pretreated substrate 1 using hydride vapor phase epitaxy (HVPE) or metal-organic chemical vapor deposition (MOCVD) processes.

[0030] Compared with the prior art, the present invention has the following beneficial effects:

[0031] This invention proposes a high-voltage monolithic integrated bidirectional switch for gallium oxide (GaO) using a P-type nickel oxide layer and a gate field plate. By forming a vertical PN junction with an N-type GaO epitaxial layer, the advantages of RESURF technology are fully utilized to assist lateral depletion. Furthermore, the P-type nickel oxide layer has a strong dispersion effect on the electric field lines at the gate edge, which can effectively suppress the peak electric field on the gate side and improve the bidirectional breakdown voltage capability of the device. In addition, the gate field plate disperses the electric field lines on the gate side, reduces the peak electric field on the gate side, and balances the surface electric field distribution, further enhancing the bidirectional breakdown voltage capability of the device. Attached Figure Description

[0032] Figure 1 This is a schematic diagram of a high-voltage gallium oxide monolithic integrated bidirectional switch structure implemented using P-type nickel oxide and a gate field plate according to a preferred embodiment of the present invention;

[0033] Figure 2 This is a detailed process fabrication diagram of a high-voltage gallium oxide monolithic integrated bidirectional switch implemented using P-type nickel oxide and a gate field plate according to a preferred embodiment of the present invention;

[0034] Figure 3 This is a comparison diagram of the bidirectional withstand voltage of a high-voltage gallium oxide monolithically integrated bidirectional switch using P-type nickel oxide and a gate field plate, a preferred embodiment of the present invention, a gallium oxide monolithically integrated bidirectional switch using only P-type nickel oxide, and a gallium oxide monolithically integrated bidirectional switch with a conventional structure.

[0035] Figure 4 This is a comparison diagram of the surface electric field distribution of the drift region during breakdown of a high-voltage gallium oxide monolithic integrated bidirectional switch using P-type nickel oxide and a gate field plate according to a preferred embodiment of the present invention, and a gallium oxide monolithic integrated bidirectional switch using only P-type nickel oxide and a gallium oxide monolithic integrated bidirectional switch with a conventional structure.

[0036] Reference numerals: 1-substrate, 2-N-type gallium oxide epitaxial layer, 3-first P-type nickel oxide layer, 4-second P-type nickel oxide layer, 5-first dielectric layer, 6-second dielectric layer, 7-first gate metal layer, 8-second gate metal layer, 9-first gate metal field plate layer, 10-second gate metal field plate layer, 11-first highly doped N-type gallium oxide region, 12-second highly doped N-type gallium oxide region, 13-first source metal layer, 14-second source metal layer. Detailed Implementation

[0037] The following is in conjunction with the appendix Figure 1-4 The present invention will be further illustrated by the embodiments.

[0038] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0039] It should be noted that the terminology used herein is for the purpose of describing particular implementations only and is not intended to limit the exemplary implementations according to this application; as used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise; furthermore, it should be understood that when the terms “comprising” and / or “including” are used in this specification, they indicate the presence of features, steps, operations, devices, components and / or combinations thereof.

[0040] A high-voltage gallium oxide monolithically integrated bidirectional switch utilizing P-type nickel oxide and a gate field plate, reference Figure 1-4 It includes a substrate 1, an N-type gallium oxide epitaxial layer 2, a first P-type nickel oxide layer 3, a second P-type nickel oxide layer 4, a first dielectric layer 5, a second dielectric layer 6, a first gate metal layer 7, a second gate metal layer 8, a first gate metal field plate layer 9, a second gate metal field plate layer 10, a first heavily doped N-type gallium oxide region 11, a second heavily doped N-type gallium oxide region 12, a first source metal layer 13, and a second source metal layer 14;

[0041] The substrate 1 and the N-type gallium oxide epitaxial layer 2 are stacked sequentially from bottom to top; the first P-type nickel oxide layer 3 and the second P-type nickel oxide layer 4 are both deposited on top of the N-type gallium oxide epitaxial layer 2, and are arranged adjacent to each other at a predetermined distance, with the first P-type nickel oxide layer 3 close to the first gate metal layer 7 and the second P-type nickel oxide layer 4 close to the second gate metal layer 8; the first dielectric layer 5 covers the upper surface of the first P-type nickel oxide layer 3, the second P-type nickel oxide layer 4, and part of the N-type gallium oxide epitaxial layer 2; the second dielectric layer 6 covers the upper surface of the first dielectric layer 5; the first gate metal layer 7 and the second gate metal layer 8 are deposited on the first dielectric layer 5; the first gate metal field plate... Layer 9 and the second gate metal field plate layer 10 are deposited on the second dielectric layer 6; the upper surface of the first heavily doped N-type gallium oxide region 11 is in contact with the first source metal layer 13, and the lower surface is in contact with the substrate 1; the upper surface of the second heavily doped N-type gallium oxide region 12 is in contact with the second source metal layer 14, and the lower surface is in contact with the substrate 1; the remaining areas of the N-type gallium oxide epitaxial layer 2 are lightly doped; the right side of the first source metal layer 13 is in contact with the first dielectric layer 5 and the second dielectric layer 6, and the lower side is in contact with the first heavily doped N-type gallium oxide region 11; the left side of the second source metal layer 14 is in contact with the first dielectric layer 5 and the second dielectric layer 6, and the lower side is in contact with the second heavily doped N-type gallium oxide region 12;

[0042] The substrate 1 is an alumina heterostructure substrate or an iron-doped gallium oxide homostructure high-resistivity substrate;

[0043] The thickness of the N-type gallium oxide epitaxial layer 2 is 0.1~1 μm, and the electron concentration is 10. 17 ~5.0×10 17 cm -3 The electron concentration of the first highly doped N-type gallium oxide region 11 and the second highly doped N-type gallium oxide region 12 is 10. 18 ~10 20 cm -3 ;

[0044] The first P-type nickel oxide layer 3 has a thickness of 0.1~2 μm and a hole concentration of 10. 17 ~10 19 cm -3 The distance between the first gate metal layer 7 and the gate metal layer 7 is 1~5 μm;

[0045] The second p-type nickel oxide layer 4 has a thickness of 0.1~2 μm and a hole concentration of 10. 17 ~10 19 cm -3 The distance between the second gate metal layer 8 and the second gate metal layer 8 is 1~5 μm;

[0046] The first dielectric layer 5 has a thickness of 10~50 nm and is made of alumina, silicon nitride or silicon dioxide.

[0047] The second dielectric layer 6 has a thickness of 0.2~2 μm and is made of alumina, silicon nitride or silicon dioxide.

[0048] The first gate metal layer 7, the second gate metal layer 8, the first gate metal field plate layer 9, and the second gate metal field plate layer 10 are selected from at least one metal selected from Au, Ni, Pt, Cu, and TiN, wherein the length of the first gate metal field plate layer 9 and the second gate metal field plate layer 10 is 1~3 μm.

[0049] The first source metal layer 13 and the second source metal layer 14 are made of Pt metal.

[0050] Reference Figure 2 This invention fabricates a high-voltage gallium oxide monolithically integrated bidirectional switch using P-type nickel oxide and a gate field plate, and provides the following embodiments:

[0051] In this example, a gallium oxide epitaxial layer with a thickness of 0.2 μm and an electron concentration of 2.0 × 10⁻⁶ was prepared. 17 cm -3 The first P-type nickel oxide layer has a thickness of 1.5 μm, a length of 0.8 μm, and a hole concentration of 5 × 10⁻⁶. 17 cm -3 The spacing between the first gate metal layer and the second P-type nickel oxide layer is 2.4 μm; the second P-type nickel oxide layer has a thickness of 1.5 μm, a length of 0.8 μm, and a hole concentration of 5 × 10⁻⁶. 17 cm -3 A high-voltage gallium oxide monolithically integrated bidirectional switch utilizing p-type nickel oxide and a gate field plate is described, with a spacing of 2.4 μm between the first gate metal layer and the second gate metal layer; a length of 4 μm for both the first and second gate metal field plates; a length of 2.8 μm for both the first and second gate metal field plates; a spacing of 0.2 μm between the first and second p-type nickel oxide layers; and a dielectric layer thickness of 20 nm.

[0052] Step 1) Immerse the 500 μm thick alumina substrate 1 in acetone solution, anhydrous ethanol solution and deionized water in sequence for ultrasonic cleaning, and then blow the cleaned alumina substrate 1 dry with nitrogen gas. After that, heat treat the cleaned and dried alumina substrate 1 to remove surface contaminants.

[0053] Step 2) An epitaxial growth process with a thickness of 0.2 μm and an electron concentration of 2.0 × 10⁻⁶ is used. 17 cm -3 Gallium oxide epitaxial layer 2.

[0054] Step 3) Spin-coat photoresist onto the sample surface, form an opening pattern using standard photolithography, and grow a layer with a thickness of 1.5 μm, a length of 0.8 μm, and a hole concentration of 5 × 10⁻⁶ using magnetron sputtering. 17 cm -3 Nickel oxide is removed, and photoresist is stripped to form a first P-type nickel oxide layer 3 and a second P-type nickel oxide layer 4.

[0055] Step 4) Epitaxially grow a first dielectric layer 5 with a thickness of 20 nm on the sample surface.

[0056] Step 5) Epitaxially grow a second dielectric layer 6 with a thickness of 0.2 μm on the sample surface.

[0057] Step 6) Spin-coat photoresist on the sample surface and form the opening pattern of the first gate metal layer 7 and the second gate metal layer 8 using standard photolithography. According to the opening pattern, etch the second dielectric layer 6 using reactive ion etching until the upper surface of the first dielectric layer 5 is reached.

[0058] Step 7) Spin-coat photoresist onto the sample surface and form the opening pattern of the first gate metal layer 7, the second gate metal layer 8, the first gate metal field plate layer 9, and the second gate metal field plate layer 10 using standard photolithography.

[0059] Step 8) Deposit metal on the upper surfaces of the first dielectric layer 5 and the second dielectric layer 6 using evaporation or sputtering processes, and peel off the photoresist to form the first gate metal layer 7, the second gate metal layer 8, the first gate metal field plate layer 9 and the second gate metal field plate layer 10.

[0060] Step 9) Spin-coat photoresist onto the sample surface and form the opening pattern of the first source metal layer 13 and the second source metal layer 14 using standard photolithography.

[0061] Step 10) According to the opening pattern, the first dielectric layer 5 and the second dielectric layer 6 are etched using reactive ion etching process until the upper surface of the N-type gallium oxide epitaxial layer 2 is reached.

[0062] Step 11) The exposed gallium oxide epitaxial layer 2 is subjected to ion implantation to form an electron concentration of 1×10⁻⁶. 20 cm -3 The first highly doped N-type gallium oxide region 11 and the second highly doped N-type gallium oxide region 12.

[0063] Step 12) Deposit metal using evaporation or sputtering processes, and strip photoresist to form a first source metal layer 13 and a second source metal layer 14.

[0064] More specifically, the pretreatment in step 1) includes immersing the substrate 1 in acetone solution, anhydrous ethanol solution and deionized water in sequence for ultrasonic cleaning for 5 to 15 minutes each, drying the cleaned substrate 1 with nitrogen gas, and then heat-treating the cleaned and dried substrate 1 to remove surface contaminants.

[0065] More specifically, in step 2), an N-type gallium oxide epitaxial layer 2 is epitaxially grown on the pretreated substrate 1 using hydride vapor phase epitaxy (HVPE) or metal-organic chemical vapor deposition (MOCVD) processes.

[0066] More specifically, in steps 8) and 12), one or more methods, including magnetron sputtering, thermal evaporation, and electron beam evaporation, are used to deposit the metal layer.

[0067] More specifically, in steps 3), 6), 7), and 9), the specific method of spin coating is as follows: using a spin coater, set the rotation speed to 1000~3000 rpm / min and the spin coating time to 5~30 s; finally, pre-bake at a temperature of 60~150 °C for 60~120 s.

[0068] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

[0069] The working principle of this invention is as follows: Utilizing RESURF technology and field plate technology, a bidirectional high-voltage monolithic gallium oxide (GaO) integrated bidirectional switch is designed. This structure is completely symmetrical laterally and can be considered as an active device composed of two MOSFETs connected back-to-back in series. Therefore, it can achieve nearly identical bidirectional functions within a single chip, allowing current to flow bidirectionally when powered on and bidirectionally cut off when powered off. Specifically, the P-type nickel oxide layer deposited on top of the epitaxial layer forms a vertical PN junction with the N-type GaO epitaxial layer. On one hand, this junction balances the charge in the drift region, assisting lateral depletion through vertical depletion, leveraging the advantages of DR technology. On the other hand, the negative charge centers generated by the depletion of the P-type nickel oxide attract the positive charge centers generated by the depletion of the GaO epitaxial layer, thereby alleviating the electric field concentration on the gate side caused by curvature effects and enhancing the device's bidirectional breakdown voltage capability. Simultaneously, the introduction of the gate field plate further alleviates the electric field concentration on the gate side, effectively uniformizing the surface electric field distribution. Under the combined effect of the P-type nickel oxide and the gate field plate, the device's bidirectional breakdown voltage capability is significantly improved, resulting in a high-performance GaO MBDS device.

[0070] Figure 3The embodiments of the present invention provide a first P-type nickel oxide layer with a thickness of 1.5 μm, a length of 0.8 μm, and a hole concentration of 5 × 10⁻⁶. 17 cm -3 The spacing between the first gate metal layer and the second P-type nickel oxide layer is 2.4 μm; the second P-type nickel oxide layer has a thickness of 1.5 μm, a length of 0.8 μm, and a hole concentration of 5 × 10⁻⁶. 17 cm -3 A high-voltage gallium oxide monolithic integrated bidirectional switch with a spacing of 2.4 μm between the first and second gate metal layers, a length of 4 μm for both the first and second gate metal layers, a length of 2.8 μm for both the first and second gate metal field plates, and a spacing of 0.2 μm between the first and second P-type nickel oxide layers and the second P-type nickel oxide layer, is compared in terms of bidirectional withstand voltage. This is in contrast to a gallium oxide monolithic integrated bidirectional switch using only P-type nickel oxide and a conventional gallium oxide monolithic integrated bidirectional switch. According to... Figure 3 It can be seen that the forward breakdown voltage of a conventional gallium oxide monolithically integrated bidirectional switch is only 435.1 V and the reverse breakdown voltage is only 396.7 V. The forward breakdown voltage of a gallium oxide monolithically integrated bidirectional switch using only P-type nickel oxide reaches 2507 V and the reverse breakdown voltage reaches 2367 V, with the forward and reverse breakdown voltages improved by 476% and 487% respectively compared with the conventional structure. Furthermore, the high-voltage gallium oxide monolithically integrated bidirectional switch using P-type nickel oxide and a gate field plate achieves a forward breakdown voltage of 3418 V and a reverse breakdown voltage of 3229 V, with both forward and reverse breakdown voltages further improved by 36% compared with the structure using only P-type nickel oxide.

[0071] Figure 4 The embodiments of the present invention provide a first P-type nickel oxide layer with a thickness of 1.5 μm, a length of 0.8 μm, and a hole concentration of 5 × 10⁻⁶. 17 cm -3 The spacing between the first gate metal layer and the second P-type nickel oxide layer is 2.4 μm; the second P-type nickel oxide layer has a thickness of 1.5 μm, a length of 0.8 μm, and a hole concentration of 5 × 10⁻⁶. 17 cm -3 A comparison of the surface electric field distribution of the drift region during breakdown in forward mode of a high-voltage gallium oxide monolithic integrated bidirectional switch with a spacing of 2.4 μm between the first and second gate metal layers, a length of 4 μm for both the first and second gate metal layers, a length of 2.8 μm for both the first and second gate metal field plates, and a spacing of 0.2 μm between the first and second P-type nickel oxide layers. This is based on the information provided. Figure 4It is known that the electric field on the drift region surface of a conventional gallium oxide monolithic integrated bidirectional switch is mainly borne by the area at the gate edge; the electric field distribution of a gallium oxide monolithic integrated bidirectional switch using only nickel oxide is extremely uneven, and the area bearing the electric field is small; while the high-voltage gallium oxide monolithic integrated bidirectional switch using P-type nickel oxide and a gate field plate raises the electric field in the middle section, increases the area in which the drift region shares the electric field, and makes the electric field distribution more uniform, greatly improving the withstand voltage capability.

[0072] The above are preferred embodiments of the present invention. Any changes made to the technical solution of the present invention that do not exceed the scope of the technical solution of the present invention shall fall within the protection scope of the present invention.

Claims

1. A high-voltage gallium oxide monolithically integrated bidirectional switch utilizing P-type nickel oxide and a gate field plate, characterized in that, include: Substrate (1), N-type gallium oxide epitaxial layer (2), first P-type nickel oxide layer (3), second P-type nickel oxide layer (4), first dielectric layer (5), second dielectric layer (6), first gate metal layer (7), second gate metal layer (8), first gate metal field plate layer (9), second gate metal field plate layer (10), first source metal layer (13), second source metal layer (14); The substrate (1) and the N-type gallium oxide epitaxial layer (2) are stacked sequentially from bottom to top; a first highly doped N-type gallium oxide region (11) and a second highly doped N-type gallium oxide region (12) are formed at both ends of the N-type gallium oxide epitaxial layer (2), and the lower surfaces of the first highly doped N-type gallium oxide region (11) and the second highly doped N-type gallium oxide region (12) are in contact with the substrate (1); the first source metal layer (13) is deposited on the upper surface of the first highly doped N-type gallium oxide region (11), and the second source metal layer (12) is deposited on the upper surface of the first highly doped N-type gallium oxide region (11). 4) Deposited on the upper surface of the second highly doped N-type gallium oxide region (12); the first P-type nickel oxide layer (3) and the second P-type nickel oxide layer (4) are both deposited on the upper surface of the non-highly doped region of the N-type gallium oxide epitaxial layer (2), the first P-type nickel oxide layer (3) and the second P-type nickel oxide layer (4) are arranged adjacent to each other at a preset distance, and the first P-type nickel oxide layer (3) is close to the first source metal layer (13), and the second P-type nickel oxide layer (4) is close to the second source metal layer (14); the first dielectric layer (5) covers the first source metal layer (13). The undeposited surfaces of the first P-type nickel oxide layer (3), the second P-type nickel oxide layer (4), and the N-type gallium oxide epitaxial layer (2) between the second source metal layer (14); the first gate metal layer (7) and the second gate metal layer (8) are deposited on the upper surface of the first dielectric layer (5), the first gate metal layer (7) is located between the first P-type nickel oxide layer (3) and the first source metal layer (13), and the second gate metal layer (8) is located between the second P-type nickel oxide layer (4) and the second source metal layer (14); the second dielectric layer (6) covers On the undeposited surface of the first dielectric layer (5) between the first source metal layer (13) and the second source metal layer (14); the first gate metal field plate layer (9) and the second gate metal field plate layer (10) are deposited on the second dielectric layer (6), one side of the first gate metal field plate layer (9) contacts the first gate metal layer (7) and extends a predetermined length toward the second gate metal layer (8), and one side of the second gate metal field plate layer (10) contacts the second gate metal layer (8) and extends a predetermined length toward the first gate metal layer (7).

2. The high-voltage gallium oxide monolithically integrated bidirectional switch based on P-type nickel oxide and a gate field plate according to claim 1, characterized in that, The substrate (1) is an alumina heterostructure substrate or an iron-doped gallium oxide homostructure high-resistivity substrate.

3. A high-voltage gallium oxide monolithically integrated bidirectional switch based on P-type nickel oxide and a gate field plate according to claim 1, characterized in that, The thickness of the N-type gallium oxide epitaxial layer (2) is 0.1~1 μm, and the electron concentration in the non-highly doped region is 10. 17 ~5.0×10 17 cm -3 The electron concentration of the first highly doped N-type gallium oxide region (11) and the second highly doped N-type gallium oxide region (12) is 10. 18 ~10 20 cm -3 .

4. A high-voltage gallium oxide monolithically integrated bidirectional switch based on P-type nickel oxide and a gate field plate according to claim 1, characterized in that, The first P-type nickel oxide layer (3) has a thickness of 0.1~2 μm and a hole concentration of 10. 17 ~10 19 cm -3 The distance between the second P-type nickel oxide layer (4) and the first gate metal layer (7) is 1~5 μm; the thickness of the second P-type nickel oxide layer (4) is 0.1~2 μm, and the hole concentration is 10. 17 ~10 19 cm -3 The distance between the second gate metal layer (8) and the second gate metal layer (8) is 1~5 μm.

5. A high-voltage gallium oxide monolithically integrated bidirectional switch based on P-type nickel oxide and a gate field plate according to claim 1, characterized in that, The first dielectric layer (5) has a thickness of 10~50 nm and is made of aluminum oxide, silicon nitride or silicon dioxide.

6. A high-voltage gallium oxide monolithically integrated bidirectional switch based on P-type nickel oxide and a gate field plate according to claim 1, characterized in that, The second dielectric layer (6) has a thickness of 0.2 ~ 2 μm and is made of alumina, silicon nitride or silicon dioxide.

7. A high-voltage gallium oxide monolithically integrated bidirectional switch based on P-type nickel oxide and a gate field plate according to claim 1, characterized in that, The first gate metal layer (7), the second gate metal layer (8), the first gate metal field plate layer (9), and the second gate metal field plate layer (10) are selected from at least one metal selected from Au, Ni, Pt, Cu, and TiN. The first gate metal field plate layer (9) extends from the contact surface with the first gate metal layer (7) toward the second gate metal layer (8) for a length of 1 to 3 μm, and the second gate metal field plate layer (10) extends from the contact surface with the second gate metal layer (8) toward the first gate metal layer (7) for a length of 1 to 3 μm.

8. A high-voltage gallium oxide monolithically integrated bidirectional switch based on P-type nickel oxide and a gate field plate according to claim 1, characterized in that, The first source metal layer (13) and the second source metal layer (14) are made of Pt metal.

9. A method for fabricating a high-voltage gallium oxide monolithically integrated bidirectional switch using P-type nickel oxide and a gate field plate, characterized in that, The method is used to prepare the high-voltage gallium oxide monolithic integrated bidirectional switch according to any one of claims 1-8, and includes the following steps: Step 1: Pre-treat the substrate (1) to remove surface contaminants; Step 2: An N-type gallium oxide epitaxial layer (2) is epitaxially grown on the upper surface of the pretreated substrate (1); Step 3: Spin-coat photoresist on the surface of the N-type gallium oxide epitaxial layer (2), form an opening pattern using standard photolithography, grow nickel oxide on the surface, and peel off the photoresist to form the first P-type nickel oxide layer (3) and the second P-type nickel oxide layer (4). Step 4: A first dielectric layer (5) is grown on the surface of the first P-type nickel oxide layer (3) and the second P-type nickel oxide layer (4), and on the undeposited upper surface of the N-type gallium oxide epitaxial layer (2). Step 5: Grow a second dielectric layer (6) on the upper surface of the first dielectric layer (5); Step 6: Spin-coat photoresist on the upper surface of the second dielectric layer (6), and form the opening pattern of the first gate metal layer (7) and the second gate metal layer (8) using standard photolithography. According to the opening pattern, etch the second dielectric layer (6) using reactive ion etching until the upper surface of the first dielectric layer (5) is reached. Step 7: Spin-coat photoresist on the upper surface of the second dielectric layer (6) and form the opening pattern of the first gate metal layer (7), the second gate metal layer (8), the first gate metal field plate layer (9) and the second gate metal field plate layer (10) using standard photolithography process; Step 8: Deposit metal on the upper surface of the first dielectric layer (5) and the second dielectric layer (6) using evaporation or sputtering process, and peel off the photoresist to form the first gate metal layer (7), the second gate metal layer (8), the first gate metal field plate layer (9) and the second gate metal field plate layer (10). Step 9: Spin-coat photoresist onto the upper surfaces of the second dielectric layer (6), the first gate metal layer (7), and the second gate metal layer (8), and form the opening patterns of the first source metal layer (13) and the second source metal layer (14) using standard photolithography process; Step 10: According to the opening pattern, the first dielectric layer (5) and the second dielectric layer (6) are etched using reactive ion etching process until the upper surface of the N-type gallium oxide epitaxial layer (2) is reached; Step 11: The upper surface of the etched gallium oxide epitaxial layer (2) is subjected to ion implantation to form a first highly doped N-type gallium oxide region (11) and a second highly doped N-type gallium oxide region (12). Step 12: Deposit metal on the upper surface of the first highly doped N-type gallium oxide region (11) and the second highly doped N-type gallium oxide region (12) using evaporation or sputtering process, and peel off the photoresist to form the first source metal layer (13) and the second source metal layer (14).

10. The method for fabricating a high-voltage gallium oxide monolithic integrated bidirectional switch using P-type nickel oxide and a gate field plate according to claim 9, characterized in that, In step 2, an N-type gallium oxide epitaxial layer (2) is epitaxially grown on the pretreated substrate (1) using hydride vapor phase epitaxy (HVPE) or metal-organic chemical vapor deposition (MOCVD) processes.

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