Picture synchronization output method, apparatus and device
By adjusting the number of reference clock cycles for synchronized screen output while keeping the reference clock cycle constant, the high cost and complexity caused by the additional introduction of microcontrollers and clock chips in existing technologies are solved, and stable synchronized screen output is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- XIAN NOVASTAR TECH
- Filing Date
- 2021-09-22
- Publication Date
- 2026-05-29
AI Technical Summary
In existing technologies, maintaining synchronized screen output requires the introduction of additional microcontrollers and clock chips, which increases costs and system control complexity.
The phase difference between the screen to be output and the screen to be output is detected by the GENLOCK module, and the number of reference clock cycles of the output screen is adjusted while the reference clock cycle remains unchanged to achieve synchronous output.
This reduces system control complexity and hardware costs while ensuring the stability of synchronized screen output and avoiding issues such as screen flickering and black screens.
Smart Images
Figure CN115842893B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of image display technology, and more specifically, to a method, apparatus, and device for synchronous image output. Background Technology
[0002] With the rapid development of computing and storage capabilities, the video processing industry faces a wide variety of image and video sizes, requiring input screen sizes to be scaled point-to-point to the display screen size. Image and display screen sizes range from as small as 280P to as large as 8K resolution, and both can be freely adapted to each other. However, this introduces additional latency in the image display chain. Different devices process images at different locations, and then all images are stitched together. To achieve simultaneous display of the same image, a GENLOCK (phase-locked loop) function is needed. This ensures that all systems process the same image at the same time, and that display synchronization guarantees a synchronized output image. It also ensures stable output image switching between different frame rates, preventing flickering, blackouts, and blurring.
[0003] In related technologies, a common approach is to use a GENLOCK module to detect the phase difference between the desired output frame and the actual output frame. Then, a microcontroller dynamically adjusts the frequency of a reference clock, modifying the size of the reference clock cycle while maintaining a constant number of reference clock cycles for each frame to compensate for frame lead or lag. While this solution can maintain synchronized output, it requires an additional microcontroller and clock chip, increasing both cost and system control complexity.
[0004] There is currently no effective solution to the above problems. Summary of the Invention
[0005] This application provides a method, apparatus, and device for synchronized screen output, which at least solves the technical problems in the related art where maintaining synchronized screen output requires the additional introduction of a microcontroller and clock chip, resulting in high costs and complex control processes.
[0006] According to one aspect of the embodiments of this application, a method for synchronous output of a screen is provided, comprising: acquiring a first input screen and a first output screen corresponding to the first input screen; outputting a first output screen based on the first output screen, and determining a phase difference between the first output screen and the first output screen; acquiring a second input screen adjacent to the first input screen and a second output screen corresponding to the second input screen, and determining a first number of reference clock cycles corresponding to the second output screen based on the second output screen and the phase difference; and outputting the second output screen within the first number of reference clock cycles.
[0007] Optionally, the first input screen at a first frame rate is acquired; and the first output screen at a second frame rate is determined based on the first input screen at the first frame rate.
[0008] Optionally, the first output frame at a third frame rate is output based on the first output frame at the second frame rate.
[0009] Optionally, a second number of reference clock cycles corresponding to the first output frame is determined based on the second frame rate; a third number of reference clock cycles corresponding to the first output frame is determined based on the third frame rate; and the phase difference is determined based on the second number and the third number.
[0010] Optionally, a fourth number of reference clock cycles corresponding to the second output screen is determined; a fifth number of reference clock cycles corresponding to the phase difference is determined; and the first number is determined based on the fourth number and the fifth number.
[0011] Optionally, the phase difference is compared with a preset threshold; when the phase difference is less than the preset threshold, the second output frame is determined to be the next frame of the first output frame; when the phase difference is greater than the preset threshold, the number of frames in the second output frame is determined as the target number of frames based on the phase difference, wherein the target number of frames is not less than two.
[0012] Optionally, when the second output screen is a single frame, the second output screen is output within the first number of reference clock cycles; when the second output screen is multiple frames, a sixth number of reference clock cycles corresponding to each frame in the second output screen is determined based on the first number and the target number of frames, and one frame in the second output screen is output within each of the sixth number of reference clock cycles.
[0013] Optionally, the length of the reference clock cycle is a fixed value.
[0014] According to another aspect of the embodiments of this application, a screen synchronization output device is also provided, comprising: an acquisition module, configured to acquire a first input screen and a first output screen corresponding to the first input screen; a first output module, configured to output a first output screen based on the first output screen and determine a phase difference between the first output screen and the first output screen; a determination module, configured to acquire a second input screen adjacent to the first input screen and a second output screen corresponding to the second input screen, and determine a first number of reference clock cycles corresponding to the second output screen based on the second output screen and the phase difference; and a second output module, configured to output the second output screen within the first number of reference clock cycles.
[0015] According to another aspect of the embodiments of this application, a screen synchronization output device is also provided, including: a memory and a processor, wherein the memory stores a computer program, and the processor is configured to execute the above-described screen synchronization output method through the computer program.
[0016] In this embodiment, a first input screen and a first output screen corresponding to the first input screen are first acquired. A first output screen is then output based on the first output screen, and the phase difference between the first output screen and the first output screen is determined. Next, a second input screen adjacent to the first input screen and a second output screen corresponding to the second input screen are acquired. A first number of reference clock cycles corresponding to the second output screen is determined based on the second output screen and the phase difference. The second output screen is then output within the first number of reference clock cycles. By using the GENLOCK module to determine the phase difference between the first output screen and the first output screen, and adjusting the number of reference clock cycles corresponding to the second output screen while keeping the reference clock cycle size constant, synchronous screen output can be achieved. This significantly reduces system control complexity and solves the technical problems in related technologies where maintaining synchronous screen output requires the additional introduction of a microcontroller and clock chip, resulting in high costs and complex control processes. Attached Figure Description
[0017] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:
[0018] Figure 1 This is a schematic diagram of a screen synchronization output system based on related technologies;
[0019] Figure 2 This is a schematic diagram illustrating the principle of synchronized image output based on relevant technologies;
[0020] Figure 3 This is a flowchart illustrating a method for synchronous screen output according to an embodiment of this application;
[0021] Figure 4 This is a schematic diagram of the input and output structure of a GENLOCK module according to an embodiment of this application;
[0022] Figure 5 This is a schematic diagram illustrating the principle of synchronized screen output according to an embodiment of this application;
[0023] Figure 6 This is a schematic diagram illustrating another principle of synchronized screen output according to an embodiment of this application;
[0024] Figure 7 This is a schematic diagram of a screen synchronization output device according to an embodiment of this application. Detailed Implementation
[0025] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.
[0026] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0027] To better understand the embodiments of this application, some nouns or terms that appear in the description of the embodiments of this application are translated and explained as follows:
[0028] GENLOCK (Synchronization Phase Lock): Synchronizes the field frequency of input and output screen data, ensuring phase delay jitter is in the microsecond range.
[0029] Example 1
[0030] In related technologies, when displaying an image, after determining the input image, the desired output image can be determined based on the input image. Then, the actual output image is output based on the input image. During this process, the GENLOCK module continuously monitors the phase difference between each frame of the image to be output and the output image, and feeds this feedback to the MCU (Microcontroller Unit). The MCU reconfigures the clock chip based on this phase difference, dynamically adjusting the REFER CLK (reference clock) frequency to speed up or delay the generation of the output image, ensuring that the image to be output and the output image are in phase and frequency. Typically, the phase deviation between the image to be output and the output image needs to be controlled to be less than 1µs.
[0031] Specifically, with Figure 2 For example, the reference clock period corresponding to the image to be output is the input stable period, and the reference clock period corresponding to the output image is the output stable period. Assuming the frame rate of the image to be output is 1 (1 stable frame per second), generated by 10 reference clock periods, after outputting the first frame, it is found to be one reference clock period ahead of the first image to be output (i.e., it only took 0.9 seconds). This extra 0.1 seconds must be made up in the next output frame, meaning the second output frame needs to be output within 1.1 seconds. However, since the number of reference clock periods corresponding to the second output frame is still 10, the MCU must modify the reference clock frequency. That is, while maintaining the number of reference clock periods, the size of the reference clock period is modified to compensate for the 0.1-second lead. It should be noted that the logic for phase lag is the same as the logic for lead; it also involves maintaining the number of reference clock periods per output frame while modifying the size of the reference clock period to compensate for lead or lag.
[0032] While the above process can achieve synchronized screen output, it increases both cost and system control complexity due to the need for additional MCU and clock chip. To address these issues, this application proposes a novel solution: considering the low system requirements of the GENLOCK module's input / output interfaces, instead of adjusting the reference clock cycle size in real-time to compensate for time differences, the time difference can be compensated by increasing or decreasing the number of reference clock cycles. This solution reduces hardware costs and system control complexity while ensuring synchronized input and output screens, and also guarantees a smooth, flicker-free, and clear output screen.
[0033] Specifically, this application provides an embodiment of a screen synchronization output method. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.
[0034] Figure 3 This is a method for synchronously outputting images according to an embodiment of this application, such as... Figure 3 As shown, the method includes at least steps S302-S308, wherein:
[0035] Step S302: Obtain the first input screen and the first output screen corresponding to the first input screen.
[0036] The first input screen is one or more frames of input screen. To achieve accurate synchronization of input and output screens, it is usually necessary to detect the phase difference frame by frame. Therefore, the first input screen is preferably one frame. The first output screen is the screen to be output based on the first output screen. Since the frame rate of the screen to be output by the user may be different from the frame rate of the input screen, the frame rate of the input screen needs to be adjusted. That is, the content of the first output screen and the first input screen are the same, but the frame rate is not necessarily the same.
[0037] Specifically, the process first acquires the first input frame at a first frame rate, and then determines the first output frame at a second frame rate based on the first input frame at the first frame rate. The first and second frame rates can be the same or different. For example, the frame rate of the first input frame is 60, while the frame rate of the first output frame can be either 60 or 30, and can be set by the user.
[0038] Step S304: Output the first output screen based on the first output screen to be output, and determine the phase difference between the first output screen to be output and the first output screen.
[0039] Specifically, based on the first image to be output at the second frame rate, the first output image at the third frame rate is output, where the first output image is the actual output image. Understandably, due to system latency and other reasons, there will be a deviation between the actual output frame rate and the expected output frame rate, that is, there will be a phase difference between the first image to be output and the first output image. This phase difference is detected by the GENLOCK module.
[0040] Figure 4 A schematic diagram of an optional GENLOCK module input / output structure is shown. The GENLOCK module receives an input screen and a corresponding output screen, outputs an output screen based on the output screen, and detects the phase difference between the output screen and the output screen.
[0041] In some optional embodiments of this application, since a clock chip is no longer introduced to adjust the size of the reference clock cycle, i.e. the length of the reference clock cycle is a fixed value, the number of reference clock cycles can be used to reflect the phase difference between the screen to be output and the screen to be output.
[0042] Specifically, the second number of reference clock cycles corresponding to the first output frame can be determined based on the second frame rate; the third number of reference clock cycles corresponding to the first output frame can be determined based on the third frame rate; and the phase difference can be determined based on the second and third numbers.
[0043] For example, assuming a reference clock cycle of 0.1s, the second frame rate of the first output frame is 1 frame of stable image per second, corresponding to 10 reference clock cycles; the third frame rate of the first output frame is 1 frame of stable image per 0.9 seconds, corresponding to 9 reference clock cycles; the first output frame is 1 reference clock cycle ahead of the first output frame, and the phase difference is -1 reference clock cycle, or -0.1s ("-" indicates ahead, "+" indicates lag).
[0044] Step S306: Obtain the second input screen adjacent to the first input screen and the second output screen corresponding to the second input screen, and determine the first number of reference clock cycles corresponding to the second output screen based on the second output screen and the phase difference.
[0045] Step S308: Output the second output screen within the first number of reference clock cycles.
[0046] Once the phase difference between the first output frame and the first output frame is determined, the lead or lag of the frame can be compensated by adjusting the number of reference clock cycles corresponding to one or more second output frames adjacent to the first output frame.
[0047] Specifically, a fourth number of reference clock cycles corresponding to the second output screen can be determined; a fifth number of reference clock cycles corresponding to the phase difference can be determined; and a first number can be determined based on the fourth and fifth numbers.
[0048] For example, the second output frame is still a stable frame at 1 frame per second, generated by 10 reference clock cycles, i.e., the fourth quantity is 10, and the phase difference is -1 reference clock cycles as determined above, i.e., the fifth quantity is -1. At this time, it can be determined that the first quantity of the reference clock cycles corresponding to the second output frame is 10-(-1)=11. That is, outputting the second frame within 11 reference clock cycles can compensate for the previous frame being ahead, thereby synchronizing the output frame with the frame to be output.
[0049] Understandably, when the phase difference between the first frame to be output and the first output frame is small, the lead or lag can be compensated directly by increasing or decreasing the number of reference clock cycles in the next adjacent frame without significantly affecting the actual output image quality. However, when the phase difference between the first frame to be output and the first output frame is large, compensating for the lead or lag only in the next frame, while ensuring phase synchronization between the output and the frame to be output, can lead to excessively large differences in the number of reference clock cycles between adjacent frames, easily causing screen flickering or black screens. Therefore, when the phase difference between the first frame to be output and the first output frame is large, it is best to compensate for the lead or lag in subsequent consecutive frames to ensure that the frame rate of the output frame can be correctly recognized by the subsequent modules, thus preventing screen flickering, black screens, or distorted images.
[0050] In some optional embodiments of this application, the phase difference can be compared with a preset threshold; when the phase difference is less than the preset threshold, the second output frame is determined to be the frame following the first output frame; when the phase difference is greater than the preset threshold, the number of frames in the second output frame is determined as the target number of frames based on the phase difference, and the target number of frames is not less than two. The preset threshold can be determined through multiple experiments to ensure that the target number of frames is as small as possible without issues such as screen flickering, black screens, or distorted screens in the actual output frame.
[0051] Specifically, when the phase difference is less than a preset threshold, the second output image is one frame, and this frame of the second output image is output within the first number of reference clock cycles.
[0052] by Figure 5 For example, assuming the preset threshold is 3 reference clock cycles, the reference clock cycle corresponding to the output image is the input stable cycle, the reference clock cycle corresponding to the output image is the output stable cycle, and the frame rate of the output image is 1, that is, 1 stable image per second, corresponding to 10 reference clock cycles. Among them, the output of the first frame only takes 0.9s, corresponding to 9 reference clock cycles. At this time, the phase difference is 0.1s, that is, it is ahead of 1 reference clock cycle, which is less than the preset threshold. Therefore, the 1 reference clock cycle ahead is directly compensated in the second frame output image, and the number of reference clock cycles corresponding to the second frame output image is determined to be 11. That is, the second frame output image is output within 11 reference clock cycles (1.1s), and the synchronous output of the image can be achieved.
[0053] When the phase difference is greater than the preset threshold, the second output screen consists of multiple frames. It is necessary to determine the sixth number of reference clock cycles corresponding to each frame in the second output screen based on the first number and the target number of frames. Within each sixth number of reference clock cycles, one frame in the second output screen is output.
[0054] by Figure 6 For example, assuming the preset threshold is 3 reference clock cycles, the reference clock cycle corresponding to the output image is the input stable cycle, and the reference clock cycle corresponding to the output image is the output stable cycle, the frame rate of the output image is 1, that is, 1 stable image per second, corresponding to 10 reference clock cycles. Among them, the output of the first frame only takes 0.6s, corresponding to 6 reference clock cycles. At this time, the phase difference is 0.4s, that is, it is ahead of 4 reference clock cycles, which is greater than the preset threshold. Therefore, the 4 ahead reference clock cycles can be compensated in the next two adjacent frames. The number of reference clock cycles corresponding to the second output image is adjusted to 10, and the number of reference clock cycles corresponding to the third output image is adjusted to 14, so that the phase difference between the two adjacent output images is 4 reference clock cycles. This ensures that the frame rate of the output image can be correctly recognized by the subsequent modules. By outputting the second output image within 1s and the third output image within 1.4s, the screen can be output synchronously without flickering, black screen, or screen distortion.
[0055] In this embodiment, a first input screen and a first output screen corresponding to the first input screen are first acquired. A first output screen is then output based on the first output screen, and the phase difference between the first output screen and the first output screen is determined. Next, a second input screen adjacent to the first input screen and a second output screen corresponding to the second input screen are acquired. A first number of reference clock cycles corresponding to the second output screen is determined based on the second output screen and the phase difference. The second output screen is then output within the first number of reference clock cycles. By using the GENLOCK module to determine the phase difference between the first output screen and the first output screen, and adjusting the number of reference clock cycles corresponding to the second output screen while keeping the reference clock cycle size constant, synchronous screen output can be achieved. This significantly reduces system control complexity and solves the technical problems in related technologies where maintaining synchronous screen output requires the additional introduction of a microcontroller and clock chip, resulting in high costs and complex control processes.
[0056] Example 2
[0057] According to an embodiment of this application, a screen synchronization output device for implementing the above-described screen synchronization output method is also provided, such as... Figure 7 As shown, the device includes an acquisition module 70, a first output module 72, a determination module 74, and a second output module 76, wherein:
[0058] The acquisition module 70 is used to acquire the first input screen and the first output screen corresponding to the first input screen.
[0059] The first input screen is one or more frames of input screen. To achieve accurate synchronization of input and output screens, it is usually necessary to detect the phase difference frame by frame. Therefore, the first input screen is preferably one frame. The first output screen is the screen to be output based on the first output screen. Since the frame rate of the screen to be output by the user may be different from the frame rate of the input screen, the frame rate of the input screen needs to be adjusted. That is, the content of the first output screen and the first input screen are the same, but the frame rate is not necessarily the same.
[0060] Specifically, the first input frame at a first frame rate is first acquired, and then the first output frame at a second frame rate is determined based on the first input frame at the first frame rate. The first frame rate and the second frame rate can be the same or different.
[0061] The first output module 72 is used to output a first output screen based on a first screen to be output, and to determine the phase difference between the first screen to be output and the first output screen.
[0062] Specifically, based on the first image to be output at the second frame rate, the first output image at the third frame rate is output, where the first output image is the actual output image. Understandably, due to system latency and other reasons, there will be a deviation between the actual output frame rate and the expected output frame rate, that is, there will be a phase difference between the first image to be output and the first output image. This phase difference is detected by the GENLOCK module.
[0063] In some optional embodiments of this application, since a clock chip is no longer introduced to adjust the size of the reference clock cycle, i.e. the length of the reference clock cycle is a fixed value, the number of reference clock cycles can be used to reflect the phase difference between the screen to be output and the screen to be output.
[0064] Specifically, the second number of reference clock cycles corresponding to the first output frame can be determined based on the second frame rate; the third number of reference clock cycles corresponding to the first output frame can be determined based on the third frame rate; and the phase difference can be determined based on the second and third numbers.
[0065] The determining module 74 is used to acquire a second input screen adjacent to the first input screen and a second output screen corresponding to the second input screen, and to determine a first number of reference clock cycles corresponding to the second output screen based on the second output screen and the phase difference.
[0066] The second output module 76 is used to output a second output screen within a first number of reference clock cycles.
[0067] Once the phase difference between the first output frame and the first output frame is determined, the lead or lag of the frame can be compensated by adjusting the number of reference clock cycles corresponding to one or more second output frames adjacent to the first output frame.
[0068] Specifically, a fourth number of reference clock cycles corresponding to the second output screen can be determined; a fifth number of reference clock cycles corresponding to the phase difference can be determined; and a first number can be determined based on the fourth and fifth numbers.
[0069] Understandably, when the phase difference between the first frame to be output and the first output frame is small, the lead or lag can be compensated directly by increasing or decreasing the number of reference clock cycles in the next adjacent frame without significantly affecting the actual output image quality. However, when the phase difference between the first frame to be output and the first output frame is large, compensating for the lead or lag only in the next frame, while ensuring phase synchronization between the output and the frame to be output, can lead to excessively large differences in the number of reference clock cycles between adjacent frames, easily causing screen flickering or black screens. Therefore, when the phase difference between the first frame to be output and the first output frame is large, it is best to compensate for the lead or lag in subsequent consecutive frames to ensure that the frame rate of the output frame can be correctly recognized by the subsequent modules, thus preventing screen flickering, black screens, or distorted images.
[0070] In some optional embodiments of this application, the phase difference can be compared with a preset threshold; when the phase difference is less than the preset threshold, the second output frame is determined to be the frame following the first output frame; when the phase difference is greater than the preset threshold, the number of frames in the second output frame is determined as the target number of frames based on the phase difference, and the target number of frames is not less than two. The preset threshold can be determined through multiple experiments to ensure that the target number of frames is as small as possible without issues such as screen flickering, black screens, or distorted screens in the actual output frame.
[0071] Specifically, when the phase difference is less than a preset threshold, the second output image is one frame, and this frame of the second output image is output within the first number of reference clock cycles. When the phase difference is greater than the preset threshold, the second output image is multiple frames, and it is necessary to determine the sixth number of reference clock cycles corresponding to each frame in the second output image based on the first number and the target number of frames, and output one frame of the second output image within each sixth number of reference clock cycles.
[0072] It should be noted that each module in the screen synchronization output device in this application embodiment corresponds one-to-one with the screen synchronization output method implementation steps in embodiment 1. Since embodiment 1 has been described in detail, some details not shown in this embodiment can be referred to embodiment 1, and will not be elaborated further here.
[0073] Example 3
[0074] According to an embodiment of this application, a screen synchronization output device is also provided. The device includes a memory and a processor, wherein the memory stores a computer program, and the processor is configured to execute the screen synchronization output method of embodiment 1 through the computer program.
[0075] Optionally, during the execution of the computer program, the processor performs the following steps: acquiring a first input screen and a first output screen corresponding to the first input screen; outputting a first output screen based on the first output screen, and determining the phase difference between the first output screen and the first output screen; acquiring a second input screen adjacent to the first input screen and a second output screen corresponding to the second input screen, and determining a first number of reference clock cycles corresponding to the second output screen based on the second output screen and the phase difference; and outputting the second output screen within the first number of reference clock cycles.
[0076] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.
[0077] In the above embodiments of this application, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.
[0078] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. The device embodiments described above are merely illustrative; for example, the division of units can be a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual couplings, direct couplings, or communication connections may be through some interfaces; indirect couplings or communication connections between units or modules may be electrical or other forms.
[0079] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.
[0080] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.
[0081] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard drive, magnetic disk, or optical disk.
[0082] The above are merely preferred embodiments of this application. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of this application, and these improvements and modifications should also be considered within the scope of protection of this application.
Claims
1. A method for synchronized video output, characterized in that, include: Obtain the first input screen and the first output screen corresponding to the first input screen; Output a first output image based on the first output image to be output, and determine the phase difference between the first output image and the first output image; Obtain a second input screen adjacent to the first input screen and a second output screen corresponding to the second input screen, and determine a first number of reference clock cycles corresponding to the second output screen based on the second output screen and the phase difference; The second output screen is output within the first number of reference clock cycles; The length of the reference clock cycle is a constant. Acquiring a first input screen and a first output screen corresponding to the first input screen includes: Obtain the first input frame at the first frame rate; The first output frame at the second frame rate is determined based on the first input frame at the first frame rate; Outputting a first output screen based on the first output screen to be output, including: The first output frame at a third frame rate is output based on the first output frame at the second frame rate; Determining the phase difference between the first image to be output and the first output image includes: The second number of reference clock cycles corresponding to the first frame to be output is determined based on the second frame rate; The third number of reference clock cycles corresponding to the first output frame is determined based on the third frame rate. The phase difference is determined based on the second quantity and the third quantity; Determining a first number of reference clock cycles corresponding to the second output screen based on the second output screen and the phase difference includes: Determine the fourth number of reference clock cycles corresponding to the second output screen; Determine the fifth number of reference clock cycles corresponding to the phase difference; The first quantity is determined based on the fourth quantity and the fifth quantity.
2. The method according to claim 1, characterized in that, Before determining the first number of reference clock cycles corresponding to the second output screen based on the second output screen and the phase difference, the method further includes: The phase difference is compared with a preset threshold. When the phase difference is less than the preset threshold, the second output frame is determined to be the frame following the first output frame; When the phase difference is greater than the preset threshold, the number of frames in the second output screen is determined as the target number of frames based on the phase difference, wherein the target number of frames is not less than two.
3. The method according to claim 2, characterized in that, Outputting the second output screen within the first number of reference clock cycles includes: When the second output frame is one frame, the second output frame is output within the first number of reference clock cycles; When the second output screen consists of multiple frames, a sixth number of reference clock cycles corresponding to each frame in the second output screen is determined based on the first number and the target number of frames, and one frame in the second output screen is output within each of the sixth number of reference clock cycles.
4. A screen synchronization output device, applied to the screen synchronization output method according to claim 1, characterized in that, include: The acquisition module is used to acquire a first input screen and a first output screen corresponding to the first input screen; The first output module is used to output a first output image based on the first output image and to determine the phase difference between the first output image and the first output image. The determining module is used to acquire a second input screen adjacent to the first input screen and a second output screen corresponding to the second input screen, and to determine a first number of reference clock cycles corresponding to the second output screen based on the second output screen and the phase difference. The second output module is used to output the second output screen within the first number of reference clock cycles.
5. A video synchronization output device, characterized in that, include: A memory and a processor, wherein the memory stores a computer program, and the processor is configured to execute the screen synchronization output method according to any one of claims 1 to 3 through the computer program.