Semiconductor device

Abstract

An inventive concept of a semiconductor device includes a first channel pattern and a second channel pattern spaced apart from each other on a substrate, a separation structure between the first channel pattern and the second channel pattern, and a gate electrode on the first channel pattern, the second channel pattern, and the separation structure. The separation structure includes a first pattern adjacent to the first channel pattern and the second channel pattern, and a second pattern between the first channel pattern and the second channel pattern. A portion of an upper surface of the first pattern is at a higher level than an upper surface of the second pattern.

Description

Cross-reference to related applications

[0001] This patent application claims priority to Korean Patent Application No. 10-2025-0021026, filed on February 18, 2025, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure generally relates to a semiconductor device. Background Technology

[0003] Semiconductor devices can include integrated circuits, including metal-oxide-semiconductor field-effect transistors (MOSFETs). As the size of semiconductor devices continues to shrink, the size of MOSFETs also shrinks. This shrinkage of MOSFETs can lead to a degradation in the operating characteristics of semiconductor devices. Therefore, various research efforts are underway to develop semiconductor devices that can overcome the limitations imposed by high integration and improve performance. Summary of the Invention

[0004] In general, this disclosure relates to a semiconductor device having improved electrical properties.

[0005] According to some embodiments, a semiconductor device includes: a first channel pattern and a second channel pattern spaced apart from each other on a substrate; a separation structure between the first channel pattern and the second channel pattern; and a gate electrode on the first channel pattern, the second channel pattern, and the separation structure, wherein the separation structure includes: a first pattern adjacent to the first channel pattern and the second channel pattern; and a second pattern between the first channel pattern and the second channel pattern, and a portion of the upper surface of the first pattern is located at a higher height than the upper surface of the second pattern.

[0006] According to some embodiments, this disclosure relates to a semiconductor device, comprising: an active pattern on a substrate; a channel pattern, each including a plurality of semiconductor patterns on the active pattern; a separation structure between the channel patterns; a gate electrode on the channel patterns and the separation structure; a first gate dicing pattern overlapping the separation structure; and a second gate dicing pattern spaced apart from the first gate dicing pattern and penetrating the gate electrode, wherein the separation structure includes a first pattern adjacent to the channel pattern and a second pattern spaced apart from the channel pattern, and the uppermost surface of the first pattern is coplanar with the upper surface of the gate electrode.

[0007] According to some embodiments, this disclosure relates to a semiconductor device comprising: a first active pattern and a second active pattern spaced apart from each other on a substrate; a first channel pattern on the first active pattern and a second channel pattern on the second active pattern; a first source / drain pattern between the first channel patterns and a second source / drain pattern between the second channel patterns; a separation structure between adjacent first and second channel patterns in a first direction; a gate electrode on the first and second channel patterns and the separation structure; a gate capping pattern on the gate electrode; a first gate dicing pattern on at least one separation structure of the separation structure; and a second gate dicing pattern spaced apart from the separation structure and penetrating the gate electrode, wherein each separation structure includes a first pattern and a second pattern filling the interior of the first pattern, and a portion of the first pattern extends onto the second pattern.

[0008] According to some embodiments, this disclosure relates to a method of manufacturing a semiconductor device, the method comprising: forming a channel pattern on an active pattern; forming a separation structure between the channel patterns; forming a gate electrode on the channel pattern and the separation structure; and forming a gate dicing pattern that penetrates the gate electrode and contacts the separation structure, wherein the separation structure includes a first pattern adjacent to the channel pattern and a second pattern in the first pattern, and a portion of the first pattern further extends onto the second pattern.

[0009] According to some embodiments, this disclosure relates to a method of manufacturing a semiconductor device, wherein forming a discrete structure may include forming a first layer and a second layer on a channel pattern.

[0010] According to some embodiments, this disclosure relates to a method of manufacturing a semiconductor device, wherein a first pattern may be formed by a first layer and a second pattern may be formed by a second layer.

[0011] According to some embodiments, this disclosure relates to a method of manufacturing a semiconductor device, wherein each channel pattern may include a plurality of semiconductor patterns, and the method further includes forming a sacrificial pattern between the plurality of semiconductor patterns.

[0012] According to some embodiments, this disclosure relates to a method of manufacturing a semiconductor device, wherein the sacrificial pattern may include a material having etch selectivity relative to a first pattern and a second pattern.

[0013] According to some embodiments, this disclosure relates to a method of manufacturing a semiconductor device, wherein a gate dicing pattern may be formed from a portion of a first pattern in a self-aligned manner.

[0014] According to some embodiments, this disclosure relates to a method of manufacturing a semiconductor device, the method comprising forming a gate insulating layer covering the channel pattern between forming a channel pattern and forming a discrete structure. Attached Figure Description

[0015] The exemplary embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0016] Figure 1 This is a plan view showing an example of a semiconductor device according to some embodiments.

[0017] Figure 2A , Figure 2B , Figure 2C , Figure 2D and Figure 2E It is based on some implementation methods Figure 1 The cross-sectional views taken from lines A-A', B-B', C-C', D-D', and E-E'.

[0018] Figure 3A , Figure 3B , Figure 3C , Figure 3D and Figure 3E This is an enlarged view used to illustrate a portion of a semiconductor device according to some embodiments.

[0019] Figure 4A , Figure 4B , Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 6A , Figure 6B , Figure 6C , Figure 7A , Figure 7B , Figure 7C , Figure 8A , Figure 8B , Figure 8C , Figure 9A , Figure 9B , Figure 9C , Figure 10A , Figure 10B , Figure 10C , Figure 11A , Figure 11B , Figure 11C , Figure 12A , Figure 12B and Figure 12C This is a diagram illustrating an example of a method for manufacturing a semiconductor device according to some embodiments. Detailed Implementation

[0020] In the following description, exemplary embodiments will be described in detail with reference to the accompanying drawings.

[0021] Figure 1 This is a plan view showing an example of a semiconductor device according to some embodiments. Figures 2A to 2EThis is an example of a semiconductor device according to some embodiments. Figure 1 The cross-sectional view taken from lines A-A', B-B', C-C', D-D', and E-E'.

[0022] exist Figure 1 and Figures 2A to 2E In this disclosure, the semiconductor device may include a substrate 100. A plurality of logic transistors constituting a logic circuit may be disposed on the substrate 100. For example, the substrate 100 may be a substrate comprising a silicon-based insulating layer. More specifically, the substrate 100 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. In this disclosure, each of phrases such as “A or B,” “at least one of A and B,” “at least one of A or B,” “A, B, or C,” “at least one of A, B, and C,” and “at least one of A, B, or C” may include any one of the items listed together in the corresponding phrase or all possible combinations thereof.

[0023] The substrate 100 may have the shape of a plate extending along a plane defined by a first direction D1 and a second direction D2. The upper surface of the substrate 100 may be parallel to the first direction D1 and the second direction D2. The third direction D3 may be orthogonal to the upper surface of the substrate 100. For example, the first direction D1, the second direction D2, and the third direction D3 may be orthogonal to each other. In this specification, the first direction D1 and the second direction D2 may be referred to as the horizontal direction. The third direction D3 may be referred to as the vertical direction.

[0024] An active pattern AP can be disposed on the substrate 100. Each active pattern AP may include a first active pattern AP1 and a second active pattern AP2. The active pattern AP may be defined by a first trench TR1 and a second trench TR2 in the substrate 100. For example, the first active pattern AP1 and the second active pattern AP2 of each of the active patterns AP that are adjacent to each other in the first direction D1 may be defined by the first trench TR1. The active patterns AP that are adjacent to each other in the first direction D1 may be defined by the second trench TR2.

[0025] Each of the first active pattern AP1 and the second active pattern AP2 of the active pattern AP can extend in the second direction D2. The first active pattern AP1 and the second active pattern AP2 of the active pattern AP can be part of the substrate 100. For example, the first active pattern AP1 and the second active pattern AP2 of the active pattern AP can be part of the substrate 100 that protrudes in a third direction D3 perpendicular to the upper surface of the substrate 100. However, for ease of illustration, the substrate 100 and the first active pattern AP1 and the second active pattern AP2 are implemented with different configurations.

[0026] A device isolation pattern ST may be disposed on a substrate 100. The device isolation pattern ST may fill a first trench TR1 and a second trench TR2. An active pattern AP and its first active pattern AP1 and second active pattern AP2 may be spaced apart from each other in a first direction D1. In a plan view, the device isolation pattern ST may surround the first active pattern AP1 and the second active pattern AP2 of the active pattern AP. The upper surface of the device isolation pattern ST may be coplanar with, but is not limited to, the upper surfaces of the first active pattern AP1 and the second active pattern AP2 of the active pattern AP. For example, the device isolation pattern ST may include an insulating material, such as silicon oxide.

[0027] The first channel pattern CH1 and the second channel pattern CH2 can be respectively disposed on the first active pattern AP1 and the second active pattern AP2 of the active pattern AP. The first channel pattern CH1 and the second channel pattern CH2 can be adjacent to each other in the first direction D1. The first channel pattern CH1 and the second channel pattern CH2 adjacent to each other in the first direction D1 can be spaced apart from each other in the first direction D1, and a separation structure SS, described later, can be inserted therebetween. Each of the first channel pattern CH1 and the second channel pattern CH2 can be set to multiple, and can be spaced apart from each other in the second direction D2.

[0028] Each of the first channel pattern CH1 and the second channel pattern CH2 may include a first semiconductor pattern SP1, a second semiconductor pattern SP2, a third semiconductor pattern SP3, and a fourth semiconductor pattern SP4. The first to fourth semiconductor patterns SP1, SP2, SP3, and SP4 may be spaced apart from each other in a vertical direction (e.g., third direction D3). For example, the first to fourth semiconductor patterns SP1, SP2, SP3, and SP4 may include crystalline silicon. According to some embodiments, each of the first to fourth semiconductor patterns SP1, SP2, SP3, and SP4 may be a nanosheet.

[0029] First source / drain pattern SD1 and second source / drain pattern SD2 can be respectively disposed on first active pattern AP1 and second active pattern AP2 of active pattern AP. First source / drain pattern SD1 can be located on both sides of first channel pattern CH1 and electrically connected to first channel pattern CH1. Second source / drain pattern SD2 can be located on both sides of second channel pattern CH2 and electrically connected to second channel pattern CH2. For example, each first source / drain pattern SD1 can be located between multiple first channel patterns CH1, and each second source / drain pattern SD2 can be located between multiple second channel patterns CH2. For example, first source / drain pattern SD1 and second source / drain pattern SD2 can include at least one of silicon and silicon germanium.

[0030] The first source / drain pattern SD1 and the second source / drain pattern SD2 may include impurity regions having a first conductivity type (e.g., p-type) or a second conductivity type (e.g., n-type). According to some embodiments, the first source / drain pattern SD1 and the second source / drain pattern SD2 may include impurity regions having the same conductivity type. According to some embodiments, the first source / drain pattern SD1 and the second source / drain pattern SD2 may include impurity regions having different conductivity types.

[0031] Separation structures SS can be disposed on substrate 100. Each separation structure SS can be located between a first channel pattern CH1 and a second channel pattern CH2 that are adjacent to each other in a first direction D1. In a planar view, the separation structures SS can be spaced apart from each other in the first direction D1 and the second direction D2, and can be arranged in two dimensions. Furthermore, each separation structure SS can have a columnar shape extending in a third direction D3. Accordingly, the first channel pattern CH1 and the second channel pattern CH2 that are adjacent to each other in the first direction D1 can be spaced apart from each other. Each separation structure SS can overlap with a device isolation pattern ST in a first trench TR1. For example, the separation structure SS can include, but is not limited to, an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, and silicon oxycarbide (SiOC).

[0032] Each separate structure SS may include a first pattern PT1 and a second pattern PT2. The first pattern PT1 may be adjacent to a first channel pattern CH1 and a second channel pattern CH2. The second pattern PT2 may be located inside the first pattern PT1. For example, the first pattern PT1 may be located between the second pattern PT2 and the first channel pattern CH1, and between the second pattern PT2 and the second channel pattern CH2. That is, the first pattern PT1 may extend between the second pattern PT2 and the first channel pattern CH1 and the second channel pattern CH2. The second pattern PT2 may be spaced apart from the first channel pattern CH1 and the second channel pattern CH2. According to some embodiments, the first pattern PT1 may have a cylindrical shape including an inner surface, and the second pattern PT2 may have a cylindrical shape that fills the inner surface of the first pattern PT1.

[0033] Gate electrodes GE can be disposed on a first channel pattern CH1, a second channel pattern CH2, and a discrete structure SS. Each gate electrode GE can extend in a first direction D1 and be spaced apart in a second direction D2. The gate electrodes GE can surround three surfaces of each of the first semiconductor patterns to the fourth semiconductor patterns SP1, SP2, SP3, and SP4 in each of the first and second channel patterns CH1 and CH2. For example, the gate electrodes GE can be located on the upper surface, lower surface, and side surface of each of the first to the fourth semiconductor patterns SP1, SP2, SP3, and SP4. Each gate electrode GE can be spaced apart in the first direction D1 by a second gate cleaved pattern CT2 between a first gate cleaved pattern CT1 and / or an active pattern AP on the discrete structure SS.

[0034] Each gate electrode GE may include a metal pattern MP and a fill metal pattern FMP on the metal pattern MP. The metal pattern MP may fill between the first to fourth semiconductor patterns SP1, SP2, SP3, and SP4 of each of the first channel patterns CH1 and the second channel patterns CH2. The fill metal pattern FMP may cover the metal pattern MP. For example, the fill metal pattern FMP may not be disposed between the first to fourth semiconductor patterns SP1, SP2, SP3, and SP4 of each of the first channel patterns CH1 and the second channel patterns CH2. The fill metal pattern FMP may be spaced apart from the first to fourth semiconductor patterns SP1, SP2, SP3, and SP4 of each of the first channel patterns CH1 and the second channel patterns CH2 by the metal pattern MP therebetween.

[0035] The portion of the gate electrode GE that overlaps with the first channel pattern CH1 and the second channel pattern CH2 may have a first width W1 in the second direction D2. The gate insulating layer GI may be located on both sides of this portion of the gate electrode GE. When the first gate dicing pattern CT1 is not provided, another portion of the gate electrode GE that overlaps with the separation structure SS may have a second width W2 in the second direction D2. The first pattern PT1 and the gate insulating layer GI may be located on both sides of this other portion of the gate electrode GE. According to the first pattern PT1, the first width W1 of one portion of the gate electrode GE may be greater than the second width W2 of the other portion of the gate electrode GE. For example, the gate electrode GE may have different widths along the horizontal direction.

[0036] According to some embodiments, the metal pattern MP may include a work function metal that adjusts the threshold voltage of the transistor. The composition of the work function metal can be adjusted to achieve a target threshold voltage for the transistor. For example, the metal pattern MP may include titanium nitride (TiN), tantalum nitride (TaN), titanium oxynitride (TiON), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tungsten carbonitride (WCN), or molybdenum nitride (MoN). In some embodiments, the metal pattern MP may include metal oxynitride, metal carbon oxide, or metal carbonitride. The filled metal pattern FMP may include a material with lower contact resistance compared to the metal pattern MP. For example, the filled metal pattern FMP may include a low-resistance metal, such as at least one of aluminum (Al), tungsten (W), titanium (Ti), and tantalum (Ta).

[0037] The inner gate spacer IGS can be disposed between the metal pattern MP of the gate electrode GE and the first source / drain pattern SD1, and between the metal pattern MP of the gate electrode GE and the second source / drain pattern SD2. For example, the inner gate spacer IGS may not be disposed between the first channel pattern CH1 and the second channel pattern CH2 and the separation structure SS. According to some embodiments, the inner gate spacer (IGS) can be omitted.

[0038] A gate insulating layer GI can be disposed between the gate electrode GE and the first to fourth semiconductor patterns SP1, SP2, SP3, and SP4 of the first channel pattern CH1 and the second channel pattern CH2. The gate insulating layer GI can surround all four surfaces of each of the first to fourth semiconductor patterns SP1, SP2, SP3, and SP4. For example, the gate insulating layer GI can cover the upper, lower, and side surfaces of each of the first to fourth semiconductor patterns SP1, SP2, SP3, and SP4. For example, the gate insulating layer GI can comprise silicon oxide, silicon oxynitride, and / or a high-k material. In this document, a high-k material can be a material with a dielectric constant higher than that of silicon oxide.

[0039] The gate insulating layer GI can contact each discrete structure SS. For example, the gate insulating layer GI can be disposed on the lower surface of each discrete structure SS. The gate insulating layer GI can extend between the discrete structure SS and the capping insulating layer CI, which will be described later. The gate insulating layer GI can partially cover the outer surface of the first pattern PT1. The gate insulating layer GI can extend from the region between the lower surface of the discrete structure SS and the device isolation pattern ST to the region between the gate electrode GE and the active pattern AP.

[0040] A gate capping pattern GP can be disposed on the gate electrode GE. Each gate capping pattern in the gate capping pattern GP can extend along the gate electrode GE in a first direction D1 and can be spaced apart from each other in a second direction D2. The gate capping pattern GP can cover the upper surface of each gate electrode GE. For example, the gate capping pattern GP can include at least one of SiON, SiCN, SiOCN, and SiN.

[0041] An upper insulating pattern 110 may be disposed on the substrate 100. The upper insulating pattern 110 may cover the first source / drain pattern SD1 and the second source / drain pattern SD2. Furthermore, the upper insulating pattern 110 may be located between the discrete structures SS. The upper surface of the upper insulating pattern 110 may be substantially coplanar with the upper surface of the gate cap pattern GP. For example, the upper insulating pattern 110 may include an insulating material, such as silicon oxide.

[0042] A capping insulating layer CI can be disposed between the upper insulating pattern 110 and the first source / drain pattern SD1 and the second source / drain pattern SD2. The capping insulating layer CI can extend on the device isolation pattern ST and can cover the first source / drain pattern SD1 and the second source / drain pattern SD2. Furthermore, the capping insulating layer CI can extend between the upper insulating pattern 110 and the separation structure SS. For example, the capping insulating layer CI can include an insulating material different from the upper insulating pattern 110. According to some embodiments, the capping insulating layer CI can include a single layer or multiple layers of different insulating materials.

[0043] A first gate dicing pattern CT1 may be disposed on a discrete structure SS. Each first gate dicing pattern CT1 may overlap with each discrete structure SS. The first gate dicing pattern CT1 may penetrate a portion of the gate cap pattern GP and a portion of the gate electrode GE to contact the discrete structure SS. The gate electrodes GE corresponding to each of the first channel pattern CH1 and the second channel pattern CH2 may be spaced apart from each other in a first direction D1 by the first gate dicing pattern CT1. In a plan view, each first gate dicing pattern CT1 may have a circular or elliptical shape. Accordingly, the first gate dicing pattern CT1 can be easily formed in a small size. For example, the first gate dicing pattern CT1 may not be disposed on some of the discrete structures SS. That is, one of the first gate dicing patterns CT1 may be disposed on at least one discrete structure SS.

[0044] When the first gate dicing pattern CT1 is not provided, the gate electrode GE may not be spaced apart by the first gate dicing pattern CT1 in the first direction D1. The gate electrode GE may cover the discrete structure SS. Adjacent gate electrodes GE in the first direction D1, as well as the first channel pattern CH1 and the second channel pattern CH2, may constitute part of a single transistor. Accordingly, a transistor with a relatively long channel length can be formed.

[0045] A second gate dicing pattern CT2 can be disposed on the substrate 100. The second gate dicing pattern CT2 can extend in a second direction D2 between the first gate dicing patterns CT1. The second gate dicing pattern CT2 can be horizontally spaced from the first gate dicing patterns CT1 and the separation structure SS. In a plan view, the second gate dicing pattern CT2 can have a linear or strip-like shape. The second gate dicing pattern CT2 can penetrate the gate cap pattern GP and the gate electrode GE. The second gate dicing pattern CT2 can extend on top of the device isolation pattern ST. The gate electrodes GE on different active patterns AP can be spaced apart from each other in a first direction D1, and the second gate dicing pattern CT2 is located between them. For example, the vertical length of the second gate dicing pattern CT2 in a third direction D3 can be greater than the vertical length of each first gate dicing pattern CT1 in a third direction D3.

[0046] According to some embodiments, the first gate dicing pattern CT1 and the second gate dicing pattern CT2 may include at least one of SiON, SiCN, SiOCN, and SiN, and are the same as the gate capping pattern GP. In this case, the interface between the first gate dicing pattern CT1 and the second gate dicing pattern CT2 and the gate capping pattern GP may not be visible. In some embodiments, the first gate dicing pattern CT1 and the second gate dicing pattern CT2 may include at least one of SiON, SiCN, SiOCN, and SiN, and are different from the gate capping pattern GP. In this case, the interface between the first gate dicing pattern CT1 and the second gate dicing pattern CT2 and the gate capping pattern GP is visible.

[0047] An active contact AC may be disposed in the upper insulating pattern 110. The active contact AC may penetrate the upper insulating pattern 110 and extend to the corresponding first source / drain pattern SD1 and second source / drain pattern SD2. The active contact AC may be electrically connected to the corresponding first source / drain pattern SD1 and second source / drain pattern SD2. For example, the active contact AC may include at least one of a metallic material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.) and a metal nitride (e.g., nitrides of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.).

[0048] The gate contact GC can be disposed within the gate cap pattern GP. The gate contact GC can penetrate the gate cap pattern GP and be electrically connected to the corresponding gate electrode GE. For example, the gate contact GC can include at least one of a metallic material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.) and a metal nitride (e.g., nitrides of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.).

[0049] A metal layer ML can be disposed on the upper insulating pattern 110. The metal layer ML may include wiring structures therein. The wiring structures of the metal layer ML can be connected to the active contacts AC and the gate contact GC. For example, the metal layer ML can be electrically connected to the first source / drain pattern SD1 and the second source / drain pattern SD2 and the gate electrode GE through the active contacts AC and the gate contact GC. Adjacent transistors can send electrical signals to and receive electrical signals from each other through the metal layers ML. According to some embodiments, multiple metal layers ML can be disposed and stacked on a third direction D3.

[0050] Figures 3A to 3E This is an enlarged view used to illustrate a portion of a semiconductor device according to some embodiments. Figure 3A yes Figure 2A A magnified view of region X1 in the image. Figure 3B yes Figure 2D A magnified view of region X2 in the image. Figure 3C yes Figure 2E A magnified view of the Y1 region. Figure 3D yes Figure 2D A magnified view of the Y2 region. Figure 3E yes Figure 2E A magnified view of the Y1 region.

[0051] exist Figures 3A to 3D In the separation structure SS, the first pattern PT1 may have a first side surface PT1S1 perpendicular to the first direction D1 and a second side surface PT1S2 perpendicular to the second direction D2. For example, the first side surface PT1S1 of the first pattern PT1 may be adjacent to the first channel pattern CH1 and the second channel pattern CH2. The second side surface PT1S2 of the first pattern PT1 may be adjacent to the capping insulation layer CI and the upper insulation pattern 110. The second side surface PT1S2 of the first pattern PT1 may extend further than the first side surface PT1S1 in the third direction D3.

[0052] The first pattern PT1 of the separated structure SS may have a first upper surface PT1U1 and a second upper surface PT1U2 located at a height higher than the first upper surface PT1U1. In other words, the first pattern PT1 may have upper surfaces with different heights. In this specification, height may refer to... Figure 2A The height (or length) of the upper surface or lower surface of the substrate 100 in the third direction D3. For example, the second upper surface PT1U2 of the first pattern PT1 can correspond to the uppermost surface of the first pattern PT1.

[0053] The first upper surface PT1U1 of the first pattern PT1 can be at the same height as the upper surface PT2U of the second pattern PT2 and the lower surface CT1L of the first gate dicing pattern CT1. The second upper surface PT1U2 of the first pattern PT1 can be at a higher height than the upper surface PT2U of the second pattern PT2 and the lower surface CT1L of the first gate dicing pattern CT1. The second upper surface PT1U2 of the first pattern PT1 can be coplanar with the upper surface GEU of the gate electrode GE. The second upper surface PT1U2 of the first pattern PT1 can be in contact with the gate capping pattern GP.

[0054] A portion of the first pattern PT1 can extend further onto the second pattern PT2. Therefore, a portion of the upper surface of the first pattern PT1 can be located at a higher height than the upper surface PT2U of the second pattern PT2.

[0055] The upper surface PT2U of the second pattern PT2 in the separated structure SS can be located at a height higher than the lower surface SPL of the fourth semiconductor pattern SP4 of each of the first channel patterns CH1 and the second channel patterns CH2. For example, the upper surface PT2U of the second pattern PT2 can be located between the lower surface SPL and the upper surface SPU of the fourth semiconductor pattern SP4. In some embodiments, the upper surface PT2U of the second pattern PT2 can be substantially coplanar with the upper surface SPU of the fourth semiconductor pattern SP4. In some embodiments, the upper surface PT2U of the second pattern PT2 can be located at a height higher than the upper surface SPU of the fourth semiconductor pattern SP4. That is, the first upper surface PT1U1 of the first pattern PT1 and the upper surface PT2U of the second pattern PT2 can be located at a height higher than the lower surface SPL of the uppermost semiconductor pattern among the plurality of semiconductor patterns of each of the first channel patterns CH1 and the second channel patterns CH2.

[0056] The gate insulating layer GI can be located between the third semiconductor pattern SP3 and the fourth semiconductor pattern SP4 of the first channel pattern CH1 and the second channel pattern CH2 and the first pattern PT1 of the discrete structure SS, and between the capping insulating layer CI and the first pattern PT1 of the discrete structure SS. For example, the gate insulating layer GI can partially contact the first side surface PT1S1 of the first pattern PT1 and surround it. Figure 2AEach of the first semiconductor patterns CH1 and the second channel pattern CH2 in the first semiconductor pattern PT1, SP2, SP3, and SP4 is represented. The gate insulating layer GI may not extend into the recessed region ID of the first pattern PT1, which will be described later. Furthermore, the gate insulating layer GI may extend in a third direction D3 between the capping insulating layer CI and the first pattern PT1. The gate insulating layer GI may contact the second side surface PT1S2 of the first pattern PT1. The gate insulating layer GI may be aligned with the second upper surface PT1U2 of the first pattern PT1. Accordingly, the gate insulating layer GI may contact at least a portion of the side surface of the first pattern PT1.

[0057] The first pattern PT1 of the separated structure SS may have a recessed region ID on its first side surface PT1S1. For example, the recessed region ID may be a region recessed towards the second pattern PT2 on the first side surface PT1S1 of the first pattern PT1. Therefore, the first side surface PT1S1 of the first pattern PT1 may have a groove. In some embodiments, the first pattern PT1 may not have a recessed region ID on its second side surface PT1S2. The second side surface PT1S2 of the first pattern PT1 may not have a groove, but instead have a constant slope.

[0058] The recessed region ID of the first pattern PT1 can be located between the third semiconductor pattern SP3 and the fourth semiconductor pattern SP4 of the first channel pattern CH1 and the second channel pattern CH2. The recessed region ID can be spaced apart from the third semiconductor pattern SP3 and the fourth semiconductor pattern SP4 on a third-direction D3. In other words, the recessed region ID can be vertically aligned with... Figure 2A The first semiconductor patterns of the first channel pattern CH1 and the second channel pattern CH2 are spaced apart to the fourth semiconductor patterns SP1, SP2, SP3, and SP4. Based on the recessed region ID of the first pattern PT1, the metal pattern MP of each gate electrode GE can be closer to the discrete structure SS than the third semiconductor pattern SP3 and the fourth semiconductor pattern SP4 of the first channel pattern CH1 and the second channel pattern CH2. For example, the metal pattern MP of each gate electrode GE can be closer than... Figure 2A The first semiconductor patterns CH1 and CH2, and the fourth semiconductor patterns SP1, SP2, SP3, and SP4, are closer to the second pattern PT2 of the discrete structure SS. Therefore, the overlap length between the gate electrode GE and the first channel pattern CH1 and the second channel pattern CH2 can be increased. Correspondingly, the gate controllability of the gate electrode GE can be improved.

[0059] The first gate diced pattern CT1 can be located on and in contact with the discrete structure SS. The lower surface CT1L of the first gate diced pattern CT1 can be in contact with the first upper surface PT1U1 of the first pattern PT1 and the upper surface PT2U of the second pattern PT2. The lower side surface CT1S of the first gate diced pattern CT1 can be in contact with the metal pattern MP of each gate electrode GE and the first pattern PT1 of the discrete structure SS. For example, the first side surface PT1S1 of the first pattern PT1 may not extend to the lower side surface CT1S of the first gate diced pattern CT1, but the second side surface PT1S2 of the first pattern PT1 may further extend to the lower side surface CT1S of the first gate diced pattern CT1. That is, a portion of the first pattern PT1 can partially cover the lower side surface CT1S of the first gate diced pattern CT1.

[0060] In this paper, the first gate dicing pattern CT1 can be a structure used for electrically isolating adjacent gate electrodes GE. When the first gate dicing pattern CT1 is provided, the gate electrodes GE on the first channel pattern CH1 and the second channel pattern CH2 can be spaced apart from each other in the first direction D1 to operate as independent transistors. When the first gate dicing pattern CT1 is not provided, the gate electrodes GE on the first channel pattern CH1 and the second channel pattern CH2 can be connected together to operate as a single transistor. Therefore, transistors with different channel lengths can be formed together in a single logic cell.

[0061] The first pattern PT1 of the separation structure SS prevents a portion of the gate electrode GE from remaining on the lower surface CT1S of the first gate dicing pattern CT1. Therefore, the gate electrode GE on the first channel pattern CH1 and the gate electrode GE on the second channel pattern CH2 can be electrically separated from each other. More specifically, to prevent parasitic capacitance caused by the residual portion of the gate electrode GE, the separation structure SS can be formed before forming the gate electrode GE. The portion of the gate electrode GE that overlaps with the separation structure SS through the first pattern PT1, which has a different upper surface height, can be located within the first pattern PT1.

[0062] The portion of the gate electrode GE located between the second side surfaces PT1S2 of the first pattern PT1 can have a relatively small second width W2 according to the first pattern PT1. Therefore, the size of the first gate dicing pattern CT1 required to separate the gate electrode GE in the first direction D1 can be reduced. Furthermore, the first gate dicing pattern CT1 can be formed in a self-aligned manner through the second side surfaces PT1S2 of the first pattern PT1. Therefore, the first gate dicing pattern CT1 can be easily formed in a smaller size, and a semiconductor device with improved electrical characteristics and integration can be provided.

[0063] exist Figure 3E In the separation structure SS, the first pattern PT1 may have a recessed region ID recessed from its first side surface PT1S1. Each recessed region ID of the first pattern PT1 may be recessed from the first side surface PT1S1 of the first pattern PT1 toward the second pattern PT2. According to some embodiments, each recessed region ID of the first pattern PT1 may be further recessed in a third direction D3. Each recessed region ID of the first pattern PT1 may be a region recessed in both the first direction D1 and the third direction D3. In this case, the inner surface of each recessed region ID may be a curved surface, but is not limited thereto.

[0064] According to some embodiments, the second pattern PT2 of the separated structure SS may further include a protrusion at its top. For example, the protrusion of the second pattern PT2 may extend into the metal pattern MP of the gate electrode GE. In this case, the second pattern PT2 may have an upper surface PT2U that is not parallel to the first direction D1 and the second direction D2. For example, the upper surface PT2U of the second pattern PT2 may be an uneven surface with a non-constant slope. Therefore, the first upper surface PT1U1 of the first pattern PT1 and the upper surface PT2U of the second pattern PT2 may not be coplanar. The upper surface PT2U of the second pattern PT2 may be located at a higher height than the first upper surface PT1U1 of the first pattern PT1.

[0065] When the first gate dicing pattern CT1 is disposed on the discrete structure SS, the protrusion of the second pattern PT2 is not visible. In other words, when the first gate dicing pattern CT1 is not disposed, the protrusion of the second pattern PT2 of the discrete structure SS is visible.

[0066] Figures 4A to 12C This is a diagram illustrating an example of a method for manufacturing a semiconductor device according to some embodiments. Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A and Figure 12A It is along Figure 1 The cross-sectional view taken by line A-A' in the diagram. Figure 5B It is along Figure 1 The cross-sectional view taken by line B-B' in the diagram. Figure 4B , Figure 5C , Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B and Figure 11B It is along Figure 1 The cross-sectional view taken from line C-C' in the diagram. Figure 5D, Figure 6C , Figure 7C , Figure 8C , Figure 9C , Figure 10C , Figure 11C and Figure 12B It is along Figure 1 The cross-sectional view taken by line D-D' in the diagram. Figure 12C It is along Figure 1 The cross-sectional view taken from line E-E' in the diagram.

[0067] exist Figure 4A and Figure 4B The substrate 100 may be provided. The upper surface of the substrate 100 may be parallel to a first direction D1 and a second direction D2 that intersect each other. The upper surface of the substrate 100 may be perpendicular to a third direction D3. For example, the first direction D1, the second direction D2, and the third direction D3 may be orthogonal to each other. The substrate 100 may be a substrate including silicon, germanium, silicon-germanium, etc., or a compound semiconductor substrate, but is not limited thereto.

[0068] A stacked pattern STP can be formed on a substrate 100. Forming the stacked pattern STP may include: alternately forming a semiconductor layer SL and a sacrificial layer SAL on the substrate 100, and performing a patterning process. The patterning process may include removing the top of the substrate 100 along with the semiconductor layer SL and the sacrificial layer SAL. This forms an active pattern AP that includes a first active pattern AP1 and a second active pattern AP2, and a first trench TR1 and a second trench TR2 defining the active pattern AP. Each of the first active pattern AP1 and the second active pattern AP2 of the active pattern AP may extend in a second direction D2.

[0069] The stacked pattern STP may include alternating semiconductor layers SL and sacrificial layers SAL stacked on a third-direction D3. The sacrificial layer SAL may include a material that is etch-selective relative to the semiconductor layers SL. In the process for removing the sacrificial layer SAL described below, the semiconductor layers SL may not be removed or may be removed in small amounts. For example, the semiconductor layers SL may include one of silicon, germanium, and silicon-germanium, while the sacrificial layer SAL may include another of silicon, germanium, and silicon-germanium.

[0070] Device isolation pattern ST can be formed in a first trench TR1 and a second trench TR2. Device isolation pattern ST can fill each of the first trench TR1 and the second trench TR2. Forming device isolation pattern ST may include: forming an insulating layer covering the first trench TR1, the second trench TR2 and the stacked pattern STP, and performing a planarization process on the insulating layer to expose the stacked pattern STP again.

[0071] Then, a first sacrificial pattern PP1 can be formed covering the stacked pattern STP and the device isolation pattern ST. The upper surface of the first sacrificial pattern PP1 can be located at a higher height than the upper surface of the stacked pattern STP. For example, the first sacrificial pattern PP1 can include amorphous silicon and / or polycrystalline silicon.

[0072] exist Figure 5A , Figure 5B , Figure 5C and Figure 5D In this process, a mask pattern can be formed on the first sacrificial pattern PP1, and an etching process can be performed using the mask pattern. The etching process may include removing a portion of the stacked pattern STP and a portion of the first active pattern AP1 and the second active pattern AP2.

[0073] A sacrificial contact pattern PH can be formed in a first active pattern AP1 and a second active pattern AP2. The sacrificial contact pattern PH may include a material that has etch selectivity relative to the first active pattern AP1 and the second active pattern AP2. For example, the sacrificial contact pattern PH may be formed by an epitaxial growth process and may include silicon germanium.

[0074] A first source / drain pattern SD1 and a second source / drain pattern SD2 can be formed on each sacrificial contact pattern PH. The sacrificial contact pattern PH can be used as a seed layer to form the first source / drain pattern SD1 and the second source / drain pattern SD2 in a selective epitaxial growth (SEG) process. Each of the first source / drain pattern SD1 and the second source / drain pattern SD2 can be located between stacked patterns STP.

[0075] During the formation of the first source / drain pattern SD1 and the second source / drain pattern SD2, dopants can be implanted in situ into the first source / drain pattern SD1 and the second source / drain pattern SD2. However, this disclosure is not limited to this, and dopants can also be implanted after the formation of the first source / drain pattern SD1 and the second source / drain pattern SD2.

[0076] Then, a capping insulating layer CI can be formed on the substrate 100. The capping insulating layer CI can cover the first source / drain pattern SD1 and the second source / drain pattern SD2, the first sacrificial pattern PP1 and the device isolation pattern ST with a uniform thickness.

[0077] An upper insulating pattern 110 may be formed on a first source / drain pattern SD1 and a second source / drain pattern SD2. The upper insulating pattern 110 may cover the capping insulating layer CI. Forming the upper insulating pattern 110 may include performing a planarization process on the upper insulating pattern 110. The planarization process may include re-exposing the first sacrificial pattern PP1.

[0078] The exposed first sacrificial pattern PP1 can be selectively removed. Removing the first sacrificial pattern PP1 can include a wet etching process that selectively removes polysilicon using an etchant. By removing the first sacrificial pattern PP1, an external region ORG can be formed. Due to the external region ORG, the stacked pattern STP can be exposed to the outside.

[0079] The sacrificial layer SAL of the stacked pattern STP exposed through the external region ORG can be selectively removed. The sacrificial layer SAL can be selectively removed to form the internal region IRG. The etching process for selectively removing the sacrificial layer SAL can remove only the sacrificial layer SAL while completely preserving the semiconductor layer SL. The etching process for removing the sacrificial layer SAL can have a high etching rate for silicon-germanium. The remaining semiconductor layer SL can be formed from the first to fourth semiconductor patterns SP1, SP2, SP3, and SP4. Correspondingly, a first channel pattern CH1 and a second channel pattern CH2, each comprising the first to fourth semiconductor patterns SP1, SP2, SP3, and SP4, can be formed.

[0080] exist Figure 6A , Figure 6B and Figure 6C In this process, an inner gate spacer IGS can be formed in the inner region IRG. The inner gate spacer IGS can be located between and contact the first source / drain pattern SD1 (or the second source / drain pattern SD2). For example, the inner gate spacer IGS can include silicon oxide and a low-k material.

[0081] After forming the inner gate spacer IGS, a gate insulating layer GI with a uniform thickness can be formed in the inner region IRG and the outer region ORG. The gate insulating layer GI can cover the first channel pattern CH1 and the second channel pattern CH2, the active pattern AP, the device isolation pattern ST, and the capping insulating layer CI. For example, the gate insulating layer GI can surround each of the first semiconductor pattern to the fourth semiconductor pattern SP1, SP2, SP3, and SP4 of the first channel pattern CH1 and the second channel pattern CH2.

[0082] After forming the gate insulating layer GI, a second sacrificial pattern PP2 can be formed between the first semiconductor pattern to the fourth semiconductor pattern SP1, SP2, SP3 and SP4 of the first channel pattern CH1 and the second channel pattern CH2. Forming the second sacrificial pattern PP2 may include forming a sacrificial layer on the substrate 100 and performing a wet etching process to partially remove the sacrificial layer.

[0083] A sacrificial layer can fill the inner region IRG between the first semiconductor pattern to the fourth semiconductor patterns SP1, SP2, SP3, and SP4. The sacrificial layer can be formed with a uniform thickness in the remaining regions excluding the inner region IRG. As a result, there is a difference in the etch rate of the sacrificial layer between the inner region IRG and the remaining regions. Accordingly, a portion of the sacrificial layer between the first semiconductor pattern to the fourth semiconductor patterns SP1, SP2, SP3, and SP4 can be retained to form a second sacrificial pattern PP2.

[0084] According to some embodiments, the second sacrificial pattern PP2 may include a material that has etch selectivity relative to the first layer PL1 and the second layer PL2 described below. For example, the second sacrificial pattern PP2 may include at least one of TiN, AlO, SiN, etc.

[0085] exist Figure 7A , Figure 7B and Figure 7C In this process, a first layer PL1 can be formed on the substrate 100. The first layer PL1 can extend on the upper surface of the device isolation pattern ST and on the side surface of the upper insulating pattern 110 on the first channel pattern CH1 and the second channel pattern CH2. The first layer PL1 can partially contact the gate insulating layer GI and the second sacrificial pattern PP2. The first layer PL1 can be formed to have a uniform thickness. For example, the thickness of the first layer PL1 can be from about 1 nm to about 5 nm.

[0086] According to some embodiments, the first layer PL1 may include a material that has etch selectivity relative to the second sacrificial pattern PP2. For example, the first layer PL1 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, etc.

[0087] A first preliminary insulating pattern 120 may be formed on the first layer PL1. Forming the first preliminary insulating pattern 120 may include performing a planarization process on the first preliminary insulating pattern 120. Due to the planarization process, the upper surface of the first preliminary insulating pattern 120 may be located at a lower height than the upper surface of the upper insulating pattern 110. Therefore, a portion of the first layer PL1 may be exposed by the first preliminary insulating pattern 120.

[0088] exist Figure 8A , Figure 8B and Figure 8C In this process, an etching process can be performed on the first layer PL1. The etching process can remove a portion of the first layer PL1 that is exposed by the first preliminary insulating pattern 120. Therefore, the height of the first layer PL1 between the upper insulating patterns 110 can be reduced.

[0089] The first preliminary insulating pattern 120 can be removed, and a second preliminary insulating pattern 130 can be formed. The second preliminary insulating pattern 130 can be located between the first channel pattern CH1 and the second channel pattern CH2, and on the first layer PL1. The second preliminary insulating pattern 130 can expose other portions of the first layer PL1 that cover the first channel pattern CH1, the second channel pattern CH2, and the component isolation pattern ST. For example, the second preliminary insulating pattern 130 may not overlap with the first channel pattern CH1 and the second channel pattern CH2, but is not limited thereto.

[0090] The second preliminary insulating pattern 130 can be used as a mask to perform an etching process. The etching process can remove other portions of the first layer PL1 exposed by the second preliminary insulating pattern 130. Therefore, the portion of the first layer PL1 remaining between the first channel pattern CH1 and the second channel pattern CH2 can be formed as the first pattern PT1. For example, the first pattern PT1 can have a cylindrical shape with an inner surface.

[0091] The first pattern PT1 may have a first upper surface PT1U1 between the first channel pattern CH1 and the second channel pattern CH2 (see reference). Figure 3A (Description) and the second upper surface PT1U2 between the upper insulating patterns 110 (reference) Figure 3B (Description). Therefore, the first pattern PT1 can have an upper surface with different heights.

[0092] exist Figure 9A , Figure 9B and Figure 9C In this process, the second preliminary insulating pattern 130 can be removed, and a second layer PL2 can be formed on the substrate 100. The second layer PL2 can be formed to a uniform thickness by a deposition process. The thickness of the second layer PL2 can be greater than the thickness of the first layer PL1. For example, the thickness of the second layer PL2 can be about 2 nm to about 5 nm.

[0093] More specifically, the second layer PL2 can be formed on the first channel pattern CH1, the second channel pattern CH2, and the device isolation pattern ST with a uniform thickness. In some embodiments, the second layer PL2 can completely fill the inner surface of the first pattern PT1. Therefore, the etching rate of the second layer PL2 between the inside and outside of the first pattern PT1 may differ.

[0094] According to some embodiments, the second layer PL2 may include a material that has etch selectivity relative to the second sacrificial pattern PP2. For example, the second layer PL2 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, etc., which are different from the first layer PL1.

[0095] exist Figure 10A , Figure 10B and Figure 10C In this process, an etching process can be performed on the second layer PL2. A portion of the second layer PL2 can be removed by the etching process. For example, the etching process can be a wet etching process that selectively removes the second layer PL2. As described above, since the second layer PL2 has different exposure areas inside and outside the first pattern PT1, the etching rate may differ. Accordingly, a portion of the second layer PL2 in the first pattern PT1 may remain and form the second pattern PT2. Accordingly, separate structures SS, each comprising the first pattern PT1 and the second pattern PT2, can be formed.

[0096] The second pattern PT2 can have a columnar shape within the first pattern PT1. The upper surface of the second pattern PT2 can be... Figure 3A The first upper surface PT1U1 of the first pattern PT1 is coplanar. The upper surface of the second pattern PT2 can be located at a position greater than that of the first pattern PT1. Figure 3B The second upper surface PT1U2 of the first pattern PT1 has a lower height. A portion of the first pattern PT1 can extend from the second pattern PT2 on the third direction D3. Therefore, a portion of the first pattern PT1 can be exposed by the second pattern PT2.

[0097] According to some implementations, the second pattern PT2 may include a reference. Figure 3E The protrusion described. Furthermore, the etching process can remove a portion of the first pattern PT1 simultaneously with the removal of the second pattern PT2.

[0098] Then, an etching process can be performed to selectively remove the second sacrificial pattern PP2. The internal region IRG between the first semiconductor pattern and the fourth semiconductor patterns SP1, SP2, SP3, and SP4 can be exposed again. The first pattern PT1 and the second pattern PT2 may include a material that is etch-selective relative to the second sacrificial pattern PP2, such that the first pattern PT1 and the second pattern PT2 are not removed.

[0099] After removing the second sacrificial pattern PP2, a portion of the first pattern PT1 can be removed to form the recessed region ID. The first pattern PT1 can be recessed from the side surface of the first pattern PT1 (exposed by the internal region IRG) toward the second pattern PT2.

[0100] exist Figure 11A , Figure 11B and Figure 11C In this configuration, the gate electrode GE can be formed on the first channel pattern CH1, the second channel pattern CH2, and the discrete structure SS. Forming the gate electrode GE may include: forming a metal pattern MP; and forming a fill metal pattern FMP on the metal pattern MP. For example, the metal pattern MP may be formed to have a uniform thickness.

[0101] A metal pattern MP can be disposed between the first semiconductor pattern (CH1) and the second channel pattern (CH2), and the fourth semiconductor pattern (SP1), SP2, SP3, and SP4, filling the internal region IRG. The metal pattern MP can protrude upwards in the region overlapping with the discrete structure SS, with the protruding portion being the extension of the first pattern PT1 from the second pattern PT2 of the discrete structure SS. For example, the metal pattern MP has a lower height in the portion overlapping with the first channel pattern CH1 and the second channel pattern CH2, and a higher height in the portion overlapping with the discrete structure SS.

[0102] The fill metal pattern FMP can cover the metal pattern MP and fill the space on the active pattern AP. Then, a planarization process can be performed on the gate electrode GE. The planarization process can reduce the height of the upper surface of the gate electrode GE. For example, the upper surface of the gate electrode GE can be lower than the upper surface of the upper insulating pattern 110.

[0103] The gate cap pattern GP can be formed on the gate electrode GE. A planarization process can be performed on the gate cap pattern GP so that the upper surface of the gate cap pattern GP can be coplanar with the upper surface of the upper insulating pattern 110.

[0104] exist Figure 12A , Figure 12B and Figure 12C In this process, a mask pattern HMP with openings OP can be formed on a gate cap pattern GP. Each opening OP of the mask pattern HMP can overlap with at least one discrete structure SS. For example, some of the discrete structures SS can overlap with the openings OP of the mask pattern HMP, while other discrete structures SS may not overlap with the openings OP of the mask pattern HMP.

[0105] The number and arrangement of openings OP in the mask pattern HMP of this invention can be configured in various ways. For example, each opening OP of the mask pattern HMP can overlap with every single separation structure SS. In some embodiments, only one of the adjacent separation structures SS in the first direction D1 can overlap with the opening OP of the mask pattern HMP.

[0106] Then, an etching process can be performed using a mask pattern HMP. The etching process can partially remove the gate cap pattern GP and the gate electrode GE to expose the upper surface of the discrete structure SS.

[0107] exist Figure 2A , Figure 2B , Figure 2C and Figure 2DIn this process, a first gate dicing pattern CT1 can be formed that fills the gate capping pattern GP and the gate electrode GE. For example, the first gate dicing pattern CT1 can be formed in a self-aligned manner by extending a portion of the first pattern PT1 further onto a second pattern PT2 of the discrete structure SS. Each first gate dicing pattern CT1 can contact each discrete structure SS.

[0108] The second gate dicing pattern CT2 can be formed between the active patterns AP and penetrate the gate cap pattern GP and the gate electrode GE. The second gate dicing pattern CT2 can further extend into the device isolation pattern ST. In a plan view, the second gate dicing pattern CT2 can extend in the second direction D2.

[0109] Active contacts AC can be formed in the upper insulating pattern 110, while gate contacts GC can be formed in the gate capping pattern GP. Each active contact AC can be connected to at least one of the first source / drain pattern SD1 and the second source / drain pattern SD2, and penetrates the first upper insulating pattern 110. Each gate contact in the gate contacts GC can be connected to the gate electrode GE and penetrate the gate capping pattern GP.

[0110] A metal layer ML can be formed on the upper insulating pattern 110 and the gate cap pattern GP. Forming the metal layer ML may include forming a wiring structure connecting the active contact AC and the gate contact GC.

[0111] In some embodiments, a method of manufacturing a semiconductor device may include forming a discrete structure SS comprising a first pattern PT1 and a second pattern PT2 prior to forming a gate electrode GE. A portion of the first pattern PT1 extends vertically from the second pattern PT2, such that the gate electrode GE can be formed with a narrower width. Therefore, the first gate dicing pattern CT1, electrically separated from the gate electrode GE, is formed with a smaller size, and parasitic capacitance due to residual portions of the gate electrode GE is prevented. Thus, the electrical characteristics and integration density of the semiconductor device can be improved.

[0112] Although this disclosure contains numerous specific implementation details, these details should not be construed as limiting the scope of the claims, their equivalents, and the claims described later. In a single implementation, specific features described in the context of a standalone implementation of this disclosure may also be combined. Conversely, different features described in a single implementation context may also be implemented individually in multiple implementations, or in appropriate sub-combinations. Furthermore, although features may be described above as functioning in certain combinations, in some cases one or more features may be removed from the combination, and the combination may be for sub-combinations or variations thereof.

Claims

1. A semiconductor device, comprising: The first channel pattern and the second channel pattern are spaced apart from each other on the substrate; A separation structure is located between the first channel pattern and the second channel pattern; as well as The gate electrode is located on the first channel pattern, the second channel pattern, and the separated structure. The separation structure includes: The first pattern is adjacent to the first channel pattern and the second channel pattern; and The second pattern is located between the first groove pattern and the second groove pattern. In this pattern, a portion of the upper surface of the first pattern is higher than the upper surface of the second pattern.

2. The semiconductor device according to claim 1, further comprising: Gate dicing pattern, on the discrete structure, The gate dicing pattern is in contact with the upper surface of the second pattern.

3. The semiconductor device according to claim 2, wherein, The lower surface of the gate dicing pattern is in contact with the first pattern.

4. The semiconductor device according to claim 2, wherein, The gate dicing pattern has a circular or elliptical shape.

5. The semiconductor device according to claim 1, wherein, The first channel pattern and the second channel pattern include a plurality of semiconductor patterns spaced apart from each other in the vertical direction.

6. The semiconductor device according to claim 5, wherein, The upper surface of the second pattern of the separated structure is higher than the lower surface of the uppermost semiconductor pattern among the plurality of semiconductor patterns.

7. The semiconductor device according to claim 5, wherein, The first pattern of the separated structure has a recessed area on the side surface of the first pattern that is recessed toward the second pattern.

8. The semiconductor device according to claim 5, further comprising: A gate insulating layer is located between the gate electrode and the plurality of semiconductor patterns. The gate insulating layer surrounds multiple surfaces of each of the plurality of semiconductor patterns.

9. The semiconductor device according to claim 1, wherein, The second pattern of the separated structure includes protrusions extending into the gate electrode.

10. The semiconductor device according to claim 1, in, The first portion of the gate electrode that overlaps with the first channel pattern and the second channel pattern has a first width, and Wherein, the second portion of the gate electrode that overlaps with the separation structure has a second width that is smaller than the first width.

11. A semiconductor device, comprising: Active patterning on the substrate; The channel pattern includes a plurality of semiconductor patterns on the active pattern; Separation structures are located between the channel patterns; The gate electrode is located on the channel pattern and the separation structure. The first gate dicing pattern overlaps with the separated structure; as well as A second gate dicing pattern, spaced apart from the first gate dicing pattern, extends into the gate electrode. The separation structure includes a first pattern adjacent to the channel pattern and a second pattern spaced apart from the channel pattern. The uppermost surface of the first pattern is coplanar with the upper surface of the gate electrode.

12. The semiconductor device according to claim 11, in, The first pattern has a cylindrical shape, and The second pattern has a columnar shape as in the first pattern.

13. The semiconductor device according to claim 11, wherein, The first gate dicing pattern is in contact with the first pattern and the second pattern.

14. The semiconductor device according to claim 11, wherein, The vertical length of the first gate dicing pattern is less than the vertical length of the second gate dicing pattern.

15. The semiconductor device according to claim 11, wherein, The lower surface of the first gate dicing pattern is lower than the uppermost surface of the first pattern.

16. The semiconductor device according to claim 11, wherein, The uppermost surface of the first pattern is higher than the upper surface of the second pattern.

17. The semiconductor device according to claim 11, wherein, The first gate dicing pattern is aligned with the first pattern.

18. A semiconductor device, comprising: The first active pattern and the second active pattern are spaced apart from each other on the substrate; The first channel pattern is on the first active pattern. The second channel pattern is on the second active pattern; A first source / drain pattern between the first channel patterns, and a second source / drain pattern between the second channel patterns; A separation structure is located between the first channel pattern and the second channel pattern; The gate electrode is located on the first channel pattern, the second channel pattern, and the separated structure. A gate capping pattern is applied to the gate electrode. A first gate dicing pattern is formed on at least one of the discrete structures; as well as The second gate dicing pattern is spaced apart from the separation structure and extends into the gate electrode. The separation structure includes a first pattern and a second pattern, wherein the second pattern is disposed within the first pattern, and The first pattern extends from the second pattern to the lower surface of the first gate dicing pattern.

19. The semiconductor device according to claim 18, in, The first gate dicing pattern has a circular or elliptical shape, and The second gate dicing pattern extends in a second direction that intersects with the first direction.

20. The semiconductor device according to claim 18, in, The first pattern has an upper surface with different heights, and The uppermost surface of the first pattern is higher than the upper surface of the second pattern and the lower surface of the first gate dicing pattern.

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