Display panel and display device

Abstract

The application provides a display panel and a display device; the display panel comprises a substrate, a driving transistor and a storage capacitor arranged on the substrate, the storage capacitor is electrically connected with the driving transistor, the storage capacitor comprises a first plate and a second plate arranged oppositely, the second plate is arranged on the side of the first plate away from the substrate, and a through hole is arranged in the second plate; at least one gap is arranged on the edge of the second plate, the projection of the gap on the substrate does not overlap with the projection of the through hole on the substrate, so that the overlapping area of the second plate and the first plate is reduced, the capacitance of the storage capacitor is reduced, the charging voltage of the storage capacitor is prevented from being too large to have a negative effect on the off effect of the driving transistor, and the technical problem of image sticking of the display panel is improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] In current OLED (Organic Light-Emitting Diode) display panels, the intermediate process of the pixel driving circuit requires charging the storage capacitor with data voltage to turn off the driving transistor and prevent the light-emitting device from emitting light. In order to improve the problem of image retention in the display panel, a larger data voltage is usually required. However, when the data voltage exceeds a certain value, it has a negative effect on the cutoff of the driving transistor, exacerbating the image retention problem and causing abnormal display of the display panel. Summary of the Invention

[0003] This application provides a display panel and a display device to solve the technical problem of display abnormalities in existing display panels.

[0004] This application provides a display panel, which includes a substrate and a driving transistor and a storage capacitor disposed on the substrate. The storage capacitor is electrically connected to the driving transistor. The storage capacitor includes a first electrode plate and a second electrode plate disposed opposite to each other, and the second electrode plate is disposed on the side of the first electrode plate away from the substrate. The second electrode plate has a through hole, and the edge of the second electrode plate has at least one notch. The orthographic projection of one of the notches on the substrate does not overlap with the orthographic projection of the through hole on the substrate.

[0005] This application provides a display device, which includes the display panel as described above.

[0006] Other features and advantages of this application will be described in detail in the following detailed description section.

[0007] This application improves the technical problem of image retention on the display panel by providing at least one notch at the edge of the second electrode plate, wherein the orthographic projection of one of the notches on the substrate does not overlap with the orthographic projection of the through hole on the substrate. This reduces the overlap area between the second electrode plate and the first electrode plate, reduces the capacitance of the storage capacitor, avoids the negative effect of excessive charging voltage of the storage capacitor on the cutoff of the driving transistor, and improves the technical problem of image retention on the display panel. Attached Figure Description

[0008] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0009] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0010] Figure 1 This is a first structural diagram of the display panel of this application.

[0011] Figure 2 This is a structural diagram of the pixel driving circuit in the display panel of this application.

[0012] Figure 3 This is a diagram of the film structure of the display panel in this application.

[0013] Figure 4 This is a first type of film layer stacking diagram of sub-pixels within repeating units in the display panel of this application; Figure 5 for Figure 4 Structure diagram of the first gate layer; Figure 6 for Figure 4 Structure diagram of the first active layer; Figure 7 for Figure 4 Stack diagram of the first gate layer and the first active layer; Figure 8 for Figure 4 Structure diagram of the second gate layer; Figure 9 for Figure 4 A stack-up diagram of the second gate layer, the first gate layer, and the first active layer; Figure 10 for Figure 4 Structure diagram of the second active layer; Figure 11 for Figure 4 Structure diagram of the third gate layer; Figure 12 for Figure 4 A stack-up diagram of the first gate layer, the first active layer, the second active layer, the second gate layer, and the third gate layer; Figure 13 for Figure 4 Structural diagram of the middle shading layer; Figure 14 for Figure 4Stack diagram of the light-shielding layer, the first gate layer, the first active layer, the second active layer, the second gate layer, and the third gate layer; Figure 15 for Figure 4 Structure diagram of the first source-drain layer in the middle; Figure 16 for Figure 4 A stack-up diagram of the first gate layer, the first active layer, the second active layer, the second gate layer, the third gate layer, and the first source / drain layer; Figure 17 for Figure 4 Structure diagram of the second source / drain layer; Figure 18 for Figure 4 Another structural diagram of the second plate in a storage capacitor; Figure 19 This is a second type of film layer stacking diagram of the sub-pixels in the display panel of this application; Figure 20a for Figure 19 A structural diagram of the first plate in a storage capacitor; Figure 20b for Figure 19 A structural diagram of the second plate in a storage capacitor; Figure 20c for Figure 19 Stacked diagram of storage capacitors; Figure 21 This is a third type of film layer stacking diagram of the sub-pixels in the display panel of this application; Figure 22a for Figure 21 A structural diagram of the first plate in a storage capacitor; Figure 22b for Figure 21 A structural diagram of the second plate in a storage capacitor; Figure 22c for Figure 21 Stacked diagram of storage capacitors; Figure 23 To and Figure 21 Structure diagram of the adapted second source-drain layer. Detailed Implementation

[0014] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0015] Please see Figures 1 to 23This application proposes a display panel 100, which includes a substrate 110 and a driving transistor T1 and a storage capacitor Cst disposed on the substrate 110. The storage capacitor Cst is electrically connected to the driving transistor T1. The storage capacitor Cst includes a first plate Cst1 and a second plate Cst2 disposed opposite to each other, and the second plate Cst2 is disposed on the side of the first plate Cst1 away from the substrate 110.

[0016] In this embodiment, the second electrode plate Cst2 is provided with a through hole HL0, and the edge of the second electrode plate Cst2 is provided with at least one notch 50. The orthographic projection of one of the at least one notch 50 on the substrate 110 does not overlap with the orthographic projection of the through hole HL0 on the substrate 110.

[0017] To improve the image retention problem, current display panels 100 typically require charging a large data voltage into the storage capacitor Cst to turn off the driving transistor T1 and prevent the light-emitting device LED from emitting light. However, when the data voltage exceeds a certain value, its effect on the cutoff of the driving transistor T1 becomes negative. For example, when the charging voltage of the storage capacitor Cst exceeds 6.5V, the cutoff effect of the driving transistor T1 weakens, causing the light-emitting device LED to emit light and exacerbating the image retention problem.

[0018] This application provides at least one notch 50 at the edge of the second electrode plate Cst2, wherein the orthographic projection of one of the notches 50 on the substrate 110 does not overlap with the orthographic projection of the through hole HL0 on the substrate 110. This reduces the overlap area between the second electrode plate Cst2 and the first electrode plate Cst1, thereby reducing the capacitance of the storage capacitor Cst and consequently reducing the charging voltage of the storage capacitor Cst. For example, the charging voltage of the storage capacitor Cst is less than or equal to 6.5V. This avoids the problem that an excessively high charging voltage of the storage capacitor Cst would have a negative effect on the cutoff function of the driving transistor T1, thus improving the technical problem of image retention in the display panel 100.

[0019] The technical solution of this application will now be described in conjunction with specific embodiments.

[0020] Please see Figure 1The display panel 100 includes a display area AA and a non-display area NA adjacent to the display area AA. The display area AA contains multiple rows of sub-pixels. Optionally, the non-display area NA surrounds the display area AA, so that the display area AA is surrounded by the non-display area NA. The display area AA is the area within the display panel 100 used for display functions, and it contains multiple display units that implement its display functions. The non-display area NA may be a border area of ​​the display panel 100, and it may contain functional components that assist the display units within the display area AA in displaying information.

[0021] Please see Figure 1 A bonding terminal 400 is provided on the lower side of the display area AA. The bonding terminal 400 can be connected to an external circuit and transmits the signal input from the external circuit to the data trace, thereby driving the display panel 100 to display the image. For example, the bonding terminal 400 can be bonded to a chip or a flip-chip film to provide power and drive signals to the display panel 100.

[0022] In this embodiment, multiple light-emitting devices (LEDs) and pixel driving circuits (PCs) for driving the LEDs can be arrayed within the display area AA. The pixel driving circuit PC can be aTbC or other pixel driving circuits, where a and b are positive integers. This application does not impose specific limitations. The following description uses an 8T2C pixel driving circuit PC as an example.

[0023] Please see Figure 2 The pixel driving circuit PC may include a switching transistor T2, a driving transistor T1, a compensation transistor T3, a first reset transistor T4, a second reset transistor T7, a third reset transistor T8, a first light-emitting transistor T5, a second light-emitting transistor T6, a boost capacitor Cboost, and a storage capacitor Cst.

[0024] Please see Figure 2 The first electrode of the switching transistor T2 is electrically connected to the data line Data, the second electrode of the switching transistor T2 is electrically connected to the first node A, and the gate of the switching transistor T2 is electrically connected to the switching control line Pscan1. The first electrode of driving transistor T1 is electrically connected to the first node A, the second electrode of driving transistor T1 is electrically connected to the second node B, and the gate of driving transistor T1 is electrically connected to the third node Q; the first electrode of compensation transistor T3 is electrically connected to the third node Q, the second electrode of compensation transistor T3 is electrically connected to the second node B, and the gate of compensation transistor T3 is electrically connected to the compensation control line Nscan1; the first electrode of the first reset transistor T4 is electrically connected to the first reset line Vi1, the second electrode of the first reset transistor T4 is electrically connected to the third node Q, and the gate of the first reset transistor T4 is electrically connected to the first reset control line Nscan2; the first electrode of the second reset transistor T7 is electrically connected to the second reset line Vi2, the second electrode of the second reset transistor T7 is electrically connected to the fourth node D, i.e., the anode AN of the light-emitting device LED, and the gate of the second reset transistor T7 is electrically connected to the second reset control line Pscan2; the first electrode of the third reset transistor T8... The third reset transistor T8 is electrically connected to the third reset line Vi3. The second electrode of the third reset transistor T8 is electrically connected to the first node A, and the gate of the third reset transistor T8 is electrically connected to the second reset control line Pscan2. The first electrode of the first light-emitting transistor T5 is electrically connected to the high potential line VDD, the second electrode of the first light-emitting transistor T5 is electrically connected to the first node A, and the gate of the first light-emitting transistor T5 is electrically connected to the light-emitting control line EM. The first electrode of the second light-emitting transistor T6 is electrically connected to the second node B, the second electrode of the second light-emitting transistor T6 is electrically connected to the fourth node D, and the gate of the second light-emitting transistor T6 is electrically connected to the light-emitting control line EM. One end of the boost capacitor Cboost is connected to the third node Q, and the other end of the boost capacitor Cboost is connected to the gate of the switching transistor T2. One end of the storage capacitor Cst is connected to the third node Q, and the other end of the storage capacitor Cst is connected to the high potential line VDD. The cathode of the light-emitting device LED is connected to the low potential line VSS.

[0025] In this embodiment, the high potential line VDD is used to provide a constant high potential to the pixel driving circuit PC, and the low potential line VSS is used to provide a constant low potential to the pixel driving circuit PC.

[0026] In this embodiment, the switching transistor T2, driving transistor T1, second reset transistor T7, third reset transistor T8, first light-emitting transistor T5, and second light-emitting transistor T6 can be either P-type transistors or N-type transistors, and the compensation transistor T3 and first reset transistor T4 can be either P-type transistors or N-type transistors. This application uses the example of switching transistor T2, driving transistor T1, second reset transistor T7, third reset transistor T8, first light-emitting transistor T5, and second light-emitting transistor T6 being P-type transistors, and compensation transistor T3 and first reset transistor T4 being N-type transistors for illustration.

[0027] In this embodiment, the capacitance of the boost capacitor Cboost is smaller than the capacitance of the storage capacitor Cst. In this embodiment, the storage capacitor Cst is mainly used to maintain the stability of the potential of the third node Q; therefore, the capacitance of the storage capacitor Cst is relatively large.

[0028] In this embodiment, the first electrode is the input terminal of the transistor and the second electrode is the output terminal of the transistor. The first electrode can be either the source or the drain, and the second electrode can be either the source or the drain. The following description uses the first electrode as the drain and the second electrode as the source.

[0029] The film layer of the display panel 100 of this application is described below.

[0030] Please see Figure 3 The display area AA and the non-display area NA of the display panel 100 may be provided with a substrate 110 and an array driving layer 120 disposed on the substrate 110; within the display area AA, the display panel 100 may also be provided with a pixel definition layer PDL, a light-emitting device layer EL and an encapsulation layer TEE disposed on the array driving layer 120.

[0031] In this embodiment, the substrate 110 supports various layers disposed on the substrate 110. When the display panel 100 is a bottom-emitting light-emitting display device or a double-sided light-emitting display device, a transparent substrate is used. When the display panel 100 is a top-emitting light-emitting display device, a semi-transparent or opaque substrate, as well as a transparent substrate, can be used.

[0032] In this embodiment, the substrate 110 may be made of an insulating material such as glass, quartz, or polymer resin. The substrate 110 may be a rigid substrate or a flexible substrate that can be bent, folded, rolled, etc. Examples of flexible materials for flexible substrates include, but are not limited to, polyimide (PI).

[0033] In this embodiment, the substrate 110 may include a first flexible substrate, a first barrier layer, a second flexible substrate, and a second barrier layer stacked together. The first flexible substrate and the second flexible substrate may be formed of the same material, such as polyimide, and the first barrier layer and the second barrier layer may be formed of an inorganic material, for example, including at least one of SiOx and SiNx.

[0034] Please see Figure 3 The array driving layer 120 may include multiple thin-film transistors. The thin-film transistors may be etch-block type, back-channel etch type, or classified into bottom-gate thin-film transistors, top-gate thin-film transistors, etc., according to the position of the gate and the active layer, or classified into N-type thin-film transistors and P-type thin-film transistors according to their performance.

[0035] Please see Figure 3 The array driving layer 120 may include a light-shielding layer 121 disposed on the substrate 110, a buffer layer 122 disposed on the light-shielding layer 121, a first active layer 123 disposed on the buffer layer 122, a first insulating layer 124 disposed on the first active layer 123, a first gate layer 125 disposed on the first insulating layer 124, a second insulating layer 126 disposed on the first gate layer 125, a second gate layer 127 disposed on the second insulating layer 126, a third insulating layer 128 disposed on the second gate layer 127, a second active layer 129 disposed on the third insulating layer 128, and a second active layer 129 disposed on the substrate 110. The second active layer 129 comprises a fourth insulating layer 130, a third gate layer 131 disposed on the fourth insulating layer 130, a fifth insulating layer 132 disposed on the third gate layer 131, a first source-drain layer 133 disposed on the fifth insulating layer 132, a first planarization layer 134 disposed on the first source-drain layer 133, a second source-drain layer 135 disposed on the first planarization layer 134, a second planarization layer 136 disposed on the second source-drain layer 135, a light-emitting device layer EL and a pixel definition layer PDL disposed on the second planarization layer 136, and a packaging layer TFE disposed on the pixel definition layer PDL.

[0036] Please see Figure 3 The light-shielding layer 121 is used to block external light from entering the thin-film transistor from the bottom. The material of the light-shielding layer 121 can be made of black light-shielding material, such as black light-shielding metal or black organic material.

[0037] Please see Figure 3 The buffer layer 122 can cover the light-shielding layer 121. The buffer layer 122 is used to isolate the light-shielding layer 121 from the upper metal material. The material of the buffer layer 122 may be composed of a compound consisting of nitrogen, silicon and oxygen elements, such as a single layer of silicon oxide film or a stacked structure of silicon oxide and silicon nitride.

[0038] In this embodiment, the light-shielding layer 121 can also be embedded within the buffer layer 122.

[0039] Please see Figure 3 The first active layer 123 is disposed on the buffer layer 122, and the second active layer 129 is disposed on the third insulating layer 128. In this application, the material of the first active layer 123 can be silicon semiconductor, such as low temperature polycrystalline silicon, and the material of the second active layer 129 can be oxide semiconductor, such as metal oxide.

[0040] Please see Figure 3The first insulating layer 124, the second insulating layer 126, the third insulating layer 128, the fourth insulating layer 130, and the fifth insulating layer 132 are respectively disposed on the corresponding metal layer or semiconductor layer, so that the metal layer or semiconductor layer of different layers is disposed separately; the materials of the first insulating layer 124, the second insulating layer 126, the third insulating layer 128, the fourth insulating layer 130, and the fifth insulating layer 132 can be inorganic materials composed of at least two elements in silicon oxynitride or organic materials with planarity, or they can be stacked single or multiple film layers, such as silicon oxide, silicon nitride, aluminum oxide, etc. stacked structure.

[0041] Please see Figure 3 The first gate layer 125, the second gate layer 127, and the third gate layer 131 are respectively disposed on the corresponding insulating layer. The materials of the first gate layer 125, the second gate layer 127, and the third gate layer 131 can be metals such as Cr, W, Ti, Ta, Mo, Al, and Cu, or single-layer or multi-layer metal structures composed of at least two of the above metals.

[0042] Please see Figure 3 The first source-drain layer 133 is disposed on the fifth insulating layer 132, and the second source-drain layer 135 is disposed on the first planarization layer 134. The materials of the first source-drain layer 133 and the second source-drain layer 135 can be metals such as Cr, W, Ti, Ta, Mo, Al, Cu, or single-layer or multi-layer metal structures composed of at least two of the above metals.

[0043] Please see Figure 3 The first planarization layer 134 and the second planarization layer 136 are laid in a whole layer to ensure the flatness of the film layer of the array driving layer 120. The materials of the first planarization layer 134 and the second planarization layer 136 can be inorganic materials composed of silicon oxynitride, or organic materials with flatness, such as flexible materials such as polytetrafluoroethylene.

[0044] It should be noted that the number of source and drain layers in this application can be set as needed. For example, this application has two source and drain layers, or it can have three source and drain layers. Similarly, the number of the three metal layers, the first gate layer 125, the second gate layer 127, and the third gate layer 131, can be set as needed.

[0045] Please see Figure 3 The display panel 100 may further include an anode layer AN disposed on the second planarization layer 136, a light-emitting layer ELa disposed on the anode layer AN, and a cathode layer CA disposed on the light-emitting layer ELa. The anode layer AN includes a plurality of anodes, the pixel definition layer PDL includes a plurality of pixel openings corresponding one-to-one with the plurality of anodes, and each pixel opening exposes the upper surface of one of the anodes. The light-emitting layer ELa may include a plurality of light-emitting pixels corresponding one-to-one with the plurality of anodes.

[0046] In this embodiment, the pixel definition layer (PDL) may consist of only one film layer, which can be a transparent material or contain a light-blocking material; alternatively, the PDL may consist of two film layers. For example, the PDL may include a first pixel definition layer and a second pixel definition layer, where the transmittance of the first pixel definition layer is greater than that of the second pixel definition layer. Both the first and second pixel definition layers are formed using light-transmitting photoresist, the difference being that the second pixel definition layer contains a light-blocking material. The hydrophilicity of the first pixel definition layer may be greater than that of the second pixel definition layer. The positions of the first and second pixel definition layers can be set as needed.

[0047] Please see Figure 3 The encapsulation layer TFE covers the pixel definition layer PDL and continuously covers multiple pixel openings and multiple light-emitting pixels; wherein, the encapsulation layer TFE may include at least a first inorganic encapsulation layer, a first organic encapsulation layer and a second inorganic encapsulation layer stacked on the pixel definition layer PDL.

[0048] It should be noted that a touch layer, a color resist layer, and a cover layer may also be provided on the side of the encapsulation layer TFE away from the substrate 110, and this application does not impose specific limitations.

[0049] Please see Figure 4 The plurality of sub-pixels PX includes a plurality of repeating units RU arranged along a first direction X and a second direction Y. Each repeating unit RU has two sub-pixels PX, and the patterns of at least a portion of the film layers in the two pixel driving circuits PC within a repeating unit RU are symmetrically arranged with the center line of the repeating unit RU as the axis. This center line may be parallel to the second direction Y. Alternatively, the patterns of at least a portion of the film layers in the two pixel driving circuits PC within a repeating unit RU are identical. The following description uses the symmetrical arrangement of the film layer patterns in two adjacent pixel driving circuits PC as an example.

[0050] It should be noted that due to limitations in processes and equipment, the film patterns in the different pixel driving circuits PCs of this application have slight differences in actual products. Therefore, the symmetrical arrangement of this application is only within the error range. At the same time, in order to set the connection point with the upper structure, some structures widen the pattern in the area where the connection point is located, so that the pattern is asymmetrical, which is also within the error range.

[0051] Please see Figure 4 and Figure 5 , Figure 4 This is a film stacking diagram of a repeating unit RU in the display panel 100 of this application. Figure 5 for Figure 4The structural diagram of the first gate layer 125.

[0052] Please see Figure 5 The first gate layer 125 includes a first reset line Vi1, a switch control line Pscan1, a light emission control line EM, and a second reset control line Pscan2 extending along the first direction X. The second reset control line Pscan2, the light emission control line EM, the switch control line Pscan1, and the first reset line Vi1 are arranged sequentially at intervals along the second direction Y, and the first reset line Vi1, the switch control line Pscan1, the light emission control line EM, and the second reset control line Pscan2 within a repeating unit RU are connected to each other.

[0053] Please see Figure 5 The first gate layer 125 further includes a first plate Cst1 of the storage capacitor Cst disposed between the switch control line Pscan1 and the light emission control line EM. The first plate Cst1 is spaced apart from the switch control line Pscan1 and the light emission control line EM, and the distance between the first plate Cst1 and the switch control line Pscan1 is greater than the distance between the first plate Cst1 and the light emission control line EM. At the same time, two first plates Cst1 in a repeating unit RU are spaced apart.

[0054] Please see Figure 4 and Figure 6 , Figure 6 for Figure 4 The structural diagram of the first active layer 123.

[0055] Please see Figure 6 The first active layer 123 includes the switching active portion T2A of the switching transistor T2, the first light-emitting active portion T5A of the first light-emitting transistor T5, the driving active portion T1A of the driving transistor T1, the second light-emitting active portion T6A of the second light-emitting transistor T6, the second reset active portion T7A of the second reset transistor T7, the third reset active portion T8A of the third reset transistor T8, and the first extension segment ET1.

[0056] Please see Figure 6The active switching part T2A, the first light-emitting active part T5A, and the driving active part T1A are connected to the first connection point N1. The driving active part T1A and the second light-emitting active part T6A are connected to the second connection point N2. The second light-emitting active part T6A and the second reset active part T7A are connected to the third connection point N3. The third reset active part T8A is spaced apart from the above active parts. The third reset active part T8A extends along the second direction Y and is located between the second reset active part T7A and the first light-emitting active part T5A. The first extension segment ET1 is electrically connected to the first connection point N1 and is located between the first connection point N1 and the first light-emitting active part T5A. At the same time, the two first light-emitting active parts T5A in a repeating unit RU are connected at the end away from the first node N1.

[0057] Please see Figure 6 The active switching part T2A, the first light-emitting active part T5A, the second light-emitting active part T6A, the second reset active part T7A, and the third reset active part T8A extend along the second direction Y and are strip-shaped. The first extension segment ET1 extends along the first direction X and is strip-shaped. The active driving part T1A can be U-shaped.

[0058] Please see Figure 7 , Figure 7 for Figure 4 The stack-up diagram of the first gate layer 125 and the first active layer 123.

[0059] Please see Figure 7 The light-emitting control line EM overlaps with the first light-emitting active part T5A. The light-emitting control line EM in the overlapping area is multiplexed as the first light-emitting gate T5G. The first light-emitting active part T5A in the overlapping area is the channel of the first light-emitting transistor T5. The end of the first light-emitting active part T5A away from the first connection point N1 is multiplexed as the drain T5D of the first light-emitting transistor T5. The end of the first light-emitting active part T5A close to the first connection point N1 is multiplexed as the source T5S of the first light-emitting transistor T5. That is, the structure of the area where the first connection point N1 is located is the first node A in the pixel driving circuit PC.

[0060] Please see Figure 7The light-emitting control line EM overlaps with the second light-emitting active part T6A. The light-emitting control line EM in the overlapping area is multiplexed as the second light-emitting gate T6G. The second light-emitting active part T6A in the overlapping area is the channel of the second light-emitting transistor T6. The end of the second light-emitting active part T6A away from the second connection point N2 is multiplexed as the source T6S of the second light-emitting transistor T6. The end of the second light-emitting active part T6A near the second connection point N2 is multiplexed as the drain T6D of the second light-emitting transistor T6. That is, the structure of the area where the second connection point N2 is located is the second node B in the pixel driving circuit PC. The structure of the area where the third connection point N3 is located is the position connected to the anode AN in the pixel driving circuit PC.

[0061] Please see Figure 7 The second reset control line Pscan2 and the second reset active part T7A have an overlapping portion. The second reset control line Pscan2 in the overlapping area is multiplexed as the second reset gate T7G. The second reset active part T7A in the overlapping area is the channel of the second reset transistor T7. The end of the second reset active part T7A near the third connection point N3 is multiplexed as the source T7S of the second reset transistor T7. The end of the second reset active part T7A away from the third connection point N3 is multiplexed as the drain T7D of the second reset transistor T7.

[0062] Please see Figure 7 The second reset control line Pscan2 and the third reset active part T8A have an overlapping portion. The second reset control line Pscan2 in the overlapping area is multiplexed as the third reset gate T8G. The third reset active part T8A in the overlapping area is the channel of the third reset transistor T8. The end of the third reset active part T8A near the light-emitting control line EM is multiplexed as the source T8S of the third reset transistor T8, and the end of the third reset active part T8A away from the light-emitting control line EM is multiplexed as the drain T8D of the third reset transistor T8.

[0063] Please see Figure 7 The switch control line Pscan1 and the active switch section T2A have an overlapping portion. The switch control line Pscan1 in the overlapping area is multiplexed as the switch gate T2G. The active switch section T2A in the overlapping area is the channel of the switch transistor T2. The end of the active switch section T2A near the first connection point N1 is multiplexed as the source T2S of the switch transistor T2, and the end of the active switch section T2A away from the first connection point N1 is multiplexed as the drain T2D of the switch transistor T2.

[0064] Please see Figure 7The first plate Cst1 of the storage capacitor Cst overlaps with the driving active part T1A, and the first plate Cst1 of the storage capacitor Cst is reused as the gate of the driving transistor T1. The part of the driving active part T1A that overlaps with the first plate Cst1 is the channel of the driving transistor T1. The end of the driving active part T1A near the first connection point N1 is reused as the drain T1D of the driving transistor T1, and the end of the driving active part T1A near the second connection point N2 is reused as the source T1S of the driving transistor T1.

[0065] Please see Figure 4 and Figure 8 , Figure 8 for Figure 4 The structural diagram of the second gate layer 127.

[0066] Please see Figure 8 The second gate layer 127 includes a first first reset control line Nscan2a and a first compensation control line Nscan1a arranged at intervals along the second direction Y. The first first reset control line Nscan2a and the first compensation control line Nscan1a both extend along the first direction X. In the first direction X, the first first reset control line Nscan2a in two adjacent sub-pixels PX are connected, and the first compensation control line Nscan1a in two adjacent sub-pixels PX are connected.

[0067] Please see Figure 8 The second gate layer 127 also includes a second electrode Cst2 of the storage capacitor Cst. The second electrode Cst2 is located on the side of the first compensation control line Nscan1a away from the first reset control line Nscan2a. The second electrode Cst2 in two adjacent sub-pixels PX are connected. A through hole HL0 is formed in the middle region of the second electrode Cst2.

[0068] Please see Figure 9 , Figure 9 for Figure 4 A stack-up diagram of the second gate layer 127, the first gate layer 125, and the first active layer 123.

[0069] Please see Figure 9 The first reset control line Nscan2a is located between the first reset line Vi1 and the switch control line Pscan1, and the first compensation control line Nscan1a is located between the switch control line Pscan1 and the first electrode Cst1.

[0070] Please see Figure 9The second electrode plate Cst2 is disposed opposite to the first electrode plate Cst1, and the second electrode plate Cst2 and the first electrode plate Cst1 have an overlapping portion, and at least a portion of the outer contour of the second electrode plate Cst2 extends beyond the outer contour of the first electrode plate Cst1.

[0071] Please see Figure 4 , Figures 10 to 12 , Figure 10 for Figure 4 Structure diagram of the second active layer 129 in the middle. Figure 11 for Figure 4 The structural diagram of the third gate layer 131 in the middle. Figure 12 for Figure 4 The stack-up diagram of the third gate layer 131, the second active layer 129, the second gate layer 127, the first gate layer 125, and the first active layer 123.

[0072] exist Figure 10 In the structure, the second active layer 129 includes the first reset active part T4A of the first reset transistor T4 and the compensation active part T3A of the compensation transistor T3. The first reset active part T4A and the compensation active part T3A both extend along the second direction Y and are elongated. The first reset active part T4A and the compensation active part T3A are connected to the fourth connection point N4.

[0073] exist Figure 11 In the structure, the third gate layer 131 includes a second first reset control line Nscan2b, a second compensation control line Nscan1b, and a third reset line Vi3 arranged at intervals along the second direction Y. The first reset control line Nscan2b and the compensation control line Nscan1b both extend along the first direction X. In the first direction X, the second first reset control line Nscan2b in two adjacent sub-pixels PX are connected, the second compensation control line Nscan1b in two adjacent sub-pixels PX are connected, and the third reset line Vi3 in two adjacent sub-pixels PX are connected.

[0074] exist Figure 12 In the structure, the first reset control line Nscan2a and the second reset control line Nscan2b have overlapping portions, and the first reset control line Nscan2a and the second reset control line Nscan2b together constitute the first reset control line Nscan2; the first compensation control line Nscan1a and the second compensation control line Nscan1b have overlapping portions, and the first compensation control line Nscan1a and the second compensation control line Nscan1b together constitute the compensation control line Nscan1.

[0075] exist Figure 12In the structure, the first reset control line Nscan2a and the second reset control line Nscan2b both overlap with the first reset active part T4A, and the first reset control line Nscan2a and the second reset control line Nscan2b in the overlapping area are both multiplexed as the first reset gate T4G; the first reset active part T4A in the overlapping area is the channel of the first reset transistor T4, the end of the first reset active part T4A near the fourth connection point N4 is multiplexed as the source T4S of the first reset transistor T4, and the end of the first reset active part T4A away from the fourth connection point N4 is multiplexed as the drain T4D of the first reset transistor T4. That is, the structure of the area where the fourth connection point N4 is located is the third node Q in the pixel driving circuit PC, and the control signals transmitted by the first reset control line Nscan2a and the second reset control line Nscan2b can be the same or different.

[0076] exist Figure 12 In the structure, the first compensation control line Nscan1a and the second compensation control line Nscan1b both overlap with the compensation active portion T3A of the compensation transistor T3, and the first compensation control line Nscan1a and the second compensation control line Nscan1b in the overlapping area are both multiplexed as the compensation gate T3G; the compensation active portion T3A in the overlapping area is the channel of the compensation transistor T3, the end of the compensation active portion T3A near the fourth connection point N4 is multiplexed as the drain T3D of the compensation transistor T3, and the end of the compensation active portion T3A away from the fourth connection point N4 is multiplexed as the source T3S of the compensation transistor T3, and the control signals transmitted by the first compensation control line Nscan1a and the second compensation control line Nscan1b can be the same or different.

[0077] exist Figure 12 In the structure, the third reset line Vi3 can have an overlapping portion with the second reset control line Pscan2.

[0078] exist Figure 12 In the structure, the first reset control line Nscan2a is multiplexed as the bottom gate of the first reset transistor T4, and the second reset control line Nscan2b is multiplexed as the top gate of the first reset transistor T4. In order to prevent light from entering the channel of the first reset transistor T4, the overlap area between the first reset control line Nscan2a and the first reset active part T4A is greater than the overlap area between the second reset control line Nscan2b and the first reset active part T4A.

[0079] Similarly, the first compensation control line Nscan1a is multiplexed as the bottom gate of the compensation transistor T3, and the second compensation control line Nscan1b is multiplexed as the top gate of the compensation transistor T3. In order to prevent light from entering the channel of the compensation transistor T3, the overlap area between the first compensation control line Nscan1a and the compensation active part T3A is greater than the overlap area between the second compensation control line Nscan1b and the compensation active part T3A.

[0080] Please see Figure 4 , Figure 13 and Figure 14 , Figure 13 for Figure 4 Structural diagram of the middle shading layer 121 Figure 14 for Figure 4 The stack-up diagram of the third gate layer 131, the second active layer 129, the second gate layer 127, the first gate layer 125, the first active layer 123 and the light-shielding layer 121.

[0081] exist Figure 13 In the structure, the light-shielding layer 121 includes a first light-shielding part TL1, a second light-shielding part TL2, a third light-shielding part TL3, and a fourth light-shielding part TL4. The second light-shielding part TL2 extends along the second direction Y, and the third light-shielding part TL3 and the fourth light-shielding part TL4 extend along the first direction X. Two first light-shielding parts TL1 in the same repeating unit RU are connected through the third light-shielding part TL3. In the first direction X, adjacent first light-shielding parts TL1 in two adjacent repeating units RU are connected through the fourth light-shielding part TL4. In the second direction Y, adjacent first light-shielding parts TL1 in two adjacent repeating units RU are connected through the second light-shielding part TL2.

[0082] exist Figure 13 and Figure 14 In the structure, the first light-shielding part TL1 is block-shaped and can serve as a shielding structure. Therefore, the outer contour area of ​​the first light-shielding part TL1 in this application can be larger than the outer contour area of ​​the first electrode plate Cst1, and the orthographic projection of the first electrode plate Cst1 on the light-shielding layer 121 can be located within the first light-shielding part TL1.

[0083] Please see Figure 4 , Figure 15 and Figure 16 , Figure 15 for Figure 4 Structure diagram of the first source / drain layer 133 in the middle. Figure 16 for Figure 4 A stack-up diagram of the first gate layer 125, the first active layer 123, the second active layer 129, the second gate layer 127, the third gate layer 131, and the first source / drain layer 133.

[0084] Please see Figure 14 The first source-drain layer 133 also includes a first connection segment CT1 and a second connection segment CT2 connected together. The first connection segment CT1 extends along the first direction X, and the second connection segment extends along the second direction Y. Two adjacent repeating units RU share a second connection segment CT2. The end of the second connection segment CT2 away from the first connection segment CT1 passes through a via and is connected to the end of the first light-emitting active part T5A near the second reset control line Pscan2. The end of the second connection segment CT2 near the first connection segment CT1 passes through a via and is electrically connected to the area between two adjacent second plates Cst2. The end of the first connection segment CT1 near the fifth connection segment CT5 passes through a via and is electrically connected to the high potential line VDD of the upper layer.

[0085] Please see Figure 15 and Figure 16 The first source-drain layer 133 also includes a third connection segment CT3. One end of the third connection segment CT3 passes through a via and is connected to the first reset line Vi1. The other end of the third connection segment CT3 passes through a via and is connected to the end of the first reset active part T4A away from the fourth connection point N4.

[0086] Please see Figure 15 and Figure 16 The first source-drain layer 133 also includes a fourth connection segment CT4. One end of the fourth connection segment CT4 passes through a via and is connected to the data line Data. The other end of the fourth connection segment CT4 passes through a via and is connected to the end of the active part of the switch T2A away from the first connection point N1.

[0087] Please see Figure 15 and Figure 16 The first source-drain layer 133 also includes a fifth connection segment CT5. One end of the fifth connection segment CT5 passes through a via and is connected to the end of the compensation active part T3A near the fourth connection point N4. The other end of the fifth connection segment CT5 passes through the through hole HL0 in the second electrode plate Cst2 and is connected to the first electrode plate Cst1. The fifth connection segment CT5 is used to transmit the potential of the third node Q.

[0088] Please see Figure 15 and Figure 16 The first source-drain layer 133 also includes a sixth connection segment CT6. One end of the sixth connection segment CT6 passes through a via and is connected to the end of the compensation active part T3A away from the fourth connection point N4. The other end of the sixth connection segment CT6 passes through a via and is connected to the end of the second light-emitting active part T6A away from the third connection point N3, that is, it is electrically connected to the structure in the area where the second connection point N2 is located.

[0089] Please see Figure 15 and Figure 16The first source-drain layer 133 also includes a seventh connection segment CT7. One end of the seventh connection segment CT7 passes through a via and is electrically connected to the structure in the area where the third connection point N3 is located. The other end of the seventh connection segment CT7 passes through a via and is connected to the upper metal layer.

[0090] Please see Figure 15 and Figure 16 The first source-drain layer 133 also includes an eighth connection segment CT8. One end of the eighth connection segment CT8 passes through a via and is connected to the first extension segment ET1. The other end of the eighth connection segment CT8 passes through a via and is connected to the end of the third reset active part T8A near the light emission control line EM.

[0091] In this embodiment, the third reset line Vi3 includes a reset horizontal segment Vi3a and a reset extension segment Vi3b. The reset horizontal segment Vi3a extends along the first direction X, and the reset extension segment Vi3b extends along the second direction Y. The reset extension segment Vi3b has an overlapping portion with the eighth connecting segment CT8, which is equivalent to the reset extension segment Vi3b overlapping with the area where the first node is located.

[0092] Please see Figure 15 and Figure 16 The first source-drain layer 133 also includes a ninth connection segment CT9. The ninth connection segment CT9 has a recessed structure away from the second reset control line Pscan2. One end of the ninth connection segment CT9 passes through a via and is connected to the recessed structure of the third reset line Vi3. The other end of the ninth connection segment CT9 passes through a via and is connected to the end of the third reset active part T8A away from the light emission control line EM. The two ninth connection segments CT9 in a repeating unit RU are electrically connected at the location of the recessed structure.

[0093] Please see Figure 15 and Figure 16 The first source-drain layer 133 also includes a tenth connection segment CT10, one end of the tenth connection segment CT10 is electrically connected to the end of the second reset active part T7A away from the light emission control line EM, and the other end of the tenth connection segment CT10 is connected to the second reset line Vi2.

[0094] It should be noted that the second reset line Vi2 is not shown in the accompanying drawings of this application. The second reset line Vi2 may be disposed in at least one of the first gate layer 125, the first source-drain layer 133, and the second source-drain layer 135.

[0095] Please see Figure 4 and Figure 17 , Figure 17 for Figure 4 The structural diagram of the second source-drain layer 135 in the middle.

[0096] Please see Figure 4and Figure 17 The second source-drain layer 135 includes a high-potential line VDD and a data line Data arranged along the first direction X, and both the high-potential line VDD and the data line Data extend along the second direction Y.

[0097] In this embodiment, the second source-drain layer 135 further includes an eleventh connection segment CT1, one end of which is connected to the seventh connection segment CT7, and the other end of which is connected to the anode AN of the light-emitting device LED.

[0098] It should be noted that the second source-drain layer 135 may also include multiple reset connection lines extending along the second direction Y and spaced apart along the first direction X. The longitudinally arranged reset connection lines may be electrically connected to the horizontally arranged first reset line Vi1, second reset line Vi2 and third reset line Vi3 respectively, so as to form a horizontal and vertical mesh structure with multiple first reset lines Vi1, multiple second reset lines Vi2, and multiple third reset lines Vi3. The three different reset lines form three different mesh structures and are insulated from each other, which reduces the impedance of the reset lines transmitted by the three types of reset lines.

[0099] Please see Figure 8 and Figure 9 The second electrode plate Cst2 is also provided with a through hole HL0 in the middle area, and the second electrode plate Cst2 is provided with a notch 50. The notch 50 is located on one side of the through hole HL0, and the orthographic projection of the notch 50 on the substrate 110 does not overlap with the orthographic projection of the through hole HL0 on the substrate 110.

[0100] For example, in Figure 8 In the structure, the second electrode plate Cst2 includes a first sub-part 610, a second sub-part 620, a third sub-part 630, and a fourth sub-part 640 located around the through hole HL0. The first sub-part 610, the second sub-part 620, the third sub-part 630, and the fourth sub-part 640 are connected to each other end-to-end. The first sub-part 610 and the second sub-part 620 are arranged opposite each other in the second direction Y, and the third sub-part 630 and the fourth sub-part 640 are arranged opposite each other in the first direction X. The first sub-part 610 is located near the switch control line Pscan1, the second sub-part 620 is located near the light emission control line EM, the third sub-part 630 is located near the second connection point N2, and the fourth sub-part 640 is located near the first connection point N1.

[0101] In this embodiment, the notch 50 may be located on the edge of the first sub-part 610 away from the second sub-part 620, or the notch 50 may be located on the edge of the second sub-part 620 away from the first sub-part 610, or the notch 50 may be located on the edge of the third sub-part 630 away from the fourth sub-part 640, or the notch 50 may be located on the edge of the fourth sub-part 640 away from the third sub-part 630; for example. Figure 8 In the structure, the notch 50 is provided on the edge of the first sub-part 610 away from the second sub-part 620.

[0102] Please see Figure 8 and Figure 9 The notch 50 reduces the overlap area between the second electrode Cst2 and the first electrode Cst1, which in turn reduces the capacitance of the storage capacitor Cst. This reduces the charging voltage applied to the driving transistor T1 by the storage capacitor Cst, avoiding the negative effect on the cutoff of the driving transistor T1 and improving the technical problem of image retention in the display panel 100.

[0103] Please see Figure 8 The through hole HL0 is connected to the notch 50, which is equivalent to cutting off the first sub-part 610 so that the first sub-part 610 forms two spaced-apart structures; or, please refer to Figure 18 The through hole HL0 can be connected to the notch 50, which is equivalent to the first sub-part 610 not being cut off.

[0104] Please see Figure 8 The width of the notch 50 in the first direction X can be less than or equal to the width of the through hole HL0 in the first direction X.

[0105] In another embodiment, when the data voltage is large, the area of ​​the notch 50 can be further increased to reduce the overlap area between the second electrode plate Cst2 and the first electrode plate Cst1. Then, the width of the notch 50 in the first direction X can be greater than or equal to the width of the through hole HL0 in the first direction X.

[0106] It should be noted that the notch 50 of this application may also be provided at the edge of at least one of the first sub-part 610, the second sub-part 620, the third sub-part 630 and the fourth sub-part 640.

[0107] Please see Figures 19 to 20c , Figure 19 This is a second type of film layer stacking diagram for the sub-pixel PL in the display panel 100 of this application. Figures 20a to 20c for Figure 19 The exploded and stacked diagrams of the storage capacitor Cst.

[0108] In this embodiment, the first sub-part 610 is provided with a first notch 510, and the first notch 510 penetrates the edge of the first sub-part 610 away from the through hole HL0. The second sub-part 620 is provided with a second notch 520, and the second notch 520 penetrates the edge of the second sub-part 620 away from the through hole HL0.

[0109] In this embodiment, the orthographic projections of the first notch 510 and the second notch 520 on the substrate 110 do not overlap with the orthographic projection of the through hole HL0 on the substrate 110.

[0110] In this embodiment, the sidewalls G1G2 and R1R2 of the first notch 510 have a first width H1 in the first direction X, and the sidewalls K1K2 and J1J2 in the second notch 520 have a second width H2 in the first direction X. The first width H1 and the second width H2 can be equal.

[0111] Each sub-pixel PL is provided with a first electrode plate Cst1 and a second electrode plate Cst2. When the first electrode plate Cst1 and the second electrode plate Cst2 overlap, due to process errors, the first electrode plate Cst1 and the second electrode plate Cst2 in different sub-pixels PL will be misaligned to varying degrees during the overlap. This is especially true when the second electrode plate Cst2 only has a notch 50 on one side of its edge; for example, for... Figure 20b and Figure 20c When the structure is misaligned in the second direction Y, the reduced overlap area of ​​the second electrode plate Cst2 and the first electrode plate Cst1 in different sub-pixels PL is different. This results in different charging voltages applied to the driving transistor T1 by the storage capacitor Cst in different sub-pixels PL, leading to differences in the luminous brightness of the light-emitting device LED and causing display abnormalities.

[0112] In this embodiment, the first notch 510 and the second notch 520 are located on opposite sides of the through hole HL0. Taking the first notch 510 on the edge of the first sub-part 610 and the second notch 520 on the edge of the second sub-part 620 as an example, when the second electrode plate Cst2 is misaligned in the second direction Y, if the overlap area between the first notch 510 and the first electrode plate Cst1 increases, the overlap area between the second notch 520 and the first electrode plate Cst1 decreases; similarly, if the overlap area between the first notch 510 and the first electrode plate Cst1 decreases, the overlap area between the second notch 520 and the first electrode plate Cst1 increases. When the second electrode plate Cst2 is misaligned in the second direction Y, the relatively set first notch 510 and second notch 520 can compensate for the change in the overlapping area of ​​the first notch 510 and the first electrode plate Cst1 with the change in the overlapping area of ​​the second notch 520 and the first electrode plate Cst1. This makes the overlapping area of ​​the second electrode plate Cst2 and the first electrode plate Cst1 in different sub-pixels PL the same, which is equivalent to making the capacitance of the storage capacitor Cst in different sub-pixels PL the same. This makes the charging voltage applied to the driving transistor T1 by the storage capacitor Cst in different sub-pixels PL the same, thus ensuring the display effect of the display panel.

[0113] Similarly, when the second electrode plate Cst2 is misaligned in the first direction X, since the overlapping areas of the first notch 510 and the second notch 520 with the first electrode plate Cst1 remain unchanged, when the second electrode plate Cst2 is misaligned in the first direction X, the relatively set first notch 510 and the second notch 520 can compensate for the change in the overlapping area of ​​the first notch 510 with the first electrode plate Cst1 and the change in the overlapping area of ​​the second notch 520 with the first electrode plate Cst1. This makes the overlapping area of ​​the second electrode plate Cst2 with the first electrode plate Cst1 in different sub-pixels PL the same, which is equivalent to making the capacitance of the storage capacitor Cst in different sub-pixels PL the same, and making the charging voltage applied to the driving transistor T1 by the storage capacitor Cst in different sub-pixels PL the same, thus ensuring the display effect of the display panel.

[0114] Similarly, when the third sub-part 630 and the fourth sub-part 640 are respectively provided with a first notch 510 and a second notch 520, and misalignment occurs in the second direction Y, the overlap area between the first notch 510 and the first electrode plate Cst1 remains unchanged, and the overlap area between the second notch 520 and the first electrode plate Cst1 remains unchanged. Therefore, the overlap area between the second electrode plate Cst2 and the first electrode plate Cst1 in different sub-pixels PL is the same. When a misalignment occurs in the first direction X, the change in the overlapping area of ​​the first notch 510 and the first electrode Cst1 is compensated by the change in the overlapping area of ​​the second notch 520 and the first electrode Cst1, so that the overlapping area of ​​the second electrode Cst2 and the first electrode Cst1 is the same in different sub-pixels PL.

[0115] In this embodiment, one of the first notch 510 and the second notch 520 communicates with the through hole HL0, and the other of the first notch 510 and the second notch 520 is spaced apart from the through hole HL0; or, both the first notch 510 and the second notch 520 are spaced apart from the through hole HL0.

[0116] For example, please see Figure 20b and Figure 20c The first sub-part 610 and the second sub-part 620 extend along the first direction X. The width of the first sub-part 610 in the second direction Y is less than the width of the second sub-part 620 in the second direction Y. The first notch 510 communicates with the through hole HL0, and the second notch 520 is spaced apart from the through hole HL0.

[0117] In this embodiment, the first notch 510 and the second notch 520 are symmetrically arranged with respect to the first center line O1 of the second electrode plate Cst2, and the first center line is parallel to the extending directions of the first sub-part 610 and the second sub-part 620; for example, please refer to Figure 20b and Figure 20c The dimensions of the sidewalls G1G2 and R1R2 of the first notch 510 in the second direction Y are first dimensions H3, and the dimensions of the sidewalls K1K2 and J1J2 of the second notch 520 in the second direction Y are second dimensions H4. The first dimensions H3 and the second dimensions H4 are equal, and the first width H1 and the second width H2 are equal.

[0118] It should be noted that, taking the first notch 510 located in the first sub-part 610 and the second notch 520 located in the second sub-part 620 as an example, the first notch 510 and the second notch 520 in this application only need to ensure that the first width H1 and the second width H2 are equal. The centerline of the first notch 510 in the second direction Y and the centerline of the second notch 520 in the second direction Y do not need to be collinear. Similarly, when the first notch 510 is located in the third sub-part 630 and the second notch 520 is located in the fourth sub-part 630, when the first width H1 and the second width H2 are equal, the centerline of the first notch 510 in the first direction X and the centerline of the second notch 520 in the first direction X do not need to be collinear.

[0119] It should be noted that the overlap area between the first notch 510 and the first electrode Cst1 represents the overlap area between the film material filling the first notch 510 and the first electrode Cst1, that is, the area of ​​the first electrode Cst1 within the first notch 510 that is not covered by the second electrode Cst2; the overlap area between the second notch 520 and the first electrode Cst1 represents the overlap area between the film material filling the second notch 520 and the second electrode Cst2, that is, the area of ​​the first electrode Cst1 within the second notch 520 that is not covered by the second electrode Cst2.

[0120] Please see Figure 21 and Figure 22c , Figure 21 This is a third layer stacking diagram of the sub-pixel PL in the display panel 100 of this application. Figures 22a to 22c for Figure 21 The exploded and stacked diagrams of the storage capacitor Cst.

[0121] In this embodiment, the second electrode plate Cst2 has intersecting first diagonal line MN and second diagonal line BE. The second electrode plate Cst2 is provided with a third notch 530 and a fourth notch 540 at the edge of the first diagonal line MN; or / and, the second electrode plate Cst2 is provided with a third notch 530 and a fourth notch 540 at the edge of the second diagonal line BE.

[0122] That is, this application can provide notches 50 at the two diagonal positions of the second electrode plate Cst2, for example, in Figure 22b In this application, a third notch 530 and a fourth notch 540 may be provided on the edge corresponding to the second diagonal line BE of the second electrode plate Cst2, respectively. The third notch 530 is provided on the side of the second electrode plate Cst2 away from the data line Data, and the fourth notch 540 is provided on the side of the second electrode plate Cst2 close to the data line Data.

[0123] In this embodiment, when the second electrode plate Cst2 is misaligned in the second direction Y, if the overlap area between the third notch 530 and the first electrode plate Cst1 increases, the overlap area between the fourth notch 540 and the first electrode plate Cst1 decreases; similarly, if the overlap area between the third notch 530 and the first electrode plate Cst1 decreases, the overlap area between the fourth notch 540 and the first electrode plate Cst1 increases. Therefore, when the second electrode plate Cst2 is misaligned in the second direction Y, the changes in the overlap area between the third notch 530 and the fourth notch 540 set on the second diagonal BE, and the changes in the overlap area between the third notch 530 and the second electrode plate Cst2, can compensate for each other, so that the overlap area between the second electrode plate Cst2 and the first electrode plate Cst1 in different sub-pixels PL is the same, which is equivalent to making the capacitance of the storage capacitor Cst in different sub-pixels PL the same, and the charging voltage applied to the driving transistor T1 by the storage capacitor Cst in different sub-pixels PL is the same, thus ensuring the display effect of the display panel.

[0124] Similarly, when the second electrode plate Cst2 is misaligned in the first direction X, if the overlap area between the third notch 530 and the first electrode plate Cst1 increases, the overlap area between the fourth notch 540 and the first electrode plate Cst1 decreases; if the overlap area between the third notch 530 and the first electrode plate Cst1 decreases, the overlap area between the fourth notch 540 and the first electrode plate Cst1 increases. Therefore, when the second electrode plate Cst2 is misaligned in the first direction X, the changes in the overlap area between the third notch 530 and the fourth notch 540 set on the second diagonal BE and the second electrode plate Cst2 can compensate for each other, so that the overlap area between the second electrode plate Cst2 and the first electrode plate Cst1 in different sub-pixels PL is the same, and the charging voltage applied to the driving transistor T1 by the storage capacitor Cst in different sub-pixels PL is the same, thus ensuring the display effect of the display panel.

[0125] Similarly, for the third notch 530 and the fourth notch 540 set on the first diagonal MN, the overlapping area of ​​the second electrode plate Cst2 and the first electrode plate Cst1 in different sub-pixels PL can be the same, so that the charging voltage applied to the driving transistor T1 by the storage capacitor Cst in different sub-pixels PL is the same.

[0126] Please see Figure 22b and Figure 22cThe third notch 530 has a first sidewall AB and a second sidewall BC connected together, and the fourth notch 540 has a third sidewall DE and a fourth sidewall EF connected together. The first sidewall AB and the third sidewall DE extend along a first direction X, and the second sidewall BC and the fourth sidewall EF extend along a second direction Y. The portion of the first sidewall AB that overlaps with the first electrode plate Cst1 is a first side length L1, the portion of the second sidewall BC that overlaps with the first electrode plate Cst1 is a second side length L2, the portion of the third sidewall DE that overlaps with the first electrode plate Cst1 is a third side length L3, and the portion of the fourth sidewall EF that overlaps with the first electrode plate Cst1 is a fourth side length L4.

[0127] In this embodiment, the first side length L1 and the third side length L3 may be equal, or / and, and the second side length L2 and the fourth side length L4 may be equal.

[0128] For example, when the first side length L1 and the third side length L3 are equal, when the second electrode Cst2 is misaligned in the second direction Y, the increase in the area of ​​the overlap between the third notch 530 and the first electrode Cst1 is equal to the decrease in the area of ​​the overlap between the fourth notch 540 and the first electrode Cst1, or the decrease in the area of ​​the overlap between the third notch 530 and the first electrode Cst1 is equal to the increase in the area of ​​the overlap between the fourth notch 540 and the first electrode Cst1.

[0129] For example, when the second side length L2 and the fourth side length L4 are equal, when the second electrode Cst2 is misaligned in the first direction X, the increase in the area of ​​the overlap between the third gap 530 and the first electrode Cst1 is equal to the decrease in the area of ​​the overlap between the fourth gap 540 and the first electrode Cst1, or the decrease in the area of ​​the overlap between the third gap 530 and the first electrode Cst1 is equal to the increase in the area of ​​the overlap between the fourth gap 540 and the first electrode Cst1, so that the overlap area between the second electrode Cst2 and the first electrode Cst1 is the same in different sub-pixels PL.

[0130] It should be noted that the overlap area between the third notch 530 and the first electrode plate Cst1 represents the overlap area between the film material filling the third notch 530 and the first electrode plate Cst1, that is, the area of ​​the first electrode plate Cst1 within the third notch 530 that is not covered by the second electrode plate Cst2; the overlap area between the fourth notch 540 and the first electrode plate Cst1 represents the overlap area between the film material filling the fourth notch 540 and the second electrode plate Cst2, that is, the area of ​​the first electrode plate Cst1 within the fourth notch 540 that is not covered by the second electrode plate Cst2.

[0131] Please see Figure 21The display panel 100 also includes an electrical connection line EC for transmitting the potential of the third node Q, the other end of which passes through the third notch 530 and is electrically connected to the first electrode plate Cst1.

[0132] In this embodiment, the third notch 530 can be reused as the through hole HL0, and the orthographic projection of the fourth notch 540 on the substrate 110 does not overlap with the orthographic projection of the through hole HL0 on the substrate 110.

[0133] In this embodiment, the electrical connection line EC is equivalent to the fifth connection segment CT5 in the first source-drain layer 133. One end of the electrical connection line EC passes through a via and is connected to the end of the compensation active part T3A near the fourth connection point N4. The other end of the electrical connection line EC passes through the through hole HL0 in the second electrode plate Cst2 and is connected to the first electrode plate Cst1. That is, this application does not provide a through hole HL0, and directly uses the third notch 530 to electrically connect the compensation active part T3A and the first electrode plate Cst1.

[0134] It should be noted that, since the fourth gap 540 is close to the first connecting segment CT1, in order to avoid short-circuiting the electrical connection line EC and the first connecting segment CT1, the electrical connection line EC of this application only passes through the third gap 530 and is electrically connected to the first electrode plate Cst1.

[0135] In this embodiment, since the electrical connection line EC needs to pass through the third notch 530 to connect with the first electrode plate Cst1, in order to avoid short-circuiting the electrical connection line EC and the second electrode plate Cst2, this application can make the area of ​​the first electrode plate Cst1 corresponding to the third notch 530 larger than the area of ​​the first electrode plate Cst1 corresponding to the fourth notch 540; or, when the areas of the third notch 530 and the fourth notch 540 are large enough, the area of ​​the first electrode plate Cst1 corresponding to the third notch 530 can be equal to the area of ​​the first electrode plate Cst1 corresponding to the fourth notch 540.

[0136] It should be noted that in the above embodiments of this application, in the plurality of sub-pixels PL, the area of ​​the first electrode plate Cst overlapping with the at least one notch 50 is the same, that is, the sum of the areas of the first electrode plate Cst1 within the at least one notch 50 that are not covered by the second electrode plate Cst2 is the same in different sub-pixels PL.

[0137] For example, in Figures 19 to 20cIn the embodiment, the change in the overlapping area of ​​the first notch 510 and the first electrode Cst1 is mutually compensated with the change in the overlapping area of ​​the second notch 520 and the first electrode Cst1, so that the overlapping area of ​​the second electrode Cst2 and the first electrode Cst1 is the same in different sub-pixels PL. That is, the sum of the areas of the first electrode Cst1 that are not covered by the second electrode Cst2 in the first notch 510 and the second notch 520 is the same in different sub-pixels PL.

[0138] For example, in Figures 21 to 22c In this process, the change in the overlapping area between the third notch 530 and the second electrode plate Cst2 and the change in the overlapping area between the fourth notch 540 and the second electrode plate Cst2 can compensate for each other, so that the overlapping area between the second electrode plate Cst2 and the first electrode plate Cst1 is the same in different sub-pixels PL. That is, it is equivalent to the sum of the areas of the first electrode plate Cst1 that are not covered by the second electrode plate Cst2 in the third notch 530 and the fourth notch 540 being the same in different sub-pixels PL.

[0139] Similarly, when the second electrode plate Cst2 has three or more of the aforementioned notches 50, the above-mentioned limitations are also satisfied.

[0140] It should be noted that, in the above embodiments, the orthographic projection of the notch 20 on the substrate 110 can be characterized as the orthographic projection of the film material in the area where the notch 50 is located on the substrate 110; the orthographic projection of the through hole HL0 on the substrate 110 can be characterized as the orthographic projection of the film material in the area where the through hole HL0 is located on the substrate 110.

[0141] In the above embodiments, please refer to Figure 3 In this application, the electrical connection EC is electrically connected to the first electrode plate Cst1 through the connection hole HL1. The connection hole HL1 penetrates the second insulating layer 126, the third insulating layer 128, the fourth insulating layer 130, and the fifth insulating layer 132, and the connection hole HL1 also passes through the through hole HL0.

[0142] It should be noted that, in the top view, the hole HL1 of this application is located within the through hole HL0 on the plane where the second electrode plate is located, and the hole HL1 is located on the hole wall of the second electrode plate on the side away from the substrate, at least partially within the through hole HL0.

[0143] Please see Figure 23 The display panel 100 further includes a high potential line VDD extending along the second direction Y, the high potential line VDD being electrically connected to the second electrode plate Cst2, and the high potential line VDD covering the third notch 530.

[0144] and Figure 17 Compared to the previous structure, this application can provide an extension EP on the side of the high potential line VDD near the eleventh connection segment, the extension EP covering the third notch 530.

[0145] In this embodiment, since the electrical connection line EC is used to transmit the potential of the third node Q, and the potential of the third node Q is related to the cutoff or conduction of the driving transistor T1, in order to avoid the upper layer circuit forming a coupling capacitor with the electrical connection line EC in the third gap 530 and affecting the potential of the third node Q, this application provides an extension EP on the high potential line VDD to cover the electrical connection line EC in the third gap 530, so as to avoid the fluctuation of the potential of the third node Q, ensure the stability of the potential of the third node Q, and improve the display stability of the display panel 100.

[0146] It should be noted that this application also proposes a display device, which includes the aforementioned display panel, and the display device of this application can be any product or component with display function, such as a vehicle screen, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0147] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0148] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0149] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0150] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A display panel, characterized in that, The device includes a substrate and a driving transistor and a storage capacitor disposed on the substrate. The storage capacitor is electrically connected to the driving transistor. The storage capacitor includes a first electrode plate and a second electrode plate disposed opposite to each other, and the second electrode plate is disposed on the side of the first electrode plate away from the substrate. The second electrode plate has a through hole, and the edge of the second electrode plate has at least one notch, wherein the orthographic projection of one of the notches on the substrate does not overlap with the orthographic projection of the through hole on the substrate.

2. The display panel according to claim 1, characterized in that, The display panel includes a plurality of sub-pixels, and each of the sub-pixels has the storage capacitor; Among the multiple sub-pixels, the area of ​​overlap between the first electrode plate and the at least one notch is the same.

3. The display panel according to claim 1, characterized in that, The second electrode plate also has a through hole in the middle area, and the notch is located on one side of the through hole.

4. The display panel according to claim 3, characterized in that, The through hole and the notch are spaced apart.

5. The display panel according to claim 3, characterized in that, The through hole is connected to the notch.

6. The display panel according to claim 3, characterized in that, The second electrode plate includes a first sub-part and a second sub-part, which are located on opposite sides of the through hole; The first sub-part has a first notch that penetrates the edge of the first sub-part away from the through hole, and the second sub-part has a second notch that penetrates the edge of the second sub-part away from the through hole.

7. The display panel according to claim 6, characterized in that, One of the first notch and the second notch communicates with the through hole, and the other of the first notch and the second notch is spaced apart from the through hole; Alternatively, both the first notch and the second notch are spaced apart from the through hole.

8. The display panel according to claim 7, characterized in that, The first sub-part and the second sub-part extend along a first direction, and the width of the first sub-part in the second direction is smaller than the width of the second sub-part in the second direction; The first notch is connected to the through hole, and the second notch is spaced apart from the through hole.

9. The display panel according to claim 6, characterized in that, The sidewall of the first notch has a first width in a first direction, and the second notch has a second width in the first direction, wherein the first width and the second width are equal.

10. The display panel according to claim 9, characterized in that, The first notch and the second notch are symmetrically arranged with respect to the first center line of the second electrode plate, and the first center line is parallel to the extension direction of the first sub-part and the second sub-part.

11. The display panel according to claim 1, characterized in that, The second electrode plate has intersecting first and second diagonals, and the second electrode plate has a third notch and a fourth notch respectively at the edges of the first diagonal; or / and, The second electrode plate has a third notch and a fourth notch on the edge of the second diagonal.

12. The display panel according to claim 11, characterized in that, The third notch has a first sidewall and a second sidewall connected to each other, and the fourth notch has a third sidewall and a fourth sidewall connected to each other. The first sidewall and the third sidewall extend along a first direction, and the second sidewall and the fourth sidewall extend along a second direction. Wherein, the portion of the first sidewall that overlaps with the first electrode plate is the first side length, the portion of the second sidewall that overlaps with the first electrode plate is the second side length, the portion of the third sidewall that overlaps with the first electrode plate is the third side length, and the portion of the fourth sidewall that overlaps with the first electrode plate is the fourth side length. The first side length is equal to the third side length, or / and the second side length is equal to the fourth side length.

13. The display panel according to claim 11, characterized in that, The display panel also includes: A switching transistor is electrically connected to the driving transistor at the first node; A compensation transistor is electrically connected to the driving transistor at a second node, and the gate of the driving transistor is electrically connected to the compensation transistor and the first plate at a third node. Electrical connection wires are used to transmit the potential of the third node; The data line is electrically connected to the input terminal of the switching transistor; The third notch is located on the side of the second electrode plate away from the data line. The third notch is reused as the through hole. One end of the electrical connection line is electrically connected to the input terminal of the compensation transistor, and the other end of the electrical connection line passes through the third notch and is electrically connected to the first electrode plate.

14. The display panel according to claim 13, characterized in that, The area of ​​the first electrode plate corresponding to the third notch is greater than or equal to the area of ​​the first electrode plate corresponding to the fourth notch.

15. The display panel according to claim 13, characterized in that, The display panel also includes a high-potential line extending along a second direction, the high-potential line being electrically connected to the second electrode plate; The high-potential line covers the third gap.

16. The display panel according to any one of claims 1 to 15, characterized in that, The display panel also includes: A first reset transistor, the output of which is electrically connected to the gate of the driving transistor; The second reset transistor has its output terminal electrically connected to the anode of the light-emitting device; The first light-emitting transistor, wherein the output terminal of the first light-emitting transistor is electrically connected to the first node; The second light-emitting transistor has its input terminal and the output terminal of the driving transistor electrically connected to the second node, and its output terminal is electrically connected to the anode of the light-emitting device.

17. The display panel according to any one of claims 1 to 15, characterized in that, The display panel includes: Substrate; A first active layer is disposed on one side of the substrate, and the first active layer includes the driving active portion of the driving transistor. A first gate layer is disposed on the side of the first active layer away from the substrate, and the first gate layer includes the first electrode of the storage capacitor; A second gate layer is disposed on the side of the first gate layer away from the substrate, and the second gate layer includes the second electrode of the storage capacitor.

18. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 17.

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