Semiconductor element with support layer and method for manufacturing the same

Abstract

A semiconductor device and a method of manufacturing a semiconductor device are disclosed. The semiconductor device includes a substrate including at least four active portions and at least two support portions connecting the at least four active portions. Two of the active portions are arranged along a first direction and separated by an opening. The other two of the active portions are arranged along a second direction perpendicular to the first direction, separated by the opening, and the two of the active portions arranged along the first direction are located therebetween. The other two of the active portions arranged along the second direction are separated from the two of the active portions arranged along the first direction by grooves. The support portions are arranged along the second direction, separated by the opening, and connected to three of the active portions, respectively.

Description

Technical Field

[0001] This application claims priority to U.S. Patent Application No. 19 / 057,214 (i.e., priority date "February 19, 2025"), the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to a semiconductor device and a method for manufacturing the same, and more specifically, to a semiconductor device having a support layer and a method for manufacturing the same. Background Technology

[0003] Semiconductor components are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. The size of semiconductor components continues to shrink to meet the ever-increasing demands for computing power. However, this shrinkage process also introduces many problems, and these problems are constantly increasing. Therefore, challenges remain in improving quality, yield, performance, and reliability, as well as reducing complexity.

[0004] The discussion in the prior art paragraph is for background information only. The statements in the discussion of the prior art paragraph are not an admission that the content disclosed in this paragraph constitutes prior art to this disclosure, and nothing in the discussion of the prior art paragraph shall be construed as an admission that any part of this application, including the part in the discussion of the prior art paragraph, constitutes prior art to this disclosure. Summary of the Invention

[0005] This disclosure provides a semiconductor device comprising: a substrate including: at least four active portions; and at least two support portions connected to the at least four active portions. In a top perspective view, two of the at least four active portions are arranged along a first direction and separated by an opening. In the top perspective view, another two of the at least four active portions are arranged along a second direction perpendicular to the first direction, separated by the opening, with the two active portions arranged along the first direction located therebetween. In the top perspective view, the other two active portions arranged along the second direction are separated from the two active portions arranged along the first direction by a plurality of grooves. In the top perspective view, the at least two support portions are arranged along the second direction, separated by the opening, and respectively connected to three of the at least four active portions.

[0006] Another aspect of this disclosure provides a semiconductor element, comprising: a substrate including: four active portions arranged in a diamond configuration in a top view; and two support portions located at the center of the four active portions and surrounded by the four active portions in a top view, wherein the two support portions are respectively connected to three of the four active portions.

[0007] This disclosure also provides a method for manufacturing a semiconductor device, comprising: providing a substrate; performing a first substrate etching process using a primary mask layer as a mask to form a plurality of recesses in the substrate; forming a secondary mask layer on the substrate and filling the plurality of recesses; performing a second substrate etching process using the secondary mask layer as a mask to form a plurality of openings in the substrate and constructing a plurality of active portions and a plurality of support portions, wherein, in a top perspective view, the plurality of active portions are arranged along a first direction and a second direction perpendicular to the first direction, the plurality of active portions arranged along the first direction are separated by the plurality of openings, and the plurality of active portions arranged along the second direction are separated by the plurality of recesses; the plurality of support portions surround the plurality of openings and are respectively connected to three of the plurality of active portions, and are subjected to an oxide treatment to transform the plurality of support portions into a removable layer; and removing the removable layer to transform the plurality of recesses into a plurality of trenches.

[0008] Due to the design of the semiconductor device disclosed herein, multiple support portions SP can provide additional structural stability to multiple active portions AP, preventing their collapse. This significantly improves the yield and reliability of the semiconductor device 1A.

[0009] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, thereby enabling a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure through modifications or design of other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the concept and scope of this disclosure as defined by the claims. Attached Figure Description

[0010] A more comprehensive understanding of the disclosure of this application can be obtained by referring to the accompanying drawings in conjunction with the embodiments and claims. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale. In fact, for clarity of discussion, the dimensions of various features can be arbitrarily increased or decreased.

[0011] Figure 1 This is a flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0012] Figure 2 This is a top view illustrating a semiconductor element at an intermediate stage according to an embodiment of the present disclosure;

[0013] Figures 3 to 6 It is a sectional view, exemplified along... Figure 2The section lines A-A', B-B', and C-C' in the diagram represent a portion of the manufacturing process of a semiconductor device according to an embodiment of this disclosure.

[0014] Figure 7 This is a top view illustrating a semiconductor element at an intermediate stage according to an embodiment of the present disclosure;

[0015] Figure 8 and Figure 9 It is a sectional view, exemplified along... Figure 7 The section lines A-A', B-B', and C-C' in the diagram represent a portion of the manufacturing process of a semiconductor device according to an embodiment of this disclosure.

[0016] Figure 10 This is a top view illustrating a semiconductor element at an intermediate stage according to an embodiment of the present disclosure;

[0017] Figure 11 and Figure 12 It is a sectional view, exemplified along... Figure 10 The section lines A-A', B-B', and C-C' in the diagram represent a portion of the manufacturing process of a semiconductor device according to an embodiment of this disclosure.

[0018] Figure 13 The top view illustrates a semiconductor element at an intermediate stage according to an embodiment of the present disclosure; and

[0019] Figures 14 to 20 It is a sectional view, exemplified along... Figure 13 The section lines A-A', B-B', and C-C' in the diagram represent a portion of the manufacturing process of a semiconductor device according to an embodiment of this disclosure.

[0020] Explanation of reference numerals in the attached figures:

[0021] 1A: Semiconductor components

[0022] 10: Method

[0023] 101: Substrate

[0024] 101TS: Top Surface

[0025] 103: Bottom hard mask layer

[0026] 105: Top hard mask layer

[0027] 300: Isolation Structure

[0028] 301: Repair Layer

[0029] 301TS: Top surface

[0030] 303: External filler layer

[0031] 303TS: Top surface

[0032] 305: Central Layer

[0033] 305TS: Top surface

[0034] 307: Internal filler layer

[0035] 307TS: Top Surface

[0036] 309: Protective layer

[0037] 309BS: Bottom surface

[0038] 309TS: Top surface

[0039] 501: First filler material

[0040] 503: Second filler material

[0041] 710: Main mask layer

[0042] 711: Main Body

[0043] 711S: Side

[0044] 713: Connection part

[0045] 730: Secondary mask layer

[0046] 750: Removable layer

[0047] AP: Active component

[0048] A1: Active part

[0049] A2: Active part

[0050] A3: Active Part

[0051] A4: Active Part

[0052] BS1: Bottom surface

[0053] BS2: Bottom surface

[0054] BS3: Bottom surface

[0055] D1: Direction

[0056] D2: Direction

[0057] OP1: Opening

[0058] P1: Hole Pattern

[0059] R1: Groove

[0060] SP: Support section

[0061] SP1: Support Section

[0062] SP2: Support Section

[0063] SW1: Sidewall

[0064] SW2: Sidewall

[0065] S11: Steps

[0066] S13: Steps

[0067] S15: Steps

[0068] S17: Steps

[0069] T1: Thickness

[0070] T2: Thickness

[0071] TR: Trench

[0072] VL1: Vertical height

[0073] VL2: Vertical height

[0074] VL3: Vertical Height

[0075] VL4: Vertical height Detailed Implementation

[0076] This disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and configurations described below are provided to simplify this disclosure. Of course, these are merely illustrative and not intended to be limiting. For example, in the following description, forming a first feature on or above a second feature can include embodiments in which the first and second features are formed in direct contact, or embodiments in which an additional feature is formed between the first and second features such that the first and second features may not be in direct contact. Furthermore, element symbols and / or letters may be repeated in various examples in this disclosure. Such repetition is for simplicity and clarity and is not in itself a limitation on the relationship between the various embodiments and / or configurations discussed.

[0077] Furthermore, for ease of description, spatially related terms such as "below," "under," "lower part," "above," "upper part," or other similar terms may be used herein to describe the relative relationship between one element or feature and another shown in the accompanying drawings. In addition to the orientations depicted in the figures, spatially related terms are intended to cover different orientations of the element in use or operation. The element may be oriented in other ways (rotated 90 degrees or otherwise), and the spatially relative descriptors used herein may be interpreted accordingly.

[0078] It should be understood that when a component or layer is referred to as being "connected to" or "coupled to" another component or layer, it may be directly connected to or coupled to the other component or layer, or there may be intermediate components or intermediate layers.

[0079] It should be understood that although the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. Unless otherwise stated, these terms are used only to distinguish one component from another. Thus, for example, the first component, first member, or first part discussed below may be referred to as the second component, second member, or second part without departing from the teachings of this disclosure.

[0080] Unless the context otherwise indicates, terms such as “identical,” “equal,” “plane,” or “coplanar” as used herein do not necessarily mean exactly identical orientations, layouts, locations, shapes, dimensions, quantities, or other measures of reference, but are intended to cover substantially identical orientations, layouts, locations, shapes, dimensions, quantities, or other measures of reference within an acceptable range of possible variations (e.g., due to manufacturing processes). The term “substantially” may be used herein to reflect this meaning. For example, articles described as “substantially identical,” “substantially equal,” or “substantially coplanar” may be exactly identical, equal, or coplanar, or may be substantially identical, equal, or coplanar within an acceptable range of possible variations (e.g., due to manufacturing processes).

[0081] In this disclosure, semiconductor element generally refers to an element that can operate using semiconductor properties, and electro-optic elements, light-emitting display elements, semiconductor circuits and electronic components are all included in the category of semiconductor element.

[0082] It should be noted that, in the description of this disclosure, "above" (or "up") corresponds to the direction of the arrow in the Z direction, and "below" (or "down") corresponds to the opposite direction of the arrow in the Z direction.

[0083] Figure 1 This is a flowchart illustrating a method 10 for manufacturing a semiconductor element 1A according to an embodiment of the present disclosure. Figure 2 This is a top view illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. Figures 3 to 6 It is a sectional view, exemplified along... Figure 2 The section lines A-A', B-B', and C-C' in the diagram represent a portion of the manufacturing process of a semiconductor element 1A according to an embodiment of this disclosure.

[0084] See Figures 1 to 6In step S11, a substrate 101 may be provided, and a plurality of grooves R1 may be formed in the substrate 101.

[0085] See Figure 2 and Figure 3 The substrate 101 may include a main semiconductor substrate. The main semiconductor substrate may be formed of materials such as elemental semiconductors, for example, silicon or germanium; compound semiconductors, such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or other group III-V or group II-VI compound semiconductors; or combinations thereof. In some embodiments, the substrate 101 may be formed of materials such as silicon, germanium, silicon germanium, silicon carbon, silicon germanium carbon, gallium, gallium arsenide, indium arsenide, indium phosphide, or other group IV-IV, III-V, or II-VI semiconductor materials. In some embodiments, the substrate 101 may be formed of materials such as indium antimonide, gallium nitride, gallium phosphide, gallium arsenide phosphide, gallium arsenide nitride, indium gallium arsenide, indium gallium phosphide, gallium aluminum arsenide, aluminum gallium indium, aluminum gallium phosphide, indium aluminum gallium phosphide, gallium indium arsenide, gallium indium nitride, indium gallium phosphide, gallium indium antimonide, indium antimonide arsenide, aluminum nitride, aluminum gallium nitride, zinc selenide, diamond (C), or gallium oxide (Ga2O3). In some embodiments, the substrate 101 may be doped with various types of dopants, such as, but not limited to, boron, aluminum, gallium, indium, arsenic, or phosphorus.

[0086] In some embodiments, substrate 101 may include a semiconductor-on-insulator substrate, which comprises, from bottom to top, a handle substrate, an insulating layer, and a topmost semiconductor material layer. The handle substrate and the topmost semiconductor material layer may be formed of the same material as the aforementioned main semiconductor substrate. The insulating layer may be a crystalline or amorphous dielectric material, such as an oxide and / or a nitride. For example, the insulating layer may be a dielectric oxide, such as silicon oxide. Another example is that the insulating layer may be a dielectric nitride, such as silicon nitride or boron nitride. Yet another example is that the insulating layer may comprise a stack of dielectric oxides and dielectric nitrides in any order, which is a stack of silicon oxide and either silicon nitride or boron nitride. The insulating layer may have a thickness between about 10 nm and 200 nm.

[0087] In some embodiments, the crystal orientation of the substrate 101 (or the top semiconductor layer) may be <100> , <110> or <111> In this embodiment, the substrate 101 may be formed of silicon.

[0088] It should be noted that the term "about," which modifies the amount of ingredients, components, or reactants in this disclosure, refers, for example, to numerical variations that may occur through typical measurement and liquid handling procedures used to prepare concentrates or solutions. Furthermore, variations may occur due to unintentional errors in the measurement procedures, differences in the manufacture, source, or purity of the ingredients used to prepare the composition or to carry out the method, etc. In one aspect, the term "about" means within 10% of the reported value. In another aspect, the term "about" means within 5% of the reported value. In yet another aspect, the term "about" means within 10%, 9%, 8%, 7%, 6%, 5%, 4%, 3%, 2%, or 1% of the reported value.

[0089] See Figure 2 and Figure 3 A bottom hard mask layer 103 can be formed on the substrate 101. In some embodiments, the bottom hard mask layer 103 can be formed of, for example, silicon oxide. In some embodiments, the bottom hard mask layer 103 can be formed by rapidly thermally oxidizing the substrate 101 in an oxide / oxynitride atmosphere. In some embodiments, the temperature of the rapid thermal oxidation can be about 1000°C. It should be noted that, for clarity, the bottom hard mask layer 103 is not shown in the top view.

[0090] See Figure 2 and Figure 3 A top hard mask layer 105 can be formed on the bottom hard mask layer 103. In some embodiments, the top hard mask layer 105 can be formed of, for example, silicon oxide. In some embodiments, the top hard mask layer 105 can be formed by, for example, chemical vapor deposition or plasma-enhanced chemical vapor deposition. For example, a silicate or silicon source, multiple dopant sources, and an ozone source can be used, and the top hard mask layer 105 can be deposited by chemical vapor deposition. In some embodiments, the dopant source may be optional. In some embodiments, the dopant source may be, for example, triethyl borate, triethyl phosphate, triethyl phosphite, trimethyl phosphate, or trimethyl phosphite. In some embodiments, the silicate or silicon source may be, for example, tetramethyl orthosilicate. The dopant source may result in the presence of impurity atoms, such as phosphorus or boron, in the top hard mask layer 105. It should be noted that, for clarity, the top hard mask layer 105 is not shown in the top view.

[0091] See Figure 2 and Figure 3A primary mask layer 710 can be formed on the top hard mask layer 105. In some embodiments, the primary mask layer 710 may be a photoresist layer. The primary mask layer 710 may include a pattern comprising a plurality of body portions 711 and a plurality of connecting portions 713. For clarity and convenience, only one body portion 711 and two connecting portions 713 are described herein.

[0092] In the top perspective view, the main body 711 may have a rectangular (or linear) cross-sectional profile extending along direction D1. Direction D1 is inclined relative to both the X and Y directions. The two connecting parts 713 may be located between the two sides 711S of the main body 711 and arranged along direction D2 perpendicular to direction D1. In other words, the two connecting parts 713 may also be separated by the main body 711.

[0093] In some embodiments, a plurality of main body portions 711 may be arranged alternately along a second direction D2. A plurality of connecting portions 713 may be arranged between the plurality of main body portions 711 and connect adjacent and paired plurality of main body portions 711. Adjacent and paired plurality of main body portions 711 refers to two main body portions 711 that are adjacent to each other.

[0094] See Figure 4 A hard mask etching process is performed using the main mask layer 710 as a mask to remove a portion of the top hard mask layer 105 and a portion of the bottom hard mask layer 103. After the hard mask etching process, the pattern of the main mask layer 710 can be transferred to the bottom hard mask layer 103 and the top hard mask layer 105.

[0095] In some embodiments, the etching rate of the top hard mask layer 105 (or the bottom hard mask layer 103) in the hard mask etching process may be faster than the etching rate of the substrate 101 in the hard mask etching process. For example, during the hard mask etching process, the ratio of the etching rate of the top hard mask layer 105 (or the bottom hard mask layer 103) to the substrate 101 may be between about 100:1 and about 2:1. As another example, during the hard mask etching process, the ratio of the etching rate of the top hard mask layer 105 (or the bottom hard mask layer 103) to the substrate 101 may be between about 100:1 and about 10:1.

[0096] In some embodiments, the primary mask layer 710 may be removed after pattern transfer is completed. In some embodiments, the removal of the primary mask layer 710 may be, for example, an ashing process or other suitable semiconductor process.

[0097] See Figure 5An etching process (also known as a first substrate etching process) can be performed using the bottom hard mask layer 103 and the top hard mask layer 105 as masks to remove a portion of the substrate 101. This process results in the formation of multiple grooves R1.

[0098] It should be noted that, in the description of this disclosure, if there is a vertical plane and the root mean square roughness of a surface deviates from the vertical plane by no more than three times the root mean square roughness of the surface, then the surface is considered "substantially vertical".

[0099] In some embodiments, the etching rate of substrate 101 in the first substrate etching process may be faster than the etching rate of the top hard mask layer 105 (or bottom hard mask layer 103) in the first substrate etching process. For example, during the first substrate etching process, the ratio of the etching rate of substrate 101 to the etching rate of the top hard mask layer 105 (or bottom hard mask layer 103) may be between about 100:1 and about 2:1. As another example, during the first substrate etching process, the ratio of the etching rate of substrate 101 to the etching rate of the top hard mask layer 105 (or bottom hard mask layer 103) may be between about 100:1 and about 10:1.

[0100] In some embodiments, a post-etch cleaning process can be performed after the formation of the plurality of grooves R1. The post-etch cleaning process can include three stages, with inter-stage rinsing between each stage. Specifically, during the first stage of the post-etch cleaning process, after the formation of the plurality of grooves R1, a first cleaning solution can be applied to the intermediate semiconductor element. The first cleaning solution can be rinsed by a first inter-stage rinsing. During the second stage of the post-etch cleaning process, a second cleaning solution can be applied to the intermediate semiconductor element, and the second cleaning solution can subsequently be rinsed by a second inter-stage rinsing. During the third stage of the post-etch cleaning process, a third cleaning solution can be applied to the intermediate semiconductor element, and subsequently rinsed by a post-stage rinsing.

[0101] In some embodiments, during the first stage of the post-etching cleaning process, the intermediate semiconductor element may be rotated at a rate between about 10 rpm and about 2000 rpm, or between about 100 rpm and 1000 rpm. A first cleaning solution may be sprayed onto the intermediate semiconductor element to cover the entire front side of the intermediate semiconductor element. While the first cleaning solution is applied to the front side of the intermediate semiconductor element, water or other suitable solution may be applied to the back side of the intermediate semiconductor element to clean the back side of the intermediate semiconductor element.

[0102] In some embodiments, the first cleaning solution may include dilute hydrofluoric acid. The concentration of the first cleaning solution may be between about 5 parts deionized water to 1 part hydrofluoric acid, about 1000 parts deionized water to 1 part hydrofluoric acid, about 300 parts deionized water to 1 part hydrofluoric acid, or about 50 parts deionized water to 1 part hydrofluoric acid. Generally, the front side of the intermediate semiconductor device can be exposed to the first cleaning solution for a sufficient time to etch the sacrificial oxide (typically about...). to ) or natural oxides (usually about In some embodiments, the process time of the first stage of the post-etching cleaning process may be between about 20 seconds and about 50 seconds, about 40 seconds, or about 30 seconds. In some embodiments, the process time of the first stage of the post-etching cleaning process may be between about 1 minute and about 5 minutes.

[0103] In some embodiments, the first cleaning solution may include fluorides, organic acid salts, and / or glyoxylic acid.

[0104] The first cleaning solution may include fluorides as a component for removing etching residues from the trench etching process. Examples of fluorides may include hydrofluoric acid and ammonium fluoride or amine fluoride salts, such as ammonium fluoride, ammonium hydrogen fluoride, methylamine hydrofluoride, ethylamine hydrofluoride, propylamine hydrofluoride, tetramethylammonium fluoride, tetraethylammonium fluoride, ethanolamine hydrofluoride, methylethanolamine hydrofluoride, dimethylethanolamine hydrofluoride, and triethylenediamine hydrofluoride. In some embodiments, the concentration of fluoride in the first cleaning solution may be determined based on the composition of the etching residues. For example, the concentration of fluoride may be between about 0.1% by mass and about 5% by mass of the total composition of the first cleaning solution, or between about 0.2% by mass and about 3% by mass of the total composition of the first cleaning solution.

[0105] Organic acid salts may include, for example, ammonium oxalate, ammonium tartrate, ammonium citrate, and ammonium acetate. Organic acid salts may act as pH adjusters or buffers in the first cleaning solution. The concentration of the organic acid salt may be between about 0.1% by mass and about 10% by mass of the total composition of the first cleaning solution, or between about 0.3% by mass and about 5% by mass of the total composition of the first cleaning solution.

[0106] The glyoxylic acid contained in the first cleaning solution can act as a corrosion inhibitor.

[0107] In some embodiments, the first cleaning solution may further include a photoresist removal component. Examples of photoresist removal components include tetramethylammonium hydroxide and / or monomethylamine.

[0108] An inter-stage rinse can be performed after the first stage of the post-etch cleaning process. During the inter-stage rinse, the intermediate semiconductor device following the first stage of the post-etch cleaning process can be rotated at a rate between about 10 rpm and about 1000 rpm while being rinsed with deionized water. In some embodiments, the rinse temperature can be between about 19°C and about 23°C. In some embodiments, the process time of the inter-stage rinse can be between about 20 seconds and about 50 seconds or about 30 seconds.

[0109] In some embodiments, before rinsing the intermediate semiconductor elements, the deionized water used for the first-stage inter-rinse can be oxygenated or ozonated by dissolving oxygen or ozone gas. Dissolved oxygen or dissolved ozone can be added to the deionized water as an oxidant at a concentration greater than 1 ppm. For example, the concentration of dissolved oxygen or ozone can be between about 1 ppm and about 200 ppm, or between about 2 ppm and about 20 ppm. Alternatively, the deionized water can be saturated with dissolved oxygen or ozone. Or, hydrogen peroxide can be added to the deionized water as an oxidant at a concentration greater than 100 ppm. Regardless of the oxidant used, it should have an oxidation potential sufficient to oxidize the most inert metal in the solution. Copper (Cu) 2+ With a standard reduction potential of 0.3V, it is typically the most inert metal present. Therefore, a standard reduction potential greater than 0.5V is required. Oxygen or ozone dissolves the metal ions and prevents precipitation by oxidizing the metal ions in solution. This makes the first-stage rinsing more efficient and helps reduce process time.

[0110] In some embodiments, the deionized water used for the first-stage inter-rinse may include dissolved carbon dioxide to dissipate static electricity accumulated in the deionized water. The static electricity accumulated in the deionized water may originate from the rotation of intermediate semiconductor elements. The dissolved carbon dioxide may also make the deionized water more acidic, thus reducing any metal contamination. In some embodiments, an amount of carbon dioxide sufficient to dissipate static electricity may be dissolved in the deionized water. For example, the amount of carbon dioxide dissolved in the deionized water may be sufficient to reduce the resistivity of the deionized water to less than 5 MΩ·cm.

[0111] In some embodiments, the deionized water used for the first-stage inter-rinse may be mixed with isopropanol or any other liquid with a surface tension less than that of deionized water. Isopropanol can assist in faster removal of chemicals by spreading the deionized water over the front side of the intermediate semiconductor element. Isopropanol can also help rinse away byproducts from the intermediate semiconductor element during rotation. Alternatively, isopropanol vapor can be blown onto the front side of the intermediate semiconductor element during rinsing to assist the first-stage inter-rinse.

[0112] In some embodiments, during the second stage of the post-etching cleaning process, the intermediate semiconductor element, after rinsing between the first and second stages, can be rotated at a rate between about 10 rpm and about 2000 rpm or between about 100 rpm and 1000 rpm. A second cleaning solution can be sprayed onto the intermediate semiconductor element to cover the entire front side of the intermediate semiconductor element. While applying the second cleaning solution to the front side of the intermediate semiconductor element, water or other suitable solution can be applied to the back side of the intermediate semiconductor element to clean the back side of the intermediate semiconductor element.

[0113] In some embodiments, the second cleaning solution may be an alkaline solution, comprising, for example, an aqueous solution of an inorganic compound (e.g., sodium hydroxide, potassium hydroxide, and ammonium hydroxide) and an aqueous solution of an organic compound (e.g., tetramethylammonium hydroxide and choline). The second cleaning solution may also include hydrogen peroxide. The purpose of the ammonium hydroxide and hydrogen peroxide in the second cleaning solution is to remove particles and residual organic contaminants from the front side of the intermediate semiconductor device.

[0114] For example, in this embodiment, the second cleaning solution may include ammonium hydroxide, hydrogen peroxide, and water. The ammonium hydroxide, hydrogen peroxide, and water may be present at concentrations defined by dilution ratios between 5 / 1 / 1 and 1000 / 1 / 1. In some embodiments, the ammonium hydroxide / hydrogen peroxide ratio may vary between 0.05 / 1 and 5 / 1. In some embodiments, hydrogen peroxide is not used at all. The ammonium hydroxide in the second cleaning solution is derived from a solution of ammonia at a concentration of 28-29% w / w relative to water. The hydrogen peroxide in the second cleaning solution is derived from a solution of hydrogen peroxide at a concentration of 31-32% w / w relative to water. Due to the ammonium hydroxide and hydrogen peroxide, the pH of the second cleaning solution may be between about 9 and 12 or between about 10 and 11.

[0115] In some embodiments, the second cleaning solution may further include dissolved hydrogen. The dissolved hydrogen in the second cleaning solution can provide cavitation (bubble generation) to the second cleaning solution. Providing cavitation to the second cleaning solution can enhance the post-etching cleaning process. In some embodiments, the concentration of dissolved hydrogen may be between about 0.01 mg / L and about 5 mg / L, or between about 0.1 mg / L and about 5 mg / L. In some embodiments, other suitable cavitation gases may also be used, such as nitrogen, helium, argon, or oxygen. For example, dissolved oxygen at a concentration between about 1 mg / L and about 20 mg / L may be used in the second cleaning solution.

[0116] In some embodiments, the process time for the second stage of the post-etching cleaning process may be between about 30 seconds and about 100 seconds, between about 30 seconds and 90 seconds, or between about 30 seconds and about 60 seconds. In some embodiments, the temperature of the second cleaning solution may be between about 40°C and about 85°C.

[0117] A second-stage rinse can be performed after the second stage of the post-etching cleaning process. The second-stage rinse can be performed using a similar process to the first-stage rinse, and will not be repeated here.

[0118] In some embodiments, during the third stage of the post-etching cleaning process, the intermediate semiconductor element, after rinsing between the third stages, can be rotated at a rate between about 10 rpm and about 2000 rpm or between about 100 rpm and 1000 rpm. A third cleaning solution can be sprayed onto the intermediate semiconductor element to cover its entire front side. Simultaneously with applying the third cleaning solution to the front side of the intermediate semiconductor element, water or other suitable solution can be applied to the back side of the intermediate semiconductor element to clean it.

[0119] In some embodiments, the third cleaning solution may be an acidic solution, including, for example, aqueous solutions of inorganic acids (e.g., hydrochloric acid, hydrofluoric acid, sulfuric acid, and nitric acid) and aqueous solutions of organic acids (e.g., oxalic acid, citric acid, malonic acid, malic acid, fumaric acid, and maleic acid). In some embodiments, the third cleaning solution may also include hydrogen peroxide. The concentration of the acidic solution may be between about 0.001% by weight and about 10% by weight, or between about 0.01% by weight and about 5% by weight. When the concentration is too low, the cleaning effect may be insufficient. When the concentration is too high, metal corrosion of the washing equipment or other related equipment may occur.

[0120] Post-stage rinsing can be performed after the third stage of the post-etching cleaning process. The post-stage rinsing can be performed using a similar process to the first inter-stage rinsing, and will not be repeated here.

[0121] In some embodiments, the second and third stages of the post-etching cleaning process may be optional. In other words, only the first stage of the post-etching cleaning process may be performed. In some embodiments, the third stage of the post-etching cleaning process may be optional. In other words, only the first and second stages of the post-etching cleaning process may be performed.

[0122] See Figure 6 The top hard mask layer 105 and the bottom hard mask layer 103 can be removed by, for example, an etching process (e.g., a wet etching process or a dry etching process). In this embodiment, the top hard mask layer 105 and the bottom hard mask layer 103 can be removed by a wet etching process. In some embodiments, during the etching process, the ratio of the etching rate of the top hard mask layer 105 (or the bottom hard mask layer 103) to the substrate 101 can be between about 100:1 and about 1.05:1, between about 15:1 and about 2:1, or between about 10:1 and about 2:1.

[0123] Figure 7 This is a top view illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 8 and Figure 9 It is a sectional view, exemplified along... Figure 7 The section lines A-A', B-B', and C-C' in the diagram represent a portion of the manufacturing process of a semiconductor element 1A according to an embodiment of this disclosure. Figure 10 This is a top view illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 11 and Figure 12 It is a sectional view, exemplified along... Figure 10 The section lines A-A', B-B', and C-C' in the diagram represent a portion of the manufacturing process of a semiconductor element 1A according to an embodiment of this disclosure.

[0124] See Figure 1 and Figures 7 to 11 In step S13, multiple openings OP1 can be formed in the substrate 101 to construct multiple active portions AP and multiple support portions SP of the substrate 101.

[0125] See Figure 7 and Figure 8 A secondary mask layer 730 can be formed on the substrate 101 to temporarily fill a plurality of recesses R1. The secondary mask layer 730 may contain a plurality of hole patterns P1, thereby exposing a specific portion of the top surface 101TS of the substrate 101. It is worth noting that none of the recesses R1 are exposed through the hole patterns P1 of the secondary mask layer 730.

[0126] See Figure 9 An etching process (also known as a second substrate etching process) can be performed using a secondary mask layer 730 as a mask to remove a portion of the substrate 101. This process results in the formation of multiple openings OP1.

[0127] See Figure 10 and Figure 11 The secondary mask layer 730 can be removed to expose the substrate 101. In some embodiments, the removal of the secondary mask layer 730 can be, for example, an ashing process or other suitable semiconductor process. After the removal of the secondary mask layer 730, multiple recesses R1 and multiple openings OP1 can be exposed simultaneously.

[0128] It should be noted that in the top view Figure 10 In the process, different cross-sectional lines are used to depict shallow features of the substrate 101, such as multiple grooves R1 and multiple openings OP1, to enhance the focus and improve clarity.

[0129] See Figure 10 and Figure 11 Multiple grooves R1 and multiple openings OP1 can construct (or divide) the substrate 101 into multiple active parts AP and multiple support parts SP.

[0130] In the top perspective view, each of the multiple active parts AP can have an approximately linear or rectangular cross-sectional profile. These active parts can be arranged along direction D1 and separated by multiple openings OP1. Furthermore, the active parts can also be arranged along direction D2 (or the Y direction) and separated by multiple grooves R1. Each of the multiple support parts SP can have an approximately semi-circular cross-sectional profile. Each support part SP can simultaneously connect three adjacent active parts AP: two arranged along direction D1 and one arranged along direction D2, adjacent to the two active parts along direction D1. Two adjacent support parts SP can be arranged along direction D2 and separated by openings OP1.

[0131] In other words, in the top perspective view, the four active parts AP can form a set arranged in a diamond or rhomboid configuration, with two arranged along direction D1 and two along direction D2 (or the Y direction, e.g., active parts A3 and A4). The two active parts AP arranged along direction D1 (e.g., active parts A1 and A2) can be separated by an opening OP1. The two active parts arranged along direction D1 are located between the two active parts arranged along direction D2 (e.g., active parts A3 and A4). Adjacent active parts (e.g., A1 / A3, A2 / A3, A1 / A4, or A2 / A4) are separated by multiple grooves R1.

[0132] Two support portions SP (e.g., support portion SP1 and support portion SP2) can be centrally located to connect four active portions AP. In other words, the two support portions SP can be surrounded by four active portions AP. Specifically, support portion SP1 can connect active portions A1, A2, and A3, and can be surrounded by multiple grooves R1 along direction D1. Support portion SP2 can connect active portions A1, A2, and A4, and can also be surrounded by multiple grooves R1 along direction D1. The two support portions SP1 and SP2 can be arranged along direction D2 and separated by an opening OP1. The two support portions SP (e.g., support portion SP1 and support portion SP2) can each have a semi-annular cross-sectional profile, and the openings face opposite directions. For example, viewed from the top view, the opening of support portion SP1 faces to the right, while the opening of support portion SP2 faces to the left.

[0133] In some embodiments, in a cross-sectional perspective view, the bottom surface BS1 of the groove R1 may be located at a vertical height VL1, which is lower than the vertical height VL2 of the bottom surface BS2 of the opening OP1.

[0134] In some embodiments, the aspect ratio of the plurality of recesses R1 may be between about 4:1 and about 12:1. In some embodiments, the sidewalls SW1 of the plurality of recesses R1 may be substantially vertical. In some embodiments, the aspect ratio of the plurality of openings OP1 may be between about 3:1 and about 11:1. In some embodiments, the sidewalls SW2 of the plurality of openings OP1 may be substantially vertical.

[0135] In some comparative embodiments, openings and multiple recesses may cause the active portions to become unstable due to their high aspect ratio, potentially leading to short circuits in the semiconductor device. In contrast, in this disclosure, multiple support portions SP can provide additional structural stability to the multiple active portions AP, preventing their collapse. This significantly improves the yield and reliability of the semiconductor device 1A.

[0136] In some embodiments, after the formation of the plurality of openings OP1, a process similar to... Figure 5 The post-etching cleaning process shown is not repeated here.

[0137] Figure 13 This is a top view illustrating a semiconductor element at an intermediate stage according to an embodiment of the present disclosure. Figures 14 to 20 It is a sectional view, exemplified along... Figure 13 The section lines A-A', B-B', and C-C' in the diagram represent a portion of the manufacturing process of a semiconductor element 1A according to an embodiment of this disclosure.

[0138] See Figure 1 and Figures 12 to 14 In step S15, oxygen treatment can be performed to transform multiple support portions SP into removable layers 750, and the removable layers 750 can be removed to form multiple trenches TR.

[0139] See Figure 12 Multiple support portions SP of substrate 101 can be oxidized by oxygen treatment to form a removable layer 750. Furthermore, during this oxygen treatment process, the surfaces of multiple active portions AP, multiple recesses R1, and multiple openings OP1 can also be compliantly oxidized. These oxidized areas are collectively referred to as a portion of the removable layer 750. In some embodiments, the removable layer 750 may include silicon oxide.

[0140] In some embodiments, oxygen treatment may involve an ashing process. This plasma-based process may... Figure 11 The intermediate semiconductor element shown is exposed to oxygen plasma, thereby effectively oxidizing the support portion SP and forming a thin silicon oxide layer on the substrate surface. This oxidation occurs when oxygen free radicals interact with silicon and convert it into silicon oxide. The ashing process can use oxygen alone or a combination of oxygen and nitrogen, the latter increasing the concentration of oxygen free radicals. In some embodiments, the radio frequency (RF) power applied during the ashing process can range from about 100W to about 1000W, while the substrate temperature can be maintained between about 20°C and about 250°C.

[0141] It should be noted that in the top view Figure 13 In this process, shallow features of the substrate 101 are depicted using different profile lines, such as trenches TR, to enhance emphasis and improve clarity.

[0142] See Figure 13 and Figure 14The removable layer 750 can be removed, causing multiple grooves R1 to connect along direction D1 to form multiple trenches TR. Adjacent trenches TR can be interconnected via openings OP1 along direction D2. In some embodiments, the bottom surface BS3 of the multiple trenches TR can be located at a vertical height VL3, which is lower than the vertical height VL2 of the bottom surface BS2 of the multiple openings OP1.

[0143] In some embodiments, the removable layer 750 can be removed by applying vaporized hydrogen fluoride to the removable layer 750. In some embodiments, this removal process may include a catalyst such as water vapor or alcohol to enhance the etching reaction on silicon oxide. For example, the presence of water vapor can promote the formation of reactive substances that interact with silicon oxide. In some embodiments, the pressure of the removal process may be between about 75 Torr and about 150 Torr. In some embodiments, the temperature of the removal process may be between about 20°C and about 30°C.

[0144] See Figure 1 and Figures 15 to 20 In step S17, an isolation structure 300 can be formed in multiple trenches TR and multiple openings OP1.

[0145] See Figure 15 A repair layer 301 can be compliantly formed on the substrate 101, the plurality of trenches TR, and the plurality of openings OP1. In some embodiments, the repair layer 301 can be formed of, for example, silicon. In some embodiments, the repair layer 301 can be formed by, for example, atomic layer deposition, chemical vapor deposition, or other suitable deposition processes. In some embodiments, the repair layer 301 can fill the seams of the plurality of trenches TR and the plurality of openings OP1. In some embodiments, the repair layer 301 can serve as a buffer layer or a stress-reducing layer. The repair layer 301 can be used to alleviate mechanical stress caused by the difference in the coefficients of thermal expansion between the substrate 101 and the insulating material to be subsequently filled.

[0146] See Figure 16 An outer filler layer 303 can be compliantly formed on the repair layer 301. The multiple trenches TR and multiple openings OP1 may not be completely filled by the outer filler layer 303. In some embodiments, the outer filler layer 303 may comprise silicon oxide or other suitable insulating material.

[0147] In some embodiments, the outer filler layer 303 may be formed of, for example, silicon oxide. In some embodiments, the outer filler layer 303 may be formed by, for example, chemical vapor deposition, plasma-enhanced chemical vapor deposition, or other suitable deposition processes.

[0148] In some embodiments, the outer filler layer 303 can be formed by thermal oxidation and subsequent deposition processes. For example, the formation of the outer filler layer 303 can begin in an oxide / oxide-nitrogen atmosphere by... Figure 16 The intermediate semiconductor element shown undergoes rapid thermal oxidation to compliantly form a thin layer (not shown for clarity) on the repair layer 301. Subsequently, a flowable layer (not shown for clarity) can be compliantly formed on this thin layer. Finally, this flowable layer can be transformed into an external filler layer 303.

[0149] In some embodiments, the flowable layer may include a compound having unsaturated bonds (e.g., double and triple bonds). The flowable layer may be characterized as a soft, jelly-like layer, a gel with liquid flow properties, or a liquid layer, but is not limited to these. The flowable layer can flow into and fill small substrate gaps without forming voids or weak seams. A thermal process can then be performed to transform the flowable layer into an outer filler layer 303 by curing it. The thermal process can break unsaturated bonds into free radicals, and the compound can be cross-linked via these free radicals. This allows the flowable layer to be cured. In some embodiments, the volume of the flowable layer may decrease during the thermal process. Therefore, the outer filler layer 303 can have a greater density than the flowable layer. The outer filler layer 303 can be located in the position previously occupied by the flowable layer.

[0150] In some embodiments, the flowable layer may be a flowable silicon-and-nitrogen-containing layer. A carbon-free silicon-containing precursor can be mixed with a radical nitrogen precursor to form the flowable silicon-and-nitrogen-containing layer. The flowability of the flowable silicon-and-nitrogen-containing layer allows it to flow into narrow substrate gaps or narrow trenches. During the formation of the flowable silicon-and-nitrogen-containing layer, the temperature of the substrate 101 may be less than 120°C, less than 100°C, less than 80°C, or less than 60°C.

[0151] The carbon-free silicon-containing precursor can be, for example, a silicon-and-nitrogen precursor, a silicon-and-hydrogen precursor, or a silicon-nitrogen-and-hydrogen-containing precursor. In some embodiments, the carbon-free silicon-containing precursor can also be oxygen-free. The lack of oxygen results in a lower concentration of silanol (Si-OH) groups in the flowable silicon-and-nitrogen layer formed from the carbon-free silicon-containing precursor. Excess silanol portions in the flowable silicon-and-nitrogen layer may lead to increased porosity and shrinkage during subsequent processes that remove the hydroxyl (-OH) moieties from the flowable silicon-and-nitrogen layer.

[0152] In some embodiments, the carbon-free silicon-containing precursor may include silyl-amines, such as monosilyl-amines (H₂N(SiH₃)), disilyl-amines (HN(SiH₃)₂), and trisilyl-amines (N(SiH₃)₃). The flow rate of the silyl-amine may be greater than or about 200 sccm, greater than or about 300 sccm, or greater than or about 500 sccm. These silyl-amines may be mixed with an additional gas, which may serve as a carrier gas, a reactant gas, or both. Examples of such additional gases include hydrogen (H₂), nitrogen (N₂), ammonia (NH₃), helium (He), and argon (Ar).

[0153] In some embodiments, carbon-free silicon-containing precursors may include silanes alone, or silanes mixed with other silicon-containing gases (e.g., trisilylamine, N(SiH3)3), hydrogen-containing gases (e.g., H2), and / or nitrogen-containing gases (e.g., N2, NH3).

[0154] In some embodiments, carbon-free silicon-containing precursors may include disilane, trisilane, higher-order silane, or silyl chloride, either alone or in combination with silylamine.

[0155] A radical nitrogen precursor can be generated by delivering ammonia to the plasma region. The radical nitrogen precursor can then be delivered to mix with a carbon-free silicon-containing precursor. The flow rate of ammonia delivered to the plasma region can be greater than or about 300 sccm, greater than or about 500 sccm, or greater than or about 700 sccm. In some embodiments, a gas (e.g., nitrogen and hydrogen) can be used to adjust the nitrogen:hydrogen atomic flow ratio. In some embodiments, a gas (e.g., helium or argon) can be used as the carrier gas for delivering ammonia to the plasma region.

[0156] In some embodiments, radical nitrogen precursors can be generated without the use of ammonia. One or more gases, including hydrogen, nitrogen, and hydrazine, can be delivered to the plasma region to generate radical nitrogen precursors.

[0157] Subsequently, a curing process and an annealing process can be sequentially applied to the flowable silicon- and nitrogen-containing layer (i.e., the flowable layer) in an oxygen-containing atmosphere to transform the flowable silicon- and nitrogen-containing layer into an external filler layer 303 formed of silicon oxide. In some embodiments, the substrate temperature of the curing process can be below or at about 400°C. For example, the substrate temperature of the curing process can be between about 100°C and about 200°C. In some embodiments, the substrate temperature of the annealing process can be between about 500°C and about 1100°C. In some embodiments, the oxygen-containing atmosphere may include one or more oxygen-containing gases, such as molecular oxygen, ozone, water vapor, hydrogen peroxide, and nitrogen oxides (e.g., nitric oxide, nitrous oxide, etc.).

[0158] Alternatively, in some embodiments, the flowable layer can be formed by reacting a vapor-phase precursor with a co-reactant. The flowable layer may have flow characteristics capable of providing consistent filling of the substrate gaps of the substrate 101. Subsequently, a post-deposition treatment may be performed, and the flowable layer may be physically densified and / or chemically transformed to reduce its flowability. After the post-deposition treatment, the flowable layer can be transformed into an external filler layer 303. In some embodiments, the densified flowable layer can be considered as cured. In some embodiments, physical densification of the flowable layer may involve shrinking the flowable layer. In some embodiments, the post-deposition treatment may involve replacing the chemicals in the flowable layer, thereby producing a denser, larger-volume external filler layer 303.

[0159] In some embodiments, the flowable layer may be flowable silicon oxide, silicon nitride, or silicon oxynitride. In some embodiments, the flowable layer may be silicon carbide or silicon carbide. In some embodiments, the cavity pressure used to form the flowable layer may be between about 1 Torr and 200 Torr, between 10 Torr and 75 Torr, or about 10 Torr. In some embodiments, the substrate temperature used to form the flowable layer may be between about -20°C and about 100°C, between about -20°C and about 30°C, or between about -10°C and about 10°C.

[0160] In some embodiments, the gas-phase precursor may include a silicon-containing precursor or a carbon-containing precursor. Co-reactants may include an oxidant, a catalyst, a surfactant, or an inert carrier gas.

[0161] Silicon-containing precursors may include, but are not limited to: silanes, disilanes, trisilanes, hexasilanes, cyclohexasilanes, alkoxysilanes, aminosilanes, alkylsilanes, tetraisocyanatesilanes (TICS), hydrogen silsesquioxanes, T8-hydridospherosiloxanes, or 1,2-dimethoxy-1,1,2,2-tetramethyldisilane.

[0162] Alkoxysilanes can include tetraoxymethylcyclotetrasiloxane (TOMCTS), octamethylcyclotetrasiloxane (OMCTS), tetraethoxysilane (TEOS), triethoxysilane (TES), trimethoxysilane (TriMOS), methyltriethoxyorthosilicate (MTEOS), tetramethylorthosilicate (TMOS), and methyltrimethoxysilane (MTMOS). Alkane (dimethyldimethoxysilane, DMDMOS), diethoxysilane (DES), dimethoxysilane (DMOS), triphenylethoxysilane, 1-(triethoxysilyl)-2-(diethoxymethylsilyl)ethane, tri-t-butoxylsilanol, hexamethoxydisilane (HMODS), hexaethoxydisilane (HEODS), or tert-butoxydisilane. Aminosilanes may include bis-tert-butylaminosilane (BTBAS) or tris(dimethylamino)silane.

[0163] Carbon-containing precursors may include, but are not limited to: trimethylsilane (3MS), tetramethylsilane (4MS), diethoxymethylsilane (DEMS), dimethyldimethoxysilane, methyl-triethoxysilane (MTES), methyl-trimethoxysilane, methyl-diethoxysilane, trimethoxymethylsilane, dimethoxymethylsilane, or bis(trimethylsilyl)carbodiimide.

[0164] Oxidizing agents may include, but are not limited to: ozone, hydrogen peroxide, oxygen, water, alcohols, nitric oxide, nitrogen dioxide, nitrous oxide, carbon monoxide, or carbon dioxide. Alcohols may include, for example, methanol, ethanol, or isopropanol.

[0165] Catalysts may include, but are not limited to: proton precursor catalysts, halogenated compounds, inorganic acids, bases, chlorodiethoxysilanes, methanesulfonic acid, trifluoromethanesulfonic acid, chlorodimethoxysilanes, pyridine, acetyl chloride, chloroacetic acid, dichloroacetic acid, trichloroacetic acid, oxalic acid, benzoic acid, or triethylamine. Proton precursor catalysts may include nitric acid, hydrofluoric acid, phosphoric acid, sulfuric acid, hydrochloric acid, bromic acid, carboxylic acid derivatives, ammonia, ammonium hydroxide, hydrazine, or hydroxylamine. Halogenated compounds may include dichlorosilanes, trichlorosilanes, methylchlorosilanes, chlorotriethoxysilanes, chlorotrimethoxysilanes, chloromethyldiethoxysilanes, chloromethyldimethoxysilanes, vinyltrichlorosilanes, diethoxydichlorosilanes, or hexachlorodisiloxanes. Inorganic acids may include formic acid or acetic acid. Bases may include phosphine.

[0166] Surfactants can include solvents, alcohols, ethylene glycol, or polyethylene glycol. Surfactants can be used to reduce surface tension and increase the wettability of reactants on substrate surfaces. Surfactants can also increase the miscibility of vapor-phase precursors with other reactants.

[0167] Solvents can be nonpolar or polar, and protic or aprotic. The choice of solvent can be matched to the gas-phase precursor to improve miscibility with the oxidant. Nonpolar solvents can include alkanes and alkenes; polar aprotic solvents can include acetone and acetates; polar protic solvents can include alcohols and carboxylic acid compounds.

[0168] Examples of solvents include, but are not limited to: methanol, ethanol, isopropanol, acetone, acetonitrile, dimethylformamide, dimethyl sulfoxide, tetrahydrofuran, dichloromethane, hexane, benzene, toluene, isoheptane, and diethyl ether. In some embodiments, the solvent may be introduced before other reactants.

[0169] Inert carrier gases may include nitrogen, helium, or argon.

[0170] Post-deposition treatment can crosslink and remove terminal groups, such as hydroxyl (-OH) and hydrogen (-H) groups, from the flowable layer, thereby increasing the density and hardness of the flowable layer. Post-deposition treatment can be thermal curing, exposure to downstream or direct plasma, exposure to ultraviolet or microwave radiation, or exposure to other energy sources.

[0171] When thermosetting is used as a post-deposition treatment, the thermosetting temperature can be between approximately 200°C and 600°C. The post-deposition treatment can be performed in an inert environment, an oxidizing environment, a nitriding environment, or a mixture of oxidizing and nitriding environments. An inert environment can include argon or helium. An oxidizing environment can include oxygen, ozone, water, hydrogen peroxide, nitrous oxide, nitric oxide, nitrogen dioxide, carbon monoxide, and carbon dioxide. A nitriding environment can include nitrogen, ammonia, nitrous oxide, nitric oxide, and nitrogen dioxide. The thermosetting pressure can be between approximately 0.1 Torr and approximately 10 Torr.

[0172] When exposure to downstream or direct plasma is used as a post-deposition treatment method, the plasma can be an inert plasma or a reactive plasma. Inert plasmas can be helium or argon plasmas. Reactive plasmas can include oxidizing plasmas or hydrogen-containing plasmas, wherein oxidizing plasmas include oxygen and vapor, and hydrogen-containing plasmas include hydrogen and a diluent, such as an inert gas. In some embodiments, the temperature during plasma exposure can be about 25°C or higher. In some embodiments, the temperature during plasma exposure can be between about -15°C and about 25°C.

[0173] See Figure 17 A first filler material 501 can be compliantly formed on the outer filler layer 303. This first filler material 501 may not completely fill the plurality of trenches TR and the plurality of openings OP1. In some embodiments, the first filler material 501 may be formed of a material having etch selectivity relative to the outer filler layer 303. In some embodiments, the first filler material 501 may include silicon nitride or other suitable insulating materials. In some embodiments, the first filler material 501 may serve as a stop layer for subsequent planarization or etching processes. In some embodiments, the first filler material 501 may be formed by, for example, atomic layer deposition, chemical vapor deposition, or other suitable deposition processes.

[0174] See Figure 18A second filler material 503 can be formed on this first filler material 501. This second filler material 503 can completely fill the plurality of trenches TR and the plurality of openings OP1. In some embodiments, the second filler material 503 can be formed of a material having etch selectivity relative to the first filler material 501. In some embodiments, the second filler material 503 can include the same material as the outer filler layer 303. In some embodiments, the second filler material 503 can include silicon oxide or other suitable insulating materials. In some embodiments, this second filler material 503 can be formed by, for example, chemical vapor deposition, plasma-enhanced chemical vapor deposition, or other suitable deposition processes.

[0175] In some embodiments, a high aspect ratio process can be performed to deposit this layer of second filler material 503, ensuring complete filling of the multiple trenches TR and multiple openings OP1 and covering this layer of first filler material 501. The high aspect ratio process may involve two stages. During the first stage, a low deposition rate is used to achieve more uniform trench filling and reduce the likelihood of void formation. In the second stage, a fast deposition rate is used to increase overall production efficiency by reducing deposition time. This high aspect ratio process combines a slower deposition rate stage with a higher deposition rate stage, strategically utilizing a slower deposition rate to reduce defects and a higher deposition rate to shorten deposition time. Furthermore, in some embodiments, the pressure during the high aspect ratio process may be between about 200 Torr and about 760 Torr, and the temperature may be between about 400°C and about 570°C.

[0176] In some embodiments, a two-stage annealing process may be performed after the high aspect ratio process. During the first stage of the two-stage annealing, a lower temperature environment comprising one or more oxygen-containing substances (e.g., water, oxygen, nitric oxide, or nitrous oxide) is used. The purpose of the first stage is to rearrange and strengthen the silicon oxide network, thereby preventing the formation of voids and the opening of weak seams in the multiple trenches TR and multiple openings OP1. Furthermore, the lower temperature in the first stage prevents oxygen from reacting with the trench walls and other parts of the substrate 101, resulting in the formation of undesirable oxide layers.

[0177] Subsequently, in the second stage of the two-stage annealing, a higher temperature environment without oxygen is employed. The purpose of the second stage is to further rearrange the structure of the second filler material 503 and remove moisture, both of which increase the density of this layer of second filler material 503. The environment during the second stage can be, for example, substantially pure nitrogen, a mixture of nitrogen and an inert gas (e.g., helium, neon, argon, or xenon), or substantially pure inert gas. It may also include reducing gases such as hydrogen or ammonia. The second stage facilitates high-temperature densification without causing oxidation of the substrate 101.

[0178] See Figure 19 After two-stage annealing, a planarization process, such as chemical mechanical polishing, can be performed until the top surface 303TS of the outer filler layer 303 is exposed to remove excess material and provide a substantially flat surface for subsequent process steps. The outer filler layer 303 can serve as a stop layer in the planarization process. After the planarization process, the remaining first filler material 501 can be referred to as a plurality of center layers 305, and the remaining second filler material 503 can be referred to as a plurality of inner filler layers 307. At this stage, the top surface 303TS of the outer filler layer 303, the top surface 305TS of the plurality of center layers 305, and the top surface 307TS of the plurality of inner filler layers 307 can be substantially coplanar.

[0179] See Figure 20 A surface oxidation process can be performed to oxidize the tops of the multiple central layers 305. In this embodiment, the central layers 305 are formed of silicon nitride. The oxidized ends of the multiple central layers 305 can be referred to as multiple protective layers 309. In other words, the multiple protective layers 309 can be respectively and correspondingly disposed on the multiple central layers 305. The repair layer 301, the outer filling layer 303, the central layers 305, the inner filling layer 307, and the multiple protective layers 309 together constitute the isolation structure 300.

[0180] In some embodiments, the surface oxidation process can be a low-temperature plasma oxidation process. The low-temperature plasma oxidation process for converting silicon nitride into silicon oxide may involve several steps and specific process conditions. First, the surface oxidation process... Figure 19The intermediate semiconductor device shown is loaded into a plasma-enhanced chemical vapor deposition chamber maintained at a cryogenic temperature between approximately 200°C and approximately 400°C. A mixture of oxygen and an inert gas (e.g., nitrogen or argon) is then introduced into the chamber at a controlled flow rate. The oxygen flow rate can be set between approximately 10 standard cubic centimeters per minute (sccm) and approximately 100 sccm, while the inert gas flow rate can vary between approximately 50 sccm and approximately 500 sccm. Radio frequency (RF) power can be applied to generate a cryogenic plasma with a power level between approximately 50 W and approximately 300 W. The RF power excites the gas mixture, generating active substances including oxygen radicals, which play a crucial role in the cryogenic plasma oxidation process.

[0181] During the low-temperature plasma oxidation process, oxygen radicals react with the silicon nitride surface, converting it into silicon oxide without requiring high temperatures. The low-temperature plasma oxidation process is self-limiting, meaning the reaction rate decreases as the silicon nitride layer is converted into silicon oxide. The oxidation time can be carefully controlled to achieve the desired thickness of several protective layers 309, and the oxidation time typically ranges from several minutes to tens of minutes, depending on the desired film thickness and properties. After the oxidation step, the plasma is deactivated, and a purge gas (typically nitrogen) is introduced into the chamber to remove any residual active materials and byproducts.

[0182] For the sake of brevity, clarity and convenience, only one separator layer 109 will be described.

[0183] See Figure 20 The bottom surface 309BS of the protective layer 309 may be located at a vertical height VL4, which is higher than the top surface 101TS of the substrate 101 or the top surface 301TS of the repair layer 301. In some embodiments, the thickness T1 of the protective layer 309 may be less than the thickness T2 of the outer filler layer 303. In some embodiments, the ratio of the thickness T1 of the protective layer 309 to the thickness T2 of the outer filler layer 303 may be between about 0.1 and about 0.8 or between about 0.3 and about 0.6.

[0184] Multiple protective layers 309 are used to prevent the underlying central layer 305 from being removed during subsequent etching processes. After the subsequent etching process, the top surface 303TS of the outer filler layer 303 and the top surface 309TS of the protective layer 309 can be substantially coplanar. In other words, the surface of the semiconductor device 1A can remain intact and substantially flat to facilitate subsequent semiconductor processes. This improves the reliability of the semiconductor device 1A.

[0185] In some comparative embodiments, if the protective layer 309 is absent, the central layer 305, which can be formed from silicon nitride, may also be removed during subsequent etching processes, resulting in small grooves. This could potentially affect the reliability of the semiconductor device.

[0186] This disclosure provides a semiconductor device comprising: a substrate including: at least four active portions; and at least two support portions connected to the at least four active portions. In a top perspective view, two of the at least four active portions are arranged along a first direction and separated by an opening. In the top perspective view, another two of the at least four active portions are arranged along a second direction perpendicular to the first direction, separated by the opening, with the two active portions arranged along the first direction located therebetween. In the top perspective view, the other two active portions arranged along the second direction are separated from the two active portions arranged along the first direction by a plurality of grooves. In the top perspective view, the at least two support portions are arranged along the second direction, separated by the opening, and respectively connected to three of the at least four active portions.

[0187] Another aspect of this disclosure provides a semiconductor element, comprising: a substrate including: four active portions arranged in a diamond configuration in a top view; and two support portions located at the center of the four active portions and surrounded by the four active portions in a top view, wherein the two support portions are respectively connected to three of the four active portions.

[0188] This disclosure also provides a method for manufacturing a semiconductor device, comprising: providing a substrate; performing a first substrate etching process using a primary mask layer as a mask to form a plurality of recesses in the substrate; forming a secondary mask layer on the substrate and filling the plurality of recesses; performing a second substrate etching process using the secondary mask layer as a mask to form a plurality of openings in the substrate and constructing a plurality of active portions and a plurality of support portions, wherein, in a top perspective view, the plurality of active portions are arranged along a first direction and a second direction perpendicular to the first direction, the plurality of active portions arranged along the first direction are separated by the plurality of openings, and the plurality of active portions arranged along the second direction are separated by the plurality of recesses; the plurality of support portions surround the plurality of openings and are respectively connected to three of the plurality of active portions, and are subjected to an oxide treatment to transform the plurality of support portions into a removable layer; and removing the removable layer to transform the plurality of recesses into a plurality of trenches.

[0189] Due to the design of the semiconductor device disclosed herein, multiple support portions SP can provide additional structural stability to multiple active portions AP, preventing their collapse. This significantly improves the yield and reliability of the semiconductor device 1A.

[0190] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives can be made without departing from the concept and scope of this disclosure as defined in the claims. For example, many of the processes described above can be implemented using different methods, and other processes or combinations thereof can be substituted for many of the processes described above.

[0191] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material compositions, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this publication that existing or future processes, machinery, manufacturing, material compositions, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Accordingly, such processes, machinery, manufacturing, material compositions, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. A semiconductor element, comprising: A substrate, comprising: At least four active components; and At least two support sections connect the at least four active sections; In one upward perspective view, two of the at least four active parts are arranged along a first direction and separated by an opening; In the upward perspective view, two of the at least four active parts are arranged along a second direction perpendicular to the first direction, separated by the opening, and the two of the at least four active parts arranged along the first direction are located therebetween. In the upward perspective view, the other two of the at least four active parts arranged along the second direction are separated from the two of the at least four active parts arranged along the first direction by a plurality of grooves; In the upward perspective view, the at least two support portions are arranged along the second direction, separated by the opening, and respectively connected to three of the at least four active portions.

2. The semiconductor device of claim 1, wherein in the top perspective view, the at least four active portions each have a linear or rectangular cross-sectional profile.

3. The semiconductor device of claim 1, wherein in the top perspective view, the at least two support portions each have a semi-annular cross-sectional profile.

4. The semiconductor device of claim 1, wherein a bottom surface of the opening and a bottom surface of the plurality of grooves are located at different vertical heights.

5. The semiconductor element of claim 1, wherein a bottom surface of the opening is located at a vertical height, which is higher than a vertical height of a bottom surface of the plurality of grooves.

6. The semiconductor element of claim 1, wherein the aspect ratio of the plurality of grooves is between about 4:1 and about 12:

1.

7. The semiconductor element of claim 1, wherein the aspect ratio of the plurality of grooves is between about 3:1 and about 11:

1.

8. The semiconductor device of claim 1, wherein the substrate comprises silicon, germanium, silicon-germanium, silicon-carbon, or silicon-germanium-carbon.

9. The semiconductor device of claim 1, wherein the crystal orientation of the substrate is <100> , <110> or <111> .

10. The semiconductor element of claim 3, wherein in the top perspective view, the opening is surrounded by the at least two support portions.

11. A semiconductor element, comprising: A substrate, comprising: The four active components are arranged in a diamond configuration in a top view; and Two support portions are located at the center of the four active portions in the top view and are surrounded by the four active portions, wherein the two support portions are respectively connected to three of the four active portions.

12. The semiconductor device of claim 11, wherein in the top perspective view, the four active portions each have a linear or rectangular cross-sectional profile.

13. The semiconductor device of claim 12, wherein in the top perspective view, the two support portions each have a semi-annular cross-sectional profile.

14. The semiconductor element of claim 13, wherein two of the four active portions are arranged along a first direction, and the other two of the four active portions are arranged along a second direction perpendicular to the first direction.

15. The semiconductor device of claim 14, further comprising: An opening is located in the substrate to separate two of the four active portions along the first direction.

16. The semiconductor device of claim 15, further comprising: Multiple grooves are located in the substrate to separate two of the four active portions from the other two of the four active portions.

17. The semiconductor element of claim 16, wherein the opening is surrounded by the two support portions.

18. The semiconductor element of claim 17, wherein the two support portions are surrounded by a plurality of grooves along the first direction.

19. The semiconductor element of claim 18, wherein a bottom surface of the opening and a bottom surface of the plurality of grooves are located at different vertical heights.

20. The semiconductor element of claim 18, wherein a bottom surface of the opening is located at a vertical height, which is higher than a vertical height of a bottom surface of the plurality of recesses.

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