A photosensitive device and a method for manufacturing a photosensitive device

Abstract

The application discloses a photosensitive device and a manufacturing method thereof. The photosensitive device comprises a semiconductor substrate, a photosensitive structure is formed in the semiconductor substrate; an insulating buried layer is located above the semiconductor substrate; a semiconductor layer is located above the insulating buried layer, and a floating diffusion region is formed in the semiconductor layer, wherein the floating diffusion region is isolated from the photosensitive structure by the insulating buried layer. In the application, the photosensitive structure in the semiconductor substrate and the floating diffusion region in the semiconductor layer are isolated by the insulating buried layer, so that the lattice damage of the substrate caused by plasma discharge in the later process is blocked, the defect area is reduced, the leakage problem of the interface between the semiconductor substrate and the semiconductor layer is effectively reduced, the generation of noise is reduced, the lateral area of the photosensitive structure is effectively increased, the influence of the area of the floating diffusion region is avoided, the energy of collected photoelectrons is improved, the full well capacity of the photosensitive device is improved, and the performance of the photosensitive device is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a photosensitive device and a method for manufacturing the photosensitive device. Background Technology

[0002] In the application of integrated circuits, the performance of various devices is affected by the structure of each layer. In particular, the widespread use of image sensors tends to use multiple transistor structures.

[0003] The manufacturing of transistors involves additional processes such as plasma implantation, which can increase interface defects in the substrate, thereby increasing the risk of leakage current and affecting the performance of photosensitive devices. Summary of the Invention

[0004] The main technical problem solved by this invention is to provide a photosensitive device and a method for manufacturing the photosensitive device, which can effectively improve the full-well capacity of the photosensitive device and reduce the interface defects of the substrate, thereby reducing leakage current and improving the performance of the photosensitive device.

[0005] To solve the above-mentioned technical problems, one technical solution adopted in this application is to provide a photosensitive device, comprising: a semiconductor substrate in which a photosensitive structure is formed; an insulating buried layer located on the semiconductor substrate; and a semiconductor layer located on the insulating buried layer, wherein a floating diffusion region is formed in the semiconductor layer, and the floating diffusion region is isolated from the photosensitive structure by the insulating buried layer.

[0006] In one embodiment of this application, it further includes: a dielectric layer located above the semiconductor layer, wherein at least a portion of the transfer transistor is formed in the dielectric layer.

[0007] In one embodiment of this application, at least a portion of the transfer transistor extends into the photosensitive structure.

[0008] In one embodiment of this application, the insulating buried layer is formed with a via through which the transfer transistor passes, such that at least a portion of the transfer transistor extends into the photosensitive structure.

[0009] In one embodiment of this application, at least a portion of the photosensitive structure is located below the floating diffusion region.

[0010] In one embodiment of this application, a first inversion isolation region is further formed in the semiconductor substrate. The first inversion isolation region is located below the floating diffusion region and is located below the buried insulating layer and / or in contact with the buried insulating layer. The first inversion isolation region is configured to isolate adjacent photosensitive structures.

[0011] In one embodiment of this application, a second inversion isolation region is formed in the semiconductor layer, wherein the second inversion isolation region is located above the photosensitive structure.

[0012] In one embodiment of this application, the second inversion isolation region is in contact with the insulating buried layer.

[0013] In one embodiment of this application, an isolation structure is further formed in the semiconductor substrate, the isolation structure being located outside the photosensitive structure and below the second inversion isolation region.

[0014] In one embodiment of this application, the isolation structure is in contact with the insulating buried layer.

[0015] In one embodiment of this application, the insulating buried layer includes a first insulating buried layer and a second insulating buried layer, wherein the first insulating buried layer is formed on the semiconductor substrate, and the second insulating buried layer is bonded to the first insulating buried layer.

[0016] In one embodiment of this application, the dielectric layer includes at least a first dielectric layer; the transfer transistor includes a connection portion and an extension portion, the connection portion being formed in the first dielectric layer, and the extension portion passing through the semiconductor layer and extending into the photosensitive structure of the semiconductor substrate.

[0017] In one embodiment of this application, the dielectric layer further includes a second dielectric layer; the second dielectric layer is located above the first dielectric layer, and a capacitor structure and a plurality of metal interconnect layers are formed in the second dielectric layer. The capacitor structure is electrically connected to the floating diffusion region, wherein the capacitor structure is located between at least two of the metal interconnect layers.

[0018] In one embodiment of this application, a plurality of other transistors are further formed in the first dielectric layer, including a first control transistor and a second control transistor; the first control transistor is electrically connected to the upper plate of the capacitor structure, and the second control transistor is electrically connected to the lower plate of the capacitor structure, wherein the first control transistor is configured to control the on / off state of the current, and the second control transistor is configured to control the on / off state of the capacitor structure and the floating diffusion region.

[0019] To solve the above-mentioned technical problems, another technical solution adopted in this application is: to provide a method for manufacturing a photosensitive device, comprising: providing a semiconductor substrate, wherein a photosensitive structure is formed in the semiconductor substrate; forming an insulating buried layer on the semiconductor substrate; forming a semiconductor layer on the insulating buried layer, wherein a floating diffusion region is formed in the semiconductor layer, wherein the floating diffusion region is isolated from the photosensitive structure by the insulating buried layer.

[0020] In one embodiment of this application, the method further includes: performing a first ion implantation from the semiconductor layer toward the semiconductor substrate to form the photosensitive structure in the semiconductor substrate; and performing a second ion implantation from the semiconductor layer toward the semiconductor substrate to form a first inversion isolation region in the semiconductor substrate, wherein the first inversion isolation region is configured to isolate adjacent photosensitive structures.

[0021] In one embodiment of this application, the method further includes: performing a third ion implantation on the semiconductor layer to form a second inversion isolation region in the semiconductor layer, wherein the second inversion isolation region is located above the photosensitive structure; and performing a fourth ion implantation on the semiconductor layer to form the floating diffusion region in the semiconductor layer, wherein the floating diffusion region is located above the first inversion isolation region, and at least a portion of the photosensitive structure is located below the floating diffusion region.

[0022] In one embodiment of this application, the method further includes: forming a dielectric layer, the dielectric layer being located above the semiconductor layer, wherein at least a portion of the transfer transistor is formed in the dielectric layer, and at least a portion of the transfer transistor extends into the photosensitive structure.

[0023] In one embodiment of this application, the method further includes: forming a groove from the semiconductor layer toward the semiconductor substrate, the groove extending to the photosensitive structure in the semiconductor substrate; forming a polycrystalline material layer that fills the groove and covers the semiconductor layer; and removing at least a portion of the polycrystalline material layer to form a plurality of transistors on the semiconductor layer, wherein the transistor extending to the photosensitive structure among the plurality of transistors is the transfer transistor.

[0024] In one embodiment of this application, the dielectric layer includes at least a first dielectric layer and a second dielectric layer; forming the dielectric layer includes: forming a first dielectric layer, the first dielectric layer covering the semiconductor layer and the gate electrodes of the plurality of transistors on the semiconductor layer; forming a second dielectric layer, the second dielectric layer covering the first dielectric layer, wherein a capacitor structure and a plurality of metal interconnect layers are formed in the second dielectric layer, the capacitor structure is electrically connected to the floating diffusion region, wherein the capacitor structure is located between at least two of the metal interconnect layers, and the upper electrode of the capacitor structure is electrically connected through a first control transistor among the plurality of transistors, and the lower electrode of the capacitor structure is electrically connected through a second control transistor among the plurality of transistors.

[0025] In one embodiment of this application, after the dielectric layer is formed, an isolation structure is formed from the semiconductor substrate toward the buried insulating layer, wherein the isolation structure is in contact with the buried insulating layer, and at least a portion of the isolation structure is located below a second inversion isolation region formed in the semiconductor layer.

[0026] Unlike existing technologies, the photosensitive device provided in this application includes: a semiconductor substrate in which a photosensitive structure is formed; an insulating buried layer located on the semiconductor substrate; and a semiconductor layer located on the insulating buried layer, in which a floating diffusion region is formed, wherein the floating diffusion region is isolated from the photosensitive structure by the insulating buried layer. In this application, by isolating the photosensitive structure in the semiconductor substrate and the floating diffusion region in the semiconductor layer through the insulating buried layer, the lattice damage to the substrate caused by plasma discharge from subsequent processes can be prevented, reducing defect surface area and effectively reducing leakage current problems at the interface between the semiconductor substrate and the semiconductor layer, thus reducing noise generation. Furthermore, it can effectively increase the lateral area of ​​the photosensitive structure, avoid the influence of the floating diffusion region area, increase the energy of collected photoelectrons, increase the full-well capacity of the photosensitive device, and thereby improve the performance of the photosensitive device. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein: Figure 1 This is a schematic diagram of the structure of the first embodiment of the photosensitive device in this application; Figure 2 This is a schematic diagram of the structure of the second embodiment of the photosensitive device in this application; Figure 3 This is a top view of one embodiment of the photosensitive device in this application; Figure 4 This is a schematic diagram of the circuit principle of the photosensitive device in this application; Figure 5 yes Figure 3 Schematic diagram of the structure of section AA in the middle; Figure 6 yes Figure 3 Schematic diagram of the structure of the middle BB section; Figure 7 This is a schematic flowchart of an embodiment of the manufacturing method of the photosensitive device in this application; Figure 8 This is a schematic diagram of a structure in an embodiment of forming an insulating buried layer and a semiconductor layer in this application; Figure 9 This is a schematic diagram of an embodiment of the photosensitive structure formed in this application; Figure 10 This is a schematic diagram of the structure of an embodiment of forming the first inverse isolation region in this application; Figure 11This is a schematic diagram of a structure of an embodiment of forming a second inverse isolation region in this application; Figure 12 This is a schematic diagram of a structure for forming a floating diffusion region in this application; Figure 13 This is a schematic diagram of a structure of an embodiment of forming a groove in this application; Figure 14 This is a schematic diagram of the structure of an embodiment of forming a gate electrode in this application; Figure 15 This is a schematic diagram of a structure forming the first dielectric layer in this application; Figure 16 This is a schematic diagram of a structure in an embodiment of forming the second dielectric layer in this application; Figure 17 This is a schematic diagram of an embodiment of the isolation structure in this application.

[0028] In the attached figures, there are a semiconductor substrate 100, a photosensitive structure 110, a first inversion isolation region 120, an isolation structure 130, an insulating buried layer 200, a first insulating buried layer 210, a second insulating buried layer 220, a via 201, a semiconductor layer 300, a groove 301, a floating diffusion region 310, a second inversion isolation region 320, a dielectric layer 400, a first dielectric layer 410, a transfer transistor TG, a gate electrode 411 of the transfer transistor TG, a connection portion 4111, an extension portion 4112, a second dielectric layer 420, a capacitor structure 421, a metal connection layer M, a first metal connection layer M1, a second metal connection layer M2, a third metal connection layer M3, a switch transistor, a DCG transistor, an RST transistor, an SF transistor, and a SEL transistor. Detailed Implementation

[0029] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0030] The terms "first," "second," and "third" in this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationships and movements between components in a specific orientation (as shown in the figures). If the specific orientation changes, the directional indications also change accordingly. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0031] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0032] The present application will now be described in detail with reference to the accompanying drawings and embodiments.

[0033] This application provides a photosensitive device and a method for manufacturing the photosensitive device, which can effectively improve the full-well capacity of the photosensitive device and reduce the interface defects of the substrate, thereby reducing leakage current and improving the performance of the photosensitive device.

[0034] Please see Figure 1 , Figure 1 This is a schematic diagram of the structure of the first embodiment of the photosensitive device in this application.

[0035] like Figure 1 As shown, the photosensitive device of this application includes: a semiconductor substrate 100, an insulating buried layer 200, and a semiconductor layer 300.

[0036] A photosensitive structure 110 is formed in a semiconductor substrate 100; an insulating buried layer 200 is located on the semiconductor substrate 100; a semiconductor layer 300 is located on the insulating buried layer 200, and a floating diffusion region 310 is formed in the semiconductor layer 300, wherein the floating diffusion region 310 is isolated from the photosensitive structure 110 by the insulating buried layer 200.

[0037] The semiconductor substrate 100 and semiconductor layer 300 can be made of any suitable semiconductor material, including but not limited to at least one of the following: silicon, germanium, silicon-germanium, silicon-germanium carbide, silicon carbide, and other semiconductor materials. The buried insulating layer 200 includes at least one of the following materials: silicon oxide, silicon nitride, silicon oxynitride, Hi-k materials, etc. The photosensitive structure 110 refers to the photosensitive region formed in the semiconductor substrate 100 by ion implantation, such as a photodiode (PD). The floating diffusion region 310 refers to the doped region formed in the semiconductor layer 300 by ion implantation, such as a floating diffusion node (FD), which acts as a storage node for receiving signal charges generated by the photodiode.

[0038] Specifically, the photosensitive device 10 includes a semiconductor substrate 100, an insulating buried layer 200 located on the semiconductor substrate 100, and a semiconductor layer 300 located on the insulating buried layer 200. A photosensitive structure 110 is formed in the semiconductor substrate 100, and a floating diffusion region 310 is formed in the semiconductor layer 300. The insulating buried layer 200 isolates the photosensitive structure 110 and the floating diffusion region 310, which can effectively increase the lateral area of ​​the photosensitive structure, avoid the influence of the floating diffusion region area, improve the energy of photoelectron collection, and improve the full-well capacity of the photosensitive device. Furthermore, the insulating buried layer 200 is located on the semiconductor substrate 100, which can block the lattice damage of the substrate caused by plasma discharge in subsequent processes, reduce the defect surface area, effectively reduce the leakage current problem caused by the interface between the semiconductor substrate and the semiconductor layer, and reduce the generation of noise.

[0039] It is understandable that one photosensitive structure 110 can correspond to one photosensitive device.

[0040] In this embodiment, by isolating the photosensitive structure in the semiconductor substrate and the floating diffusion region in the semiconductor layer through an insulating buried layer, the lattice damage of the substrate caused by plasma discharge in subsequent processes can be prevented, the defect surface area can be reduced, the leakage current problem caused by the interface between the semiconductor substrate and the semiconductor layer can be effectively reduced, and the noise generation can be reduced; it can also effectively increase the lateral area of ​​the photosensitive structure, avoid the influence of the floating diffusion region area, improve the energy of photoelectrons collected, improve the full-well capacity of the photosensitive device, and thus improve the performance of the photosensitive device.

[0041] In some embodiments, a dielectric layer 400 is also included.

[0042] Please see Figure 2 , Figure 2 This is a schematic diagram of the structure of the second embodiment of the photosensitive device in this application.

[0043] like Figure 2As shown, the photosensitive device 10 includes: a semiconductor substrate 100, an insulating buried layer 200 located on the semiconductor substrate 100, a semiconductor layer 300 located on the insulating buried layer 200, and a dielectric layer 400 located on the semiconductor layer 300; a photosensitive structure 110 is formed in the semiconductor substrate 100, and a floating diffusion region 310 is formed in the semiconductor layer 300, the floating diffusion region 310 being isolated from the photosensitive structure 110 by the insulating buried layer 200; a transfer transistor TG (Transfer Gate) is formed in the dielectric layer 400, at least a portion of the transfer transistor TG extending into the photosensitive structure 110, for example, the gate electrode 411 of the transfer transistor TG extending into the photosensitive structure 110.

[0044] The buried insulating layer 200 can be a single-layer or multi-layer structure; the semiconductor layer 300 can be a single-layer or multi-layer structure; the dielectric layer 400 includes any suitable dielectric layer known in the art, including but not limited to oxide layers and nitride layers, and the dielectric layer 400 can be a single-layer or multi-layer structure. The gate electrode refers to the gate of the transistor.

[0045] For example, the buried insulating layer 200 includes a first buried insulating layer 210 and a second buried insulating layer 220, wherein the first buried insulating layer 210 is formed on the semiconductor substrate 100, and the second buried insulating layer 220 is bonded to the first buried insulating layer 210.

[0046] It is understandable that the gate electrode of the transfer transistor TG extends through the semiconductor layer 300 and the insulating buried layer 200 into the photosensitive structure 110 of the semiconductor substrate 100. That is, the gate electrode of the transfer transistor TG is set as a vertical gate structure, which can effectively enhance the control and conversion of photoelectrons by the photosensitive device, thereby improving the full-well capacity of the photosensitive device.

[0047] In some embodiments, the insulating buried layer 200 is formed with a via 201 through which at least a portion of the transfer transistor TG passes, i.e., through which the gate electrode 411 of the transfer transistor TG passes, so that at least a portion of the transfer transistor TG extends into the photosensitive structure 110.

[0048] Among them, through hole 201 refers to a through hole that penetrates the insulating buried layer 200, and there can be one or more.

[0049] Specifically, at least one via 201 is formed in the insulating buried layer 200, and each via 201 corresponds to the gate electrode 411 of a transfer transistor TG. The gate electrode 411 of the transfer transistor TG can extend into the photosensitive structure 110 of the semiconductor substrate 100 through the via 201.

[0050] In some embodiments, the gate electrode 411 of the transfer transistor TG extends to a depth of 100-1000 nm into the semiconductor substrate 100, which can be adjusted according to the actual doping of the photosensitive structure 110 and / or the driving voltage of the transfer transistor TG, so that all electrons of the photosensitive structure 110 can flow to the floating diffusion region 310 under the control of the gate electrode of the transfer transistor TG.

[0051] In some embodiments, the width of the via 201 is greater than the width of the extension of the gate electrode 411 of the transfer transistor TG in the direction perpendicular to the buried insulating layer 200. For example, the width of the extension of the gate electrode 411 of the transfer transistor TG is 80-100 nm, while the width of the via 201 is 90-115 nm. When the transfer transistor TG is turned on, photoelectrons can flow upwards along the gate electrode 411 of the transfer transistor TG to the floating diffusion region 310, thereby collecting photoelectron signals.

[0052] In some embodiments, at least a portion of the photosensitive structure 110 is located below the floating diffusion region 310.

[0053] Specifically, based on the formation of the insulating buried layer 200, the photosensitive structure 110 of the semiconductor substrate 100 and the floating diffusion region 310 in the semiconductor layer 300 are isolated, thereby allowing the area of ​​the photosensitive structure 110 to extend inward, increasing the equivalent area of ​​the photosensitive structure 110. That is, the equivalent area of ​​the photosensitive structure 110 is no longer limited by the floating diffusion region 310, thereby improving the full-well capacity of the photosensitive device, and thus improving the imaging capability and dynamic range of the photosensitive device.

[0054] In some embodiments, a first inversion isolation region 120 is further formed in the semiconductor substrate 100. The first inversion isolation region 120 is located below the floating diffusion region 310 and is located below and / or in contact with the insulating buried layer 200. The first inversion isolation region 120 is configured to isolate the adjacent photosensitive structure 110.

[0055] The first inversion isolation region 120 is an inversion isolation region formed by ion implantation in the semiconductor substrate 100, that is, a region formed by inversion doping, used to achieve electrical isolation between devices; that is, introducing doping with the opposite conductivity type to the semiconductor substrate 100 in a specific region to form a high-resistivity isolation layer, that is, forming the first inversion isolation region 120, thereby preventing current leakage between adjacent photosensitive devices.

[0056] Specifically, with Figure 2Taking the formation of two photosensitive structures 110 as an example, photosensitive structures 110 are formed on both sides of the first inversion isolation region 120. The first inversion isolation region 120 is located below the insulating buried layer 200 and in contact with the insulating buried layer 200, or the first inversion isolation region 120 is located in the insulating buried layer 200 but is not in contact with the insulating buried layer 200.

[0057] In some embodiments, a second inversion isolation region 320 is further formed in the semiconductor layer 300, wherein the second inversion isolation region 320 is located above the photosensitive structure 110.

[0058] The second inversion isolation region 320 is an inversion isolation region formed by ion implantation in the semiconductor layer 300, that is, a region formed by inversion doping, used to achieve electrical isolation between devices; that is, introducing doping with the opposite conductivity type to the semiconductor layer 300 in a specific region to form a high-resistivity isolation layer, that is, forming the second inversion isolation region 320, thereby preventing current leakage between adjacent photosensitive devices.

[0059] Specifically, with Figure 2 Taking the formation of two second inverse isolation regions 320 as an example, one of the second inverse isolation regions 320 is located above the photosensitive structure 110 on the left side of the first inverse isolation region 120, and the other second inverse isolation region 320 is located above the photosensitive structure 110 on the left side of the first inverse isolation region 120.

[0060] It is understandable that the second inversion isolation zone 320 may be in contact with the insulating buried layer 200, or the second inversion isolation zone 320 may not be in contact with the insulating buried layer 200.

[0061] In some embodiments, an isolation structure 130 is further formed in the semiconductor substrate 100. The isolation structure 130 is located outside the photosensitive structure 110, and at least a portion of the isolation structure 130 is located below the second inversion isolation region 320, wherein the isolation structure 130 is in contact with the insulating buried layer 200.

[0062] Among them, the isolation structure 130 refers to the electrical isolation between adjacent photosensitive devices, namely DTI (DeepTrench Isolation), which is achieved by etching deep trenches and filling them with insulating material.

[0063] Specifically, the isolation structure 130 extends from the bottom of the semiconductor substrate 100 into the semiconductor substrate 100 and contacts the buried insulating layer 200, and at least a portion of the isolation structure 130 is below the second inversion isolation region 320; furthermore, the isolation structure 130 is outside the photosensitive structure 110 and may or may not contact it; as Figure 2As shown, when two photosensitive structures 110 are formed, there are corresponding two isolation structures 130. That is, through the cooperation of the first inversion isolation region 120, the insulating buried layer 200, the second inversion isolation region 320 and the isolation structure 130, an isolation space is formed to isolate each individual photosensitive device, thereby achieving electrical isolation between adjacent photosensitive devices.

[0064] It is understandable that the isolation structure 130 can be a deep trench isolation structure, a shallow trench isolation structure, or a combination of a shallow trench isolation structure and a doped isolation structure.

[0065] In some embodiments, the dielectric layer 400 includes at least a first dielectric layer 410. The transfer transistor TG includes a connection portion 4111 and an extension portion 4112, that is, the gate electrode 411 of the transfer transistor TG includes a connection portion 4111 and an extension portion 4112. The connection portion 4111 is formed in the first dielectric layer 410, and the extension portion 4112 passes through the semiconductor layer 300 and extends into the photosensitive structure 110 of the semiconductor substrate 100. In a first direction X parallel to the buried insulating layer 200, the width of the connection portion 4111 is greater than the width (diameter) of the via 201 of the buried insulating layer 200, while the width of the extension portion 4112 is smaller than the width (diameter) of the via 201 of the buried insulating layer 200.

[0066] The first dielectric layer 410 includes any suitable dielectric layer known in the art, including but not limited to oxide layers and nitride layers. The first dielectric layer 410 can be a single-layer structure or a multi-layer structure.

[0067] Specifically, the connecting portion 4111 and the extension portion 4112 are integrated as the gate electrode 411 of the transfer transistor TG. The width of the extension portion 4112 is smaller than the width of the through hole 201 of the insulating buried layer 200, so that when the transfer transistor TG is turned on, photoelectrons can flow upward along the gate to the floating diffusion region 310, thereby realizing the collection of photoelectron signals.

[0068] In some embodiments, the dielectric layer 400 further includes a second dielectric layer 420. The second dielectric layer 420 is located above the first dielectric layer 410, and a capacitor structure 421 and multiple metal interconnect layers M are formed in the second dielectric layer 420. The capacitor structure 421 is electrically connected to the floating diffusion region 310, wherein the capacitor structure 421 is located at least between two adjacent metal interconnect layers M.

[0069] The second dielectric layer 420 includes any suitable dielectric layer known in the art, including but not limited to oxide layers and nitride layers. The second dielectric layer 420 can be a single-layer structure or a multi-layer structure. The capacitor structure 421 includes any suitable capacitor structure known in the art, such as a MIM capacitor (Metal-Insulator-Metal capacitor).

[0070] Specifically, a second dielectric layer 420 is formed on the first dielectric layer 410, and multiple metal interconnect layers M are formed in the second dielectric layer, for example, three metal interconnect layers. Then, the capacitor structure 421 can be located between the first metal interconnect layer M1 and the second metal interconnect layer M2, or the capacitor structure 421 can be located between the second metal interconnect layer M2 and the third metal interconnect layer M3, or the capacitor structure 421 can be formed between the first metal interconnect layer M1 and the second metal interconnect layer M2 as well as between the second metal interconnect layer M2 and the third metal interconnect layer M3.

[0071] It is understandable that the capacitor structure 421 can be a planar MIM capacitor structure. Without increasing the height of the metal layer, the planar array MIM capacitor structure can be integrated to improve the full well capacity (FWC) and dynamic range (DR) of the overall photosensitive device.

[0072] In some embodiments, at least a portion of a plurality of other transistors are also formed in the first dielectric layer 410, including a first control transistor and a second control transistor; the first control transistor is electrically connected to the upper plate of the capacitor structure 421, and the second control transistor is electrically connected to the lower plate of the capacitor structure 421, wherein the first control transistor is configured to control the switching on and off of current, and the second control transistor is configured to control the switching on and off of the capacitor structure 421 and the floating diffusion region 310.

[0073] It is understood that at least a portion of the first control transistor is located in the first dielectric layer 410, and at least a portion of the second control transistor is located in the first dielectric layer 410; each transistor may also extend into the semiconductor substrate 100, for example, the source and drain of the transistor extend into the semiconductor substrate 100.

[0074] The first control transistor can be a switch transistor, and the second control transistor can be a DCG transistor (Dual Conversion Gain Transistor).

[0075] To more clearly illustrate the distribution of multiple transistors, the following explanation combines top views, cross-sectional views from different angles, and circuit diagrams.

[0076] Please see Figures 3-6 , Figure 3 This is a top view of one embodiment of the photosensitive device in this application; Figure 4 This is a schematic diagram of the circuit principle of the photosensitive device in this application; Figure 5 yes Figure 3 Schematic diagram of the structure of section AA in the middle; Figure 6 yes Figure 3 A schematic diagram of the structure of the BB cross section.

[0077] like Figure 3 As shown, taking four transfer transistors TG as an example, the four photosensitive structures 110 are distributed around the same floating diffusion region 310, for example, the four photosensitive structures 110 form a matrix, the floating diffusion region 310 is located between the four photosensitive structures 110, and at least a part of each photosensitive structure 110 is below the floating diffusion region 310; each photosensitive structure 110 corresponds to the gate electrode 411 of a transfer transistor TG, and the transfer transistor TG is above the area of ​​the photosensitive structure 110.

[0078] It is understandable that the photosensitive structure 110 can serve as the source of the transfer transistor TG, the floating diffusion region 310 can serve as the drain of the transfer transistor TG, and the floating diffusion region 310 can serve as the common drain of multiple transfer transistors TG.

[0079] Other transistors include the Switch transistor, DCG transistor, RST transistor (Reset), SF transistor (Source Follower), and SEL transistor (Select).

[0080] Specifically, the photosensitive structure 110 serves as the first source and drain of the transfer transistor TG, and the floating diffusion region 310 serves as the second source and drain of the transfer transistor TG; the first source and drain of the switch transistor are electrically connected to the upper plate of the capacitor structure 421, and the second source and drain of the switch transistor are connected to VDD (supply voltage terminal); the first source and drain of the RST transistor are electrically connected to VDD (supply voltage terminal), and the second source and drain of the RST transistor are electrically connected to the lower plate of the capacitor structure 421; the first source and drain of the DCG transistor are electrically connected to the lower plate of the capacitor structure 421. Next, the second source and drain of the DCG transistor are electrically connected to the floating diffusion region 310, and the second source and drain of the ST transistor and the first source and drain of the DCG transistor serve as a common source drain; the gate electrode of the SF transistor is electrically connected to the floating diffusion region 310, the first source and drain of the SF transistor are electrically connected to VDD (supply voltage terminal), the second source and drain of the SF transistor are electrically connected to the first source and drain of the SEL transistor, and the second source and drain of the SF transistor and the first source and drain of the SEL transistor serve as a common source drain; the second source and drain of the SEL transistor are electrically connected to Vout (output voltage terminal), as... Figure 4 As shown.

[0081] It is understandable that when the DCG transistor is turned on (conducting), the floating diffusion region 310 and the capacitor structure 421 are connected in parallel between the DCG transistor and VDD (supply voltage terminal).

[0082] exist Figure 3 Based on this, the AA cross-section passes through two photosensitive structures 110, two transfer transistors TG, and a floating diffusion region 310.

[0083] like Figure 5As shown, two photosensitive structures 110 are formed in the semiconductor substrate 100, located on both sides of the first inversion isolation region 120, and two isolation structures 130 are located in the semiconductor substrate 100 outside the corresponding photosensitive structure 110, and the isolation structures 130 are in contact with the insulating buried layer 200; the insulating buried layer 200 covers the semiconductor substrate 100, and the insulating buried layer 200 has two corresponding vias 201; the semiconductor layer 300 covers the insulating buried layer 200, and a floating diffusion region 310 is formed in the semiconductor layer 300, the floating diffusion region 310 is located above the first inversion isolation region 120, and is located above at least a portion of each photosensitive structure 110; two second inversion isolation regions 320 are also formed in the semiconductor layer 300, and at least a portion of each second inversion isolation region 320 is located above the corresponding isolation structure 130. A first dielectric layer 410 covers the semiconductor layer 300. Two transfer transistors TG are formed in the first dielectric layer, and the gate electrode 411 of the transfer transistor TG extends into the photosensitive structure 110. The width of the extension portion 4112 of the gate electrode 411 of the transfer transistor TG is smaller than the width of the via 201, while the width of the connection portion 4111 of the gate electrode 411 of the transfer transistor TG is larger than the width of the via 201. A second dielectric layer 420 covers the first dielectric layer 410, and multiple metal interconnect layers M are formed in the second dielectric layer 420.

[0084] like Figure 6 As shown, a Switch transistor, a DCG transistor, and an RST transistor are also formed in the first dielectric layer 410; a capacitor structure 421 is also formed in the second dielectric layer 420, and the capacitor structure 421 is located between at least two adjacent metal interconnect layers M; wherein, the upper plate of the capacitor structure 421 is electrically connected to the first source and drain of the Switch transistor, and the lower plate of the capacitor structure 421 is electrically connected to the first source and drain of the DCG transistor.

[0085] Compared to current technologies, the isolation structure 130 in this application extends to the buried insulating layer 200, which contacts the second inversion isolation region 320. The buried insulating layer 200 and the isolation structure 130 form a fully enclosed structure, completely isolating the individual photosensitive structure 110 and effectively reducing leakage current within the photosensitive structure 110. Furthermore, it eliminates the need for an STI structure and ion implantation isolation, reducing the damage to the semiconductor substrate 100 caused by the etching plasma during the STI process, thereby further reducing leakage current in the photosensitive structure 110.

[0086] In this embodiment, by isolating the photosensitive structure in the semiconductor substrate and the floating diffusion region in the semiconductor layer through an insulating buried layer, the lattice damage of the substrate caused by plasma discharge in subsequent processes can be prevented, the defect surface area can be reduced, the leakage current problem caused by the interface between the semiconductor substrate and the semiconductor layer can be effectively reduced, and the noise generation can be reduced; it can also effectively increase the lateral area of ​​the photosensitive structure, avoid the influence of the floating diffusion region area, improve the energy of photoelectrons collected, improve the full-well capacity of the photosensitive device, and thus improve the performance of the photosensitive device.

[0087] This application also provides a method for manufacturing a photosensitive device.

[0088] Please see Figure 7 , Figure 7 This is a schematic flowchart of an embodiment of the manufacturing method of the photosensitive device in this application.

[0089] like Figure 7 As shown, a method for manufacturing a photosensitive device includes: S10. Provide a semiconductor substrate in which a photosensitive structure is formed; S20. An insulating buried layer is formed on a semiconductor substrate; S30. A semiconductor layer is formed on an insulating buried layer, and a floating diffusion region is formed in the semiconductor layer, wherein the floating diffusion region is isolated from the photosensitive structure by the insulating buried layer.

[0090] The manufacturing method will be explained below with reference to the accompanying drawings.

[0091] Please see Figures 8-17 , Figure 8 This is a schematic diagram of a structure in an embodiment of forming an insulating buried layer and a semiconductor layer in this application; Figure 9 This is a schematic diagram of an embodiment of the photosensitive structure formed in this application; Figure 10 This is a schematic diagram of the structure of an embodiment of forming the first inverse isolation region in this application; Figure 11 This is a schematic diagram of a structure of an embodiment of forming a second inverse isolation region in this application; Figure 12 This is a schematic diagram of a structure for forming a floating diffusion region in this application; Figure 13 This is a schematic diagram of a structure of an embodiment of forming a groove in this application; Figure 14 This is a schematic diagram of the structure of an embodiment of forming a gate electrode in this application; Figure 15 This is a schematic diagram of a structure forming the first dielectric layer in this application; Figure 16 This is a schematic diagram of a structure in an embodiment of forming the second dielectric layer in this application; Figure 17 This is a schematic diagram of an embodiment of the isolation structure in this application.

[0092] like Figure 8As shown, a semiconductor substrate 100 is provided, an insulating buried layer 200 is formed on the semiconductor substrate 100, and a semiconductor layer 300 is formed on the insulating buried layer 200, wherein the insulating buried layer 200 has through holes 201.

[0093] In some embodiments, the buried insulating layer 200 may include a first buried insulating layer and a second buried insulating layer. The first buried insulating layer is formed on a semiconductor substrate 100, and the second buried insulating layer is formed on a semiconductor layer 300. The semiconductor substrate 100 with the first buried insulating layer and the semiconductor layer 300 with the second buried insulating layer are bonded together. The bonded first and second buried insulating layers then constitute the buried insulating layer 200. (See also...) Figure 2 .

[0094] Next, as Figure 9 As shown, a photosensitive structure 110 is formed in a semiconductor substrate 100 using a high aspect ratio photolithography process and an ion implantation process.

[0095] Specifically, for areas outside the photosensitive structure 110, a mask can be used for coverage, such as photoresist. Then, deep ion implantation is performed on the areas not covered by the photoresist to form the photosensitive structure 110 in the semiconductor substrate 100, and the photoresist is removed. For example, the height:width ratio in a high aspect ratio lithography process can be set to 30:1.

[0096] It is understood that there can be multiple photosensitive structures 110, each photosensitive structure 110 corresponding to a photosensitive device, and the photosensitive structures 110 are arranged at intervals with each other.

[0097] Next, as Figure 10 As shown, an ion implantation process is used to form a first inversion isolation region 120 in a semiconductor substrate 100.

[0098] Specifically, for the area outside the first inversion isolation region 120, a mask can be used for coverage, such as photoresist, and then deep ion implantation can be performed on the area not covered by photoresist to form the first inversion isolation region 120 in the semiconductor substrate 100, and the photoresist can be removed.

[0099] It is understood that the first inversion isolation region 120 is located between adjacent photosensitive structures 110 and is used to isolate the adjacent photosensitive structures 110.

[0100] Next, as Figure 11 As shown, an ion implantation process is used to form a second inversion isolation region 320 in the semiconductor layer 300.

[0101] Specifically, for the area outside the second inversion isolation region 320, a mask can be used to cover it, such as photoresist, and then ion implantation can be performed on the uncovered area to form the second inversion isolation region 320 in the semiconductor layer 300, and the photoresist can be removed.

[0102] Understandably, the second inversion isolation region 320 is located above the area outside the photosensitive structure 110.

[0103] Next, as Figure 12 As shown, a floating diffusion region 310 is formed in the semiconductor layer 300 using an ion implantation process.

[0104] Specifically, for the area outside the floating diffusion region 310, a mask can be used to cover it, such as photoresist, and then ion implantation can be performed on the uncovered area to form the floating diffusion region 310 in the semiconductor layer 300, and the photoresist can be removed.

[0105] It is understood that the floating diffusion region 310 is located above the first inverted isolation region 120 and above at least a portion of the photosensitive structure 110, that is, the orthographic projection of the floating diffusion region 310 covers the orthographic projection of the first inverted isolation region 120 and covers at least a portion of the orthographic projection of the photosensitive structure 110.

[0106] Next, as Figure 13 As shown, groove 301 is formed.

[0107] Specifically, for the area outside the groove 301, a mask can be used to cover it, such as photoresist, and then etching can be performed from the semiconductor layer 300 toward the semiconductor substrate 100 to form the groove 301. The groove 301 extends from the semiconductor layer 300 into the photosensitive structure 110 of the semiconductor substrate 100, and the photoresist is removed.

[0108] It is understood that the groove 301 extends along the via 201 of the buried insulating layer 200 into the semiconductor substrate 100, and in the direction perpendicular to the buried insulating layer 200, the width of the groove 301 is smaller than the width of the via 201.

[0109] In some embodiments, the groove 301 contacts the insulating buried layer 200 on the side away from the first inversion isolation region 120.

[0110] Next, as Figure 14 As shown, a transistor is formed.

[0111] Specifically, in Figure 13 Based on this, polysilicon is deposited and polysilicon etching is performed to form gate electrodes of multiple transistors on the semiconductor layer 300, wherein the gate electrode 411 of the transfer transistor TG is formed in the groove 301.

[0112] Additionally, the following are included (not shown in the attached figures): the gate electrode of the Switch transistor (not labeled in the attached figures), the gate electrode of the DCG transistor (not labeled in the attached figures), the gate electrode of the RST transistor (not labeled in the attached figures), the gate electrode of the SF transistor (not labeled in the attached figures), and the gate electrode of the SEL transistor (not labeled in the attached figures). Please refer to [the attached figures for further details]. Figure 3 .

[0113] Next, as Figure 15 As shown, a first dielectric layer 410 is formed.

[0114] Specifically, in Figure 14 Based on this, a first dielectric layer 410 is formed, which covers the semiconductor layer 300 and all transistors, i.e., covers the gate electrode of the transistor.

[0115] Next, as Figure 16 As shown, a second dielectric layer 420 is formed.

[0116] Specifically, in Figure 15 Based on this, a second dielectric layer 420 is formed, wherein multiple metal interconnect layers M are formed in the second dielectric layer 420, and a capacitor structure 421 (not shown in the figure) is formed. Please refer to [the figure for details]. Figure 6 .

[0117] It is understood that the capacitor structure 421 can be located between the first metal connection layer M1 and the second metal connection layer M2, or between the second metal connection layer M2 and the third metal connection layer M3, or the capacitor structure 421 can be formed between both the first metal connection layer M1 and the second metal connection layer M2, and between the second metal connection layer M2 and the third metal connection layer M3. It is also understood that the capacitor structure 421 can be configured across multiple metal connection layers.

[0118] In some embodiments, the capacitor structure 421 may include a multilayer stacked structure, for example, including, from top to bottom, a first NDC layer (nitrogen-doped carbide), an upper electrode layer (e.g., a TIN layer), an HK layer (high-K layer), a lower electrode layer (e.g., a TIN layer), and a second NDC layer. At least a portion of the first NDC layer, the upper electrode layer, and the HK layer may be removed, followed by deposition of a dielectric layer (e.g., silicon dioxide), photolithography, and etching to form interconnect vias (filled with a conductive material, such as copper) to bring out the upper and lower electrode layers.

[0119] Next, as Figure 17 As shown, the semiconductor substrate 100 is etched, and an isolation structure 130 is formed in the semiconductor substrate 100.

[0120] Specifically, in Figure 16Based on this, etching is performed from the semiconductor substrate 100 toward the insulating buried layer 200 to form trenches in the semiconductor substrate 100, and insulating material is filled in the trenches to form an isolation structure 130.

[0121] It is understood that the insulating buried layer 200 serves as an etching stop layer, i.e., the formed isolation structure 130 is in contact with the insulating buried layer 200; the isolation structure 130 is located outside the photosensitive structure 110, and at least a portion of the isolation structure 130 is located below the second inversion isolation region 320.

[0122] In this embodiment, by isolating the photosensitive structure in the semiconductor substrate and the floating diffusion region in the semiconductor layer through an insulating buried layer, the lattice damage of the substrate caused by plasma discharge in subsequent processes can be prevented, the defect surface area can be reduced, the leakage current problem caused by the interface between the semiconductor substrate and the semiconductor layer can be effectively reduced, and the noise generation can be reduced; it can also effectively increase the lateral area of ​​the photosensitive structure, avoid the influence of the floating diffusion region area, improve the energy of photoelectrons collected, improve the full-well capacity of the photosensitive device, and thus improve the performance of the photosensitive device.

[0123] The above description is merely an embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A photosensitive device, characterized in that, include: A semiconductor substrate in which a photosensitive structure is formed; An insulating buried layer, the insulating buried layer being located on the semiconductor substrate; A semiconductor layer is located above the insulating buried layer, and a floating diffusion region is formed in the semiconductor layer, wherein the floating diffusion region is isolated from the photosensitive structure by the insulating buried layer.

2. The photosensitive device according to claim 1, characterized in that, Also includes: A dielectric layer is located above the semiconductor layer, wherein at least a portion of the transfer transistor is formed in the dielectric layer.

3. The photosensitive device according to claim 2, characterized in that: At least a portion of the transfer transistor extends into the photosensitive structure.

4. The photosensitive device according to claim 3, characterized in that, The insulating buried layer is formed with a via through which the transfer transistor passes, such that at least a portion of the transfer transistor extends into the photosensitive structure.

5. The photosensitive device according to claim 1, characterized in that, At least a portion of the photosensitive structure is located below the floating diffusion region.

6. The photosensitive device according to claim 1, characterized in that, A first inversion isolation region is also formed in the semiconductor substrate. The first inversion isolation region is located below the floating diffusion region and is located below the buried insulating layer and / or in contact with the buried insulating layer. The first inversion isolation region is configured to isolate adjacent photosensitive structures.

7. The photosensitive device according to claim 1, characterized in that, A second inversion isolation region is formed in the semiconductor layer, wherein the second inversion isolation region is located above the photosensitive structure.

8. The photosensitive device according to claim 7, characterized in that, The second inverted isolation zone is in contact with the insulating buried layer.

9. The photosensitive device according to claim 7, characterized in that, An isolation structure is also formed in the semiconductor substrate, the isolation structure being located outside the photosensitive structure, and at least a portion of the isolation structure being located below the second inversion isolation region.

10. The photosensitive device according to claim 9, characterized in that, The isolation structure is in contact with the insulating buried layer.

11. The photosensitive device according to claim 1, characterized in that, The insulating buried layer includes a first insulating buried layer and a second insulating buried layer, wherein the first insulating buried layer is formed on the semiconductor substrate, and the second insulating buried layer is bonded to the first insulating buried layer.

12. The photosensitive device according to claim 2, characterized in that, The dielectric layer includes at least a first dielectric layer; The transfer transistor includes a connection portion and an extension portion, the connection portion being formed in the first dielectric layer, and the extension portion passing through the semiconductor layer and extending into the photosensitive structure of the semiconductor substrate.

13. The photosensitive device according to claim 12, characterized in that, The dielectric layer further includes a second dielectric layer; The second dielectric layer is located above the first dielectric layer. A capacitor structure and a plurality of metal interconnect layers are formed in the second dielectric layer. The capacitor structure is electrically connected to the floating diffusion region. The capacitor structure is located between at least two of the metal interconnect layers.

14. The photosensitive device according to claim 13, characterized in that, The first dielectric layer also contains a plurality of other transistors, including a first control transistor and a second control transistor. The first control transistor is electrically connected to the upper plate of the capacitor structure, and the second control transistor is electrically connected to the lower plate of the capacitor structure. The first control transistor is configured to control the current switching on and off, and the second control transistor is configured to control the switching on and off of the capacitor structure and the floating diffusion region.

15. A method for manufacturing a photosensitive device, characterized in that, include: A semiconductor substrate is provided in which a photosensitive structure is formed; An insulating buried layer is formed on the semiconductor substrate; A semiconductor layer is formed on the insulating buried layer, and a floating diffusion region is formed in the semiconductor layer, wherein the floating diffusion region is isolated from the photosensitive structure by the insulating buried layer.

16. The method according to claim 15, characterized in that, Also includes: A first ion implantation is performed from the semiconductor layer toward the semiconductor substrate to form the photosensitive structure in the semiconductor substrate; A second ion implantation is performed from the semiconductor layer toward the semiconductor substrate to form a first inversion isolation region in the semiconductor substrate, wherein the first inversion isolation region is configured to isolate adjacent photosensitive structures.

17. The method according to claim 16, characterized in that, Also includes: A third ion implantation is performed on the semiconductor layer to form a second inversion isolation region in the semiconductor layer, wherein the second inversion isolation region is located above the photosensitive structure; A fourth ion implantation is performed on the semiconductor layer to form the floating diffusion region in the semiconductor layer, wherein the floating diffusion region is located above the first inversion isolation region, and at least a portion of the photosensitive structure is located below the floating diffusion region.

18. The method according to claim 15, characterized in that, Also includes: A dielectric layer is formed on top of the semiconductor layer, wherein at least a portion of a transfer transistor is formed in the dielectric layer and extends into the photosensitive structure.

19. The method according to claim 18, characterized in that, Also includes: A groove is formed from the semiconductor layer toward the semiconductor substrate, the groove extending into the photosensitive structure in the semiconductor substrate; A polycrystalline material layer is formed, which fills the groove and covers the semiconductor layer; At least a portion of the polycrystalline material layer is removed to form a plurality of transistors on a semiconductor layer, wherein a transistor extending to the photosensitive structure among the plurality of transistors is the transfer transistor.

20. The method according to claim 19, characterized in that, The dielectric layer includes at least a first dielectric layer and a second dielectric layer; The formation of the dielectric layer includes: A first dielectric layer is formed, the first dielectric layer covering the semiconductor layer and the plurality of transistors on the semiconductor layer; A second dielectric layer is formed, which covers the first dielectric layer. A capacitor structure and multiple metal interconnect layers are formed in the second dielectric layer. The capacitor structure is electrically connected to the floating diffusion region. The capacitor structure is located between at least two of the metal interconnect layers. The upper electrode of the capacitor structure is electrically connected through a first control transistor among the multiple transistors, and the lower electrode of the capacitor structure is electrically connected through a second control transistor among the multiple transistors.

21. The method according to claim 18, characterized in that, After the dielectric layer is formed, an isolation structure is formed from the semiconductor substrate toward the buried insulating layer, wherein the isolation structure is in contact with the buried insulating layer and at least a portion of the isolation structure is located below a second inversion isolation region formed in the semiconductor layer.

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